From patchwork Fri Aug 12 17:24:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanumanth Pothula X-Patchwork-Id: 114929 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 18A18A0543; Fri, 12 Aug 2022 19:27:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AD97B40A82; Fri, 12 Aug 2022 19:27:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B574C40A7F for ; Fri, 12 Aug 2022 19:27:09 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27CFCZ7w028243; Fri, 12 Aug 2022 10:25:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=9zZbwve6GyYJxLnNm8Sxnj7L0KEbMSZEVfLDbIAzC7s=; b=OnSHtgzNevhWZx42mCwAXxjUqLNMleldRsyaeqVCjQ1sENrXUHH4/TkArA5gqu6dJDip bwDM0LYIJAuYTeKjlduKcNIrEkHw/2SdlpSl9ngGy086Qy/aeJMWKEj+eKqvUwXX90AI yLAnurmnbUmeGc76RCuteZQ2zn5bokVPO/kywEhd+vC+CLx+ntmqqwi6c9uY15lthhS8 XSKQNimHT6Cor6hyAHIHuzfDv19Xb6c4x6w+XfWLnpz/jYmv58aMdxAuCze6x6NZ2JzN 7G7vILirxMrfQMCd02xNeaC1CE/dZ/+5QogwkygEkFb5KXj00Zt3dtdDNiQhMuKTUMWm tg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hwsa18ggq-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 10:25:04 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 12 Aug 2022 10:25:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 12 Aug 2022 10:25:02 -0700 Received: from localhost.localdomain (unknown [10.28.36.155]) by maili.marvell.com (Postfix) with ESMTP id B82DD5B6934; Fri, 12 Aug 2022 10:24:56 -0700 (PDT) From: Hanumanth Pothula To: Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , , , , , , , , , , , , Hanumanth Pothula Subject: [PATCH v2 1/3] ethdev: introduce pool sort capability Date: Fri, 12 Aug 2022 22:54:49 +0530 Message-ID: <20220812172451.1208933-1-hpothula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812104648.1019978-1-hpothula@marvell.com> References: <20220812104648.1019978-1-hpothula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: d261cvZJiCUXIF928raR6MgZ52zQyVR0 X-Proofpoint-GUID: d261cvZJiCUXIF928raR6MgZ52zQyVR0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_10,2022-08-11_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Presently, the 'Buffer Split' feature supports sending multiple segments of the received packet to PMD, which programs the HW to receive the packet in segments from different pools. This patch extends the feature to support the pool sort capability. Some of the HW has support for choosing memory pools based on the packet's size. The pool sort capability allows PMD to choose a memory pool based on the packet's length. This is often useful for saving the memory where the application can create a different pool to steer the specific size of the packet, thus enabling effective use of memory. For example, let's say HW has a capability of three pools, - pool-1 size is 2K - pool-2 size is > 2K and < 4K - pool-3 size is > 4K Here, pool-1 can accommodate packets with sizes < 2K pool-2 can accommodate packets with sizes > 2K and < 4K pool-3 can accommodate packets with sizes > 4K With pool sort capability enabled in SW, an application may create three pools of different sizes and send them to PMD. Allowing PMD to program HW based on packet lengths. So that packets with less than 2K are received on pool-1, packets with lengths between 2K and 4K are received on pool-2 and finally packets greater than 4K are received on pool-3. The following two capabilities are added to the rte_eth_rxseg_capa structure, 1. pool_sort --> tells pool sort capability is supported by HW. 2. max_npool --> max number of pools supported by HW. Defined new structure rte_eth_rxseg_sort, to be used only when pool sort capability is present. If required this may be extended further to support more configurations. Signed-off-by: Hanumanth Pothula v2: - Along with spec changes, uploading testpmd and driver changes. --- lib/ethdev/rte_ethdev.c | 87 +++++++++++++++++++++++++++++++++++------ lib/ethdev/rte_ethdev.h | 45 +++++++++++++++++++-- 2 files changed, 118 insertions(+), 14 deletions(-) diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 1979dc0850..7fd5443eb8 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -1635,7 +1635,55 @@ rte_eth_dev_is_removed(uint16_t port_id) } static int -rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg, +rte_eth_rx_queue_check_sort(const struct rte_eth_rxseg *rx_seg, + uint16_t n_seg, uint32_t *mbp_buf_size, + const struct rte_eth_dev_info *dev_info) +{ + const struct rte_eth_rxseg_capa *seg_capa = &dev_info->rx_seg_capa; + uint16_t seg_idx; + + if (!seg_capa->multi_pools || n_seg > seg_capa->max_npool) { + RTE_ETHDEV_LOG(ERR, + "Invalid capabilities, multi_pools:%d differnt length segments %u exceed supported %u\n", + seg_capa->multi_pools, n_seg, seg_capa->max_nseg); + return -EINVAL; + } + + for (seg_idx = 0; seg_idx < n_seg; seg_idx++) { + struct rte_mempool *mpl = rx_seg[seg_idx].sort.mp; + uint32_t length = rx_seg[seg_idx].sort.length; + + if (mpl == NULL) { + RTE_ETHDEV_LOG(ERR, "null mempool pointer\n"); + return -EINVAL; + } + + if (mpl->private_data_size < + sizeof(struct rte_pktmbuf_pool_private)) { + RTE_ETHDEV_LOG(ERR, + "%s private_data_size %u < %u\n", + mpl->name, mpl->private_data_size, + (unsigned int)sizeof + (struct rte_pktmbuf_pool_private)); + return -ENOSPC; + } + + *mbp_buf_size = rte_pktmbuf_data_room_size(mpl); + length = length != 0 ? length : (*mbp_buf_size - RTE_PKTMBUF_HEADROOM); + if (*mbp_buf_size < length + RTE_PKTMBUF_HEADROOM) { + RTE_ETHDEV_LOG(ERR, + "%s mbuf_data_room_size %u < %u))\n", + mpl->name, *mbp_buf_size, + length); + return -EINVAL; + } + } + + return 0; +} + +static int +rte_eth_rx_queue_check_split(const struct rte_eth_rxseg *rx_seg, uint16_t n_seg, uint32_t *mbp_buf_size, const struct rte_eth_dev_info *dev_info) { @@ -1654,12 +1702,12 @@ rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg, * Check the sizes and offsets against buffer sizes * for each segment specified in extended configuration. */ - mp_first = rx_seg[0].mp; + mp_first = rx_seg[0].split.mp; offset_mask = RTE_BIT32(seg_capa->offset_align_log2) - 1; for (seg_idx = 0; seg_idx < n_seg; seg_idx++) { - struct rte_mempool *mpl = rx_seg[seg_idx].mp; - uint32_t length = rx_seg[seg_idx].length; - uint32_t offset = rx_seg[seg_idx].offset; + struct rte_mempool *mpl = rx_seg[seg_idx].split.mp; + uint32_t length = rx_seg[seg_idx].split.length; + uint32_t offset = rx_seg[seg_idx].split.offset; if (mpl == NULL) { RTE_ETHDEV_LOG(ERR, "null mempool pointer\n"); @@ -1693,7 +1741,11 @@ rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg, } offset += seg_idx != 0 ? 0 : RTE_PKTMBUF_HEADROOM; *mbp_buf_size = rte_pktmbuf_data_room_size(mpl); - length = length != 0 ? length : *mbp_buf_size; + /* On segment length == 0, update segment's length with + * the pool's length - headeroom space, to make sure enough + * space is accomidate for header. + **/ + length = length != 0 ? length : (*mbp_buf_size - RTE_PKTMBUF_HEADROOM); if (*mbp_buf_size < length + offset) { RTE_ETHDEV_LOG(ERR, "%s mbuf_data_room_size %u < %u (segment length=%u + segment offset=%u)\n", @@ -1764,7 +1816,6 @@ rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, return -EINVAL; } } else { - const struct rte_eth_rxseg_split *rx_seg; uint16_t n_seg; /* Extended multi-segment configuration check. */ @@ -1774,13 +1825,27 @@ rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, return -EINVAL; } - rx_seg = (const struct rte_eth_rxseg_split *)rx_conf->rx_seg; n_seg = rx_conf->rx_nseg; if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) { - ret = rte_eth_rx_queue_check_split(rx_seg, n_seg, - &mbp_buf_size, - &dev_info); + ret = -1; /* To make sure at least one of below conditions becomes true */ + + /* Check both NIX and application supports buffer-split capability */ + if (dev_info.rx_seg_capa.mode_split && + rx_conf->mode_flag == RTE_ETH_RXSEG_MODE_SPLIT) { + ret = rte_eth_rx_queue_check_split(rx_conf->rx_seg, n_seg, + &mbp_buf_size, + &dev_info); + } + + /* Check both NIX and application supports pool-sort capability */ + if (dev_info.rx_seg_capa.mode_sort && + rx_conf->mode_flag == RTE_ETH_RXSEG_MODE_SORT) { + ret = rte_eth_rx_queue_check_sort(rx_conf->rx_seg, n_seg, + &mbp_buf_size, + &dev_info); + } + if (ret != 0) return ret; } else { diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index de9e970d4d..9f6787d7ad 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -1204,16 +1204,46 @@ struct rte_eth_rxseg_split { uint32_t reserved; /**< Reserved field. */ }; +/** + * The pool sort capability allows PMD to choose a memory pool based on the + * packet's length. So, basically, PMD programs HW for receiving packets from + * different pools, based on the packet's length. + * + * This is often useful for saving the memory where the application can create + * a different pool to steer the specific size of the packet, thus enabling + * effective use of memory. + */ +struct rte_eth_rxseg_sort { + struct rte_mempool *mp; /**< Memory pool to allocate packets from. */ + uint16_t length; /**< Packet data length. */ + uint32_t reserved; /**< Reserved field. */ +}; + +enum rte_eth_rxseg_mode { + /** + * Buffer split mode: PMD split the received packets into multiple segments. + * @see struct rte_eth_rxseg_split + */ + RTE_ETH_RXSEG_MODE_SPLIT = RTE_BIT64(0), + /** + * Pool sort mode: PMD to chooses a memory pool based on the packet's length. + * @see struct rte_eth_rxseg_sort + */ + RTE_ETH_RXSEG_MODE_SORT = RTE_BIT64(1), +}; + /** * @warning * @b EXPERIMENTAL: this structure may change without prior notice. * * A common structure used to describe Rx packet segment properties. */ -union rte_eth_rxseg { +struct rte_eth_rxseg { /* The settings for buffer split offload. */ struct rte_eth_rxseg_split split; - /* The other features settings should be added here. */ + + /*The settings for packet sort offload. */ + struct rte_eth_rxseg_sort sort; }; /** @@ -1239,6 +1269,11 @@ struct rte_eth_rxconf { * fields on rte_eth_dev_info structure are allowed to be set. */ uint64_t offloads; + /** + * PMD may support more than one rxseg mode. This allows application + * to chose which mode to enable. + */ + enum rte_eth_rxseg_mode mode_flag; /** * Points to the array of segment descriptions for an entire packet. * Array elements are properties for consecutive Rx segments. @@ -1246,7 +1281,7 @@ struct rte_eth_rxconf { * The supported capabilities of receiving segmentation is reported * in rte_eth_dev_info.rx_seg_capa field. */ - union rte_eth_rxseg *rx_seg; + struct rte_eth_rxseg *rx_seg; uint64_t reserved_64s[2]; /**< Reserved for future fields */ void *reserved_ptrs[2]; /**< Reserved for future fields */ @@ -1827,10 +1862,14 @@ struct rte_eth_switch_info { */ struct rte_eth_rxseg_capa { __extension__ + uint32_t mode_split : 1; /**< Supports buffer split capability @see struct rte_eth_rxseg_split */ + uint32_t mode_sort : 1; /**< Supports pool sort capability @see struct rte_eth_rxseg_sort */ uint32_t multi_pools:1; /**< Supports receiving to multiple pools.*/ uint32_t offset_allowed:1; /**< Supports buffer offsets. */ uint32_t offset_align_log2:4; /**< Required offset alignment. */ uint16_t max_nseg; /**< Maximum amount of segments to split. */ + /* < Maximum amount of pools that PMD can sort based on packet/segment lengths */ + uint16_t max_npool; uint16_t reserved; /**< Reserved field. */ }; From patchwork Fri Aug 12 17:24:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanumanth Pothula X-Patchwork-Id: 114930 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0EE86A0543; Fri, 12 Aug 2022 19:27:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0134F40C35; Fri, 12 Aug 2022 19:27:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 54C7740A7F for ; Fri, 12 Aug 2022 19:27:35 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27CFCYHL028233; Fri, 12 Aug 2022 10:25:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=4DkHXZsnwv7UusinXl93ce2pvz29XOjLR/LrFJ4Gxkg=; b=d8yLeQXIa7N0NIS+YpzO9UnbAcvFE4XfkL4Ctw/m+OHyYaNA+EI51jDdxDkl8JXHWNM5 V1iuT8rRGKhzDx2I+9PNc0v5X2h0OL1WIjgQtmYYCiw/7M8qPig8P+UrnSPi6B/mOaPe y4PzQ003dHEwrzjSROVIvgUfST9iH6CFUk/K11b3NEvUALn7k6HLcNuroHYkJlbI6JSE v/hytQgPTIvggPPXGpM2gKcPSY3G4IyiYrBjv/zQuMTeI4kTb3IM6bjqrUi8/3KRYja6 2q/f7aAbFZoLgDYP6PPWbELBbdyUVUhaoRaFhMIBZ8EAer3PVpXCf2WnMggGLw7Hy/uZ KA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hwsa18gjf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 12 Aug 2022 10:25:30 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 12 Aug 2022 10:25:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 12 Aug 2022 10:25:28 -0700 Received: from localhost.localdomain (unknown [10.28.36.155]) by maili.marvell.com (Postfix) with ESMTP id 7A5A15B6936; Fri, 12 Aug 2022 10:25:22 -0700 (PDT) From: Hanumanth Pothula To: Aman Singh , Yuying Zhang CC: , , , , , , , , , , , , , , Hanumanth Pothula Subject: [PATCH v2 2/3] app/testpmd: add command line argument 'rxseg-mode' Date: Fri, 12 Aug 2022 22:54:50 +0530 Message-ID: <20220812172451.1208933-2-hpothula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812172451.1208933-1-hpothula@marvell.com> References: <20220812104648.1019978-1-hpothula@marvell.com> <20220812172451.1208933-1-hpothula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: bXTnOt8EO172mOLw0PTDnDTWseqvkQVR X-Proofpoint-GUID: bXTnOt8EO172mOLw0PTDnDTWseqvkQVR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_10,2022-08-11_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org With rxseg-mode command line argument, application can choose either buffer split or pool sort capability. This might be helpful if HW has support for both capabilities and application wants to enable one of them. By default, buffer-split capability is enabled to enable pool-sort capability pass command line argument, '--rxseg-mode=2'. Signed-off-by: Hanumanth Pothula --- app/test-pmd/parameters.c | 16 ++++++++++++++++ app/test-pmd/testpmd.c | 35 ++++++++++++++++++++++++++--------- app/test-pmd/testpmd.h | 2 ++ app/test-pmd/util.c | 4 ++-- 4 files changed, 46 insertions(+), 11 deletions(-) diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c index e3c9757f3f..c3876a9b5f 100644 --- a/app/test-pmd/parameters.c +++ b/app/test-pmd/parameters.c @@ -213,6 +213,9 @@ usage(char* progname) printf(" --hairpin-mode=0xXX: bitmask set the hairpin port mode.\n" " 0x10 - explicit Tx rule, 0x02 - hairpin ports paired\n" " 0x01 - hairpin ports loop, 0x00 - hairpin port self\n"); + printf(" --rxseg-mode: provide rxseg capbility\n" + " 1 - Bufer-split capability\n" + " 2 - Pool-sort capability\n"); } #ifdef RTE_LIB_CMDLINE @@ -710,6 +713,7 @@ launch_args_parse(int argc, char** argv) { "record-burst-stats", 0, 0, 0 }, { PARAM_NUM_PROCS, 1, 0, 0 }, { PARAM_PROC_ID, 1, 0, 0 }, + { "rxseg-mode", 1, 0, 0 }, { 0, 0, 0, 0 }, }; @@ -1510,6 +1514,18 @@ launch_args_parse(int argc, char** argv) num_procs = atoi(optarg); if (!strcmp(lgopts[opt_idx].name, PARAM_PROC_ID)) proc_id = atoi(optarg); + if (!strcmp(lgopts[opt_idx].name, "rxseg-mode")) { + char *end = NULL; + unsigned int n; + + errno = 0; + n = strtoul(optarg, &end, 0); + if (errno != 0 || end == optarg || + n < RTE_ETH_RXSEG_MODE_SPLIT || n > RTE_ETH_RXSEG_MODE_SORT) + rte_exit(EXIT_FAILURE, "invalid rxseg mode\n"); + else + rxseg_mode = (uint8_t)n; + } break; case 'h': usage(argv[0]); diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index addcbcac85..b5b4fcd66e 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -411,6 +411,9 @@ uint8_t clear_ptypes = true; /* Hairpin ports configuration mode. */ uint16_t hairpin_mode; +/* send Rxseg mode */ +uint8_t rxseg_mode = RTE_ETH_RXSEG_MODE_SPLIT; + /* Pretty printing of ethdev events */ static const char * const eth_event_desc[] = { [RTE_ETH_EVENT_UNKNOWN] = "unknown", @@ -2656,7 +2659,7 @@ rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, uint16_t nb_rx_desc, unsigned int socket_id, struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp) { - union rte_eth_rxseg rx_useg[MAX_SEGS_BUFFER_SPLIT] = {}; + struct rte_eth_rxseg rx_useg[MAX_SEGS_BUFFER_SPLIT] = {}; unsigned int i, mp_n; int ret; @@ -2670,24 +2673,38 @@ rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, goto exit; } for (i = 0; i < rx_pkt_nb_segs; i++) { - struct rte_eth_rxseg_split *rx_seg = &rx_useg[i].split; + struct rte_eth_rxseg_split *rx_split = &rx_useg[i].split; + struct rte_eth_rxseg_sort *rx_sort = &rx_useg[i].sort; struct rte_mempool *mpx; + /* * Use last valid pool for the segments with number * exceeding the pool index. */ mp_n = (i >= mbuf_data_size_n) ? mbuf_data_size_n - 1 : i; mpx = mbuf_pool_find(socket_id, mp_n); - /* Handle zero as mbuf data buffer size. */ - rx_seg->length = rx_pkt_seg_lengths[i] ? - rx_pkt_seg_lengths[i] : - mbuf_data_size[mp_n]; - rx_seg->offset = i < rx_pkt_nb_offs ? - rx_pkt_seg_offsets[i] : 0; - rx_seg->mp = mpx ? mpx : mp; + if (rxseg_mode == RTE_ETH_RXSEG_MODE_SPLIT) { + /** + * On Segment length zero, update length as, + * buffer size - headroom size + * to make sure enough space is accomidate for header. + */ + rx_split->length = rx_pkt_seg_lengths[i] ? + rx_pkt_seg_lengths[i] : + mbuf_data_size[mp_n] - RTE_PKTMBUF_HEADROOM; + rx_split->offset = i < rx_pkt_nb_offs ? + rx_pkt_seg_offsets[i] : 0; + rx_split->mp = mpx ? mpx : mp; + } else if (rxseg_mode == RTE_ETH_RXSEG_MODE_SORT) { + rx_sort->length = rx_pkt_seg_lengths[i] ? + rx_pkt_seg_lengths[i] : + mbuf_data_size[mp_n] - RTE_PKTMBUF_HEADROOM; + rx_sort->mp = mpx ? mpx : mp; + } } rx_conf->rx_nseg = rx_pkt_nb_segs; rx_conf->rx_seg = rx_useg; + rx_conf->mode_flag = (enum rte_eth_rxseg_mode)rxseg_mode; ret = rte_eth_rx_queue_setup(port_id, rx_queue_id, nb_rx_desc, socket_id, rx_conf, NULL); rx_conf->rx_seg = NULL; diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index fb2f5195d3..0dcb3abf01 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -621,6 +621,8 @@ extern struct rte_ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */ extern uint32_t burst_tx_retry_num; /**< Burst tx retry number for mac-retry. */ +extern uint8_t rxseg_mode; + #ifdef RTE_LIB_GRO #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32 #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \ diff --git a/app/test-pmd/util.c b/app/test-pmd/util.c index fd98e8b51d..f9df5f69ef 100644 --- a/app/test-pmd/util.c +++ b/app/test-pmd/util.c @@ -150,8 +150,8 @@ dump_pkt_burst(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[], print_ether_addr(" - dst=", ð_hdr->dst_addr, print_buf, buf_size, &cur_len); MKDUMPSTR(print_buf, buf_size, cur_len, - " - type=0x%04x - length=%u - nb_segs=%d", - eth_type, (unsigned int) mb->pkt_len, + " - pool=%s - type=0x%04x - length=%u - nb_segs=%d", + mb->pool->name, eth_type, (unsigned int) mb->pkt_len, (int)mb->nb_segs); ol_flags = mb->ol_flags; if (ol_flags & RTE_MBUF_F_RX_RSS_HASH) { From patchwork Fri Aug 12 17:24:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanumanth Pothula X-Patchwork-Id: 114931 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 17DC7A0543; Fri, 12 Aug 2022 19:27:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 041F9410D2; Fri, 12 Aug 2022 19:27:52 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id CAF5342BC0 for ; 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Fri, 12 Aug 2022 10:25:45 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 12 Aug 2022 10:25:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 12 Aug 2022 10:25:43 -0700 Received: from localhost.localdomain (unknown [10.28.36.155]) by maili.marvell.com (Postfix) with ESMTP id 44F925B6934; Fri, 12 Aug 2022 10:25:36 -0700 (PDT) From: Hanumanth Pothula To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , , , , , , , , , , , , Hanumanth Pothula Subject: [PATCH v2 3/3] net/cnxk: introduce pool sort capability Date: Fri, 12 Aug 2022 22:54:51 +0530 Message-ID: <20220812172451.1208933-3-hpothula@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220812172451.1208933-1-hpothula@marvell.com> References: <20220812104648.1019978-1-hpothula@marvell.com> <20220812172451.1208933-1-hpothula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: IoFiNnD8WzEl4O8AOCdqzED5sd_dGsjX X-Proofpoint-GUID: IoFiNnD8WzEl4O8AOCdqzED5sd_dGsjX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-12_10,2022-08-11_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Presently, HW is programmed only to receive packets from LPB pool. Making all packets received from LPB pool. But, CNXK HW supports two pools, - SPB -> packets with smaller size (less than 4K) - LPB -> packets with bigger size (greater than 4K) Patch enables pool sorting capability, pool is selected based on packet's length. So, basically, PMD programs HW for receiving packets from both SPB and LPB pools based on the packet's length. This is achieved by enabling rx buffer split offload, RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT. This allows the application to send more than one pool(in our case two) to the driver, with different segment(packet) lengths, which helps the driver to configure both pools based on segment lengths. This is often useful for saving the memory where the application can create a different pool to steer the specific size of the packet, thus enabling effective use of memory. Signed-off-by: Hanumanth Pothula --- doc/guides/nics/features/cnxk.ini | 1 + doc/guides/nics/features/cnxk_vec.ini | 1 + drivers/net/cnxk/cnxk_ethdev.c | 93 ++++++++++++++++++++++++--- drivers/net/cnxk/cnxk_ethdev.h | 4 +- drivers/net/cnxk/cnxk_ethdev_ops.c | 7 ++ 5 files changed, 96 insertions(+), 10 deletions(-) diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 1876fe86c7..e1584ed740 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +pool sort = Y Speed capabilities = Y Rx interrupt = Y Lock-free Tx queue = Y diff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini index 5d0976e6ce..a63d35aae7 100644 --- a/doc/guides/nics/features/cnxk_vec.ini +++ b/doc/guides/nics/features/cnxk_vec.ini @@ -4,6 +4,7 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +pool sort = Y Speed capabilities = Y Rx interrupt = Y Lock-free Tx queue = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 24182909f1..6bf04dde96 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -537,6 +537,64 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) plt_free(txq_sp); } +static int +cnxk_nix_process_rx_conf(const struct rte_eth_rxconf *rx_conf, + struct rte_mempool **lpb_pool, struct rte_mempool **spb_pool, + uint16_t *lpb_len, uint16_t *spb_len) +{ + struct rte_eth_rxseg_sort rx_seg0; + struct rte_eth_rxseg_sort rx_seg1; + const char *platform_ops; + struct rte_mempool_ops *ops; + + if (*lpb_pool || !rx_conf->rx_seg || rx_conf->rx_nseg != CNXK_NIX_NUM_POOLS_MAX || + !rx_conf->rx_seg[0].sort.mp || !rx_conf->rx_seg[1].sort.mp) { + plt_err("invalid arguments"); + return -EINVAL; + } + + rx_seg0 = rx_conf->rx_seg[0].sort; + rx_seg1 = rx_conf->rx_seg[1].sort; + + if (rx_seg0.length >= rx_seg0.mp->elt_size || rx_seg1.length >= rx_seg1.mp->elt_size) { + plt_err("mismatch in packet length & pool length seg0_len:%u pool0_len:%u"\ + "seg1_len:%u pool1_len:%u", rx_seg0.length, rx_seg0.mp->elt_size, + rx_seg1.length, rx_seg1.mp->elt_size); + return -EINVAL; + } + + if (rx_seg0.length > rx_seg1.length) { + *lpb_pool = rx_seg0.mp; + *spb_pool = rx_seg1.mp; + + *lpb_len = rx_seg0.length; + *spb_len = rx_seg1.length; + } else { + *lpb_pool = rx_seg1.mp; + *spb_pool = rx_seg0.mp; + + *lpb_len = rx_seg1.length; + *spb_len = rx_seg0.length; + } + + if ((*spb_pool)->pool_id == 0) { + plt_err("Invalid pool_id"); + return -EINVAL; + } + + platform_ops = rte_mbuf_platform_mempool_ops(); + ops = rte_mempool_get_ops((*spb_pool)->ops_index); + if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) { + plt_err("mempool ops should be of cnxk_npa type"); + return -EINVAL; + } + + plt_info("spb_pool:%s lpb_pool:%s lpb_len:%u spb_len:%u\n", (*spb_pool)->name, + (*lpb_pool)->name, *lpb_len, *spb_len); + + return 0; +} + int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, uint32_t nb_desc, uint16_t fp_rx_q_sz, @@ -553,6 +611,10 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, uint16_t first_skip; int rc = -EINVAL; size_t rxq_sz; + uint16_t lpb_len = 0; + uint16_t spb_len = 0; + struct rte_mempool *lpb_pool = mp; + struct rte_mempool *spb_pool = NULL; /* Sanity checks */ if (rx_conf->rx_deferred_start == 1) { @@ -560,15 +622,22 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, goto fail; } + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) { + rc = cnxk_nix_process_rx_conf(rx_conf, &lpb_pool, &spb_pool, + &lpb_len, &spb_len); + if (rc) + goto fail; + } + platform_ops = rte_mbuf_platform_mempool_ops(); /* This driver needs cnxk_npa mempool ops to work */ - ops = rte_mempool_get_ops(mp->ops_index); + ops = rte_mempool_get_ops(lpb_pool->ops_index); if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) { plt_err("mempool ops should be of cnxk_npa type"); goto fail; } - if (mp->pool_id == 0) { + if (lpb_pool->pool_id == 0) { plt_err("Invalid pool_id"); goto fail; } @@ -585,13 +654,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, /* Its a no-op when inline device is not used */ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY || dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) - roc_nix_inl_dev_xaq_realloc(mp->pool_id); + roc_nix_inl_dev_xaq_realloc(lpb_pool->pool_id); /* Increase CQ size to Aura size to avoid CQ overflow and * then CPT buffer leak. */ if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) - nb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc); + nb_desc = nix_inl_cq_sz_clamp_up(nix, lpb_pool, nb_desc); /* Setup ROC CQ */ cq = &dev->cqs[qid]; @@ -606,23 +675,29 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, /* Setup ROC RQ */ rq = &dev->rqs[qid]; rq->qid = qid; - rq->aura_handle = mp->pool_id; + rq->aura_handle = lpb_pool->pool_id; rq->flow_tag_width = 32; rq->sso_ena = false; /* Calculate first mbuf skip */ first_skip = (sizeof(struct rte_mbuf)); first_skip += RTE_PKTMBUF_HEADROOM; - first_skip += rte_pktmbuf_priv_size(mp); + first_skip += rte_pktmbuf_priv_size(lpb_pool); rq->first_skip = first_skip; rq->later_skip = sizeof(struct rte_mbuf); - rq->lpb_size = mp->elt_size; rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); + rq->lpb_size = lpb_len ? lpb_len : lpb_pool->elt_size; /* Enable Inline IPSec on RQ, will not be used for Poll mode */ if (roc_nix_inl_inb_is_enabled(nix)) rq->ipsech_ena = true; + if (spb_pool) { + rq->spb_ena = 1; + rq->spb_aura_handle = spb_pool->pool_id; + rq->spb_size = spb_len; + } + rc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started); if (rc) { plt_err("Failed to init roc rq for rq=%d, rc=%d", qid, rc); @@ -645,7 +720,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, /* Queue config should reflect global offloads */ rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads; rxq_sp->qconf.nb_desc = nb_desc; - rxq_sp->qconf.mp = mp; + rxq_sp->qconf.mp = lpb_pool; rxq_sp->tc = 0; rxq_sp->tx_pause = (dev->fc_cfg.mode == RTE_ETH_FC_FULL || dev->fc_cfg.mode == RTE_ETH_FC_TX_PAUSE); @@ -664,7 +739,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, goto free_mem; } - plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, mp->name, nb_desc, + plt_nix_dbg("rq=%d pool=%s nb_desc=%d->%d", qid, lpb_pool->name, nb_desc, cq->nb_desc); /* Store start of fast path area */ diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 4cb7c9e90c..d60515d50a 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -44,6 +44,8 @@ #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096 /* Max supported SQB count */ #define CNXK_NIX_TX_MAX_SQB 512 +/* LPB & SPB */ +#define CNXK_NIX_NUM_POOLS_MAX 2 /* If PTP is enabled additional SEND MEM DESC is required which * takes 2 words, hence max 7 iova address are possible @@ -83,7 +85,7 @@ RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER | \ RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH | \ RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \ - RTE_ETH_RX_OFFLOAD_SECURITY) + RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT | RTE_ETH_RX_OFFLOAD_SECURITY) #define RSS_IPV4_ENABLE \ (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \ diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 1592971073..6174a586be 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -69,6 +69,13 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + + devinfo->rx_seg_capa = (struct rte_eth_rxseg_capa){ + .mode_sort = 1, + .multi_pools = 1, + .max_npool = CNXK_NIX_NUM_POOLS_MAX, + }; + return 0; }