From patchwork Tue Aug 16 05:52:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115109 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 060DEA00C3; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDF2441155; Mon, 15 Aug 2022 23:57:33 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id A4B41410D3 for ; Mon, 15 Aug 2022 23:57:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600652; x=1692136652; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VgnNeQ0jjCXbeJQ6n9Hna6bGN8IVXKIITMTH0pzIo28=; b=VUM+6jqD8CWoEbsMva27eK/Pci6lWIbtrbZqsaIR108AwG2i68mnFA1X K8sr0bPn1t/L5iqgDJdeV+IOl/x5Xy2yP2tHBvGCRe3WgixvkZksXxQwX fF0Y0KmnMYmeu0Mw29hUm6KvHY0/x1UL4E0u2TqHOkOyjB1NyMFp2Ltax iSFl4RPUzRWQg2WZMj/fBvAm1lKbqoc5w7FKYPrzsBDH+UAvFhAlMwBUj W4Lzs3/KWhvsp85wfTxFSFKtv04LpMAVHeZfOVt19Snv3KnMTw8Bci3xe 7sZ567C1g+JD7VM4JoX6x4gncgY6AsQq/StKhdvaQiuaCU6XmriPpb3w4 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862702" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862702" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826016" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:31 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 01/33] baseband/acc100: update dev close function Date: Mon, 15 Aug 2022 22:52:26 -0700 Message-Id: <20220816055258.107564-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Free harq_layout and reset device pointers. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 7349bb5bad..8b13a96307 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -340,6 +340,8 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc100_device *d, int i = 0; uint32_t q_sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len(); uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues; + /* Free first in case this is a reconfiguration */ + rte_free(d->sw_rings_base); /* Find an aligned block of memory to store sw rings */ while (i < ACC100_SW_RING_MEM_ALLOC_ATTEMPTS) { @@ -768,7 +770,11 @@ acc100_dev_close(struct rte_bbdev *dev) rte_free(d->tail_ptrs); rte_free(d->info_ring); rte_free(d->sw_rings_base); + rte_free(d->harq_layout); d->sw_rings_base = NULL; + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->harq_layout = NULL; } /* Ensure all in flight HW transactions are completed */ usleep(ACC100_LONG_WAIT); @@ -4665,7 +4671,8 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc100_device *d, } printf("Number of 5GUL engines %d\n", numEngines); - rte_free(d->sw_rings_base); + if (d->sw_rings_base != NULL) + rte_free(d->sw_rings_base); usleep(ACC100_LONG_WAIT); } From patchwork Tue Aug 16 05:52:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115110 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CDF42A00C3; Mon, 15 Aug 2022 23:57:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B980F427EB; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 468AF410D3 for ; Mon, 15 Aug 2022 23:57:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600653; x=1692136653; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SptOaxJDL4DE9GKwoDebSnfhYWFipGKGTzl3APfly80=; b=UbmL2BFj+cyIYihmY1GXFUB3ms47zQQj2zq/l+XCoebtE+E8Dfts1QVV wLgLT+BlUl0CNMROObvV2S3l23w0Ds3LAzoMhHORYfAgQ5+RGmLUwcnKA PPojP4xVJegG8c0lK1DHfmiIkP4pAmtvzq/RKCj/RbvxTjNBgsAeFbFKf clX101YeSIgcFAR/UO3Vcv7R9ZZXbN9Hu0bm2oDBlQnzhbRSksb1J3GtO 2QUy4dds6V7lZojpgWHCNWySErMCPFis1Yz2Fvy7pQIgBiSCq75kYpnFZ Sx2OhhRYxIIRkQXIo3pEa8lgxM9XsU+1pwjqZuD8MO8hg75JMjyryAt0w w==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862703" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862703" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826020" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:31 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 02/33] baseband/acc100: quit queue setup for undef dev Date: Mon, 15 Aug 2022 22:52:27 -0700 Message-Id: <20220816055258.107564-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move check for undefined device before allocating queue data structure. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 8b13a96307..b7daef3d84 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -831,6 +831,10 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, struct acc100_queue *q; int16_t q_idx; + if (d == NULL) { + rte_bbdev_log(ERR, "Undefined device"); + return -ENODEV; + } /* Allocate the queue data structure. */ q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q), RTE_CACHE_LINE_SIZE, conf->socket); @@ -838,10 +842,6 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, rte_bbdev_log(ERR, "Failed to allocate queue memory"); return -ENOMEM; } - if (d == NULL) { - rte_bbdev_log(ERR, "Undefined device"); - return -ENODEV; - } q->d = d; q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); From patchwork Tue Aug 16 05:52:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115111 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4AEFDA00C3; Mon, 15 Aug 2022 23:57:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87B7C427F6; Mon, 15 Aug 2022 23:57:37 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id BBBDB410EA for ; Mon, 15 Aug 2022 23:57:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600653; x=1692136653; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FPa3CnxWHZeyGlrvaQtER4A5HMbPsQZH7v4EOOErzTs=; b=WUsRNts05AMvxHeqv4lG5pFM3L1x564az54nzI6xb4JJNkSc23uPOBrB kyJLomwO9TLDxxECoGs3Wn9/Y2dlkla46uzH93RrWxNw4UEhr9/piFL5X oS+4ZQOf6HMWtecqpKhupcr6ER21ic9gwPuZ+JEYgBQx+rRoA0lguf5pr xhwKsJb1j9DCTZzRRJ1XA2iIIXOh1Vv78NOZvXwzFx43UZxPyMrVfvJxS 1py6J4mGWQNfzuyHnNyuEaTElWUah6YnnnkxkSqTnUrEe1sNE2YevPBQJ e4MT5rHj9DZrvoIHYyIf+I4BcS2bR5ZXi88USYIMcCJoUzZj8KniibMox Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862704" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862704" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826023" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 03/33] baseband/acc100: add default e value for FCW Date: Mon, 15 Aug 2022 22:52:28 -0700 Message-Id: <20220816055258.107564-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update frame control word LDPC encoder fill function to take a default e value as a parameter. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index b7daef3d84..a07692faa9 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1271,7 +1271,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index) /* Fill in a frame control word for LDPC encoding. */ static inline void acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op, - struct acc100_fcw_le *fcw, int num_cb) + struct acc100_fcw_le *fcw, int num_cb, uint32_t default_e) { fcw->qm = op->ldpc_enc.q_m; fcw->nfiller = op->ldpc_enc.n_filler; @@ -1280,7 +1280,7 @@ acc100_fcw_le_fill(const struct rte_bbdev_enc_op *op, fcw->ncb = op->ldpc_enc.n_cb; fcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_enc.basegraph, op->ldpc_enc.rv_index); - fcw->rm_e = op->ldpc_enc.cb_params.e; + fcw->rm_e = (default_e == 0) ? op->ldpc_enc.cb_params.e : default_e; fcw->crc_select = check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH); fcw->bypass_intlv = check_bit(op->ldpc_enc.op_flags, @@ -2528,7 +2528,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; - acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num); + acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0); /** This could be done at polling */ acc100_header_init(&desc->req); @@ -2590,7 +2590,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; - acc100_fcw_le_fill(op, &desc->req.fcw_le, 1); + acc100_fcw_le_fill(op, &desc->req.fcw_le, 1, 0); input = op->ldpc_enc.input.data; output_head = output = op->ldpc_enc.output.data; From patchwork Tue Aug 16 05:52:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115112 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE6EFA00C3; Mon, 15 Aug 2022 23:57:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 57D634280E; Mon, 15 Aug 2022 23:57:38 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id E0948410D3 for ; Mon, 15 Aug 2022 23:57:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600654; x=1692136654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XTYjQEUm5MpVPBG2OWNuyF3F2Td/SZPA5/XFp+fIses=; b=XvOAWxjwDMicWUTJPDQfoW81/6gAzMw2zsFQXgCo3yOTaTUvFLIjK7u2 ftGxGFur+RGA2AJvEFY3byEmN78A+23yPt2EL1KS9++5SlaSFT4b7ncZh szZEHZ6x7UETL+DlhGd55d3Ak7QIMPIOL4r4efa0VA113WvqEbJvXKtXx iq13+jio37sutm4TaRTQtxKy0fFuk/6lFZjxP9PXhy/AIEFTj9hPlr4ze gdisHML7aHrZOZCD6qRJbwjx13Nr4edaa8GiitmldKvDjJv/DonoOg7dK Sjx6K1MvH/BeW9bvcGHBCRk+lLcx53+ye5tPN7FQj+ZlsP6SZh/9cOXV5 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862705" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862705" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826026" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 04/33] baseband/acc100: add LDPC encoder padding function Date: Mon, 15 Aug 2022 22:52:29 -0700 Message-Id: <20220816055258.107564-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LDPC Encoder input may need to be padded to avoid small beat for ACC100. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index a07692faa9..4f96b595eb 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1307,7 +1307,6 @@ acc100_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_td *fcw) RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } -#ifdef RTE_LIBRTE_BBDEV_DEBUG static inline bool is_acc100(struct acc100_queue *q) @@ -1320,7 +1319,6 @@ validate_op_required(struct acc100_queue *q) { return is_acc100(q); } -#endif /* Fill in a frame control word for LDPC decoding. */ static inline void @@ -1776,12 +1774,24 @@ acc100_dma_desc_te_fill(struct rte_bbdev_enc_op *op, return 0; } +/* May need to pad LDPC Encoder input to avoid small beat for ACC100 */ +static inline uint16_t +pad_le_in(uint16_t blen, struct acc100_queue *q) +{ + if (!is_acc100(q)) + return blen; + uint16_t last_beat = blen % 64; + if ((last_beat > 0) && (last_beat <= 8)) + blen += 8; + return blen; +} + static inline int acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, struct acc100_dma_req_desc *desc, struct rte_mbuf **input, struct rte_mbuf *output, uint32_t *in_offset, uint32_t *out_offset, uint32_t *out_length, - uint32_t *mbuf_total_left, uint32_t *seg_total_left) + uint32_t *mbuf_total_left, uint32_t *seg_total_left, struct acc100_queue *q) { int next_triplet = 1; /* FCW already done */ uint16_t K, in_length_in_bits, in_length_in_bytes; @@ -1805,8 +1815,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - in_length_in_bytes, - seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -2534,7 +2543,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, acc100_header_init(&desc->req); desc->req.numCBs = num; - in_length_in_bytes = ops[0]->ldpc_enc.input.data->data_len; + in_length_in_bytes = pad_le_in(ops[0]->ldpc_enc.input.data->data_len, q); out_length = (enc->cb_params.e + 7) >> 3; desc->req.m2dlen = 1 + num; desc->req.d2mlen = num; @@ -2603,7 +2612,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, ret = acc100_dma_desc_le_fill(op, &desc->req, &input, output, &in_offset, &out_offset, &out_length, &mbuf_total_left, - &seg_total_left); + &seg_total_left, q); if (unlikely(ret < 0)) return ret; From patchwork Tue Aug 16 05:52:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115113 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C12D8A00C3; Mon, 15 Aug 2022 23:57:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2B6C742825; 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15 Aug 2022 14:57:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826030" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 05/33] baseband/acc100: add scatter-gather support Date: Mon, 15 Aug 2022 22:52:30 -0700 Message-Id: <20220816055258.107564-6-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add flag to support scatter-gather for the mbuf Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 45 ++++++++++++++++-------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 4f96b595eb..31d6ad422a 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1588,6 +1588,8 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, * Store information about device capabilities * @param next_triplet * Index for ACC100 DMA Descriptor triplet + * @param scattergather + * Flag to support scatter-gather for the mbuf * * @return * Returns index of next triplet on success, other value if lengths of @@ -1597,12 +1599,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, static inline int acc100_dma_fill_blk_type_in(struct acc100_dma_req_desc *desc, struct rte_mbuf **input, uint32_t *offset, uint32_t cb_len, - uint32_t *seg_total_left, int next_triplet) + uint32_t *seg_total_left, int next_triplet, + bool scattergather) { uint32_t part_len; struct rte_mbuf *m = *input; - part_len = (*seg_total_left < cb_len) ? *seg_total_left : cb_len; + if (scattergather) + part_len = (*seg_total_left < cb_len) ? + *seg_total_left : cb_len; + else + part_len = cb_len; cb_len -= part_len; *seg_total_left -= part_len; @@ -1738,7 +1745,9 @@ acc100_dma_desc_te_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - length, seg_total_left, next_triplet); + length, seg_total_left, next_triplet, + check_bit(op->turbo_enc.op_flags, + RTE_BBDEV_TURBO_ENC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -1815,7 +1824,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet, false); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -1903,7 +1912,9 @@ acc100_dma_desc_td_fill(struct rte_bbdev_dec_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, kw, - seg_total_left, next_triplet); + seg_total_left, next_triplet, + check_bit(op->turbo_dec.op_flags, + RTE_BBDEV_TURBO_DEC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -2005,7 +2016,9 @@ acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, input_length, - seg_total_left, next_triplet); + seg_total_left, next_triplet, + check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, @@ -3145,8 +3158,9 @@ enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, fcw = &desc->req.fcw_ld; q->d->fcw_ld_fill(op, fcw, harq_layout); - /* Special handling when overusing mbuf */ - if (fcw->rm_e < ACC100_MAX_E_MBUF) + /* Special handling when using mbuf or not */ + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)) seg_total_left = rte_pktmbuf_data_len(input) - in_offset; else @@ -3222,9 +3236,12 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, r = op->ldpc_dec.tb_params.r; while (mbuf_total_left > 0 && r < c) { - - seg_total_left = rte_pktmbuf_data_len(input) - in_offset; - + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)) + seg_total_left = rte_pktmbuf_data_len(input) + - in_offset; + else + seg_total_left = op->ldpc_dec.input.length; /* Set up DMA descriptor */ desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); @@ -3249,8 +3266,9 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, sizeof(desc->req.fcw_td) - 8); rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); #endif - - if (seg_total_left == 0) { + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER) + && (seg_total_left == 0)) { /* Go to the next mbuf */ input = input->next; in_offset = 0; @@ -3261,7 +3279,6 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, current_enqueued_cbs++; r++; } - #ifdef RTE_LIBRTE_BBDEV_DEBUG if (check_mbuf_total_left(mbuf_total_left) != 0) return -EINVAL; From patchwork Tue Aug 16 05:52:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115114 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6A737A00C3; Mon, 15 Aug 2022 23:58:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 208C84282B; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 85CD9410D3 for ; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600654; 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15 Aug 2022 14:57:32 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 06/33] baseband/acc100: add HARQ index helper function Date: Mon, 15 Aug 2022 22:52:31 -0700 Message-Id: <20220816055258.107564-7-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor code to use the HARQ index helper function and make harq_idx uint32. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 32 +++++++++++------------- 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 31d6ad422a..97e4078a24 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1307,6 +1307,11 @@ acc100_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_td *fcw) RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } +/* Convert offset to harq index for harq_layout structure */ +static inline uint32_t hq_index(uint32_t offset) +{ + return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK; +} static inline bool is_acc100(struct acc100_queue *q) @@ -1326,7 +1331,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, union acc100_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; - uint16_t harq_index; + uint32_t harq_index; uint32_t l; bool harq_prun = false; @@ -1365,8 +1370,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); - harq_index = op->ldpc_dec.harq_combined_output.offset / - ACC100_HARQ_OFFSET; + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ harq_prun = ((op->ldpc_dec.harq_combined_output.offset % @@ -1446,12 +1450,6 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, } } -/* Convert offset to harq index for harq_layout structure */ -static inline uint32_t hq_index(uint32_t offset) -{ - return (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK; -} - /* Fill in a frame control word for LDPC decoding for ACC101 */ static inline void acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, @@ -2135,12 +2133,11 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, struct rte_bbdev_dec_op *prev_op = desc->op_addr; op->ldpc_dec.harq_combined_output.length = prev_op->ldpc_dec.harq_combined_output.length; - int16_t hq_idx = op->ldpc_dec.harq_combined_output.offset / - ACC100_HARQ_OFFSET; - int16_t prev_hq_idx = - prev_op->ldpc_dec.harq_combined_output.offset - / ACC100_HARQ_OFFSET; - harq_layout[hq_idx].val = harq_layout[prev_hq_idx].val; + uint32_t harq_idx = hq_index( + op->ldpc_dec.harq_combined_output.offset); + uint32_t prev_harq_idx = hq_index( + prev_op->ldpc_dec.harq_combined_output.offset); + harq_layout[harq_idx].val = harq_layout[prev_harq_idx].val; #ifndef ACC100_EXT_MEM struct rte_bbdev_op_data ho = op->ldpc_dec.harq_combined_output; @@ -2972,10 +2969,9 @@ harq_loopback(struct acc100_queue *q, struct rte_bbdev_dec_op *op, bool ddr_mem_in = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE); union acc100_harq_layout_data *harq_layout = q->d->harq_layout; - uint16_t harq_index = (ddr_mem_in ? + uint32_t harq_index = hq_index(ddr_mem_in ? op->ldpc_dec.harq_combined_input.offset : - op->ldpc_dec.harq_combined_output.offset) - / ACC100_HARQ_OFFSET; + op->ldpc_dec.harq_combined_output.offset); uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); From patchwork Tue Aug 16 05:52:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115115 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E29A9A00C3; Mon, 15 Aug 2022 23:58:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F2F2342B6D; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id D2F22427F0 for ; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600655; x=1692136655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pYFOrOtbYC/cHtu+I4NTp6AQY5Jb8bYV9qnyul+d9Z0=; b=InWqWk5RXNCzxlGfz3EMqAaVoj9ZfbSozQ2odxqP2gyf/lAQUFv/u9dv v1eDhNm2OC0rTzIH+mCZejecjxKniIwEaqak9nrGha54HOQ74pX21Rjn3 hmqxUlm1zety17Gn/yu2kXUb2oHh22XHHCeQoLUfqvze6qdLEnFPmNPro 0I+Tq59oeSEOa23axDKWIUekW+EOy1J1ImMGALObm20yEae1fvj8tbnX/ sHOfC/DgeTy21tvW32mWdYkXaxQ8Zui1+Rg9dOKdZv99GRe3w6EdaC0yk aq7zGIT1GXRCNUcphLqWKqHesTizYjyTbKvv4iK/62ipHZukyBcnDMnsy Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862711" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862711" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826036" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:33 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 07/33] baseband/acc100: avoid mux for small inbound frames Date: Mon, 15 Aug 2022 22:52:32 -0700 Message-Id: <20220816055258.107564-8-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update check_mux to avoid multiplexing small inbound frames. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 97e4078a24..fbd6605802 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3551,20 +3551,25 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, } /* Check we can mux encode operations with common FCW */ -static inline bool +static inline int16_t check_mux(struct rte_bbdev_enc_op **ops, uint16_t num) { uint16_t i; if (num <= 1) - return false; + return 1; for (i = 1; i < num; ++i) { /* Only mux compatible code blocks */ if (memcmp((uint8_t *)(&ops[i]->ldpc_enc) + ACC100_ENC_OFFSET, (uint8_t *)(&ops[0]->ldpc_enc) + ACC100_ENC_OFFSET, ACC100_CMP_ENC_SIZE) != 0) - return false; + return i; } - return true; + /* Avoid multiplexing small inbound size frames */ + int Kp = (ops[0]->ldpc_enc.basegraph == 1 ? 22 : 10) * + ops[0]->ldpc_enc.z_c - ops[0]->ldpc_enc.n_filler; + if (Kp <= ACC100_LIMIT_DL_MUX_BITS) + return 1; + return num; } /** Enqueue encode operations for ACC100 device in CB mode. */ @@ -3586,7 +3591,8 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, } avail--; enq = RTE_MIN(left, ACC100_MUX_5GDL_DESC); - if (check_mux(&ops[i], enq)) { + enq = check_mux(&ops[i], enq); + if (enq > 1) { ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i], desc_idx, enq); if (ret < 0) { From patchwork Tue Aug 16 05:52:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115116 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7BD3A00C3; Mon, 15 Aug 2022 23:58:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C2BFC42B71; Mon, 15 Aug 2022 23:57:41 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 02952415D7 for ; Mon, 15 Aug 2022 23:57:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600655; x=1692136655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yNYCIiFzNpleixAQV22k2KvzGCHv1v+jy8rCuLOQyCc=; b=HBLz2FQYuVLopaiUlQqOrt+RnUHbUoenpF4zOKVbwek+CVmtUp2ogRva 3oPa2v+zPVd0prPwmSpA2YUZXxRqaixPWyVWYQbOMB53PK+xYM9V/bbqY qNmWisq7ak/BvkRo7X0xQlaM41uG4ykEp5fMxFrs8bk8trFQWTJ9/i4fs 6gX+xNdiGwNv1hczhWmruU7oCZEgUadDL6HJG6hiuMd3m1z7esFLYDUnC SPFVm3cVlfAn0GMLU3J6s7A98XXVl12SeDm0QW1cyJmhaYTL7FbopZGph iSExVHlaUqbNmvC55zZhIt5nlEHLGFPvt2FxqF8XWY/Hsy1/jqcWHAJaI g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862712" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862712" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826040" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:33 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 08/33] baseband/acc100: separate validation functions from debug Date: Mon, 15 Aug 2022 22:52:33 -0700 Message-Id: <20220816055258.107564-9-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use new flag RTE_LIBRTE_BBDEV_SKIP_VALIDATE enable/disable validation functions. The validation API will be enabled by default. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 37 ++++++++++++------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index fbd6605802..6c6e3e1072 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2225,7 +2225,8 @@ acc100_dma_enqueue(struct acc100_queue *q, uint16_t n, } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE + /* Validates turbo encoder parameters */ static inline int validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) @@ -2482,10 +2483,10 @@ enqueue_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, seg_total_left; struct rte_mbuf *input, *output_head, *output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo encoder validation failed"); + rte_bbdev_log(ERR, "Turbo encoder validation rejected"); return -EINVAL; } #endif @@ -2536,10 +2537,10 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, uint16_t in_length_in_bytes; struct rte_bbdev_op_ldpc_enc *enc = &ops[0]->ldpc_enc; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_enc_op(ops[0], q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -2598,10 +2599,10 @@ enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, seg_total_left; struct rte_mbuf *input, *output_head, *output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG /* Validate op structure */ +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -2655,10 +2656,10 @@ enqueue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, struct rte_mbuf *input, *output_head, *output; uint16_t current_enqueued_cbs = 0; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo encoder validation failed"); + rte_bbdev_log(ERR, "Turbo encoder validation rejected"); return -EINVAL; } #endif @@ -2727,7 +2728,7 @@ enqueue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) @@ -2878,10 +2879,10 @@ enqueue_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *input, *h_output_head, *h_output, *s_output_head, *s_output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo decoder validation failed"); + rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; } #endif @@ -3102,10 +3103,10 @@ enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, return ret; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC decoder validation failed"); + rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } #endif @@ -3207,10 +3208,10 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *input, *h_output_head, *h_output; uint16_t current_enqueued_cbs = 0; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC decoder validation failed"); + rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } #endif @@ -3300,10 +3301,10 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, *s_output_head, *s_output; uint16_t current_enqueued_cbs = 0; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo decoder validation failed"); + rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; } #endif From patchwork Tue Aug 16 05:52:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115117 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 427E2A00C3; Mon, 15 Aug 2022 23:58:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A3E8C42B78; Mon, 15 Aug 2022 23:57:42 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 29BC1427F2 for ; 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d="scan'208";a="666826043" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:34 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 09/33] baseband/acc100: add LDPC transport block support Date: Mon, 15 Aug 2022 22:52:34 -0700 Message-Id: <20220816055258.107564-10-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add LDPC enqueue functions to handle transport blocks. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 1 + drivers/baseband/acc100/rte_acc100_pmd.c | 197 ++++++++++++++++++++++- 2 files changed, 196 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 0c9810ca56..19a1f434bc 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -135,6 +135,7 @@ #define ACC100_DEC_OFFSET (80) #define ACC100_EXT_MEM /* Default option with memory external to CPU */ #define ACC100_HARQ_OFFSET_THRESHOLD 1024 +#define ACC100_LIMIT_DL_MUX_BITS 534 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 6c6e3e1072..b0f41f15cb 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2588,6 +2588,61 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, return num; } +/* Enqueue one encode operations for ACC100 device for a partial TB + * all codes blocks have same configuration multiplexed on the same descriptor + */ +static inline void +enqueue_ldpc_enc_part_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, + uint16_t total_enqueued_descs, int16_t num_cbs, uint32_t e, + uint16_t in_len_B, uint32_t out_len_B, uint32_t *in_offset, + uint32_t *out_offset) +{ + + union acc100_dma_desc *desc = NULL; + struct rte_mbuf *output_head, *output; + int i, next_triplet; + struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; + + + uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + acc100_fcw_le_fill(op, &desc->req.fcw_le, num_cbs, e); + + /** This could be done at polling */ + acc100_header_init(&desc->req); + desc->req.numCBs = num_cbs; + + desc->req.m2dlen = 1 + num_cbs; + desc->req.d2mlen = num_cbs; + next_triplet = 1; + + for (i = 0; i < num_cbs; i++) { + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset(enc->input.data, + *in_offset); + *in_offset += in_len_B; + desc->req.data_ptrs[next_triplet].blen = in_len_B; + next_triplet++; + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset( + enc->output.data, *out_offset); + *out_offset += out_len_B; + desc->req.data_ptrs[next_triplet].blen = out_len_B; + next_triplet++; + enc->output.length += out_len_B; + output_head = output = enc->output.data; + mbuf_append(output_head, output, out_len_B); + } + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + rte_memdump(stderr, "FCW", &desc->req.fcw_le, + sizeof(desc->req.fcw_le) - 8); + rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); +#endif + +} + /* Enqueue one encode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, @@ -2728,6 +2783,76 @@ enqueue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } +/* Enqueue one encode operations for ACC100 device in TB mode. + * returns the number of descs used + */ +static inline int +enqueue_ldpc_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, + uint16_t enq_descs, uint8_t cbs_in_tb) +{ +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE + if (validate_ldpc_enc_op(op, q) == -1) { + rte_bbdev_log(ERR, "LDPC encoder validation failed"); + return -EINVAL; + } +#endif + uint8_t num_a, num_b; + uint16_t desc_idx; + uint8_t r = op->ldpc_enc.tb_params.r; + uint8_t cab = op->ldpc_enc.tb_params.cab; + union acc100_dma_desc *desc; + uint16_t init_enq_descs = enq_descs; + uint16_t input_len_B = ((op->ldpc_enc.basegraph == 1 ? 22 : 10) * + op->ldpc_enc.z_c - op->ldpc_enc.n_filler) >> 3; + if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + input_len_B -= 3; + + if (r < cab) { + num_a = cab - r; + num_b = cbs_in_tb - cab; + } else { + num_a = 0; + num_b = cbs_in_tb - r; + } + uint32_t in_offset = 0, out_offset = 0; + + while (num_a > 0) { + uint32_t e = op->ldpc_enc.tb_params.ea; + uint32_t out_len_B = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_a, ACC100_MUX_5GDL_DESC); + num_a -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_B, &in_offset, &out_offset); + enq_descs++; + } + while (num_b > 0) { + uint32_t e = op->ldpc_enc.tb_params.eb; + uint32_t out_len_B = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_b, ACC100_MUX_5GDL_DESC); + num_b -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_B, &in_offset, &out_offset); + enq_descs++; + } + + uint16_t return_descs = enq_descs - init_enq_descs; + /* Keep total number of CBs in first TB */ + desc_idx = ((q->sw_ring_head + init_enq_descs) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.cbs_in_tb = return_descs; /** Actual number of descriptors */ + desc->req.op_addr = op; + + /* Set SDone on last CB descriptor for TB mode. */ + desc_idx = ((q->sw_ring_head + enq_descs - 1) + & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.sdone_enable = 1; + desc->req.irq_enable = q->irq_enable; + desc->req.op_addr = op; + return return_descs; +} + #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int @@ -3302,7 +3427,10 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, uint16_t current_enqueued_cbs = 0; #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE - /* Validate op structure */ + if (cbs_in_tb == 0) { + rte_bbdev_log(ERR, "Turbo decoder invalid number of CBs"); + return -EINVAL; + } if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; @@ -3389,6 +3517,32 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, return current_enqueued_cbs; } +/* Calculates number of CBs in processed encoder TB based on 'r' and input + * length. + */ +static inline uint8_t +get_num_cbs_in_tb_ldpc_enc(struct rte_bbdev_op_ldpc_enc *ldpc_enc) +{ + uint8_t c, r, crc24_bits = 0; + uint16_t k = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c + - ldpc_enc->n_filler; + uint8_t cbs_in_tb = 0; + int32_t length; + + length = ldpc_enc->input.length; + r = ldpc_enc->tb_params.r; + c = ldpc_enc->tb_params.c; + crc24_bits = 0; + if (check_bit(ldpc_enc->op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + crc24_bits = 24; + while (length > 0 && r < c) { + length -= (k - crc24_bits) >> 3; + r++; + cbs_in_tb++; + } + return cbs_in_tb; +} + /* Calculates number of CBs in processed encoder TB based on 'r' and input * length. */ @@ -3670,6 +3824,45 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, return i; } +/* Enqueue LDPC encode operations for ACC100 device in TB mode. */ +static uint16_t +acc100_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t num) +{ + struct acc100_queue *q = q_data->queue_private; + int32_t avail = acc100_ring_avail_enq(q); + uint16_t i, enqueued_descs = 0; + uint8_t cbs_in_tb; + int descs_used; + + for (i = 0; i < num; ++i) { + cbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc); + /* Check if there are available space for further processing */ + if (unlikely(avail - cbs_in_tb < 0)) { + acc100_enqueue_ring_full(q_data); + break; + } + descs_used = enqueue_ldpc_enc_one_op_tb(q, ops[i], + enqueued_descs, cbs_in_tb); + if (descs_used < 0) { + acc100_enqueue_invalid(q_data); + break; + } + enqueued_descs += descs_used; + avail -= descs_used; + } + if (unlikely(enqueued_descs == 0)) + return 0; /* Nothing to enqueue */ + + acc100_dma_enqueue(q, enqueued_descs, &q_data->queue_stats); + + /* Update stats */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + + return i; +} + /* Check room in AQ for the enqueues batches into Qmgr */ static int32_t acc100_aq_avail(struct rte_bbdev_queue_data *q_data, uint16_t num_ops) @@ -3707,7 +3900,7 @@ acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - return acc100_enqueue_enc_tb(q_data, ops, num); + return acc100_enqueue_ldpc_enc_tb(q_data, ops, num); else return acc100_enqueue_ldpc_enc_cb(q_data, ops, num); } From patchwork Tue Aug 16 05:52:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115118 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C137A00C3; Mon, 15 Aug 2022 23:58:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 79B6142B80; Mon, 15 Aug 2022 23:57:43 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 746A2427F3 for ; Mon, 15 Aug 2022 23:57:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600655; x=1692136655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mpsyiwpcktMejjY6dEjDWWRjeC97tvehpNrjF1bl2VU=; b=e5VPlIv8SUoglyw/HEO4cUVlywVmEh/OOs1AuLxpJSc9u7EFPbP0l+wY RJMLEx8Ix25rnEWT5hMETet63u4V06atawAZrw4it+Nsb76UK7uAaSKUs ZaxOrEhtiAktpg9df+PjoeZ0mlpxAKNHDoO9XRK9iA9ivG6/FsTvX2LGg nwmSEnkky6KJVQb/Njp4+4zzjeV/rZ3Celeiw0l0I9APDgQ1Gv96xFBFf gnO/zCtQLnPeeWmyJXOW9k+xQYdMbf9DVAwHeVcOySOg6I2fUXlM+cOIX GwHt7mQvh5q7kdKisw8mUk7JxCjDGSDU/uQPlDtl7TUYiNbQtNlhBu8jJ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862714" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862714" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826046" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:34 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 10/33] baseband/acc10x: limit cases for HARQ pruning Date: Mon, 15 Aug 2022 22:52:35 -0700 Message-Id: <20220816055258.107564-11-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add flag ACC101_HARQ_PRUNING_OPTIMIZATION to limit cases when HARQ pruning is valid. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 52 +++++++++++++++++++----- 1 file changed, 41 insertions(+), 11 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index b0f41f15cb..6c639698db 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1373,17 +1373,23 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ +#ifdef ACC100_HARQ_PRUNING_OPTIMIZATION harq_prun = ((op->ldpc_dec.harq_combined_output.offset % - ACC100_HARQ_OFFSET) == 0) && - (op->ldpc_dec.harq_combined_output.offset <= UINT16_MAX - * ACC100_HARQ_OFFSET); + ACC100_HARQ_OFFSET) == 0); +#endif #endif if (fcw->hcin_en > 0) { harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) harq_in_length = harq_in_length * 8 / 6; - harq_in_length = RTE_ALIGN(harq_in_length, 64); - if ((harq_layout[harq_index].offset > 0) & harq_prun) { + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64); + /* Stronger alignment requirement when in decompression mode */ + if (fcw->hcin_decomp_mode > 0) + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 256); + if ((harq_layout[harq_index].offset > 0) && harq_prun) { rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); fcw->hcin_size0 = harq_layout[harq_index].size0; fcw->hcin_offset = harq_layout[harq_index].offset; @@ -1458,6 +1464,7 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; uint32_t harq_index; uint32_t l; + bool harq_prun = false; fcw->qm = op->ldpc_dec.q_m; fcw->nfiller = op->ldpc_dec.n_filler; @@ -1503,6 +1510,13 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); + #ifdef ACC100_EXT_MEM + /* Limit cases when HARQ pruning is valid */ +#ifdef ACC101_HARQ_PRUNING_OPTIMIZATION + harq_prun = ((op->ldpc_dec.harq_combined_output.offset % + ACC101_HARQ_OFFSET) == 0); +#endif +#endif if (fcw->hcin_en > 0) { harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) @@ -1511,9 +1525,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, - op->ldpc_dec.n_filler); /* Alignment on next 64B - Already enforced from HC output */ harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64); - fcw->hcin_size0 = harq_in_length; - fcw->hcin_offset = 0; - fcw->hcin_size1 = 0; + if ((harq_layout[harq_index].offset > 0) && harq_prun) { + rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); + fcw->hcin_size0 = harq_layout[harq_index].size0; + fcw->hcin_offset = harq_layout[harq_index].offset; + fcw->hcin_size1 = harq_in_length - + harq_layout[harq_index].offset; + } else { + fcw->hcin_size0 = harq_in_length; + fcw->hcin_offset = 0; + fcw->hcin_size1 = 0; + } } else { fcw->hcin_size0 = 0; fcw->hcin_offset = 0; @@ -1554,9 +1576,17 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, harq_out_length = RTE_MIN(harq_out_length, ncb_p); /* Alignment on next 64B */ harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); - fcw->hcout_size0 = harq_out_length; - fcw->hcout_size1 = 0; - fcw->hcout_offset = 0; + if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && + harq_prun) { + fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; + fcw->hcout_offset = k0_p & 0xFFC0; + fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; + } else { + fcw->hcout_size0 = harq_out_length; + fcw->hcout_size1 = 0; + fcw->hcout_offset = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { From patchwork Tue Aug 16 05:52:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115119 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7FFDA00C3; Mon, 15 Aug 2022 23:58:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 606F842B89; Mon, 15 Aug 2022 23:57:44 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 9A0A2415D7 for ; Mon, 15 Aug 2022 23:57:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600655; x=1692136655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pOwILnK3wgmZ81EVrKIBpc/zONvEknwxaVvGJRZIgGU=; b=Au/ESjTelTnBENGHPIWD2kbULij9rQXzfcJiF3rAUIoP5CVbgrl7yz73 IYc5BHpKg0UoNQnXQ/ZfdxifzQ0urcj/WDriOfDGK9bcxsvGM8EFe+0I4 XVrR+gakqOkITTCgqBe0FhmXqzYIwf1GXtrzseBQH5/1nmCLBa6DzfTKu /U6NQl0UsuQPrDGs1mpbhCpKf5Fapor5EeWuKRnh6qq860BnXIjPF9Yt7 zo1usenm4sn/q0Zh/T2R9crwwQM0MCEsBhAu2fxWqsrTOVhxYEZR9s0H1 KcyJfzekLZ6l5XFwgEFlboXWOG3i3voxCL90MqM4HWCmmFnJOGQCtSL6I Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862715" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862715" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826049" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:34 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 11/33] baseband/acc100: update validate LDPC enc/dec Date: Mon, 15 Aug 2022 22:52:36 -0700 Message-Id: <20220816055258.107564-12-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update validate functions to check for valid LDPC parameters, handling HARQ and transport blocks. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 297 +++++++++++++++++++++-- 1 file changed, 283 insertions(+), 14 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 6c639698db..843431748d 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2407,10 +2407,6 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) if (!validate_op_required(q)) return 0; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); - return -1; - } if (ldpc_enc->input.data == NULL) { rte_bbdev_log(ERR, "Invalid input pointer"); return -1; @@ -2419,11 +2415,9 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) rte_bbdev_log(ERR, "Invalid output pointer"); return -1; } - if (ldpc_enc->input.length > - RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { - rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", - ldpc_enc->input.length, - RTE_BBDEV_LDPC_MAX_CB_SIZE); + if (ldpc_enc->input.length == 0) { + rte_bbdev_log(ERR, "CB size (%u) is null", + ldpc_enc->input.length); return -1; } if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) { @@ -2444,13 +2438,107 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) ldpc_enc->code_block_mode); return -1; } + if (ldpc_enc->z_c > 384) { + rte_bbdev_log(ERR, + "Zc (%u) is out of range", + ldpc_enc->z_c); + return -1; + } int K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; - if (ldpc_enc->n_filler >= K) { + int N = (ldpc_enc->basegraph == 1 ? ACC100_N_ZC_1 : ACC100_N_ZC_2) + * ldpc_enc->z_c; + int q_m = ldpc_enc->q_m; + int crc24 = 0; + + if (check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_CRC_24A_ATTACH) || + check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + crc24 = 24; + if ((K - ldpc_enc->n_filler) % 8 > 0) { rte_bbdev_log(ERR, - "K and F are not compatible %u %u", + "K - F not byte aligned %u", + K - ldpc_enc->n_filler); + return -1; + } + if (ldpc_enc->n_filler > (K - 2 * ldpc_enc->z_c)) { + rte_bbdev_log(ERR, + "K - F invalid %u %u", K, ldpc_enc->n_filler); return -1; } + if ((ldpc_enc->n_cb > N) || (ldpc_enc->n_cb <= K)) { + rte_bbdev_log(ERR, + "Ncb (%u) is out of range K %d N %d", + ldpc_enc->n_cb, K, N); + return -1; + } + if (!check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) && + ((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) + || (q_m > 8))) { + rte_bbdev_log(ERR, + "Qm (%u) is out of range", + ldpc_enc->q_m); + return -1; + } + if (ldpc_enc->code_block_mode == RTE_BBDEV_CODE_BLOCK) { + if (ldpc_enc->cb_params.e == 0) { + rte_bbdev_log(ERR, + "E is null"); + return -1; + } + if (q_m > 0) { + if (ldpc_enc->cb_params.e % q_m > 0) { + rte_bbdev_log(ERR, + "E not multiple of qm %d", q_m); + return -1; + } + } + if ((ldpc_enc->z_c <= 11) && (ldpc_enc->cb_params.e > 3456)) { + rte_bbdev_log(ERR, + "E too large for small block"); + return -1; + } + if (ldpc_enc->input.length > + RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { + rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", + ldpc_enc->input.length, + RTE_BBDEV_LDPC_MAX_CB_SIZE); + return -1; + } + if (K < (int) (ldpc_enc->input.length * 8 + + ldpc_enc->n_filler) + crc24) { + rte_bbdev_log(ERR, + "K and F not matching input size %u %u %u", + K, ldpc_enc->n_filler, + ldpc_enc->input.length); + return -1; + } + } else { + if ((ldpc_enc->tb_params.c == 0) || + (ldpc_enc->tb_params.ea == 0) || + (ldpc_enc->tb_params.eb == 0)) { + rte_bbdev_log(ERR, + "TB parameter is null"); + return -1; + } + if (q_m > 0) { + if ((ldpc_enc->tb_params.ea % q_m > 0) || + (ldpc_enc->tb_params.eb % q_m > 0)) { + rte_bbdev_log(ERR, + "E not multiple of qm %d", + q_m); + return -1; + } + } + if ((ldpc_enc->z_c <= 11) && (RTE_MAX(ldpc_enc->tb_params.ea, + ldpc_enc->tb_params.eb) > 3456)) { + rte_bbdev_log(ERR, + "E too large for small block"); + return -1; + } + } return 0; } @@ -2463,8 +2551,16 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) if (!validate_op_required(q)) return 0; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); + if (ldpc_dec->input.data == NULL) { + rte_bbdev_log(ERR, "Invalid input pointer"); + return -1; + } + if (ldpc_dec->hard_output.data == NULL) { + rte_bbdev_log(ERR, "Invalid output pointer"); + return -1; + } + if (ldpc_dec->input.length == 0) { + rte_bbdev_log(ERR, "input is null"); return -1; } if ((ldpc_dec->basegraph > 2) || (ldpc_dec->basegraph == 0)) { @@ -2491,13 +2587,186 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) ldpc_dec->code_block_mode); return -1; } + /* Check Zc is valid value */ + if ((ldpc_dec->z_c > 384) || (ldpc_dec->z_c < 2)) { + rte_bbdev_log(ERR, + "Zc (%u) is out of range", + ldpc_dec->z_c); + return -1; + } + if (ldpc_dec->z_c > 256) { + if ((ldpc_dec->z_c % 32) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 128) { + if ((ldpc_dec->z_c % 16) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 64) { + if ((ldpc_dec->z_c % 8) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 32) { + if ((ldpc_dec->z_c % 4) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 16) { + if ((ldpc_dec->z_c % 2) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } int K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; - if (ldpc_dec->n_filler >= K) { + int N = (ldpc_dec->basegraph == 1 ? ACC100_N_ZC_1 : ACC100_N_ZC_2) + * ldpc_dec->z_c; + int q_m = ldpc_dec->q_m; + if (ldpc_dec->n_filler >= K - 2 * ldpc_dec->z_c) { rte_bbdev_log(ERR, "K and F are not compatible %u %u", K, ldpc_dec->n_filler); return -1; } + if ((ldpc_dec->n_cb > N) || (ldpc_dec->n_cb <= K)) { + rte_bbdev_log(ERR, + "Ncb (%u) is out of range K %d N %d", + ldpc_dec->n_cb, K, N); + return -1; + } + + if (((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) + || (q_m > 8))) { + rte_bbdev_log(ERR, + "Qm (%u) is out of range", + ldpc_dec->q_m); + return -1; + } + if (ldpc_dec->code_block_mode == RTE_BBDEV_CODE_BLOCK) { + if (ldpc_dec->cb_params.e == 0) { + rte_bbdev_log(ERR, + "E is null"); + return -1; + } + if (ldpc_dec->cb_params.e % q_m > 0) { + rte_bbdev_log(ERR, + "E not multiple of qm %d", q_m); + return -1; + } + if (ldpc_dec->cb_params.e > 512 * ldpc_dec->z_c) { + rte_bbdev_log(ERR, + "E too high"); + return -1; + } + } else { + if ((ldpc_dec->tb_params.c == 0) || + (ldpc_dec->tb_params.ea == 0) || + (ldpc_dec->tb_params.eb == 0)) { + rte_bbdev_log(ERR, + "TB parameter is null"); + return -1; + } + if ((ldpc_dec->tb_params.ea % q_m > 0) || + (ldpc_dec->tb_params.eb % q_m > 0)) { + rte_bbdev_log(ERR, + "E not multiple of qm %d", q_m); + return -1; + } + if ((ldpc_dec->tb_params.ea > 512 * ldpc_dec->z_c) || + (ldpc_dec->tb_params.eb > 512 * ldpc_dec->z_c)) { + rte_bbdev_log(ERR, + "E too high"); + return -1; + } + } + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DECODE_BYPASS)) { + rte_bbdev_log(ERR, "Avoid LDPC Decode bypass"); + return -1; + } + + /* Avoid HARQ compression for small block size */ + if ((check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) + && (K < 2048)) { + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; + } + uint32_t min_harq_input = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION) ? 256 : 64; + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + ldpc_dec->harq_combined_input.length < + min_harq_input) { + rte_bbdev_log(ERR, "HARQ input size is too small %d < %d", + ldpc_dec->harq_combined_input.length, + min_harq_input); + return -1; + } + + /* Enforce in-range HARQ input size */ + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + uint32_t max_harq_input = RTE_ALIGN_CEIL(ldpc_dec->n_cb - + ldpc_dec->n_filler, 64); + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) + max_harq_input = max_harq_input * 3 / 4; + if (ldpc_dec->harq_combined_input.length > max_harq_input) { + rte_bbdev_log(ERR, + "HARQ input size out of range %d > %d, Ncb %d F %d K %d N %d", + ldpc_dec->harq_combined_input.length, + max_harq_input, ldpc_dec->n_cb, + ldpc_dec->n_filler, K, N); + /* Fallback to flush HARQ combine */ + ldpc_dec->harq_combined_input.length = 0; + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + op->ldpc_dec.op_flags ^= + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + } + } + +#ifdef ACC100_EXT_MEM + /* Enforce in-range HARQ offset */ + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + if ((op->ldpc_dec.harq_combined_input.offset >> 10) + >= q->d->ddr_size) { + rte_bbdev_log(ERR, + "HARQin offset out of range %d > %d", + op->ldpc_dec.harq_combined_input.offset, + q->d->ddr_size); + return -1; + } + if ((op->ldpc_dec.harq_combined_input.offset & 0x3FF) > 0) { + rte_bbdev_log(ERR, + "HARQin offset not aligned on 1kB %d", + op->ldpc_dec.harq_combined_input.offset); + return -1; + } + } + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + if ((op->ldpc_dec.harq_combined_output.offset >> 10) + >= q->d->ddr_size) { + rte_bbdev_log(ERR, + "HARQout offset out of range %d > %d", + op->ldpc_dec.harq_combined_output.offset, + q->d->ddr_size); + return -1; + } + if ((op->ldpc_dec.harq_combined_output.offset & 0x3FF) > 0) { + rte_bbdev_log(ERR, + "HARQout offset not aligned on 1kB %d", + op->ldpc_dec.harq_combined_output.offset); + return -1; + } + } +#endif + return 0; } #endif From patchwork Tue Aug 16 05:52:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115120 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CABB0A00C3; Mon, 15 Aug 2022 23:58:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C8F542B92; Mon, 15 Aug 2022 23:57:45 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id E4FF1427F2 for ; Mon, 15 Aug 2022 23:57:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600656; x=1692136656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6pLu2UQPgZvdZ068Yf+oBUZijT4EJTJiTrwQ+IzR5HM=; b=K/iAQU0N3jmmSH0emlcQFYkmOlfT2hZ7meeQ4siiAjVjVbDlIczF81lh 8kCcggKU1eiWsM/Pvjveic6FZzxxYAEtP+60o1lbF2jghePk8CVsRJtwD bNU/t4BI9lMs00VeTFTC2L6iBqHl6MMSXdcyEwg63tWRMhJitn/rpH9dz jKRiPBMIZRgT3LCMtWjNydCXwUowkP9DCCjZVOkqENx/AQifRZNfav7FQ PNOdadPMRzDsGvQSmVOfU1+dfcjnGT6tapVIO9lSJvrwRyklM97VmjnMP OOyvgDwwXG/e3ETKcOzPLHfoQqSZQQx1jtFMAh5RdZ5ylb/aptzm0OQYc g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862716" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862716" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826053" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:35 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 12/33] baseband/acc100: add workaround for deRM corner cases Date: Mon, 15 Aug 2022 22:52:37 -0700 Message-Id: <20220816055258.107564-13-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add function to asses if de-ratematch pre-processing should be run in SW for corner cases. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 13 +++ drivers/baseband/acc100/rte_acc100_pmd.c | 103 ++++++++++++++++++++++- 2 files changed, 114 insertions(+), 2 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 19a1f434bc..c98a182be6 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -140,6 +140,8 @@ /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define ACC100_N_ZC_1 66 /* N = 66 Zc for BG 1 */ #define ACC100_N_ZC_2 50 /* N = 50 Zc for BG 2 */ +#define ACC100_K_ZC_1 22 /* K = 22 Zc for BG 1 */ +#define ACC100_K_ZC_2 10 /* K = 10 Zc for BG 2 */ #define ACC100_K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */ #define ACC100_K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */ #define ACC100_K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */ @@ -177,6 +179,16 @@ #define ACC100_MS_IN_US (1000) #define ACC100_DDR_TRAINING_MAX (5000) +/* Code rate limitation when padding is required */ +#define ACC100_LIM_03 2 /* 0.03 */ +#define ACC100_LIM_09 6 /* 0.09 */ +#define ACC100_LIM_14 9 /* 0.14 */ +#define ACC100_LIM_21 14 /* 0.21 */ +#define ACC100_LIM_31 20 /* 0.31 */ +#define ACC100_MAX_E (128 * 1024 - 2) + + + /* ACC100 DMA Descriptor triplet */ struct acc100_dma_triplet { uint64_t address; @@ -572,6 +584,7 @@ struct __rte_cache_aligned acc100_queue { uint8_t *lb_out; rte_iova_t lb_in_addr_iova; rte_iova_t lb_out_addr_iova; + int8_t *derm_buffer; /* interim buffer for de-rm in SDK */ struct acc100_device *d; }; diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 843431748d..e0df07bc20 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -24,6 +24,10 @@ #include "acc100_pmd.h" #include "acc101_pmd.h" +#ifdef RTE_BBDEV_SDK_AVX512 +#include +#endif + #ifdef RTE_LIBRTE_BBDEV_DEBUG RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); #else @@ -901,6 +905,16 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, rte_free(q); return -ENOMEM; } + q->derm_buffer = rte_zmalloc_socket(dev->device->driver->name, + RTE_BBDEV_TURBO_MAX_CB_SIZE * 10, + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->derm_buffer == NULL) { + rte_bbdev_log(ERR, "Failed to allocate derm_buffer memory"); + rte_free(q->lb_in); + rte_free(q->lb_out); + rte_free(q); + return -ENOMEM; + } q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out); /* @@ -921,6 +935,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q_idx = acc100_find_free_queue_idx(dev, conf); if (q_idx == -1) { + rte_free(q->derm_buffer); rte_free(q->lb_in); rte_free(q->lb_out); rte_free(q); @@ -958,6 +973,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) /* Mark the Queue as un-assigned */ d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFF - (1 << q->aq_id)); + rte_free(q->derm_buffer); rte_free(q->lb_in); rte_free(q->lb_out); rte_free(q); @@ -3515,10 +3531,42 @@ harq_loopback(struct acc100_queue *q, struct rte_bbdev_dec_op *op, return 1; } +/** Assess whether a work around is required for the deRM corner cases */ +static inline bool +derm_workaround_required(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc100_queue *q) +{ + if (!is_acc100(q)) + return false; + int32_t e = ldpc_dec->cb_params.e; + int q_m = ldpc_dec->q_m; + int z_c = ldpc_dec->z_c; + int K = (ldpc_dec->basegraph == 1 ? ACC100_K_ZC_1 : ACC100_K_ZC_2) + * z_c; + bool required = false; + if (ldpc_dec->basegraph == 1) { + if ((q_m == 4) && (z_c >= 320) && (e * ACC100_LIM_31 > K * 64)) + required = true; + else if ((e * ACC100_LIM_21 > K * 64)) + required = true; + } else { + if (q_m <= 2) { + if ((z_c >= 208) && (e * ACC100_LIM_09 > K * 64)) + required = true; + else if ((z_c < 208) && (e * ACC100_LIM_03 > K * 64)) + required = true; + } else if (e * ACC100_LIM_14 > K * 64) + required = true; + } + if (required) + rte_bbdev_log(INFO, "Running deRM pre-processing in SW"); + return required; +} + /** Enqueue one decode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, - uint16_t total_enqueued_cbs, bool same_op) + uint16_t total_enqueued_cbs, bool same_op, + struct rte_bbdev_queue_data *q_data) { int ret; if (unlikely(check_bit(op->ldpc_dec.op_flags, @@ -3574,6 +3622,57 @@ enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, &in_offset, &h_out_offset, &h_out_length, harq_layout); } else { + if (derm_workaround_required(&op->ldpc_dec, q)) { + #ifdef RTE_BBDEV_SDK_AVX512 + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec; + /* Checking input size is matching with E */ + if (dec->input.data->data_len < dec->cb_params.e) { + rte_bbdev_log(ERR, + "deRM: Input size mismatch"); + return -EFAULT; + } + /* Run first deRM processing in SW */ + struct bblib_rate_dematching_5gnr_request derm_req; + struct bblib_rate_dematching_5gnr_response derm_resp; + uint8_t *in = rte_pktmbuf_mtod_offset(dec->input.data, + uint8_t *, in_offset); + derm_req.p_in = (int8_t *) in; + derm_req.p_harq = (int8_t *) q->derm_buffer; + derm_req.base_graph = dec->basegraph; + derm_req.zc = dec->z_c; + derm_req.ncb = dec->n_cb; + derm_req.e = dec->cb_params.e; + if (derm_req.e > ACC100_MAX_E) { + rte_bbdev_log(WARNING, + "deRM: E %d > %d max", + derm_req.e, ACC100_MAX_E); + derm_req.e = ACC100_MAX_E; + } + derm_req.k0 = 0; /* Actual output from SDK */ + derm_req.isretx = false; + derm_req.rvid = dec->rv_index; + derm_req.modulation_order = dec->q_m; + derm_req.start_null_index = + (dec->basegraph == 1 ? 22 : 10) + * dec->z_c - 2 * dec->z_c + - dec->n_filler; + derm_req.num_of_null = dec->n_filler; + bblib_rate_dematching_5gnr(&derm_req, &derm_resp); + /* Force back the HW DeRM */ + dec->q_m = 1; + dec->cb_params.e = dec->n_cb - dec->n_filler; + dec->rv_index = 0; + rte_memcpy(in, q->derm_buffer, dec->cb_params.e); + /* Capture counter when pre-processing is used */ + q_data->queue_stats.enqueue_warn_count++; + #else + RTE_SET_USED(q_data); + rte_bbdev_log(WARNING, + "Corner case may require deRM pre-processing in SDK" + ); + #endif + } + struct acc100_fcw_ld *fcw; uint32_t seg_total_left; fcw = &desc->req.fcw_ld; @@ -4325,7 +4424,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m, ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e, same_op); - ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); + ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data); if (ret < 0) { acc100_enqueue_invalid(q_data); break; From patchwork Tue Aug 16 05:52:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115121 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 20656A00C3; Mon, 15 Aug 2022 23:59:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 15A9C42B98; Mon, 15 Aug 2022 23:57:46 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 1D94C427F3 for ; Mon, 15 Aug 2022 23:57:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600656; x=1692136656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jTBvDxCva+2jywFD/iRxa8kmbkUj6749qPhdJlMMffA=; b=YOQYs6iEmoEzKFpknR8pc7X/ToSBtzX6M2fSRqQYccp6it6ld2nfXjdC 1N+p4gb/6yQ7kd31KQyfLPENEfLXeeXSpZ21K0ZPS/N6UwXhaemW0knsa I61rvIfubUTLvarkftWWk4OZ81SyYPnuGcVLvP7SAHBlLAO/O+3R4zc7H JC+K7UXJtm8SHqwTdKFeC5nDah8q4Rm9CVGh1eoU8qqzdGzx80x2EMJEp A7DiHBZws7zIUFvYZMWWhJm6++j9xkzR79Yc4ld0VqqKdBr678Eqn5ELR 9jF221pPZm9Tt1gIjyM5le+rqVRYwaK7uSAL5p38NeNqhYT3ED0PcB/PY g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862717" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862717" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826057" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:35 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 13/33] baseband/acc100: enable vf2pf doorbell register Date: Mon, 15 Aug 2022 22:52:38 -0700 Message-Id: <20220816055258.107564-14-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Setup vf2pf doorbell register for ACC101 Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_vf_enum.h | 6 ++++++ drivers/baseband/acc100/rte_acc100_pmd.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/baseband/acc100/acc100_vf_enum.h b/drivers/baseband/acc100/acc100_vf_enum.h index b512af33fc..5807a9d0fd 100644 --- a/drivers/baseband/acc100/acc100_vf_enum.h +++ b/drivers/baseband/acc100/acc100_vf_enum.h @@ -70,4 +70,10 @@ enum { ACC100_VF_INT_QMGR_AQ_OVERTHRESHOLD = 9, }; +/* TIP PF2VF Comms */ +enum { + ACC100_VF2PF_STATUS_REQUEST = 0, + ACC100_VF2PF_USING_VF = 1, +}; + #endif /* ACC100_VF_ENUM_H */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index e0df07bc20..548f228f23 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -292,6 +292,13 @@ fetch_acc100_config(struct rte_bbdev *dev) acc100_conf->q_dl_5g.aq_depth_log2); } +static inline void +acc100_vf2pf(struct acc100_device *d, unsigned int payload) +{ + if (d->device_variant == ACC101_VARIANT) + acc100_reg_write(d, HWVfHiVfToPfDbellVf, payload); +} + static void free_base_addresses(void **base_addrs, int size) { @@ -712,6 +719,7 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Mark as configured properly */ d->configured = true; + acc100_vf2pf(d, ACC100_VF2PF_USING_VF); rte_bbdev_log_debug( "ACC100 (%s) configured sw_rings = %p, sw_rings_iova = %#" From patchwork Tue Aug 16 05:52:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115122 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62DA7A00C3; Mon, 15 Aug 2022 23:59:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E8FAC42B9D; Mon, 15 Aug 2022 23:57:46 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 80E62415D7 for ; Mon, 15 Aug 2022 23:57:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600656; x=1692136656; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=42KtpnR7bW3OPaWmz8GuVXsCzrr9QSbCMlXLNksG6zs=; b=YWilcU3wDgbMG25tQGLDX+gHUfc7A1OTqRygAW+dJboeggTZLNw4bb0I e8D82eqRv/EnscAx8jzyM+lSdzgleL+Q6WGT+9TnfYqyq8LC5Zr2bwDKL F8JpI/u+rBDLq6mdxc7QxcdrLSfEJS3zmMhmiHobuhhJtxy39Qi5hLn/W toyPHLIhFZEM6E5HVGefwRDVao3pTTfciH98EXO/7o9o4jas4O1rWY2EC 9LvwalQrJb0Q/E7EUlM5QOE0AA1G1XRX9ZBx5yQke40GZlwtweSgxR7FN ZnuFVlTghXJXLNiHkb2O5b0G6X4fpF7cKkUXpLaSFnRXIdytbOkCHqUPm Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862719" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862719" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826060" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:35 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 14/33] baseband/acc100: add ring companion address Date: Mon, 15 Aug 2022 22:52:39 -0700 Message-Id: <20220816055258.107564-15-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the virtual address of companion ring as part of queue information. Use this address to calculate the op address. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 12 ++ drivers/baseband/acc100/rte_acc100_pmd.c | 143 ++++++++++++++--------- 2 files changed, 100 insertions(+), 55 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index c98a182be6..20157e5886 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -126,6 +126,7 @@ #define ACC100_5GUL_SIZE_0 16 #define ACC100_5GUL_SIZE_1 40 #define ACC100_5GUL_OFFSET_0 36 +#define ACC100_COMPANION_PTRS 8 #define ACC100_FCW_VER 2 #define ACC100_MUX_5GDL_DESC 6 @@ -375,6 +376,15 @@ struct __rte_packed acc100_fcw_le { uint32_t res8; }; +struct __rte_packed acc100_pad_ptr { + void *op_addr; + uint64_t pad1; /* pad to 64 bits */ +}; + +struct __rte_packed acc100_ptrs { + struct acc100_pad_ptr ptr[ACC100_COMPANION_PTRS]; +}; + /* ACC100 DMA Request Descriptor */ struct __rte_packed acc100_dma_req_desc { union { @@ -568,6 +578,8 @@ struct __rte_cache_aligned acc100_queue { uint32_t sw_ring_depth; /* mask used to wrap enqueued descriptors on the sw ring */ uint32_t sw_ring_wrap_mask; + /* Virtual address of companion ring */ + struct acc100_ptrs *companion_ring_addr; /* MMIO register used to enqueue descriptors */ void *mmio_reg_enqueue; uint8_t vf_id; /* VF ID (max = 63) */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 548f228f23..c85d28aa5c 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -924,6 +924,17 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, return -ENOMEM; } q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out); + q->companion_ring_addr = rte_zmalloc_socket(dev->device->driver->name, + d->sw_ring_max_depth * sizeof(*q->companion_ring_addr), + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->companion_ring_addr == NULL) { + rte_bbdev_log(ERR, "Failed to allocate companion_ring memory"); + rte_free(q->derm_buffer); + rte_free(q->lb_in); + rte_free(q->lb_out); + rte_free(q); + return -ENOMEM; + } /* * Software queue ring wraps synchronously with the HW when it reaches @@ -943,6 +954,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q_idx = acc100_find_free_queue_idx(dev, conf); if (q_idx == -1) { + rte_free(q->companion_ring_addr); rte_free(q->derm_buffer); rte_free(q->lb_in); rte_free(q->lb_out); @@ -981,6 +993,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) /* Mark the Queue as un-assigned */ d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFF - (1 << q->aq_id)); + rte_free(q->companion_ring_addr); rte_free(q->derm_buffer); rte_free(q->lb_in); rte_free(q->lb_out); @@ -2900,6 +2913,10 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, } desc->req.op_addr = ops[0]; + /* Keep track of pointers even when multiplexed in single descriptor */ + struct acc100_ptrs *context_ptrs = q->companion_ring_addr + desc_idx; + for (i = 0; i < num; i++) + context_ptrs->ptr[i].op_addr = ops[i]; #ifdef RTE_LIBRTE_BBDEV_DEBUG rte_memdump(stderr, "FCW", &desc->req.fcw_le, @@ -4528,15 +4545,16 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, /* Dequeue one encode operations from ACC100 device in CB mode */ static inline int dequeue_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, - uint16_t total_dequeued_cbs, uint32_t *aq_dequeued) + uint16_t *dequeued_ops, uint32_t *aq_dequeued, + uint16_t *dequeued_descs) { union acc100_dma_desc *desc, atom_desc; union acc100_dma_rsp_desc rsp; struct rte_bbdev_enc_op *op; int i; - - desc = q->ring_addr + ((q->sw_ring_tail + total_dequeued_cbs) + int desc_idx = ((q->sw_ring_tail + *dequeued_descs) & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); @@ -4545,7 +4563,8 @@ dequeue_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, return -1; rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x num %d\n", + desc, rsp.val, desc->req.numCBs); /* Dequeue */ op = desc->req.op_addr; @@ -4566,27 +4585,32 @@ dequeue_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, desc->rsp.add_info_0 = 0; /*Reserved bits */ desc->rsp.add_info_1 = 0; /*Reserved bits */ - /* Flag that the muxing cause loss of opaque data */ - op->opaque_data = (void *)-1; - for (i = 0 ; i < desc->req.numCBs; i++) - ref_op[i] = op; + ref_op[0] = op; + struct acc100_ptrs *context_ptrs = q->companion_ring_addr + desc_idx; + for (i = 1 ; i < desc->req.numCBs; i++) + ref_op[i] = context_ptrs->ptr[i].op_addr; - /* One CB (op) was successfully dequeued */ + /* One op was successfully dequeued */ + (*dequeued_descs)++; + *dequeued_ops += desc->req.numCBs; return desc->req.numCBs; } -/* Dequeue one encode operations from ACC100 device in TB mode */ +/* Dequeue one LDPC encode operations from ACC100 device in TB mode + * That operation may cover multiple descriptors + */ static inline int dequeue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, - uint16_t total_dequeued_cbs, uint32_t *aq_dequeued) + uint16_t *dequeued_ops, uint32_t *aq_dequeued, + uint16_t *dequeued_descs) { union acc100_dma_desc *desc, *last_desc, atom_desc; union acc100_dma_rsp_desc rsp; struct rte_bbdev_enc_op *op; uint8_t i = 0; - uint16_t current_dequeued_cbs = 0, cbs_in_tb; + uint16_t current_dequeued_descs = 0, descs_in_tb; - desc = q->ring_addr + ((q->sw_ring_tail + total_dequeued_cbs) + desc = q->ring_addr + ((q->sw_ring_tail + *dequeued_descs) & q->sw_ring_wrap_mask); atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); @@ -4596,10 +4620,10 @@ dequeue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, return -1; /* Get number of CBs in dequeued TB */ - cbs_in_tb = desc->req.cbs_in_tb; + descs_in_tb = desc->req.cbs_in_tb; /* Get last CB */ last_desc = q->ring_addr + ((q->sw_ring_tail - + total_dequeued_cbs + cbs_in_tb - 1) + + *dequeued_descs + descs_in_tb - 1) & q->sw_ring_wrap_mask); /* Check if last CB in TB is ready to dequeue (and thus * the whole TB) - checking sdone bit. If not return. @@ -4615,15 +4639,17 @@ dequeue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, /* Clearing status, it will be set based on response */ op->status = 0; - while (i < cbs_in_tb) { + while (i < descs_in_tb) { desc = q->ring_addr + ((q->sw_ring_tail - + total_dequeued_cbs) + + *dequeued_descs) & q->sw_ring_wrap_mask); atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, - rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x descs %d cbs %d\n", + desc, + rsp.val, descs_in_tb, + desc->req.numCBs); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0); @@ -4637,14 +4663,14 @@ dequeue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, desc->rsp.val = ACC100_DMA_DESC_TYPE; desc->rsp.add_info_0 = 0; desc->rsp.add_info_1 = 0; - total_dequeued_cbs++; - current_dequeued_cbs++; + (*dequeued_descs)++; + current_dequeued_descs++; i++; } *ref_op = op; - - return current_dequeued_cbs; + (*dequeued_ops)++; + return current_dequeued_descs; } /* Dequeue one decode operation from ACC100 device in CB mode */ @@ -4840,12 +4866,11 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc100_queue *q = q_data->queue_private; - uint16_t dequeue_num; uint32_t avail = acc100_ring_avail_deq(q); uint32_t aq_dequeued = 0; - uint16_t i, dequeued_cbs = 0; - struct rte_bbdev_enc_op *op; + uint16_t i, dequeued_ops = 0, dequeued_descs = 0; int ret; + struct rte_bbdev_enc_op *op; if (avail == 0) return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG @@ -4854,31 +4879,34 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, return 0; } #endif + op = (q->ring_addr + (q->sw_ring_tail & + q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(ops == NULL || op == NULL)) + return 0; - dequeue_num = (avail < num) ? avail : num; + int cbm = op->turbo_enc.code_block_mode; - for (i = 0; i < dequeue_num; ++i) { - op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) - & q->sw_ring_wrap_mask))->req.op_addr; - if (op->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs, - &aq_dequeued); + for (i = 0; i < num; i++) { + if (cbm == RTE_BBDEV_TRANSPORT_BLOCK) + ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); else - ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs, - &aq_dequeued); - + ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); if (ret < 0) break; - dequeued_cbs += ret; + if (dequeued_ops >= num) + break; } q->aq_dequeued += aq_dequeued; - q->sw_ring_tail += dequeued_cbs; + q->sw_ring_tail += dequeued_descs; /* Update enqueue stats */ - q_data->queue_stats.dequeued_count += i; - - return i; + q_data->queue_stats.dequeued_count += dequeued_ops; + return dequeued_ops; } /* Dequeue LDPC encode operations from ACC100 device. */ @@ -4889,24 +4917,31 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct acc100_queue *q = q_data->queue_private; uint32_t avail = acc100_ring_avail_deq(q); uint32_t aq_dequeued = 0; - uint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0; + uint16_t i, dequeued_ops = 0, dequeued_descs = 0; int ret; - + struct rte_bbdev_enc_op *op; #ifdef RTE_LIBRTE_BBDEV_DEBUG if (unlikely(ops == 0 && q == NULL)) return 0; #endif + op = (q->ring_addr + (q->sw_ring_tail & + q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(ops == NULL || op == NULL)) + return 0; + int cbm = op->ldpc_enc.code_block_mode; - dequeue_num = RTE_MIN(avail, num); - - for (i = 0; i < dequeue_num; i++) { - ret = dequeue_enc_one_op_cb(q, &ops[dequeued_cbs], - dequeued_descs, &aq_dequeued); + for (i = 0; i < avail; i++) { + if (cbm == RTE_BBDEV_TRANSPORT_BLOCK) + ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); + else + ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); if (ret < 0) break; - dequeued_cbs += ret; - dequeued_descs++; - if (dequeued_cbs >= num) + if (dequeued_ops >= num) break; } @@ -4914,12 +4949,10 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, q->sw_ring_tail += dequeued_descs; /* Update enqueue stats */ - q_data->queue_stats.dequeued_count += dequeued_cbs; - - return dequeued_cbs; + q_data->queue_stats.dequeued_count += dequeued_ops; + return dequeued_ops; } - /* Dequeue decode operations from ACC100 device. */ static uint16_t acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, From patchwork Tue Aug 16 05:52:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115123 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7C8CA00C3; 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a="292862720" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862720" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826064" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:36 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 15/33] baseband/acc100: configure PMON control registers Date: Mon, 15 Aug 2022 22:52:40 -0700 Message-Id: <20220816055258.107564-16-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable performance monitor control registers. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 6 ++++++ drivers/baseband/acc100/rte_acc100_pmd.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 20157e5886..4a8d2e17ec 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -508,6 +508,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -537,6 +539,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWPfPermonACntrlRegVf, + .pmon_ctrl_b = HWPfPermonBCntrlRegVf, }; /* Structure holding registry addresses for VF */ @@ -566,6 +570,8 @@ static const struct acc100_registry_addr vf_reg_addr = { .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf, .qman_group_func = HWVfQmgrGrpFunction0Vf, .ddr_range = HWVfDmaDdrBaseRangeRoVf, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure associated with each queue. */ diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index c85d28aa5c..b6c2c47091 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -653,6 +653,11 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Read the populated cfg from ACC100 registers */ fetch_acc100_config(dev); + for (value = 0; value <= 2; value++) { + acc100_reg_write(d, reg_addr->pmon_ctrl_a, value); + acc100_reg_write(d, reg_addr->pmon_ctrl_b, value); + } + /* Release AXI from PF */ if (d->pf_device) acc100_reg_write(d, HWPfDmaAxiControl, 1); From patchwork Tue Aug 16 05:52:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115124 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AFF93A00C3; Mon, 15 Aug 2022 23:59:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 98CBC42BAD; Mon, 15 Aug 2022 23:57:48 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 54399427F2 for ; Mon, 15 Aug 2022 23:57:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600657; x=1692136657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1ArOTQzGCG9X9f7z5ORGl/kZW3NuMS49DnxbpSZ9yDQ=; b=S6veQ5Dp3fokImVYaMMP7tBtzwAI3zJsqoh9bPrLtCsmf9Z4aS5IH+kz Ot4EX54N3KWecze97rMaB2iR6REldSY38g0Me0d0uy/6jsgmfS7zuEMtG H12gzept53fDg0W9TQwQ+oy4EQlL8LHoeULuWo7d4N9akZ7imfd6Iedr6 f5TyBER/HkTO5i1F8QxcU6atE1K180YmewSvyugzeIkhrtk5SIYxNs8FA Og8SHhjiSXvUMWTeGue0y039b9LkqtKYvce4taJNQ51fXLnz1UrZyLnys SdJrPpY/FasoOnWkw6d8qAdmv9LzAIMol/lo+sxXnctqFVs6Tr4rzQWc/ w==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862722" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862722" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826067" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:36 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 16/33] baseband/acc100: configurable queue depth Date: Mon, 15 Aug 2022 22:52:41 -0700 Message-Id: <20220816055258.107564-17-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Make queue depth configurable based on dec/enc mode. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index b6c2c47091..2f13cbf5b9 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -970,9 +970,15 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F; q->aq_id = q_idx & 0xF; - q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ? - (1 << d->acc100_conf.q_ul_4g.aq_depth_log2) : - (1 << d->acc100_conf.q_dl_4g.aq_depth_log2); + q->aq_depth = 0; + if (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) + q->aq_depth = (1 << d->acc100_conf.q_ul_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) + q->aq_depth = (1 << d->acc100_conf.q_dl_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_DEC) + q->aq_depth = (1 << d->acc100_conf.q_ul_5g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) + q->aq_depth = (1 << d->acc100_conf.q_dl_5g.aq_depth_log2); q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base, queue_offset(d->pf_device, From patchwork Tue Aug 16 05:52:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115125 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4F33A00C3; Mon, 15 Aug 2022 23:59:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 582A342BB2; Mon, 15 Aug 2022 23:57:49 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 81DDC427F3 for ; Mon, 15 Aug 2022 23:57:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600657; x=1692136657; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fbEaaAniR8RXpmnmH6Fb59+zWyIHNTOoC/cFOwV8q3E=; b=maybRreHy1NbMyqvavEfb3pnhyo9TVdDmm2V+W3vgNU5WmUyxA77G6eu R+pa5F8vF5uLHwVlsvkhisknnZ8NY1F5bernbpNVmY+W51lzc609DLj6r oTWGlizhfJl18Ec9xpYGkfhlUQwGhsZIhVoYk8k2fUAHAKoRMQ1aXNQxl acppwuRvtbzsNj9fqxw+i7wHLWsVKmry7IsXFqiff/9K5KgtkL9d+SHv9 tU6KMBQ1+CqVAfxGHCrSsJt8Mo62fy9qQK1V7vag5y9JgBenC8LXFaSr2 yzXKSyK63wzo+Tg91lAhV6fT9qWr8b0nppMrR6qP/ZzxuMHoceprvLrXo w==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862724" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862724" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826070" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:36 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 17/33] baseband/acc100: add queue stop operation Date: Mon, 15 Aug 2022 22:52:42 -0700 Message-Id: <20220816055258.107564-18-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement queue stop operation. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 2f13cbf5b9..bf6c403bbe 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -993,6 +993,63 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, return 0; } +static inline void +acc100_print_op(struct rte_bbdev_dec_op *op, enum rte_bbdev_op_type op_type, + uint16_t index) +{ + if (op == NULL) + return; + if (op_type == RTE_BBDEV_OP_LDPC_DEC) + rte_bbdev_log(INFO, + " Op 5GUL %d %d %d %d %d %d %d %d %d %d %d %d", + index, + op->ldpc_dec.basegraph, op->ldpc_dec.z_c, + op->ldpc_dec.n_cb, op->ldpc_dec.q_m, + op->ldpc_dec.n_filler, op->ldpc_dec.cb_params.e, + op->ldpc_dec.op_flags, op->ldpc_dec.rv_index, + op->ldpc_dec.iter_max, op->ldpc_dec.iter_count, + op->ldpc_dec.harq_combined_input.length + ); + else if (op_type == RTE_BBDEV_OP_LDPC_ENC) { + struct rte_bbdev_enc_op *op_dl = (struct rte_bbdev_enc_op *) op; + rte_bbdev_log(INFO, + " Op 5GDL %d %d %d %d %d %d %d %d %d", + index, + op_dl->ldpc_enc.basegraph, op_dl->ldpc_enc.z_c, + op_dl->ldpc_enc.n_cb, op_dl->ldpc_enc.q_m, + op_dl->ldpc_enc.n_filler, op_dl->ldpc_enc.cb_params.e, + op_dl->ldpc_enc.op_flags, op_dl->ldpc_enc.rv_index + ); + } +} + +static int +acc100_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct acc100_queue *q; + struct rte_bbdev_dec_op *op; + uint16_t i; + q = dev->data->queues[queue_id].queue_private; + rte_bbdev_log(INFO, "Queue Stop %d H/T/D %d %d %x OpType %d", + queue_id, q->sw_ring_head, q->sw_ring_tail, + q->sw_ring_depth, q->op_type); + for (i = 0; i < q->sw_ring_depth; ++i) { + op = (q->ring_addr + i)->req.op_addr; + acc100_print_op(op, q->op_type, i); + } + /* ignore all operations in flight and clear counters */ + q->sw_ring_tail = q->sw_ring_head; + q->aq_enqueued = 0; + q->aq_dequeued = 0; + dev->data->queues[queue_id].queue_stats.enqueued_count = 0; + dev->data->queues[queue_id].queue_stats.dequeued_count = 0; + dev->data->queues[queue_id].queue_stats.enqueue_err_count = 0; + dev->data->queues[queue_id].queue_stats.dequeue_err_count = 0; + dev->data->queues[queue_id].queue_stats.enqueue_warn_count = 0; + dev->data->queues[queue_id].queue_stats.dequeue_warn_count = 0; + return 0; +} + /* Release ACC100 queue */ static int acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) @@ -1187,6 +1244,7 @@ static const struct rte_bbdev_ops acc100_bbdev_ops = { .info_get = acc100_dev_info_get, .queue_setup = acc100_queue_setup, .queue_release = acc100_queue_release, + .queue_stop = acc100_queue_stop, .queue_intr_enable = acc100_queue_intr_enable, .queue_intr_disable = acc100_queue_intr_disable }; From patchwork Tue Aug 16 05:52:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115126 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42DE9A00C3; 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a="292862725" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862725" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826073" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:37 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 18/33] basbeband/acc100: check turbo dec/enc input Date: Mon, 15 Aug 2022 22:52:43 -0700 Message-Id: <20220816055258.107564-19-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add NULL check for the turbo decoder and encoder input length. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index bf6c403bbe..3bbef68128 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2401,6 +2401,11 @@ validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) return -1; } + if (turbo_enc->input.length == 0) { + rte_bbdev_log(ERR, "input length null"); + return -1; + } + if (turbo_enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { tb = &turbo_enc->tb_params; if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE @@ -2420,11 +2425,12 @@ validate_enc_op(struct rte_bbdev_enc_op *op, struct acc100_queue *q) RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) + if (tb->c_neg > 0) { rte_bbdev_log(ERR, - "c_neg (%u) is out of range 0 <= value <= %u", - tb->c_neg, - RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + "c_neg (%u) expected to be null", + tb->c_neg); + return -1; + } if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", @@ -3323,6 +3329,11 @@ validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) return -1; } + if (turbo_dec->input.length == 0) { + rte_bbdev_log(ERR, "input length null"); + return -1; + } + if (turbo_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { tb = &turbo_dec->tb_params; if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE @@ -3343,11 +3354,13 @@ validate_dec_op(struct rte_bbdev_dec_op *op, struct acc100_queue *q) RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) + if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) { rte_bbdev_log(ERR, "c_neg (%u) is out of range 0 <= value <= %u", tb->c_neg, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + return -1; + } if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", From patchwork Tue Aug 16 05:52:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115127 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92073A00C3; Mon, 15 Aug 2022 23:59:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1373B42BBA; Mon, 15 Aug 2022 23:57:51 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 225AE427F9 for ; Mon, 15 Aug 2022 23:57:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600658; x=1692136658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kFe0cI2mXUksQG+8DCCtFMzgw5hbujM8HJlbfDJ7uUA=; b=f/Gywysm38doX4s6ZJwgBTF+g+nABEPthH7TkkR3CkguAx45LfnsgPvC jMUzjmPPgkiRdodyfpAAlQoPPxbPAzIMc992RB4dU4MbAZMCRoDDft2+w tvcyakZaLNT5WiMDsuIQxlVcxkpQIq5tKlTeHnvm2Nv64hOYi22Ub553M OnmR/6xZXK6/yLBJNV2k8lvZRULWVC7I9th6n7t98LBTcYkPvbxRkPq5x p490i9NQ4Xxzdu/iOSChBKUbR0N4Q+nxIbIbGTFSFecS5XvOxDPQLYp5X CVRVURLdcS/PBOE9CjMfxGRCsk0dzz3kJzjuNQzOWVjzNpfRMQRpzcg+l A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862729" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862729" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826078" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:37 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 19/33] baseband/acc100: check for unlikely operation vals Date: Mon, 15 Aug 2022 22:52:44 -0700 Message-Id: <20220816055258.107564-20-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add unlikely checks for NULL operation values. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 3bbef68128..42a5f8751e 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3151,6 +3151,10 @@ enqueue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, r = op->turbo_enc.tb_params.r; while (mbuf_total_left > 0 && r < c) { + if (unlikely(input == 0)) { + rte_bbdev_log(ERR, "Not enough input segment"); + return -EINVAL; + } seg_total_left = rte_pktmbuf_data_len(input) - in_offset; /* Set up DMA descriptor */ desc = q->ring_addr + ((q->sw_ring_head + total_enqueued_cbs) @@ -4494,6 +4498,8 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, } enqueued_cbs += ret; } + if (unlikely(enqueued_cbs == 0)) + return 0; /* Nothing to enqueue */ acc100_dma_enqueue(q, enqueued_cbs, &q_data->queue_stats); @@ -5059,6 +5065,8 @@ acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, for (i = 0; i < dequeue_num; ++i) { op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) & q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(op == NULL)) + break; if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs, &aq_dequeued); @@ -5104,6 +5112,8 @@ acc100_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, for (i = 0; i < dequeue_num; ++i) { op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) & q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(op == NULL)) + break; if (op->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs, &aq_dequeued); From patchwork Tue Aug 16 05:52:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115128 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9B3EA00C3; Mon, 15 Aug 2022 23:59:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E416442BC2; Mon, 15 Aug 2022 23:57:51 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 6904B4281A for ; Mon, 15 Aug 2022 23:57:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600658; x=1692136658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yXKivDG2WKTkvWCvDgEwYTUfJqSjcxsf180vf7Gh1k8=; b=a4wa5hC04Hxoh9YTB40MgAxUF3+7OMiviiyhdGEST7bY9PYGLuzl7ZP9 wIv1dY1q9XTweyymiXRk1rTqxlKgcoQtuHq0iHokwQbYroUOWGjA+QfYI O+A2DGdNdyi3uYVE7MufdYyIWOfpMcknXqhwOl6Wxv8usGBVJOfTTq3ON I1gsBBN74yHeAO4pouvMRmeEMU/BPPT364vygF7xs6vbVemyt3P/lMN/n 8bX47VxMmNTazTV07ZH6pA/AIaltvgd8VKfrPQ1xpdecUTRyZH66LEVKo vvZgZtrgM+9eYGK8R6f8tLJ8u04X6w/ROujmRZH830RUwCYTWpuP/fuUC A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862730" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862730" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826082" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:37 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 20/33] baseband/acc100: enforce additional check on FCW Date: Mon, 15 Aug 2022 22:52:45 -0700 Message-Id: <20220816055258.107564-21-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enforce additional check on Frame Control Word validity and add stronger alignment for decompression mode. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 48 ++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 42a5f8751e..0e91205c49 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1456,6 +1456,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, op->ldpc_dec.tb_params.ea : op->ldpc_dec.tb_params.eb; + if (unlikely(check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + (op->ldpc_dec.harq_combined_input.length == 0))) { + rte_bbdev_log(WARNING, "Null HARQ input size provided"); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); fcw->hcout_en = check_bit(op->ldpc_dec.op_flags, @@ -1511,6 +1519,20 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->hcin_offset = 0; fcw->hcin_size1 = 0; } + /* Enforce additional check on FCW validity */ + uint32_t max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, 64); + if ((fcw->hcin_size0 > max_hc_in) || + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || + ((fcw->hcin_size0 > fcw->hcin_offset) && + (fcw->hcin_size1 != 0))) { + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", + fcw->hcin_size0, fcw->hcin_size1, + fcw->hcin_offset, + fcw->ncb, fcw->nfiller); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + fcw->hcin_en = 0; + } fcw->itmax = op->ldpc_dec.iter_max; fcw->itstop = check_bit(op->ldpc_dec.op_flags, @@ -1539,10 +1561,19 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; - l = k0_p + fcw->rm_e; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); harq_out_length = (uint16_t) fcw->hcin_size0; - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; + harq_out_length = RTE_MAX(harq_out_length, l); + /* Stronger alignment when in compression mode */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 256); + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64); + /* Stronger alignment when in compression mode enforced again */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, 256); if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && harq_prun) { fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; @@ -1553,6 +1584,13 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->hcout_size1 = 0; fcw->hcout_offset = 0; } + if (fcw->hcout_size0 == 0) { + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", + fcw->hcout_size0); + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + fcw->hcout_en = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { @@ -1594,6 +1632,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, /* Disable HARQ input in that case to carry forward */ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; } + if (unlikely(fcw->rm_e == 0)) { + rte_bbdev_log(WARNING, "Null E input provided"); + fcw->rm_e = 2; + } fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); From patchwork Tue Aug 16 05:52:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115129 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 080C8A00C3; Mon, 15 Aug 2022 23:59:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A84B242BC6; Mon, 15 Aug 2022 23:57:52 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id AD94D4281C for ; Mon, 15 Aug 2022 23:57:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600658; x=1692136658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sYeBck/YenBPJY9Y5dqxl+KQ9qZ6/O8JB7nwVHBYU7c=; b=Q+e2lxahL8XwNC0XCgrTgFwoOhhmkpaKQEAIXhYKAkQqtWNx9YRQ96uD B/35zBV/7hGiZs+2+YdtfegCQy/ISxqzWH6sJKe9mk9/8T1kz/56gwB5o nOPPsAL/ig3gbusQgvjaXNXFNqG2rXxSB5rHyD2f6b/efq0UrEVEQtMEK zXZeAo2eZrbtq4kV/9ZF/jgmYjh6/GvP/396Gi72Peujz9x4M8hvZgCfu t4ukDggRfBoo6DgCuwVDfs7q5UdrLYJYenaj5VdXfPZ1TSZqfRSf2mOoj YpPGscoUFCZo02JaFo/xYlEly68DpLahcxog2t0p501qZ77eEvBVjUlOb Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862731" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862731" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826086" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:38 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 21/33] baseband/acc100: update uplink CB input length Date: Mon, 15 Aug 2022 22:52:46 -0700 Message-Id: <20220816055258.107564-22-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use the FCW E parameter for rate matching as the code block input length. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 0e91205c49..a404a06e55 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2174,7 +2174,7 @@ acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, crc24_overlap = 24; /* Compute some LDPC BG lengths */ - input_length = dec->cb_params.e; + input_length = fcw->rm_e; if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION)) input_length = (input_length * 3 + 3) / 4; From patchwork Tue Aug 16 05:52:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115130 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F211AA00C3; Tue, 16 Aug 2022 00:00:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6843842BE5; Mon, 15 Aug 2022 23:57:54 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 4F4A44281C for ; Mon, 15 Aug 2022 23:57:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600659; x=1692136659; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mX/mCbzTPLXYpXV+ZJPcvlVpbPbTjFLRNWJOFg9blRI=; b=JiqBQJ4vJF1S2z/gJct9YozHZ9BgmZpiJ5TbUmmmxibkaTaZNr6JikeT i/llY9hnrEZ/Jhye9y2PxmERhVKeAeWpJ6yrTbPTVC5wPgL+8kXSuABGR F8jol9OSB6t/KkunNIiw0wKOzAWXjiRu6kdZRSA34NP0KZq0VwzXtZI++ 0ZJHYt3iB96I5JK3VIe5Bh2o9NY4ewstGaL5Ni6r57dtR119sbZM/LdBf j+wG8fJ9w47duaJUvra5n5c5HvvzC+D1eRMG+5o/CWnNvGgneELGeD7bJ CjyLe42YtS8gSWNCJRAjMU51WleS2Iv/zr9HWGYlinstPwjTwYvnKfaQq g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862732" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862732" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826092" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:38 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 22/33] baseband/acc100: rename ldpc encode function arg Date: Mon, 15 Aug 2022 22:52:47 -0700 Message-Id: <20220816055258.107564-23-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Rename total_enqueued_cbs to total_enqueued_descs in the enqueue_ldpc_enc_n_op_cb function. No functional impact. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index a404a06e55..93d6db740d 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -2978,10 +2978,13 @@ enqueue_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, return 1; } -/* Enqueue one encode operations for ACC100 device in CB mode */ + +/* Enqueue one encode operations for ACC100 device in CB mode + * multiplexed on the same descriptor + */ static inline int enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, - uint16_t total_enqueued_cbs, int16_t num) + uint16_t total_enqueued_descs, int16_t num) { union acc100_dma_desc *desc = NULL; uint32_t out_length; @@ -2991,14 +2994,13 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops, struct rte_bbdev_op_ldpc_enc *enc = &ops[0]->ldpc_enc; #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE - /* Validate op structure */ if (validate_ldpc_enc_op(ops[0], q) == -1) { rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif - uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) + uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; acc100_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0); From patchwork Tue Aug 16 05:52:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115131 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A78B2A00C3; Tue, 16 Aug 2022 00:00:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 37B5342BEB; Mon, 15 Aug 2022 23:57:55 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 9DF5D4282B for ; Mon, 15 Aug 2022 23:57:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600659; x=1692136659; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AqbK5MszwyJ3YaCN/RhGXecoBuo/AKl7B04/C3yHmT0=; b=VWTkxZ+RBjoTLLwzbm6xpewjS51GnbvltnuQT0BpTieOcfBZZicFlaUx 0zaqJ5yvLq6pU2+0lLY1ObBnqEOoAgsvyXa9YCDJnqWrYVg1ce5O/Pi2H saOLag6Wiiv1kIW5FUPIy1ZXog/sXtsg9XKKSJ+fPSva74GwilnSwHMBZ qAzG6dVmFc6Wcu5bF7RfzwCZmIBOhQiei/BkRCtWfMxiPs7VP+F1DqNAI 8CohntQo9oMgLbbp/M/tphmsXJLECgtj1iFXVkcFcs7wiNcjz9TS8RqRk +XdCMkcbXlMX8NeaWvgw8MpU1eqJ/IE0CEJn5JdHQKe0Tp7SNOxanjM0I g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862735" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862735" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826098" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:38 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 23/33] baseband/acc100: update log messages Date: Mon, 15 Aug 2022 22:52:48 -0700 Message-Id: <20220816055258.107564-24-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add extra values for some log messages. No functional impact. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 93d6db740d..8240df76cc 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1173,6 +1173,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, /* Read and save the populated config from ACC100 registers */ fetch_acc100_config(dev); + /* Check the status of device */ dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; /* Expose number of queues */ @@ -3255,7 +3256,7 @@ enqueue_ldpc_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op, { #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -4178,8 +4179,9 @@ acc100_enqueue_status(struct rte_bbdev_queue_data *q_data, { q_data->enqueue_status = status; q_data->queue_stats.enqueue_status_count[status]++; - rte_bbdev_log(WARNING, "Enqueue Status: %d %#"PRIx64"", - status, + + rte_bbdev_log(WARNING, "Enqueue Status: %s %#"PRIx64"", + rte_bbdev_enqueue_status_str(status), q_data->queue_stats.enqueue_status_count[status]); } @@ -4879,6 +4881,7 @@ dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data, return -1; rsp.val = atom_desc.rsp.val; + rte_bbdev_log_debug("Resp. desc %p: %x\n", desc, rsp.val); /* Dequeue */ op = desc->req.op_addr; @@ -4961,8 +4964,9 @@ dequeue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op **ref_op, atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, - rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", + desc, rsp.val, + cb_idx, cbs_in_tb); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0); From patchwork Tue Aug 16 05:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115132 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 72EE7A00C3; Tue, 16 Aug 2022 00:00:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 185CB42BF4; Mon, 15 Aug 2022 23:57:56 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id E6A614282D for ; Mon, 15 Aug 2022 23:57:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600660; x=1692136660; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NlaHLg/pYuzMm26lQqDnCCakKSvZzxkzk/AIeT1hyAs=; b=PJKbUlYXHXgsxwyHlRQKKrE7hUmtXcxpzVD44Lc136OIZifg+27X+rnh vp5CNyUxXYM8l+3/k91cOZRs7DXuxbGDzU/IuNwSsm8XkUzQL3SPnmVz1 iGU0wMfBa6o20fwtqirraE8Myw8MnP2GXnIsRTmdm3SpyAPV7ffDAiNdd dQHL5KqUOjcj0mElPs3mlBV8dPJwKwLPlB8EhY+9Pq+CSMOFkgFr+30DT mJBjKsVOsiKveIgEsev5oJ2H0zTLbuviFccIppwgbgiCfjGsw7Nh/dGnd CnEtdpZ233p2f54KRlYHeW0ke5yHF3hX9prbSfrS0M7TQ+zASRSdMtRnB A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862740" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862740" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826102" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 24/33] baseband/acc100: allocate ring/queue mem when NULL Date: Mon, 15 Aug 2022 22:52:49 -0700 Message-Id: <20220816055258.107564-25-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allocate info ring, tail pointers and HARQ layout memory for a device only if it hasn't already been allocated. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/acc100_pmd.h | 9 ++++++--- drivers/baseband/acc100/rte_acc100_pmd.c | 9 ++++++--- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/baseband/acc100/acc100_pmd.h b/drivers/baseband/acc100/acc100_pmd.h index 4a8d2e17ec..f9ccb1ea8e 100644 --- a/drivers/baseband/acc100/acc100_pmd.h +++ b/drivers/baseband/acc100/acc100_pmd.h @@ -61,8 +61,10 @@ #define ACC100_SIZE_64MBYTE (64*1024*1024) /* Number of elements in an Info Ring */ #define ACC100_INFO_RING_NUM_ENTRIES 1024 -/* Number of elements in HARQ layout memory */ -#define ACC100_HARQ_LAYOUT (64*1024*1024) +/* Number of elements in HARQ layout memory + * 128M x 32kB = 4GB addressable memory + */ +#define ACC100_HARQ_LAYOUT (128*1024*1024) /* Assume offset for HARQ in memory */ #define ACC100_HARQ_OFFSET (32*1024) #define ACC100_HARQ_OFFSET_SHIFT 15 @@ -215,7 +217,8 @@ union acc100_dma_rsp_desc { timestampEn:1, iterCountFrac:8, iter_cnt:8, - rsrvd3:6, + harq_failure:1, + rsrvd3:5, sdone:1, fdone:1; uint32_t add_info_0; diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 8240df76cc..429cda2c9f 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -582,7 +582,8 @@ allocate_info_ring(struct rte_bbdev *dev) else reg_addr = &vf_reg_addr; /* Allocate InfoRing */ - d->info_ring = rte_zmalloc_socket("Info Ring", + if (d->info_ring == NULL) + d->info_ring = rte_zmalloc_socket("Info Ring", ACC100_INFO_RING_NUM_ENTRIES * sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, dev->data->socket_id); @@ -679,7 +680,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) acc100_reg_write(d, reg_addr->ring_size, value); /* Configure tail pointer for use when SDONE enabled */ - d->tail_ptrs = rte_zmalloc_socket( + if (d->tail_ptrs == NULL) + d->tail_ptrs = rte_zmalloc_socket( dev->device->driver->name, ACC100_NUM_QGRPS * ACC100_NUM_AQS * sizeof(uint32_t), RTE_CACHE_LINE_SIZE, socket_id); @@ -711,7 +713,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Continue */ } - d->harq_layout = rte_zmalloc_socket("HARQ Layout", + if (d->harq_layout == NULL) + d->harq_layout = rte_zmalloc_socket("HARQ Layout", ACC100_HARQ_LAYOUT * sizeof(*d->harq_layout), RTE_CACHE_LINE_SIZE, dev->data->socket_id); if (d->harq_layout == NULL) { From patchwork Tue Aug 16 05:52:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115133 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 43038A00C3; Tue, 16 Aug 2022 00:00:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D619A42BFC; Mon, 15 Aug 2022 23:57:56 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 2ECE742B6D for ; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600660; x=1692136660; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3ObS5mcQeDfJN3tr8IsUeO+EsLNBvLKgvWTpFn+en08=; b=AqKuyOAXr2M4tdQZUApYaninrwxezH2BoeP2Nz85bTp5P4t40rSdNPzn KdQB48vX30eivfQMLrXc6/932e5WiJLgY11CeEZ7PIDLhHuaNEnNZ8BKO 9Wd3Nwc7/vz2kCUs7LLZA2apGbZLQsSJ8nDW5wyQcws3cOSsgZKfbiUZm +WfEuwxZWLj3OAANDubXemyuAWcTOYT0VES+06IZ+VOGARl8uycconPUJ ylenFuBk+Y0hmJW7gOYv0o2GDG9ODaClZ95O7MKphXD6E41Wl5EpAef7s iNZNAcXG0HHVcjMUM7hHjMSB9C4tI5ryAZGQZOwizJg9G4BhnPGJbnE0t g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862742" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862742" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826105" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 25/33] baseband/acc100: store FCW from first CB descriptor Date: Mon, 15 Aug 2022 22:52:50 -0700 Message-Id: <20220816055258.107564-26-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the descriptor from the first code block from a transport block. Copy the LDPC FCW from the first descriptor into the rest of the CBs in that TB. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 429cda2c9f..47156fda86 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3883,6 +3883,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, uint16_t total_enqueued_cbs, uint8_t cbs_in_tb) { union acc100_dma_desc *desc = NULL; + union acc100_dma_desc *desc_first = NULL; int ret; uint8_t r, c; uint32_t in_offset, h_out_offset, @@ -3901,6 +3902,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask); desc = q->ring_addr + desc_idx; + desc_first = desc; uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET; union acc100_harq_layout_data *harq_layout = q->d->harq_layout; q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); @@ -3926,6 +3928,8 @@ enqueue_ldpc_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, & q->sw_ring_wrap_mask); desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset; desc->req.data_ptrs[0].blen = ACC100_FCW_LD_BLEN; + rte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld, + ACC100_FCW_LD_BLEN); ret = acc100_dma_desc_ld_fill(op, &desc->req, &input, h_output, &in_offset, &h_out_offset, &h_out_length, From patchwork Tue Aug 16 05:52:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115134 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DAAA9A00C3; Tue, 16 Aug 2022 00:00:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9EFA542C06; Mon, 15 Aug 2022 23:57:57 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 6F9564282D for ; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600660; x=1692136660; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T6rigay+8tvM/Cd558nK+vhSOOxRKi2Yi5pCWcnDMLI=; b=Sox5V/fB+LOLG1PubQ+xbAonxg47wr7N3drm9KNQ+wKmXajiAcwdCP/Y JHpnrsGQEvK1wBsjOX+m+2jyq0bFrewu3Hux/tRJgz2AylvlRSizHaiCU Sl2Ks5Vl8HHJFj1t8YdhYsvGkt/wGQ43jPQSTMnUZO48OSygjGWlfzRJ/ 6F0rM3PvbzgnPdcLK7gVbgww82QoUuOG8ORCeitr5J04Tz7Ag2U16uNtI vxuevVUlhPD5+fQUQSy55znVxxqo8Pjkb47O02Qe2Wm6QOXWEiFCeu1Cf O+EVAA0GivwcJE7t+4UYfEwNNjo7R4wb5vXtcJVIm00FyrwfYb8FHsilX w==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862743" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862743" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826109" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:39 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 26/33] baseband/acc100: remove input error check from enc Date: Mon, 15 Aug 2022 22:52:51 -0700 Message-Id: <20220816055258.107564-27-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Input data error check is not needed in encoder functions. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 47156fda86..188b794165 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -4712,9 +4712,6 @@ dequeue_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, /* Clearing status, it will be set based on response */ op->status = 0; - - op->status |= ((rsp.input_err) - ? (1 << RTE_BBDEV_DATA_ERROR) : 0); op->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0); op->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0); @@ -4792,8 +4789,6 @@ dequeue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op **ref_op, rsp.val, descs_in_tb, desc->req.numCBs); - op->status |= ((rsp.input_err) - ? (1 << RTE_BBDEV_DATA_ERROR) : 0); op->status |= ((rsp.dma_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0); op->status |= ((rsp.fcw_err) ? (1 << RTE_BBDEV_DRV_ERROR) : 0); From patchwork Tue Aug 16 05:52:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115135 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0A9AA00C4; Tue, 16 Aug 2022 00:00:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6029542C10; Mon, 15 Aug 2022 23:57:58 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 10DD042B70 for ; Mon, 15 Aug 2022 23:57:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600661; x=1692136661; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LUjMYwH3LLc/m/2bPBmJhZwdRA0N8QgD9Fwh6xVShbM=; b=e445B//QrFWcYf3IgePMZEh91ALIx6/LzRjoXA9YuRC0hxxi4SzgOOAv B9m6iKMq1fKELF91U7PoU/TrwYcsP4qnIaUThHc5XA0dwhpoSXHrKGLCq E/LCXKKLlKL10RZgG6FLo8SgtnnUqrMsaxw3yUcJNV0XYnqTo9mOzENEn 3vSm+h+xixQFdA5VE694FyMde5rujjIXrhB3JTsZ/9JkvTm53NlnXVFkR SOZYXBvA+pQb8LDKt5Y6UUslR9TUhaghrJURDgoOCaJ90K888z4wH52qR 2OKeMu0nqo0vTLcfxfm/pXWk/2gaRwZBZ6nySYXZQ4keoR2gz2moNJE07 Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862745" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862745" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826116" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:40 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 27/33] baseband/acc100: make desc optimization optional Date: Mon, 15 Aug 2022 22:52:52 -0700 Message-Id: <20220816055258.107564-28-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add ACC100_DESC_OPTIMIZATION flag to enable muxing of encode operations with common FCW. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 188b794165..714eb3f2b5 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -4580,9 +4580,10 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, break; } avail -= 1; - +#ifdef ACC100_DESC_OPTIMIZATION if (i > 0) same_op = cmp_ldpc_dec_op(&ops[i-1]); +#endif rte_bbdev_log(INFO, "Op %d %d %d %d %d %d %d %d %d %d %d %d\n", i, ops[i]->ldpc_dec.op_flags, ops[i]->ldpc_dec.rv_index, ops[i]->ldpc_dec.iter_max, ops[i]->ldpc_dec.iter_count, From patchwork Tue Aug 16 05:52:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115136 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C89E4A00C3; Tue, 16 Aug 2022 00:00:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 462E742C18; Mon, 15 Aug 2022 23:57:59 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 6433242B72 for ; Mon, 15 Aug 2022 23:57:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600661; x=1692136661; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uPZoEbEX4mJj2E2IOp7KGzEcjFjQY4w/GVi9Llb7A8Q=; b=BFrZ6BtrrXfc/28PQ3Or8vEKusLuI7xIbfwZ1mS+7hLWF8M+CYSifWb9 Pmhrq0UtUeyJnw2f3MQ6xQic9owvNCe2Az8mSICTCqwf8psVv+iXKKlDX /vyLPfYHpkxL6H1AcoB0EvNzF0vVDkMBgG0OVWZWSFksHx8v1VYEcnX8i xnUw6QF4VRb6qeyDmO4a0IvmyHs1Utzok+pgR8qKOlQ96Vn2a0KRIUfSj RrgIr37oFNVbv3Y9u27ipW4J2UlZ+ekb0I33ntattKSfAZLu08vaIUGjn DD3VPcxyzrMfCHupznqpk3j2Cof96b0m/9L6/s+TS46RjwseoFbvi9rUz A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862746" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862746" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826119" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:40 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 28/33] baseband/acc100: update device info Date: Mon, 15 Aug 2022 22:52:53 -0700 Message-Id: <20220816055258.107564-29-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove unused capabilities, use dummy operation as start count for number of queues. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 714eb3f2b5..11254fac74 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1082,7 +1082,6 @@ acc100_dev_info_get(struct rte_bbdev *dev, { struct acc100_device *d = dev->data->dev_private; int i; - static const struct rte_bbdev_op_cap bbdev_capabilities[] = { { .type = RTE_BBDEV_OP_TURBO_DEC, @@ -1094,7 +1093,6 @@ acc100_dev_info_get(struct rte_bbdev *dev, RTE_BBDEV_TURBO_EARLY_TERMINATION | RTE_BBDEV_TURBO_DEC_INTERRUPTS | RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN | - RTE_BBDEV_TURBO_MAP_DEC | RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | RTE_BBDEV_TURBO_DEC_CRC_24B_DROP | RTE_BBDEV_TURBO_DEC_SCATTER_GATHER, @@ -1189,12 +1187,13 @@ acc100_dev_info_get(struct rte_bbdev *dev, d->acc100_conf.q_ul_5g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = d->acc100_conf.q_dl_5g.num_aqs_per_groups * d->acc100_conf.q_dl_5g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_FFT] = 0; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d->acc100_conf.q_ul_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d->acc100_conf.q_dl_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d->acc100_conf.q_ul_5g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d->acc100_conf.q_dl_5g.num_qgroups; dev_info->max_num_queues = 0; - for (i = RTE_BBDEV_OP_TURBO_DEC; i < RTE_BBDEV_OP_LDPC_ENC; i++) + for (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_LDPC_ENC; i++) dev_info->max_num_queues += dev_info->num_queues[i]; dev_info->queue_size_lim = ACC100_MAX_QUEUE_DEPTH; dev_info->hardware_accelerated = true; From patchwork Tue Aug 16 05:52:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115137 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 68F8FA00C3; Tue, 16 Aug 2022 00:00:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 22AF042C21; Mon, 15 Aug 2022 23:58:00 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 8090442B73 for ; Mon, 15 Aug 2022 23:57:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600661; x=1692136661; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4qhAG2Qg8HuB5QMWFOhQ4i3zru0/KKCjWSDDxKbgy44=; b=IV+wVo3Kqh/kNYQ5m4aFyYQBsFY1pJwtrezXckQp64N5+k59yA03LauD UBubm5eCyB4yPnVFfmJ3Oqk8zK26GqVa601U8Hsm2ahd+eNS9tjwZfNFx YffxebqYBed3Z3yGWyLWs5PWUSom3QVyek7aFdWD59lkh7n6ZGXcuPXsC GK+D9ogygdVIlkT94S9zfO7/HX/7qDLrk7Jlw3wUS2kV8wqzrT6YzUtKP PyPUPjrzZPBAfD2UXAYNgD6OnYlENgOWVrwJXe+10nVd36wKtljI9aV/b 280Lti00a/yCoPtktVmQ66nGosh/CTMno+rLt4Jeb2PqezkKyrNptiy95 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862748" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862748" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826122" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:40 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 29/33] baseband/acc100: reduce input length for CRC24B Date: Mon, 15 Aug 2022 22:52:54 -0700 Message-Id: <20220816055258.107564-30-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Input length should be reduced only for CRC24B. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 11254fac74..7a4e6bd101 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1989,8 +1989,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c; in_length_in_bits = K - enc->n_filler; - if ((enc->op_flags & RTE_BBDEV_LDPC_CRC_24A_ATTACH) || - (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH) in_length_in_bits -= 24; in_length_in_bytes = in_length_in_bits >> 3; From patchwork Tue Aug 16 05:52:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115138 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3274A00C4; Tue, 16 Aug 2022 00:00:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E22B442BD7; Mon, 15 Aug 2022 23:58:00 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id BEDAD42B74 for ; Mon, 15 Aug 2022 23:57:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600662; x=1692136662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ciZtDSLBGq44N/8Erru+J0r/nejxbbEJoRiLLI/2ST0=; b=GkDJV2gIhQBBT3nbyEJqIcIqq8ndBlurKy4pacbk//0CRlfWdMkwbxT8 j3mIKYXDmPxjuSNzB6gNK4tcCWZrEvmbUkInaGdxdwK5cVwq/Z+k/5FnJ yUAa4k/BrQHCfOireXW4A3F5eFnYONj8riRQWthijzzuH16BNDcKYbxaU luDLSacYuTG2t294elo5/RKjGoad7POgM/YbZu6UC/7dY6QkkLhbWArCJ PIGYqQn1BQCicfywO2ipVjfQa+ACx/gpcUQ4aRcn91Ewor0tF3Wlz9+44 hEAq6Xix2sD8Ub6crlBsiMVVszEpfdfDHkkE5nSsGGknC6m1wQ3bffSVA g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862749" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862749" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826125" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:41 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 30/33] baseband/acc100: initialize ring data value Date: Mon, 15 Aug 2022 22:52:55 -0700 Message-Id: <20220816055258.107564-31-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Initialize ring data value to 0 only for PF error interrupts or for doorbell VF2PF interrupt. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 7a4e6bd101..a388a9ce3d 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -437,11 +437,12 @@ acc100_check_ir(struct acc100_device *acc100_dev) while (ring_data->valid) { if ((ring_data->int_nb < ACC100_PF_INT_DMA_DL_DESC_IRQ) || ( ring_data->int_nb > - ACC100_PF_INT_DMA_DL5G_DESC_IRQ)) + ACC100_PF_INT_DMA_DL5G_DESC_IRQ)) { rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x", ring_data->int_nb, ring_data->detailed_info); - /* Initialize Info Ring entry and move forward */ - ring_data->val = 0; + /* Initialize Info Ring entry and move forward */ + ring_data->val = 0; + } info_ring_head++; ring_data = acc100_dev->info_ring + (info_ring_head & ACC100_INFO_RING_MASK); From patchwork Tue Aug 16 05:52:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115139 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 467DEA00C4; Tue, 16 Aug 2022 00:00:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B845A42C27; Mon, 15 Aug 2022 23:58:01 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 6091E42B73 for ; Mon, 15 Aug 2022 23:57:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600662; x=1692136662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mS+iHQ40T/syL+2H5AekgFFscZbnx3pis7Sgj8KS48w=; b=BZ0gXqMZYWx4Sz9fq5762XbHeHSrkaENP0kN5FGvlBjl1YQhtn59unB8 rgZargN1ILOlW/JekF1xFN7JBailOj/gIwv1bNHDTiOidgI08C4zHQoeL 7oWbSzLnsTzATxFrMGGvNmMtvtHBV1AAG/kCu5paNfaLZe+78i0501Uta gFXvUzMu8P5cfE2dL3aANMgUzjUr4mOMY5M4fb7zqTw/ViUv3eSbrw8Mh pX6/L/mozuzdL/+UpugAkq4A8NKJQ54wF4Ezok27kxCx3AVEFp3yhYRgW bvyKfmM/Qm9AwZlaGiyT7t7gBm3s1XGkZtp04cdEHKjzuCANTseU7tWtY g==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862751" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862751" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826131" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:41 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 31/33] baseband/acc100: update debug print for LDPC FCW Date: Mon, 15 Aug 2022 22:52:56 -0700 Message-Id: <20220816055258.107564-32-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Print full size of FCW LDPC structure on debug messages. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index a388a9ce3d..125139c3bb 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3867,7 +3867,7 @@ enqueue_ldpc_dec_one_op_cb(struct acc100_queue *q, struct rte_bbdev_dec_op *op, #ifdef RTE_LIBRTE_BBDEV_DEBUG rte_memdump(stderr, "FCW", &desc->req.fcw_ld, - sizeof(desc->req.fcw_ld) - 8); + sizeof(desc->req.fcw_ld)); rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); #endif From patchwork Tue Aug 16 05:52:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115141 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74C37A00C3; Tue, 16 Aug 2022 00:01:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6D30342C31; Mon, 15 Aug 2022 23:58:03 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id B599D42B7B for ; Mon, 15 Aug 2022 23:57:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600662; x=1692136662; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r64YDbt7Szw8CVSD1LwLBBZMRsvnEOVK1Lm8XjHf3hY=; b=jkoA7wUbX2ytqBAi4oRGDkoTPzJd3vA5KdeKxxMUUFYg2FOZIuiMwzUw PZ47N8QmRcX2WpxbaPlrxfsmQ/NunKXWGjB/csL/8Lf0VYuvXQzrdE4bz LgXJC1RD/7/HKUTZYjkt7N0GS6+kcrE8/I4LlZ5+21tr31qEBgWP8yNX6 CBILWYWqEUpP4CPxpWTXBHlSw+oK5MWS8mcDX/mDsMQzs7ZY7fe4Naix7 70K1F5q80tl7TcdKyCwXSBinXs0dXPfO2ZiCAVXCzndBNokwWdRcXxXGR cAt56k8CFCJYp2LbSWP77T9u6qz0+8PxzPauHhNYJmX+3E+Ak79k9YvDo A==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862753" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862753" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826135" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:41 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 32/33] baseband/acc100: set device min alignment to 1 Date: Mon, 15 Aug 2022 22:52:57 -0700 Message-Id: <20220816055258.107564-33-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Minimum alignment of buffers set to 1 byte. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 125139c3bb..7755d6402f 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1204,7 +1204,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, d->acc100_conf.q_ul_4g.num_qgroups - 1; dev_info->default_queue_conf = default_queue_conf; dev_info->cpu_flag_reqs = NULL; - dev_info->min_alignment = 64; + dev_info->min_alignment = 1; dev_info->capabilities = bbdev_capabilities; #ifdef ACC100_EXT_MEM dev_info->harq_buffer_size = d->ddr_size; From patchwork Tue Aug 16 05:52:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 115140 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F070A00C3; Tue, 16 Aug 2022 00:01:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 93A7B42C2D; Mon, 15 Aug 2022 23:58:02 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id C1FF142B7C for ; Mon, 15 Aug 2022 23:57:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660600663; x=1692136663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GwPe4C09Skcl+FK+yqIlrcVE+s7NOjY6kUeLHRWrlAs=; b=RrO14JvBtK2FPjhw4SdyXmdqxxz1+u/HkyFEkS+cQT4OSio1jgMJ/bWP yMmzRdGtFuj8Pj5jug1Y0RGdTSQRgdXLWa7tgZcSslLcMef9kql7q7Apf 5XPJpfmFZqwb2kMuxHATkcY//lFNC5UnY2eL4w0dMnc4aU25i9ht3adtf 7X8Eh6wBC9xPmXXpQnmgLAU5Oa3CHADowZusMClmmzYBMstioUlf6JAYV lbMJOTCwrIDoVNDz1ZirdKrnrmkkdKLUahWoajEDhJmONsnGmqh1oaR1A DwCppSmeiYzj3+/cD/tKwqon+h+xC6UxBXf4Z0rH7+ssECS85znn0ceCa Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10440"; a="292862754" X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="292862754" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2022 14:57:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,239,1654585200"; d="scan'208";a="666826138" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga008.fm.intel.com with ESMTP; 15 Aug 2022 14:57:42 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v1 33/33] baseband/acc100: update meson file sdk dependency Date: Mon, 15 Aug 2022 22:52:58 -0700 Message-Id: <20220816055258.107564-34-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220816055258.107564-1-hernan.vargas@intel.com> References: <20220816055258.107564-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update meson files with FlexRAN SDK dependency. Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/meson.build | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/baseband/acc100/meson.build b/drivers/baseband/acc100/meson.build index 9a1a3b8b07..3b934a25ca 100644 --- a/drivers/baseband/acc100/meson.build +++ b/drivers/baseband/acc100/meson.build @@ -1,6 +1,27 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2020 Intel Corporation +# check for FlexRAN SDK libraries +dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false) + +if dep_dec5g.found() + ext_deps += cc.find_library('libstdc++', required: true) + ext_deps += cc.find_library('libirc', required: true) + ext_deps += cc.find_library('libimf', required: true) + ext_deps += cc.find_library('libipps', required: true) + ext_deps += cc.find_library('libsvml', required: true) + ext_deps += dep_dec5g + ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true) + ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true) + ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true) + ext_deps += dependency('flexran_sdk_turbo', required: true) + ext_deps += dependency('flexran_sdk_crc', required: true) + ext_deps += dependency('flexran_sdk_rate_matching', required: true) + ext_deps += dependency('flexran_sdk_common', required: true) + cflags += ['-DRTE_BBDEV_SDK_AVX2'] + cflags += ['-DRTE_BBDEV_SDK_AVX512'] +endif + deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci'] sources = files('rte_acc100_pmd.c')