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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT093.mail.protection.outlook.com (10.13.172.235) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5632.12 via Frontend Transport; Mon, 19 Sep 2022 16:38:58 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Mon, 19 Sep 2022 09:38:47 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 19 Sep 2022 09:38:45 -0700 From: Dariusz Sosnowski To: Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: Subject: [PATCH 1/7] ethdev: introduce hairpin memory capabilities Date: Mon, 19 Sep 2022 16:37:24 +0000 Message-ID: <20220919163731.1540454-2-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220919163731.1540454-1-dsosnowski@nvidia.com> References: <20220919163731.1540454-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT093:EE_|PH8PR12MB7027:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ec2470a-e5a1-4890-2082-08da9a5d737a X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230022)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199015)(40470700004)(36840700001)(46966006)(2906002)(8936002)(36756003)(7636003)(356005)(82740400003)(47076005)(86362001)(36860700001)(82310400005)(83380400001)(7696005)(6286002)(6666004)(55016003)(426003)(1076003)(2616005)(26005)(186003)(40460700003)(16526019)(336012)(70586007)(110136005)(5660300002)(4326008)(478600001)(70206006)(8676002)(316002)(40480700001)(41300700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:38:58.4803 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ec2470a-e5a1-4890-2082-08da9a5d737a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT093.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7027 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch introduces new hairpin queue configuration options through rte_eth_hairpin_conf struct, allowing to tune Rx and Tx hairpin queues memory configuration. Hairpin configuration is extended with the following fields: - use_locked_device_memory - If set, PMD will use specialized on-device memory to store RX or TX hairpin queue data. - use_rte_memory - If set, PMD will use DPDK-managed memory to store RX or TX hairpin queue data. - force_memory - If set, PMD will be forced to use provided memory settings. If no appropriate resources are available, then device start will fail. If unset and no resources are available, PMD will fallback to using default type of resource for given queue. Hairpin capabilities are also extended, to allow verification of support of given hairpin memory configurations. Struct rte_eth_hairpin_cap is extended with two additional fields of type rte_eth_hairpin_queue_cap: - rx_cap - memory capabilities of hairpin RX queues. - tx_cap - memory capabilities of hairpin TX queues. Struct rte_eth_hairpin_queue_cap exposes whether given queue type supports use_locked_device_memory and use_rte_memory flags. Signed-off-by: Dariusz Sosnowski --- lib/ethdev/rte_ethdev.c | 44 ++++++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 65 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 108 insertions(+), 1 deletion(-) diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 1979dc0850..edcec08231 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -1945,6 +1945,28 @@ rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id, conf->peer_count, cap.max_rx_2_tx); return -EINVAL; } + if (conf->use_locked_device_memory && !cap.rx_cap.locked_device_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use locked device memory for Rx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_rte_memory && !cap.rx_cap.rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use DPDK memory for Rx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_locked_device_memory && conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use mutually exclusive memory settings for Rx queue"); + return -EINVAL; + } + if (conf->force_memory && + !conf->use_locked_device_memory && + !conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to force Rx queue memory settings, but none is set"); + return -EINVAL; + } if (conf->peer_count == 0) { RTE_ETHDEV_LOG(ERR, "Invalid value for number of peers for Rx queue(=%u), should be: > 0", @@ -2111,6 +2133,28 @@ rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id, conf->peer_count, cap.max_tx_2_rx); return -EINVAL; } + if (conf->use_locked_device_memory && !cap.tx_cap.locked_device_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use locked device memory for Tx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_rte_memory && !cap.tx_cap.rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use DPDK memory for Tx queue, which is not supported"); + return -EINVAL; + } + if (conf->use_locked_device_memory && conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to use mutually exclusive memory settings for Tx queue"); + return -EINVAL; + } + if (conf->force_memory && + !conf->use_locked_device_memory && + !conf->use_rte_memory) { + RTE_ETHDEV_LOG(ERR, + "Attempt to force Tx queue memory settings, but none is set"); + return -EINVAL; + } if (conf->peer_count == 0) { RTE_ETHDEV_LOG(ERR, "Invalid value for number of peers for Tx queue(=%u), should be: > 0", diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index de9e970d4d..e179b0e79b 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -1273,6 +1273,28 @@ struct rte_eth_txconf { void *reserved_ptrs[2]; /**< Reserved for future fields */ }; +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * A structure used to return the Tx or Rx hairpin queue capabilities that are supported. + */ +struct rte_eth_hairpin_queue_cap { + /** + * When set, a specialized on-device memory type can be used as a backing + * storage for a given hairpin queue type. + */ + uint32_t locked_device_memory:1; + + /** + * When set, memory managed by DPDK can be used as a backing storage + * for a given hairpin queue type. + */ + uint32_t rte_memory:1; + + uint32_t reserved:30; /**< Reserved for future fields */ +}; + /** * @warning * @b EXPERIMENTAL: this API may change, or be removed, without prior notice @@ -1287,6 +1309,8 @@ struct rte_eth_hairpin_cap { /** Max number of Tx queues to be connected to one Rx queue. */ uint16_t max_tx_2_rx; uint16_t max_nb_desc; /**< The max num of descriptors. */ + struct rte_eth_hairpin_queue_cap rx_cap; /**< Rx hairpin queue capabilities. */ + struct rte_eth_hairpin_queue_cap tx_cap; /**< Tx hairpin queue capabilities. */ }; #define RTE_ETH_MAX_HAIRPIN_PEERS 32 @@ -1334,7 +1358,46 @@ struct rte_eth_hairpin_conf { * configured automatically during port start. */ uint32_t manual_bind:1; - uint32_t reserved:14; /**< Reserved bits. */ + + /** + * Use locked device memory as a backing storage. + * + * - When set, PMD will attempt to use on-device memory as a backing storage for descriptors + * and/or data in hairpin queue. + * - When set, PMD will use detault memory type as a backing storage. Please refer to PMD + * documentation for details. + * + * API user should check if PMD supports this configuration flag using + * @see rte_eth_dev_hairpin_capability_get. + */ + uint32_t use_locked_device_memory:1; + + /** + * Use DPDK memory as backing storage. + * + * - When set, PMD will attempt to use memory managed by DPDK as a backing storage + * for descriptors and/or data in hairpin queue. + * - When clear, PMD will use default memory type as a backing storage. Please refer + * to PMD documentation for details. + * + * API user should check if PMD supports this configuration flag using + * @see rte_eth_dev_hairpin_capability_get. + */ + uint32_t use_rte_memory:1; + + /** + * Force usage of hairpin memory configuration. + * + * - When set, PMD will attempt to use specified memory settings and + * if resource allocation fails, then hairpin queue setup will result in an + * error. + * - When clear, PMD will attempt to use specified memory settings and + * if resource allocation fails, then PMD will retry allocation with default + * configuration. + */ + uint32_t force_memory:1; + + uint32_t reserved:11; /**< Reserved bits. */ struct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS]; }; From patchwork Mon Sep 19 16:37:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 116440 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 472DAA00C3; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:39:04.9640 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8882365a-f231-433c-75c7-08da9a5d7757 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6824 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch extends HCA_CAP and SQ Context structs available in PRM. This fields allow checking if NIC supports storing hairpin SQ's WQ buffer in host memory and configuring such memory placement. HCA capabilities are extended with the following fields: - hairpin_sq_wq_in_host_mem - If set, then NIC supports using host memory as a backing storage for hairpin SQ's WQ buffer. - hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic block. SQ Context is extended with hairpin_wq_buffer_type which informs NIC where SQ's WQ buffer will be stored. This field can take the following values: - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be stored in unlocked device memory. - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored in host memory. Buffer is provided by PMD. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 8880a9f3b5..2b12ce0d4c 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -981,6 +981,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, } attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, log_min_stride_wqe_sz); + attr->hairpin_sq_wqe_bb_size = MLX5_GET(cmd_hca_cap_2, hcattr, + hairpin_sq_wqe_bb_size); + attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, + hairpin_sq_wq_in_host_mem); } if (attr->log_min_stride_wqe_sz == 0) attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; @@ -1698,6 +1702,7 @@ mlx5_devx_cmd_create_sq(void *ctx, MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); + MLX5_SET(sqc, sq_ctx, hairpin_wq_buffer_type, sq_attr->hairpin_wq_buffer_type); MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index af6053a788..9ac2d75df4 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -191,6 +191,8 @@ struct mlx5_hca_attr { uint32_t log_max_hairpin_queues:5; uint32_t log_max_hairpin_wq_data_sz:5; uint32_t log_max_hairpin_num_packets:5; + uint32_t hairpin_sq_wqe_bb_size:4; + uint32_t hairpin_sq_wq_in_host_mem:1; uint32_t vhca_id:16; uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; @@ -407,6 +409,7 @@ struct mlx5_devx_create_sq_attr { uint32_t non_wire:1; uint32_t static_sq_wq:1; uint32_t ts_format:2; + uint32_t hairpin_wq_buffer_type:3; uint32_t user_index:24; uint32_t cqn:24; uint32_t packet_pacing_rate_limit_index:16; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 4346279c81..04d35ca845 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2020,7 +2020,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_d8[0x3]; u8 log_max_conn_track_offload[0x5]; u8 reserved_at_e0[0x20]; /* End of DW7. */ - u8 reserved_at_100[0x700]; + u8 reserved_at_100[0x60]; + u8 reserved_at_160[0x3]; + u8 hairpin_sq_wqe_bb_size[0x5]; + u8 hairpin_sq_wq_in_host_mem[0x1]; + u8 reserved_at_169[0x697]; }; struct mlx5_ifc_esw_cap_bits { @@ -2673,6 +2677,11 @@ enum { MLX5_SQC_STATE_ERR = 0x3, }; +enum { + MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0, + MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1, +}; + struct mlx5_ifc_sqc_bits { u8 rlky[0x1]; u8 cd_master[0x1]; @@ -2686,7 +2695,9 @@ struct mlx5_ifc_sqc_bits { u8 hairpin[0x1]; u8 non_wire[0x1]; u8 static_sq_wq[0x1]; - u8 reserved_at_11[0x9]; + u8 reserved_at_11[0x4]; + u8 hairpin_wq_buffer_type[0x3]; + u8 reserved_at_18[0x2]; u8 ts_format[0x02]; u8 reserved_at_1c[0x4]; u8 reserved_at_20[0x8]; From patchwork Mon Sep 19 16:37:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 116441 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C7A45A00C3; Mon, 19 Sep 2022 18:39:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA19F42829; Mon, 19 Sep 2022 18:39:21 +0200 (CEST) Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2042.outbound.protection.outlook.com [40.107.243.42]) by mails.dpdk.org (Postfix) with ESMTP id 21915410E8 for ; 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Mon, 19 Sep 2022 09:39:08 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 19 Sep 2022 09:39:06 -0700 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: Subject: [PATCH 3/7] common/mlx5: add hairpin RQ buffer type capabilities Date: Mon, 19 Sep 2022 16:37:26 +0000 Message-ID: <20220919163731.1540454-4-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220919163731.1540454-1-dsosnowski@nvidia.com> References: <20220919163731.1540454-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT106:EE_|CY5PR12MB6624:EE_ X-MS-Office365-Filtering-Correlation-Id: 81be9133-ad98-4366-61cd-08da9a5d7fff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:39:19.5019 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81be9133-ad98-4366-61cd-08da9a5d7fff X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6624 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds new HCA capability related to hairpin RQs. This new capability, hairpin_data_buffer_locked, indicates whether HCA supports locking data buffer of hairpin RQ in ICMC (Interconnect Context Memory Cache). Struct used to define RQ configuration (RQ context) is extended with hairpin_data_buffer_type field, which configures data buffer for hairpin RQ. It can take the following values: - MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER - hairpin RQ's data buffer is stored in unlocked memory in ICMC. - MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER - hairpin RQ's data buffer is stored in locked memory in ICMC. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 12 ++++++++++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 2b12ce0d4c..95b38783dc 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -985,6 +985,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, hairpin_sq_wqe_bb_size); attr->hairpin_sq_wq_in_host_mem = MLX5_GET(cmd_hca_cap_2, hcattr, hairpin_sq_wq_in_host_mem); + attr->hairpin_data_buffer_locked = MLX5_GET(cmd_hca_cap_2, hcattr, + hairpin_data_buffer_locked); } if (attr->log_min_stride_wqe_sz == 0) attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; @@ -1285,6 +1287,7 @@ mlx5_devx_cmd_create_rq(void *ctx, MLX5_SET(rqc, rq_ctx, state, rq_attr->state); MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); + MLX5_SET(rqc, rq_ctx, hairpin_data_buffer_type, rq_attr->hairpin_data_buffer_type); MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 9ac2d75df4..cceaf3411d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -193,6 +193,7 @@ struct mlx5_hca_attr { uint32_t log_max_hairpin_num_packets:5; uint32_t hairpin_sq_wqe_bb_size:4; uint32_t hairpin_sq_wq_in_host_mem:1; + uint32_t hairpin_data_buffer_locked:1; uint32_t vhca_id:16; uint32_t relaxed_ordering_write:1; uint32_t relaxed_ordering_read:1; @@ -313,6 +314,7 @@ struct mlx5_devx_create_rq_attr { uint32_t state:4; uint32_t flush_in_error_en:1; uint32_t hairpin:1; + uint32_t hairpin_data_buffer_type:3; uint32_t ts_format:2; uint32_t user_index:24; uint32_t cqn:24; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 04d35ca845..9c1c93f916 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2024,7 +2024,8 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_160[0x3]; u8 hairpin_sq_wqe_bb_size[0x5]; u8 hairpin_sq_wq_in_host_mem[0x1]; - u8 reserved_at_169[0x697]; + u8 hairpin_data_buffer_locked[0x1]; + u8 reserved_at_16a[0x696]; }; struct mlx5_ifc_esw_cap_bits { @@ -2304,7 +2305,9 @@ struct mlx5_ifc_rqc_bits { u8 reserved_at_c[0x1]; u8 flush_in_error_en[0x1]; u8 hairpin[0x1]; - u8 reserved_at_f[0xB]; + u8 reserved_at_f[0x6]; + u8 hairpin_data_buffer_type[0x3]; + u8 reserved_at_a8[0x2]; u8 ts_format[0x02]; u8 reserved_at_1c[0x4]; u8 reserved_at_20[0x8]; @@ -2813,6 +2816,11 @@ enum { MLX5_CQE_SIZE_128B = 0x1, }; +enum { + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0, + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1, +}; + struct mlx5_ifc_cqc_bits { u8 status[0x4]; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:39:25.4322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8538fcd7-ce9a-46f6-4682-08da9a5d8388 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6783 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a capability to place hairpin Tx queue in host memory managed by DPDK. This capability is equivalent to storing hairpin SQ's WQ buffer in host memory. Hairpin Tx queue creation is extended with allocating a memory buffer of proper size (calculated from required number of packets and WQE BB size advertised in HCA capabilities). force_memory flag of hairpin queue configuration is also supported. If it is set and: - allocation of memory buffer fails, - or hairpin SQ creation fails, then device start will fail. If it is unset, PMD will fallback to creating the hairpin SQ with WQ buffer located in unlocked device memory. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_devx.c | 119 ++++++++++++++++++++++++++++++--- drivers/net/mlx5/mlx5_ethdev.c | 4 ++ 3 files changed, 116 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 8af84aef50..f564d4b771 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1384,6 +1384,8 @@ struct mlx5_txq_obj { struct mlx5_devx_obj *sq; /* DevX object for Sx queue. */ struct mlx5_devx_obj *tis; /* The TIS object. */ + void *umem_buf_wq_buffer; + struct mlx5dv_devx_umem *umem_obj_wq_buffer; }; struct { struct rte_eth_dev *dev; diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 6886ae1f22..a81b1bae47 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -1185,18 +1185,23 @@ static int mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; struct mlx5_txq_data *txq_data = (*priv->txqs)[idx]; struct mlx5_txq_ctrl *txq_ctrl = container_of(txq_data, struct mlx5_txq_ctrl, txq); - struct mlx5_devx_create_sq_attr attr = { 0 }; + struct mlx5_devx_create_sq_attr dev_mem_attr = { 0 }; + struct mlx5_devx_create_sq_attr host_mem_attr = { 0 }; struct mlx5_txq_obj *tmpl = txq_ctrl->obj; + struct mlx5dv_devx_umem *umem_obj = NULL; + void *umem_buf = NULL; uint32_t max_wq_data; MLX5_ASSERT(txq_data); MLX5_ASSERT(tmpl); tmpl->txq_ctrl = txq_ctrl; - attr.hairpin = 1; - attr.tis_lst_sz = 1; + dev_mem_attr.hairpin = 1; + dev_mem_attr.tis_lst_sz = 1; + dev_mem_attr.tis_num = mlx5_get_txq_tis_num(dev, idx); max_wq_data = priv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz; /* Jumbo frames > 9KB should be supported, and more packets. */ @@ -1208,19 +1213,103 @@ mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) rte_errno = ERANGE; return -rte_errno; } - attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; + dev_mem_attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; } else { - attr.wq_attr.log_hairpin_data_sz = + dev_mem_attr.wq_attr.log_hairpin_data_sz = (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ? max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE; } /* Set the packets number to the maximum value for performance. */ - attr.wq_attr.log_hairpin_num_packets = - attr.wq_attr.log_hairpin_data_sz - + dev_mem_attr.wq_attr.log_hairpin_num_packets = + dev_mem_attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; + dev_mem_attr.hairpin_wq_buffer_type = MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER; + if (txq_ctrl->hairpin_conf.use_rte_memory) { + uint32_t umem_size; + uint32_t umem_dbrec; + size_t alignment = MLX5_WQE_BUF_ALIGNMENT; - attr.tis_num = mlx5_get_txq_tis_num(dev, idx); - tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr); + if (alignment == (size_t)-1) { + DRV_LOG(ERR, "Failed to get WQE buf alignment."); + rte_errno = ENOMEM; + return -rte_errno; + } + /* + * It is assumed that configuration is verified against capabilities + * during queue setup. + */ + MLX5_ASSERT(hca_attr->hairpin_sq_wq_in_host_mem); + MLX5_ASSERT(hca_attr->hairpin_sq_wqe_bb_size > 0); + rte_memcpy(&host_mem_attr, &dev_mem_attr, sizeof(host_mem_attr)); + umem_size = MLX5_WQE_SIZE * + RTE_BIT32(host_mem_attr.wq_attr.log_hairpin_num_packets); + umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); + umem_size += MLX5_DBR_SIZE; + umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size, + alignment, priv->sh->numa_node); + if (umem_buf == NULL && txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(ERR, "Failed to allocate memory for hairpin TX queue"); + rte_errno = ENOMEM; + return -rte_errno; + } else if (umem_buf == NULL && !txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(WARNING, "Failed to allocate memory for hairpin TX queue." + " Falling back to TX queue located on the device."); + goto create_sq_on_device; + } + umem_obj = mlx5_glue->devx_umem_reg(priv->sh->cdev->ctx, + (void *)(uintptr_t)umem_buf, + umem_size, + IBV_ACCESS_LOCAL_WRITE); + if (umem_obj == NULL && txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(ERR, "Failed to register UMEM for hairpin TX queue"); + mlx5_free(umem_buf); + return -rte_errno; + } else if (umem_obj == NULL && !txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(WARNING, "Failed to register UMEM for hairpin TX queue." + " Falling back to TX queue located on the device."); + rte_errno = 0; + mlx5_free(umem_buf); + goto create_sq_on_device; + } + host_mem_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC; + host_mem_attr.wq_attr.wq_umem_valid = 1; + host_mem_attr.wq_attr.wq_umem_id = mlx5_os_get_umem_id(umem_obj); + host_mem_attr.wq_attr.wq_umem_offset = 0; + host_mem_attr.wq_attr.dbr_umem_valid = 1; + host_mem_attr.wq_attr.dbr_umem_id = host_mem_attr.wq_attr.wq_umem_id; + host_mem_attr.wq_attr.dbr_addr = umem_dbrec; + host_mem_attr.wq_attr.log_wq_stride = rte_log2_u32(MLX5_WQE_SIZE); + host_mem_attr.wq_attr.log_wq_sz = + host_mem_attr.wq_attr.log_hairpin_num_packets * + hca_attr->hairpin_sq_wqe_bb_size; + host_mem_attr.wq_attr.log_wq_pg_sz = MLX5_LOG_PAGE_SIZE; + host_mem_attr.hairpin_wq_buffer_type = MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY; + tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &host_mem_attr); + if (!tmpl->sq && txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(ERR, + "Port %u tx hairpin queue %u can't create SQ object.", + dev->data->port_id, idx); + claim_zero(mlx5_glue->devx_umem_dereg(umem_obj)); + mlx5_free(umem_buf); + return -rte_errno; + } else if (!tmpl->sq && !txq_ctrl->hairpin_conf.force_memory) { + DRV_LOG(WARNING, + "Port %u tx hairpin queue %u failed to allocate SQ object" + " using host memory. Falling back to TX queue located" + " on the device", + dev->data->port_id, idx); + rte_errno = 0; + claim_zero(mlx5_glue->devx_umem_dereg(umem_obj)); + mlx5_free(umem_buf); + goto create_sq_on_device; + } + tmpl->umem_buf_wq_buffer = umem_buf; + tmpl->umem_obj_wq_buffer = umem_obj; + return 0; + } + +create_sq_on_device: + tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &dev_mem_attr); if (!tmpl->sq) { DRV_LOG(ERR, "Port %u tx hairpin queue %u can't create SQ object.", @@ -1452,8 +1541,20 @@ mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj) { MLX5_ASSERT(txq_obj); if (txq_obj->txq_ctrl->is_hairpin) { + if (txq_obj->sq) { + claim_zero(mlx5_devx_cmd_destroy(txq_obj->sq)); + txq_obj->sq = NULL; + } if (txq_obj->tis) claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis)); + if (txq_obj->umem_obj_wq_buffer) { + claim_zero(mlx5_glue->devx_umem_dereg(txq_obj->umem_obj_wq_buffer)); + txq_obj->umem_obj_wq_buffer = NULL; + } + if (txq_obj->umem_buf_wq_buffer) { + mlx5_free(txq_obj->umem_buf_wq_buffer); + txq_obj->umem_buf_wq_buffer = NULL; + } #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H) } else { mlx5_txq_release_devx_resources(txq_obj); diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 05c919ed39..7f5b01ac74 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -729,6 +729,7 @@ int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_attr *hca_attr; if (!mlx5_devx_obj_ops_en(priv->sh)) { rte_errno = ENOTSUP; @@ -738,5 +739,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) cap->max_rx_2_tx = 1; cap->max_tx_2_rx = 1; cap->max_nb_desc = 8192; + hca_attr = &priv->sh->cdev->config.hca_attr; + cap->tx_cap.locked_device_memory = 0; + cap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem; return 0; } From patchwork Mon Sep 19 16:37:28 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:39:29.6965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5643d0a-7d70-4ec5-f4c9-08da9a5d8612 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4858 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds a capability to place hairpin Rx queue in locked device memory. This capability is equivalent to storing hairpin RQ's data buffers in locked internal device memory. Hairpin Rx queue creation is extended with requesting that RQ is allocated in locked internal device memory. If allocation fails and force_memory hairpin configuration is set, then hairpin queue creation (and, as a result, device start) fails. If force_memory is unset, then PMD will fallback to allocating memory for hairpin RQ in unlocked internal device memory. To allow such allocation, the user must set HAIRPIN_DATA_BUFFER_LOCK flag in FW using mlxconfig tool. Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- doc/guides/platform/mlx5.rst | 5 ++++ drivers/net/mlx5/mlx5_devx.c | 51 ++++++++++++++++++++++++++++------ drivers/net/mlx5/mlx5_ethdev.c | 2 ++ 3 files changed, 49 insertions(+), 9 deletions(-) diff --git a/doc/guides/platform/mlx5.rst b/doc/guides/platform/mlx5.rst index 38c1fdce4c..88a2961bb4 100644 --- a/doc/guides/platform/mlx5.rst +++ b/doc/guides/platform/mlx5.rst @@ -548,6 +548,11 @@ Below are some firmware configurations listed. REAL_TIME_CLOCK_ENABLE=1 +- allow locking hairpin RQ data buffer in device memory:: + + HAIRPIN_DATA_BUFFER_LOCK=1 + MEMIC_SIZE_LIMIT=0 + .. _mlx5_common_driver_options: diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index a81b1bae47..e65350bd7c 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -468,14 +468,16 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) { uint16_t idx = rxq->idx; struct mlx5_priv *priv = rxq->priv; + struct mlx5_hca_attr *hca_attr __rte_unused = &priv->sh->cdev->config.hca_attr; struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl; - struct mlx5_devx_create_rq_attr attr = { 0 }; + struct mlx5_devx_create_rq_attr unlocked_attr = { 0 }; + struct mlx5_devx_create_rq_attr locked_attr = { 0 }; struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj; uint32_t max_wq_data; MLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL && tmpl != NULL); tmpl->rxq_ctrl = rxq_ctrl; - attr.hairpin = 1; + unlocked_attr.hairpin = 1; max_wq_data = priv->sh->cdev->config.hca_attr.log_max_hairpin_wq_data_sz; /* Jumbo frames > 9KB should be supported, and more packets. */ @@ -487,20 +489,50 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) rte_errno = ERANGE; return -rte_errno; } - attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; + unlocked_attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size; } else { - attr.wq_attr.log_hairpin_data_sz = + unlocked_attr.wq_attr.log_hairpin_data_sz = (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ? max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE; } /* Set the packets number to the maximum value for performance. */ - attr.wq_attr.log_hairpin_num_packets = - attr.wq_attr.log_hairpin_data_sz - + unlocked_attr.wq_attr.log_hairpin_num_packets = + unlocked_attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; - attr.counter_set_id = priv->counter_set_id; + unlocked_attr.counter_set_id = priv->counter_set_id; rxq_ctrl->rxq.delay_drop = priv->config.hp_delay_drop; - attr.delay_drop_en = priv->config.hp_delay_drop; - tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr, + unlocked_attr.delay_drop_en = priv->config.hp_delay_drop; + unlocked_attr.hairpin_data_buffer_type = + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER; + if (rxq->hairpin_conf.use_locked_device_memory) { + /* + * It is assumed that configuration is verified against capabilities + * during queue setup. + */ + MLX5_ASSERT(hca_attr->hairpin_data_buffer_locked); + rte_memcpy(&locked_attr, &unlocked_attr, sizeof(locked_attr)); + locked_attr.hairpin_data_buffer_type = + MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER; + tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &locked_attr, + rxq_ctrl->socket); + if (!tmpl->rq && rxq->hairpin_conf.force_memory) { + DRV_LOG(ERR, "Port %u Rx hairpin queue %u can't create RQ object" + " with locked memory buffer", + priv->dev_data->port_id, idx); + return -rte_errno; + } else if (!tmpl->rq && !rxq->hairpin_conf.force_memory) { + DRV_LOG(WARNING, "Port %u Rx hairpin queue %u can't create RQ object" + " with locked memory buffer. Falling back to unlocked" + " device memory.", + priv->dev_data->port_id, idx); + rte_errno = 0; + goto create_rq_unlocked; + } + goto create_rq_set_state; + } + +create_rq_unlocked: + tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &unlocked_attr, rxq_ctrl->socket); if (!tmpl->rq) { DRV_LOG(ERR, @@ -509,6 +541,7 @@ mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq) rte_errno = errno; return -rte_errno; } +create_rq_set_state: priv->dev_data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN; return 0; } diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 7f5b01ac74..7f400da103 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -740,6 +740,8 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) cap->max_tx_2_rx = 1; cap->max_nb_desc = 8192; hca_attr = &priv->sh->cdev->config.hca_attr; + cap->rx_cap.locked_device_memory = hca_attr->hairpin_data_buffer_locked; + cap->rx_cap.rte_memory = 0; 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For purposes of this configurations the following bits of 32 bit hairpin-mode are reserved: - Bit 8 - If set, then force_memory flag will be set for hairpin RX queue. - Bit 9 - If set, then force_memory flag will be set for hairpin TX queue. - Bits 12-15 - Memory options for hairpin Rx queue: - Bit 12 - If set, then use_locked_device_memory will be set. - Bit 13 - If set, then use_rte_memory will be set. - Bit 14 - Reserved for future use. - Bit 15 - Reserved for future use. - Bits 16-19 - Memory options for hairpin Tx queue: - Bit 16 - If set, then use_locked_device_memory will be set. - Bit 17 - If set, then use_rte_memory will be set. - Bit 18 - Reserved for future use. - Bit 19 - Reserved for future use. Signed-off-by: Dariusz Sosnowski --- app/test-pmd/parameters.c | 2 +- app/test-pmd/testpmd.c | 24 +++++++++++++++++++++++- app/test-pmd/testpmd.h | 2 +- doc/guides/testpmd_app_ug/run_app.rst | 10 ++++++++-- 4 files changed, 33 insertions(+), 5 deletions(-) diff --git a/app/test-pmd/parameters.c b/app/test-pmd/parameters.c index e3c9757f3f..662e6e4a36 100644 --- a/app/test-pmd/parameters.c +++ b/app/test-pmd/parameters.c @@ -1162,7 +1162,7 @@ launch_args_parse(int argc, char** argv) if (errno != 0 || end == optarg) rte_exit(EXIT_FAILURE, "hairpin mode invalid\n"); else - hairpin_mode = (uint16_t)n; + hairpin_mode = (uint32_t)n; } if (!strcmp(lgopts[opt_idx].name, "burst")) { n = atoi(optarg); diff --git a/app/test-pmd/testpmd.c b/app/test-pmd/testpmd.c index addcbcac85..2fbd546073 100644 --- a/app/test-pmd/testpmd.c +++ b/app/test-pmd/testpmd.c @@ -409,7 +409,7 @@ bool setup_on_probe_event = true; uint8_t clear_ptypes = true; /* Hairpin ports configuration mode. */ -uint16_t hairpin_mode; +uint32_t hairpin_mode; /* Pretty printing of ethdev events */ static const char * const eth_event_desc[] = { @@ -2552,6 +2552,16 @@ port_is_started(portid_t port_id) return 1; } +#define HAIRPIN_MODE_RX_FORCE_MEMORY RTE_BIT32(8) +#define HAIRPIN_MODE_TX_FORCE_MEMORY RTE_BIT32(9) + +#define HAIRPIN_MODE_RX_LOCKED_MEMORY RTE_BIT32(12) +#define HAIRPIN_MODE_RX_RTE_MEMORY RTE_BIT32(13) + +#define HAIRPIN_MODE_TX_LOCKED_MEMORY RTE_BIT32(16) +#define HAIRPIN_MODE_TX_RTE_MEMORY RTE_BIT32(17) + + /* Configure the Rx and Tx hairpin queues for the selected port. */ static int setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) @@ -2567,6 +2577,12 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) uint16_t peer_tx_port = pi; uint32_t manual = 1; uint32_t tx_exp = hairpin_mode & 0x10; + uint32_t rx_force_memory = hairpin_mode & HAIRPIN_MODE_RX_FORCE_MEMORY; + uint32_t rx_locked_memory = hairpin_mode & HAIRPIN_MODE_RX_LOCKED_MEMORY; + uint32_t rx_rte_memory = hairpin_mode & HAIRPIN_MODE_RX_RTE_MEMORY; + uint32_t tx_force_memory = hairpin_mode & HAIRPIN_MODE_TX_FORCE_MEMORY; + uint32_t tx_locked_memory = hairpin_mode & HAIRPIN_MODE_TX_LOCKED_MEMORY; + uint32_t tx_rte_memory = hairpin_mode & HAIRPIN_MODE_TX_RTE_MEMORY; if (!(hairpin_mode & 0xf)) { peer_rx_port = pi; @@ -2606,6 +2622,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_rxq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!tx_force_memory; + hairpin_conf.use_locked_device_memory = !!tx_locked_memory; + hairpin_conf.use_rte_memory = !!tx_rte_memory; diag = rte_eth_tx_hairpin_queue_setup (pi, qi, nb_txd, &hairpin_conf); i++; @@ -2629,6 +2648,9 @@ setup_hairpin_queues(portid_t pi, portid_t p_pi, uint16_t cnt_pi) hairpin_conf.peers[0].queue = i + nb_txq; hairpin_conf.manual_bind = !!manual; hairpin_conf.tx_explicit = !!tx_exp; + hairpin_conf.force_memory = !!rx_force_memory; + hairpin_conf.use_locked_device_memory = !!rx_locked_memory; + hairpin_conf.use_rte_memory = !!rx_rte_memory; diag = rte_eth_rx_hairpin_queue_setup (pi, qi, nb_rxd, &hairpin_conf); i++; diff --git a/app/test-pmd/testpmd.h b/app/test-pmd/testpmd.h index fb2f5195d3..bc4d9788fa 100644 --- a/app/test-pmd/testpmd.h +++ b/app/test-pmd/testpmd.h @@ -542,7 +542,7 @@ extern uint16_t stats_period; extern struct rte_eth_xstat_name *xstats_display; extern unsigned int xstats_display_num; -extern uint16_t hairpin_mode; +extern uint32_t hairpin_mode; #ifdef RTE_LIB_LATENCYSTATS extern uint8_t latencystats_enabled; diff --git a/doc/guides/testpmd_app_ug/run_app.rst b/doc/guides/testpmd_app_ug/run_app.rst index 30edef07ea..c91c231094 100644 --- a/doc/guides/testpmd_app_ug/run_app.rst +++ b/doc/guides/testpmd_app_ug/run_app.rst @@ -556,10 +556,16 @@ The command line options are: Enable display of RX and TX burst stats. -* ``--hairpin-mode=0xXX`` +* ``--hairpin-mode=0xXXXX`` - Set the hairpin port mode with bitmask, only valid when hairpin queues number is set:: + Set the hairpin port configuration with bitmask, only valid when hairpin queues number is set:: + bit 18 - hairpin TX queues will use RTE memory + bit 16 - hairpin TX queues will use locked device memory + bit 13 - hairpin RX queues will use RTE memory + bit 12 - hairpin RX queues will use locked device memory + bit 9 - force memory settings of hairpin TX queue + bit 8 - force memory settings of hairpin RX queue bit 4 - explicit Tx flow rule bit 1 - two hairpin ports paired bit 0 - two hairpin ports loop From patchwork Mon Sep 19 16:37:30 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 16:39:41.0058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed32985f-6ef1-4cfa-feba-08da9a5d8cd2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB5000 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds the hairpin-conf command line parameter to flow-perf application. hairpin-conf parameter takes a hexadecimal bitmask with bits having the following meaning: - Bit 0 - Force memory settings of hairpin RX queue. - Bit 1 - Force memory settings of hairpin TX queue. - Bit 4 - Use locked device memory for hairpin RX queue. - Bit 5 - Use RTE memory for hairpin RX queue. - Bit 8 - Use locked device memory for hairpin TX queue. - Bit 9 - Use RTE memory for hairpin TX queue. Signed-off-by: Dariusz Sosnowski --- app/test-flow-perf/main.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/app/test-flow-perf/main.c b/app/test-flow-perf/main.c index f375097028..4a9206803a 100644 --- a/app/test-flow-perf/main.c +++ b/app/test-flow-perf/main.c @@ -46,6 +46,15 @@ #define DEFAULT_RULES_BATCH 100000 #define DEFAULT_GROUP 0 +#define HAIRPIN_RX_CONF_FORCE_MEMORY (0x0001) +#define HAIRPIN_TX_CONF_FORCE_MEMORY (0x0002) + +#define HAIRPIN_RX_CONF_LOCKED_MEMORY (0x0010) +#define HAIRPIN_RX_CONF_RTE_MEMORY (0x0020) + +#define HAIRPIN_TX_CONF_LOCKED_MEMORY (0x0100) +#define HAIRPIN_TX_CONF_RTE_MEMORY (0x0200) + struct rte_flow *flow; static uint8_t flow_group; @@ -61,6 +70,7 @@ static uint32_t policy_id[MAX_PORTS]; static uint8_t items_idx, actions_idx, attrs_idx; static uint64_t ports_mask; +static uint64_t hairpin_conf_mask; static uint16_t dst_ports[RTE_MAX_ETHPORTS]; static volatile bool force_quit; static bool dump_iterations; @@ -482,6 +492,7 @@ usage(char *progname) printf(" --enable-fwd: To enable packets forwarding" " after insertion\n"); printf(" --portmask=N: hexadecimal bitmask of ports used\n"); + printf(" --hairpin-conf=0xXXXX: hexadecimal bitmask of hairpin queue configuration\n"); printf(" --random-priority=N,S: use random priority levels " "from 0 to (N - 1) for flows " "and S as seed for pseudo-random number generator\n"); @@ -629,6 +640,7 @@ static void args_parse(int argc, char **argv) { uint64_t pm, seed; + uint64_t hp_conf; char **argvopt; uint32_t prio; char *token; @@ -648,6 +660,7 @@ args_parse(int argc, char **argv) { "enable-fwd", 0, 0, 0 }, { "unique-data", 0, 0, 0 }, { "portmask", 1, 0, 0 }, + { "hairpin-conf", 1, 0, 0 }, { "cores", 1, 0, 0 }, { "random-priority", 1, 0, 0 }, { "meter-profile-alg", 1, 0, 0 }, @@ -880,6 +893,13 @@ args_parse(int argc, char **argv) rte_exit(EXIT_FAILURE, "Invalid fwd port mask\n"); ports_mask = pm; } + if (strcmp(lgopts[opt_idx].name, "hairpin-conf") == 0) { + end = NULL; + hp_conf = strtoull(optarg, &end, 16); + if ((optarg[0] == '\0') || (end == NULL) || (*end != '\0')) + rte_exit(EXIT_FAILURE, "Invalid hairpin config mask\n"); + hairpin_conf_mask = hp_conf; + } if (strcmp(lgopts[opt_idx].name, "port-id") == 0) { uint16_t port_idx = 0; @@ -2035,6 +2055,12 @@ init_port(void) hairpin_conf.peers[0].port = port_id; hairpin_conf.peers[0].queue = std_queue + tx_queues_count; + hairpin_conf.use_locked_device_memory = + !!(hairpin_conf_mask & HAIRPIN_RX_CONF_LOCKED_MEMORY); + hairpin_conf.use_rte_memory = + !!(hairpin_conf_mask & HAIRPIN_RX_CONF_RTE_MEMORY); + hairpin_conf.force_memory = + !!(hairpin_conf_mask & HAIRPIN_RX_CONF_FORCE_MEMORY); ret = rte_eth_rx_hairpin_queue_setup( port_id, hairpin_queue, rxd_count, &hairpin_conf); @@ -2050,6 +2076,12 @@ init_port(void) hairpin_conf.peers[0].port = port_id; hairpin_conf.peers[0].queue = std_queue + rx_queues_count; + hairpin_conf.use_locked_device_memory = + !!(hairpin_conf_mask & HAIRPIN_TX_CONF_LOCKED_MEMORY); + hairpin_conf.use_rte_memory = + !!(hairpin_conf_mask & HAIRPIN_TX_CONF_RTE_MEMORY); + hairpin_conf.force_memory = + !!(hairpin_conf_mask & HAIRPIN_TX_CONF_FORCE_MEMORY); ret = rte_eth_tx_hairpin_queue_setup( port_id, hairpin_queue, txd_count, &hairpin_conf);