From patchwork Wed Sep 21 15:29:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 116583 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 20FDAA00C3; Wed, 21 Sep 2022 17:30:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F3D5740691; Wed, 21 Sep 2022 17:30:07 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 6A8D74067C for ; Wed, 21 Sep 2022 17:30:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663774206; x=1695310206; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=reGO35qZV6Plf7RAF6oJNjy9L6mb6C8mBWTTy2NQfvo=; b=Opy9o3uFUc8HbvTunf1gwevSVLE0M8GKBIMweF77kmn7LRcf1eVl8f9d 9o8//DhpwWv5xGd3RY7l00DfEr3PeQ3b8RtIs7Cvxl4GTXIESnKAkGDiU qwI2TO9mCEZbAghPW4GFRvx170l3fPdw8HDot2E6anJElW7Du6wINHVf9 0ZV2Cte9cbeNvzUM4oA2O1aVfpE0FcVMLdEVy9B4nHHjOYolITWqgbbU+ ErCp/ISn8LJy1/lIIEZNSjmoZN9jQtf4Hw8F7qvnkibCYV5jKRpkz7UEy lJ3VR+cd+2KeULHo/b+uzxAG7pr7SLA15AOcCdXlCYI7FsQX8mhB+kAoS Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10477"; a="287108920" X-IronPort-AV: E=Sophos;i="5.93,333,1654585200"; d="scan'208";a="287108920" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2022 08:30:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,333,1654585200"; d="scan'208";a="650119578" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga008.jf.intel.com with ESMTP; 21 Sep 2022 08:30:04 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, rashmi.shetty@intel.com, pravin.pathak@intel.com, mike.ximing.chen@intel.com, timothy.mcdaniel@intel.com, shivani.doneria@intel.com, tirthendu.sarkar@intel.com, Abdullah Sevincer Subject: [PATCH v1] event/dlb2: fix max cq_depth/enq_depth cli override Date: Wed, 21 Sep 2022 10:29:57 -0500 Message-Id: <20220921152957.733863-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch addresses an issue of enqueuing more than max_enq_depth and not able to dequeuing events equal to max_cq_depth in a single call of rte_event_enqueue_burst and rte_event_dequeue_burst. Apply fix for restricting enqueue of events to max_enq_depth so that in a single rte_event_enqueue_burst() call at most max_enq_depth events are enqueued. Also set per port and domain history list sizes based on cq_depth. This results in dequeing correct number of events as set by max_cq_depth. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 5a443acff8..e8c21c41fd 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -813,7 +813,7 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2, cfg->num_ldb_queues; cfg->num_hist_list_entries = resources_asked->num_ldb_ports * - DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; + evdev_dlb2_default_info.max_event_port_dequeue_depth; if (device_version == DLB2_HW_V2_5) { DLB2_LOG_DBG("sched domain create - ldb_qs=%d, ldb_ports=%d, dir_ports=%d, atomic_inflights=%d, hist_list_entries=%d, credits=%d\n", @@ -1538,7 +1538,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2, cfg.cq_depth = rte_align32pow2(dequeue_depth); cfg.cq_depth_threshold = 1; - cfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT; + cfg.cq_history_list_size = cfg.cq_depth; cfg.cos_id = ev_port->cos_id; cfg.cos_strict = 0;/* best effots */ @@ -2966,6 +2966,7 @@ __dlb2_event_enqueue_burst(void *event_port, struct dlb2_port *qm_port = &ev_port->qm_port; struct process_local_port_data *port_data; int retries = ev_port->enq_retries; + int num_tx; int i; RTE_ASSERT(ev_port->enq_configured); @@ -2974,8 +2975,8 @@ __dlb2_event_enqueue_burst(void *event_port, i = 0; port_data = &dlb2_port[qm_port->id][PORT_TYPE(qm_port)]; - - while (i < num) { + num_tx = RTE_MIN(num, ev_port->conf.enqueue_depth); + while (i < num_tx) { uint8_t sched_types[DLB2_NUM_QES_PER_CACHE_LINE]; uint8_t queue_ids[DLB2_NUM_QES_PER_CACHE_LINE]; int pop_offs = 0;