From patchwork Wed Oct 12 23:50:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 118097 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4C2C0A00C2; Thu, 13 Oct 2022 01:51:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 027D042C9C; Thu, 13 Oct 2022 01:51:05 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 33BB942C27 for ; Thu, 13 Oct 2022 01:51:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665618663; x=1697154663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/vH2ynVWeqxWlcXDp0YJ+YapW61F4fUpRa4BKxii08A=; b=mq3Ik0snZ7/hwVDF3GZqezNtvOKWgkJDka19N+PcjnwClbMBWVITalcy GEFiZ5LwnMQubSOSXkQtoFSscMPQ4DRzAbxdNxbrLnGKjV9h2BC+gdXaz Dq62Oxo+Z8B+F2zyI8SLul9pRZYRmvqSI761zgCQNRXETMVSZiC8tbDa2 4FFD1Nd7bodqESm0G1sE9+QM7qhPiXte5gEie0mzZylT6WhzaHY17MRn6 b5pKjkFZ+SKataHEr1GRg4+oKIWkAfghAHcI3pzkiGPsgpWXjPsa5we6G NtfuaZBo05WVKSNdSSMVMual3Mcg6ZCtatf4mOBhCOl++Pt4us19prRKh w==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="366936400" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="366936400" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2022 16:50:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="604746821" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="604746821" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga006.jf.intel.com with ESMTP; 12 Oct 2022 16:50:40 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, Abdullah Sevincer Subject: [PATCH v2 1/4] event/dlb2: remove cos from port probing Date: Wed, 12 Oct 2022 18:50:34 -0500 Message-Id: <20221012235037.3293072-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012143247.3239356-1-abdullah.sevincer@intel.com, shivani.doneria@intel.com> References: <20221012143247.3239356-1-abdullah.sevincer@intel.com, shivani.doneria@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit removes cos (class of service) from port probing criteria and applies enhancements for selection of ports from best cos when default cos (255) is used. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 5 +- drivers/event/dlb2/dlb2_priv.h | 2 +- drivers/event/dlb2/dlb2_user.h | 2 +- drivers/event/dlb2/pf/base/dlb2_hw_types.h | 2 +- drivers/event/dlb2/pf/base/dlb2_resource.c | 85 ++++++++++++++-------- 5 files changed, 60 insertions(+), 36 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index 7fd89e940b..b52ce20a4e 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -180,11 +180,12 @@ dlb2_init_port_cos(struct dlb2_eventdev *dlb2, int *port_cos) { int q; - for (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) + for (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) { + dlb2->ev_ports[q].cos_id = port_cos[q]; if (port_cos[q] != DLB2_COS_DEFAULT) { - dlb2->ev_ports[q].cos_id = port_cos[q]; dlb2->cos_ports[port_cos[q]]++; } + } } static void diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h index 9ef5bcb901..fca1720504 100644 --- a/drivers/event/dlb2/dlb2_priv.h +++ b/drivers/event/dlb2/dlb2_priv.h @@ -421,7 +421,7 @@ struct dlb2_config { }; enum dlb2_cos { - DLB2_COS_DEFAULT = -1, + DLB2_COS_DEFAULT = 255, DLB2_COS_0 = 0, DLB2_COS_1, DLB2_COS_2, diff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h index 28c6aaaf43..8739e2a5ac 100644 --- a/drivers/event/dlb2/dlb2_user.h +++ b/drivers/event/dlb2/dlb2_user.h @@ -450,7 +450,7 @@ struct dlb2_create_dir_queue_args { * - num_hist_list_entries: Number of history list entries. This must be * greater than or equal cq_depth. * - cos_id: class-of-service to allocate this port from. Must be between 0 and - * 3, inclusive. + * 3, inclusive. Should be 255 if default. * - cos_strict: If set, return an error if there are no available ports in the * requested class-of-service. Else, allocate the port from a different * class-of-service if the requested class has no available ports. diff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h index 87996ef621..be09363893 100644 --- a/drivers/event/dlb2/pf/base/dlb2_hw_types.h +++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h @@ -351,7 +351,7 @@ struct dlb2_hw { int prod_core_list[RTE_MAX_LCORE]; u8 num_prod_cores; int dir_pp_allocations[DLB2_MAX_NUM_DIR_PORTS_V2_5]; - int ldb_pp_allocations[DLB2_MAX_NUM_LDB_PORTS]; + int ldb_pp_allocations[DLB2_MAX_NUM_LDB_PORTS + DLB2_NUM_COS_DOMAINS]; /* Virtualization */ int virt_mode; diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c index 280a8e51b1..3f36acb6a4 100644 --- a/drivers/event/dlb2/pf/base/dlb2_resource.c +++ b/drivers/event/dlb2/pf/base/dlb2_resource.c @@ -577,11 +577,14 @@ static int dlb2_attach_ldb_ports(struct dlb2_hw *hw, /* Allocate num_ldb_ports from any class-of-service */ for (i = 0; i < args->num_ldb_ports; i++) { for (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) { + /* Allocate from best performing cos */ + u32 cos_idx = j + DLB2_MAX_NUM_LDB_PORTS; + u32 cos_id = hw->ldb_pp_allocations[cos_idx]; ret = __dlb2_attach_ldb_ports(hw, rsrcs, domain, 1, - j, + cos_id, resp); if (ret == 0) break; @@ -819,21 +822,29 @@ static int dlb2_pp_cycle_comp(const void *a, const void *b) /* Probe producer ports from different CPU cores */ static void -dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id) +dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type) { + struct dlb2_pp_thread_data dlb2_thread_data[DLB2_MAX_NUM_DIR_PORTS_V2_5]; struct dlb2_dev *dlb2_dev = container_of(hw, struct dlb2_dev, hw); - int i, err, ver = DLB2_HW_DEVICE_FROM_PCI_ID(dlb2_dev->pdev); + struct dlb2_pp_thread_data cos_cycles[DLB2_NUM_COS_DOMAINS]; + int ver = DLB2_HW_DEVICE_FROM_PCI_ID(dlb2_dev->pdev); + int num_ports_per_sort, num_ports, num_sort, i, err; bool is_ldb = (port_type == DLB2_LDB_PORT); - int num_ports = is_ldb ? DLB2_MAX_NUM_LDB_PORTS : - DLB2_MAX_NUM_DIR_PORTS(ver); - struct dlb2_pp_thread_data dlb2_thread_data[num_ports]; - int *port_allocations = is_ldb ? hw->ldb_pp_allocations : - hw->dir_pp_allocations; - int num_sort = is_ldb ? DLB2_NUM_COS_DOMAINS : 1; - struct dlb2_pp_thread_data cos_cycles[num_sort]; - int num_ports_per_sort = num_ports / num_sort; + int *port_allocations; pthread_t pthread; + if (is_ldb) { + port_allocations = hw->ldb_pp_allocations; + num_ports = DLB2_MAX_NUM_LDB_PORTS; + num_sort = DLB2_NUM_COS_DOMAINS; + } else { + port_allocations = hw->dir_pp_allocations; + num_ports = DLB2_MAX_NUM_DIR_PORTS(ver); + num_sort = 1; + } + + num_ports_per_sort = num_ports / num_sort; + dlb2_dev->enqueue_four = dlb2_movdir64b; DLB2_LOG_INFO(" for %s: cpu core used in pp profiling: %d\n", @@ -841,8 +852,7 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id) memset(cos_cycles, 0, num_sort * sizeof(struct dlb2_pp_thread_data)); for (i = 0; i < num_ports; i++) { - int cos = is_ldb ? (i >> DLB2_NUM_COS_DOMAINS) : 0; - + int cos = (i >> DLB2_NUM_COS_DOMAINS) % DLB2_NUM_COS_DOMAINS; dlb2_thread_data[i].is_ldb = is_ldb; dlb2_thread_data[i].pp = i; dlb2_thread_data[i].cycles = 0; @@ -861,12 +871,17 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id) DLB2_LOG_ERR(": thread join failed! err=%d", err); return; } - cos_cycles[cos].cycles += dlb2_thread_data[i].cycles; + + if (is_ldb) + cos_cycles[cos].cycles += dlb2_thread_data[i].cycles; if ((i + 1) % num_ports_per_sort == 0) { - int index = cos * num_ports_per_sort; + int index = 0; - cos_cycles[cos].pp = index; + if (is_ldb) { + cos_cycles[cos].pp = cos; + index = cos * num_ports_per_sort; + } /* * For LDB ports first sort with in a cos. Later sort * the best cos based on total cycles for the cos. @@ -880,21 +895,23 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id) } /* - * Re-arrange best ports by cos if default cos is used. + * Sort by best cos aggregated over all ports per cos + * Note: After DLB2_MAX_NUM_LDB_PORTS sorted cos is stored and so'pp' + * is cos_id and not port id. */ - if (is_ldb && cos_id == DLB2_COS_DEFAULT) - qsort(cos_cycles, num_sort, - sizeof(struct dlb2_pp_thread_data), + if (is_ldb) { + qsort(cos_cycles, num_sort, sizeof(struct dlb2_pp_thread_data), dlb2_pp_cycle_comp); + for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) + port_allocations[i + DLB2_MAX_NUM_LDB_PORTS] = cos_cycles[i].pp; + } for (i = 0; i < num_ports; i++) { - int start = is_ldb ? cos_cycles[i / num_ports_per_sort].pp : 0; - int index = i % num_ports_per_sort; - - port_allocations[i] = dlb2_thread_data[start + index].pp; + port_allocations[i] = dlb2_thread_data[i].pp; DLB2_LOG_INFO(": pp %d cycles %d", port_allocations[i], - dlb2_thread_data[start + index].cycles); + dlb2_thread_data[i].cycles); } + } int @@ -903,11 +920,10 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args) const struct dlb2_devargs *args = (const struct dlb2_devargs *)probe_args; const char *mask = NULL; int cpu = 0, cnt = 0, cores[RTE_MAX_LCORE]; - int i, cos_id = DLB2_COS_DEFAULT; + int i; if (args) { mask = (const char *)args->producer_coremask; - cos_id = args->cos_id; } if (mask && rte_eal_parse_coremask(mask, cores)) { @@ -942,8 +958,8 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args) if (hw->num_prod_cores) cpu = hw->prod_core_list[0]; - dlb2_get_pp_allocation(hw, cpu, DLB2_LDB_PORT, cos_id); - dlb2_get_pp_allocation(hw, cpu, DLB2_DIR_PORT, DLB2_COS_DEFAULT); + dlb2_get_pp_allocation(hw, cpu, DLB2_LDB_PORT); + dlb2_get_pp_allocation(hw, cpu, DLB2_DIR_PORT); return 0; } @@ -4543,7 +4559,8 @@ dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw, return -EINVAL; } - if (args->cos_id >= DLB2_NUM_COS_DOMAINS) { + if (args->cos_id >= DLB2_NUM_COS_DOMAINS && + (args->cos_id != DLB2_COS_DEFAULT || args->cos_strict)) { resp->status = DLB2_ST_INVALID_COS_ID; return -EINVAL; } @@ -4554,7 +4571,13 @@ dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw, typeof(*port)); } else { for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) { - id = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS; + if (args->cos_id == DLB2_COS_DEFAULT) { + /* Allocate from best performing cos */ + u32 cos_idx = i + DLB2_MAX_NUM_LDB_PORTS; + id = hw->ldb_pp_allocations[cos_idx]; + } else { + id = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS; + } port = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[id], typeof(*port)); From patchwork Wed Oct 12 23:50:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 118098 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 69EBFA00C2; Thu, 13 Oct 2022 01:51:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C1B2642C27; Thu, 13 Oct 2022 01:51:05 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 0BFC542C27 for ; Thu, 13 Oct 2022 01:51:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665618664; x=1697154664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hw2Z23jK2/NoCFTItVAVZZSwl2EpQ2uDI8Wvr0UOex8=; b=EQKRzYv1pk/ZqQH+brWlhtMKVwJ6EcK6JoF5LeK/2d6dwayd1BkY8pZR el8Fm8uAvEW9z/qn279gAXOFh5uBm0N1e6FjGmc7t3A73iDvG1hB9T3co e3ryzv5sIAilXCLGFph1YpH2gNFULOplt+foNn4AZzmyMhNqpZHo3LDWC 9vufCBhpOcB1lGpvEa7x1j7bGyddABYwGvrcV8CHw1Sb8kuBogh8kLLda qNkoa9lfpJmFi5ioiR/tBHDjvP0X0KTfj48aho9KaUH6RJW5UHSNKJy2x 6CY1ndZ7YsMgC1jJ4wczIpRCNQVsA3h8lvR3oyYnH+GJbqZA0LskSjz+7 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="366936403" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="366936403" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2022 16:50:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="604746838" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="604746838" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga006.jf.intel.com with ESMTP; 12 Oct 2022 16:50:41 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, Abdullah Sevincer Subject: [PATCH v2 2/4] event/dlb2: add check valid producer coremask Date: Wed, 12 Oct 2022 18:50:35 -0500 Message-Id: <20221012235037.3293072-2-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012235037.3293072-1-abdullah.sevincer@intel.com> References: <20221012143247.3239356-1-abdullah.sevincer@intel.com, shivani.doneria@intel.com> <20221012235037.3293072-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit add checks during port probing for validating producer core masks if they are a subset of eal coremask. Error is returned if producer coremask is not a subset of eal coremask. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/base/dlb2_resource.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c index 3f36acb6a4..dd8390a013 100644 --- a/drivers/event/dlb2/pf/base/dlb2_resource.c +++ b/drivers/event/dlb2/pf/base/dlb2_resource.c @@ -918,9 +918,8 @@ int dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args) { const struct dlb2_devargs *args = (const struct dlb2_devargs *)probe_args; - const char *mask = NULL; - int cpu = 0, cnt = 0, cores[RTE_MAX_LCORE]; - int i; + const char *mask = args ? args->producer_coremask : NULL; + int cpu = 0, cnt = 0, cores[RTE_MAX_LCORE], i; if (args) { mask = (const char *)args->producer_coremask; @@ -933,16 +932,17 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args) hw->num_prod_cores = 0; for (i = 0; i < RTE_MAX_LCORE; i++) { + bool is_pcore = (mask && cores[i] != -1); + if (rte_lcore_is_enabled(i)) { - if (mask) { + if (is_pcore) { /* * Populate the producer cores from parsed * coremask */ - if (cores[i] != -1) { - hw->prod_core_list[cores[i]] = i; - hw->num_prod_cores++; - } + hw->prod_core_list[cores[i]] = i; + hw->num_prod_cores++; + } else if ((++cnt == DLB2_EAL_PROBE_CORE || rte_lcore_count() < DLB2_EAL_PROBE_CORE)) { /* @@ -952,7 +952,12 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args) cpu = i; break; } + } else if (is_pcore) { + DLB2_LOG_ERR("Producer coremask(%s) must be a subset of EAL coremask", + mask); + return -1; } + } /* Use the first core in producer coremask to probe */ if (hw->num_prod_cores) From patchwork Wed Oct 12 23:50:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 118099 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41D8DA00C2; Thu, 13 Oct 2022 01:51:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EBFA942CB6; Thu, 13 Oct 2022 01:51:07 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 8801C42C94 for ; Thu, 13 Oct 2022 01:51:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665618664; x=1697154664; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vs7Gi/x+mpAsVna8+G3wDhj/fjh9l3uvjaoaRxj3N0Q=; b=Xa7hjUfLem7y2RQ32cXJiGozNnwepdAj/n19y+HJZSp+FSyVw5asXhxW G0fi+XPt6mkUQv7CuJf68VPOePCxJ5MsvWLZDsGn6CjLvK9+UPewUIUKf TS4U1rgxB8ue3hjEIZtYWnXZjXGyeBtX2cGBAhGbE4009egAHm/PB5bEM AdhlrJooMHDnizvZBtyqVjhFGJHvnNjqkCc7c31Sw264lLTfErCxYuQ2t pnpFpPVAsj0tMT3WQJIMDD8Qc+vZnWdI/FpPdhc7KDx75Kh6iogIGlxO1 bIXpuk8tO7S/RgDNkLHDIGYHSAS5gVY3X5pGgWvajKjNiICja/gAgYGrH Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="366936408" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="366936408" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2022 16:50:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="604746848" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="604746848" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga006.jf.intel.com with ESMTP; 12 Oct 2022 16:50:43 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, Abdullah Sevincer Subject: [PATCH v2 3/4] event/dlb2: remove cos from devargs Date: Wed, 12 Oct 2022 18:50:36 -0500 Message-Id: <20221012235037.3293072-3-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012235037.3293072-1-abdullah.sevincer@intel.com> References: <20221012143247.3239356-1-abdullah.sevincer@intel.com, shivani.doneria@intel.com> <20221012235037.3293072-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit removes the cos argument from devargs struct. Since cos is now per port specific only and supported through port_cos in dev_args, there is no need to to have a cos argument in dev_args struct. Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 1 - drivers/event/dlb2/dlb2_priv.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index b52ce20a4e..b200c9484e 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -4763,7 +4763,6 @@ dlb2_parse_params(const char *params, DLB2_NUM_DIR_CREDITS, DEV_ID_ARG, DLB2_QID_DEPTH_THRESH_ARG, - DLB2_COS_ARG, DLB2_POLL_INTERVAL_ARG, DLB2_SW_CREDIT_QUANTA_ARG, DLB2_HW_CREDIT_QUANTA_ARG, diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h index fca1720504..085dcf9bdc 100644 --- a/drivers/event/dlb2/dlb2_priv.h +++ b/drivers/event/dlb2/dlb2_priv.h @@ -40,7 +40,6 @@ #define DLB2_NUM_DIR_CREDITS "num_dir_credits" #define DEV_ID_ARG "dev_id" #define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh" -#define DLB2_COS_ARG "cos" #define DLB2_POLL_INTERVAL_ARG "poll_interval" #define DLB2_SW_CREDIT_QUANTA_ARG "sw_credit_quanta" #define DLB2_HW_CREDIT_QUANTA_ARG "hw_credit_quanta" @@ -661,7 +660,6 @@ struct dlb2_devargs { int num_dir_credits_override; int dev_id; struct dlb2_qid_depth_thresholds qid_depth_thresholds; - enum dlb2_cos cos_id; int poll_interval; int sw_credit_quanta; int hw_credit_quanta; From patchwork Wed Oct 12 23:50:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 118100 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41DD3A00C2; Thu, 13 Oct 2022 01:51:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D884342CBF; Thu, 13 Oct 2022 01:51:08 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id B1CDE42C27; Thu, 13 Oct 2022 01:51:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665618665; x=1697154665; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GY8NflP+AHL895eegPOvOeOvNKmF3B++ggChPIyyCo4=; b=P/tKFQQ5gnpezdbG8adcF1G2bhmo1OaESoqL/DhqFH8Pi/ipCZdUSgMc Ydud5Vnar4k43/7mb7BYgNgghz6Kw6U42liGwNsi85w0rhhMzfarjKypf sfXPESVbSXGndhFgfCDG4U6J1O5Tj9x0LWOYFl6fqfIHOhxBwHqeYXEr8 W9qQIqVVW9C1V67HIYT9bOPNPjfiGxGDfMK9jpBsaS0ZueVw8gLlBPqAH Iaa3bkThIudT/1k4PzctSW8euZx0tSin2WOm1IJExALX1S58mttbocofY IV/HfkcS22lTzLc1fG/NciGdKH+X38UfHPqKcKvXqHMGcp77pMWUBYjtc Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="366936413" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="366936413" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2022 16:50:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10498"; a="604746860" X-IronPort-AV: E=Sophos;i="5.95,180,1661842800"; d="scan'208";a="604746860" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga006.jf.intel.com with ESMTP; 12 Oct 2022 16:50:44 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, Abdullah Sevincer , stable@dpdk.org Subject: [PATCH v2 4/4] event/dlb2: fix port cos override calculation Date: Wed, 12 Oct 2022 18:50:37 -0500 Message-Id: <20221012235037.3293072-4-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012235037.3293072-1-abdullah.sevincer@intel.com> References: <20221012143247.3239356-1-abdullah.sevincer@intel.com, shivani.doneria@intel.com> <20221012235037.3293072-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit fixes a calculation error of total number of ldb ports during port cos override from dlb2 event structure. Fixes: bec8901bfe9f ("event/dlb2: support ldb port specific COS") Cc: stable@dpdk.org Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/dlb2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index b200c9484e..02f0e57208 100644 --- a/drivers/event/dlb2/dlb2.c +++ b/drivers/event/dlb2/dlb2.c @@ -848,10 +848,11 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2, } cfg->cos_strict = 0; /* Best effort */ - cfg->num_cos_ldb_ports[0] = resources_asked->num_ldb_ports - cos_ports; + cfg->num_cos_ldb_ports[0] = dlb2->cos_ports[0]; cfg->num_cos_ldb_ports[1] = dlb2->cos_ports[1]; cfg->num_cos_ldb_ports[2] = dlb2->cos_ports[2]; cfg->num_cos_ldb_ports[3] = dlb2->cos_ports[3]; + cfg->num_ldb_ports = resources_asked->num_ldb_ports - cos_ports; if (device_version == DLB2_HW_V2) cfg->num_ldb_credits = resources_asked->num_ldb_credits;