From patchwork Wed Oct 19 00:38:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118436 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5882A0560; Tue, 18 Oct 2022 18:42:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA6E741144; Tue, 18 Oct 2022 18:42:50 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id E339B40395; Tue, 18 Oct 2022 18:42:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111368; x=1697647368; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gwyd+01g6kF0VZMaCZCULw9hNkTDvbEptlyUbPOUevo=; b=iRxBGWhGhhRH4KuVAKNf05RW4ILUvI20wuvAeDMbXlBsI1lYAoTNqTSk L2LvmXyJxb3F7kZO+cikryIYnbpXf02CZHkxvCY9A7TEPy6GBxlZ7SGgB Vauiby+X4UhA5yMINy620KVr6Hwe6PsYv1D7YyG8IauPCcxc1XkEj2LtK zervFL7Bzve3U0gihFFSyBM9l9Fwiv3ll/Z/OAd3/1L7wEoBJRidYzB5W JInFxykxnUbGf7qFK+LTPEYL8iepVIKhbNMy1EuKH3eyWIb0WvjdGFRPu rRUptOXDvV1APD+R+FHDsjpNP5gsNtX3y6fOef2aMPreGLtN3NpSY7gk6 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192021" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192021" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803835980" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803835980" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:46 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 01/30] baseband/acc100: fix ring availability calculation Date: Tue, 18 Oct 2022 17:38:49 -0700 Message-Id: <20221019003918.257506-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor of the queue availability computation to prevent the application to dequeue more than what may have been enqueued. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc/rte_acc100_pmd.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index e5384223d1..3b0c8e41dc 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2861,7 +2861,7 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i; union acc_dma_desc *desc; int ret; @@ -2899,7 +2899,7 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i = 0; union acc_dma_desc *desc; int ret, desc_idx = 0; @@ -2949,7 +2949,7 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i, enqueued_cbs = 0; uint8_t cbs_in_tb; int ret; @@ -3011,7 +3011,7 @@ acc100_enqueue_dec_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i; union acc_dma_desc *desc; int ret; @@ -3050,7 +3050,7 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i, enqueued_cbs = 0; uint8_t cbs_in_tb; int ret; @@ -3083,7 +3083,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i; union acc_dma_desc *desc; int ret; @@ -3132,7 +3132,7 @@ acc100_enqueue_dec_tb(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - int32_t avail = q->sw_ring_depth + q->sw_ring_tail - q->sw_ring_head; + int32_t avail = acc_ring_avail_enq(q); uint16_t i, enqueued_cbs = 0; uint8_t cbs_in_tb; int ret; @@ -3495,12 +3495,13 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, { struct acc_queue *q = q_data->queue_private; uint16_t dequeue_num; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t i, dequeued_cbs = 0; struct rte_bbdev_enc_op *op; int ret; - + if (avail == 0) + return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG if (unlikely(ops == NULL || q == NULL)) { rte_bbdev_log_debug("Unexpected undefined pointer"); @@ -3539,7 +3540,7 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0; int ret; @@ -3579,7 +3580,7 @@ acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, { struct acc_queue *q = q_data->queue_private; uint16_t dequeue_num; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t i; uint16_t dequeued_cbs = 0; @@ -3623,7 +3624,7 @@ acc100_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, { struct acc_queue *q = q_data->queue_private; uint16_t dequeue_num; - uint32_t avail = q->sw_ring_head - q->sw_ring_tail; + uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; uint16_t i; uint16_t dequeued_cbs = 0; From patchwork Wed Oct 19 00:38:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118437 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E17C4A0560; Tue, 18 Oct 2022 18:42:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0024742670; Tue, 18 Oct 2022 18:42:51 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id B3F2C40395; Tue, 18 Oct 2022 18:42:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; 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d="scan'208";a="803835987" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:46 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 02/30] baseband/acc100: add function to check AQ availability Date: Tue, 18 Oct 2022 17:38:50 -0700 Message-Id: <20221019003918.257506-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org It is possible for some corner case to run more batch enqueue than supported. A protection is required to avoid that corner case. Enhance all ACC100 enqueue operations with check to see if there is room in the atomic queue for enqueueing batches into the queue manager Check room in AQ for the enqueues batches into Qmgr Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc/rte_acc100_pmd.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 3b0c8e41dc..7fec2283eb 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2983,7 +2983,8 @@ static uint16_t acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -2996,7 +2997,8 @@ static uint16_t acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -3164,8 +3166,11 @@ static uint16_t acc100_enqueue_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; + if (ops[0]->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_dec_tb(q_data, ops, num); else @@ -3177,11 +3182,9 @@ static uint16_t acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - struct acc_queue *q = q_data->queue_private; - int32_t aq_avail = q->aq_depth + - (q->aq_dequeued - q->aq_enqueued) / 128; + int32_t aq_avail = acc_aq_avail(q_data, num); - if (unlikely((aq_avail == 0) || (num == 0))) + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) @@ -3190,7 +3193,6 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, return acc100_enqueue_ldpc_dec_cb(q_data, ops, num); } - /* Dequeue one encode operations from ACC100 device in CB mode */ static inline int dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, From patchwork Wed Oct 19 00:38:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118438 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71C45A0560; Tue, 18 Oct 2022 18:43:05 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC5E6427EA; Tue, 18 Oct 2022 18:42:52 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 66664410F2; Tue, 18 Oct 2022 18:42:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111369; x=1697647369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AXRFiX52EGOByi1rLZyJYK4JU8QaanPp85p6WlDOquE=; b=ksCBAruXgXZ+Cd0bPEwJQw2DyoB1uEuDvX4FmFff4jLUk81SOPUQ5EqO XBHKYOqZRTsTniNQFxJSVBog14v6hXYwqxh/l8mgjUPbzc0WsdS46Ifns WH9BAgDssAaMeGKMMU0n9xbKUB3jTjNb9KE+lcbUs2uKVAR06E/eXQfln JDBUZgMMnrMM2PWiOisYOKki33B5SAF7VKpUD9tvCx50CIoLphmMvvqKv uwZDQ1ymZQ+flzfCT53a7nj0y5NOvFApal4CHwLbdLaAhVtWuiT5AXCLT Se+mItSwO1132/jiko2EtMo5jIrywPr33F/KJGnFq8AxrGRVrJCHdpcUG w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192032" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192032" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803835995" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803835995" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:47 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 03/30] baseband/acc100: memory leak fix Date: Tue, 18 Oct 2022 17:38:51 -0700 Message-Id: <20221019003918.257506-4-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move check for undefined device before allocating queue data structure. Coverity issue: 375803, 375813, 375819, 375827, 375831 Fixes: 060e7672930 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7fec2283eb..7500ef6eb5 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -663,6 +663,10 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, struct acc_queue *q; int16_t q_idx; + if (d == NULL) { + rte_bbdev_log(ERR, "Undefined device"); + return -ENODEV; + } /* Allocate the queue data structure. */ q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q), RTE_CACHE_LINE_SIZE, conf->socket); @@ -670,10 +674,6 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, rte_bbdev_log(ERR, "Failed to allocate queue memory"); return -ENOMEM; } - if (d == NULL) { - rte_bbdev_log(ERR, "Undefined device"); - return -ENODEV; - } q->d = d; q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); From patchwork Wed Oct 19 00:38:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118439 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E69BBA0560; Tue, 18 Oct 2022 18:43:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 04A93427F2; Tue, 18 Oct 2022 18:42:54 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 8825A40395; Tue, 18 Oct 2022 18:42:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111369; x=1697647369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E0M4heqfM0odSwlFVEGhnhGPzHHBEmhQndghAmwhWNg=; b=G2s/kY2L1adRaFHvYA0AO1nUsNCPUId07lSrcaQkhBSgApYAjof0CgA0 D95cG+UkUwLOqxiSgIeqeSFCUHMJCzXCt5c1KP/bJkgc6YvAiz8FEcmjC UF0qQmCheWi6CfI+spzRFfgAGKXyXPZahROg3QW805Q0MZwTiVQLIwG+R AUFoCI4Im7KQ6NwJZrZTrPdnqMz6ndRBnswx3gZCAk9s3+von4utRY+F6 HgyX2yRMD0Z7ANoQnkx9lBvR6PtjfBDS9lXDAzO9AJKQ2ptg4wnr4FDa5 GfG3mCzR4h32nKbWcRpMVNPUmvj1zSXK5TTEh0mu6v/s2YyDABCXrfKkX A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192040" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192040" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836008" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836008" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:48 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 04/30] baseband/acc100: add LDPC encoder padding function Date: Tue, 18 Oct 2022 17:38:52 -0700 Message-Id: <20221019003918.257506-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LDPC Encoder input may need to be padded to avoid small beat for ACC100. Padding 5GDL input buffer length (BLEN) to avoid case (BLEN % 64) <= 8. Adding protection for corner case to avoid for 5GDL occurrence of last beat within the ACC100 fabric with <= 8B which might trigger a fabric corner case hang issue. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7500ef6eb5..a80ecdca84 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1017,7 +1017,6 @@ acc100_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw) RTE_BBDEV_TURBO_HALF_ITERATION_EVEN); } -#ifdef RTE_LIBRTE_BBDEV_DEBUG static inline bool is_acc100(struct acc_queue *q) @@ -1030,7 +1029,6 @@ validate_op_required(struct acc_queue *q) { return is_acc100(q); } -#endif /* Fill in a frame control word for LDPC decoding. */ static inline void @@ -1355,12 +1353,28 @@ acc100_dma_fill_blk_type_in(struct acc_dma_req_desc *desc, return next_triplet; } +/* May need to pad LDPC Encoder input to avoid small beat for ACC100. */ +static inline uint16_t +pad_le_in(uint16_t blen, struct acc_queue *q) +{ + uint16_t last_beat; + + if (!is_acc100(q)) + return blen; + + last_beat = blen % 64; + if ((last_beat > 0) && (last_beat <= 8)) + blen += 8; + + return blen; +} + static inline int acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, struct acc_dma_req_desc *desc, struct rte_mbuf **input, struct rte_mbuf *output, uint32_t *in_offset, uint32_t *out_offset, uint32_t *out_length, - uint32_t *mbuf_total_left, uint32_t *seg_total_left) + uint32_t *mbuf_total_left, uint32_t *seg_total_left, struct acc_queue *q) { int next_triplet = 1; /* FCW already done */ uint16_t K, in_length_in_bits, in_length_in_bytes; @@ -1384,8 +1398,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - in_length_in_bytes, - seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -2035,7 +2048,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, acc_header_init(&desc->req); desc->req.numCBs = num; - in_length_in_bytes = ops[0]->ldpc_enc.input.data->data_len; + in_length_in_bytes = pad_le_in(ops[0]->ldpc_enc.input.data->data_len, q); out_length = (enc->cb_params.e + 7) >> 3; desc->req.m2dlen = 1 + num; desc->req.d2mlen = num; @@ -2102,7 +2115,7 @@ enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, ret = acc100_dma_desc_le_fill(op, &desc->req, &input, output, &in_offset, &out_offset, &out_length, &mbuf_total_left, - &seg_total_left); + &seg_total_left, q); if (unlikely(ret < 0)) return ret; From patchwork Wed Oct 19 00:38:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118440 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58B39A0560; Tue, 18 Oct 2022 18:43:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1072141181; 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18 Oct 2022 09:42:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836018" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836018" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:49 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 05/30] baseband/acc100: check turbo dec/enc input Date: Tue, 18 Oct 2022 17:38:53 -0700 Message-Id: <20221019003918.257506-6-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add NULL check for the turbo decoder and encoder input length. Fixes: 3bfc5f60403 ("baseband/acc100: add debug function to validate input") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index a80ecdca84..bf0d7d77e7 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1763,6 +1763,11 @@ validate_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) return -1; } + if (unlikely(turbo_enc->input.length == 0)) { + rte_bbdev_log(ERR, "input length null"); + return -1; + } + if (turbo_enc->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { tb = &turbo_enc->tb_params; if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE @@ -1782,11 +1787,12 @@ validate_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) + if (unlikely(tb->c_neg > 0)) { rte_bbdev_log(ERR, - "c_neg (%u) is out of range 0 <= value <= %u", - tb->c_neg, - RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + "c_neg (%u) expected to be null", + tb->c_neg); + return -1; + } if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", @@ -2280,6 +2286,11 @@ validate_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) return -1; } + if (unlikely(turbo_dec->input.length == 0)) { + rte_bbdev_log(ERR, "input length null"); + return -1; + } + if (turbo_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { tb = &turbo_dec->tb_params; if ((tb->k_neg < RTE_BBDEV_TURBO_MIN_CB_SIZE @@ -2300,11 +2311,13 @@ validate_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) RTE_BBDEV_TURBO_MAX_CB_SIZE); return -1; } - if (tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1)) + if (unlikely(tb->c_neg > (RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1))) { rte_bbdev_log(ERR, "c_neg (%u) is out of range 0 <= value <= %u", tb->c_neg, RTE_BBDEV_TURBO_MAX_CODE_BLOCKS - 1); + return -1; + } if (tb->c < 1 || tb->c > RTE_BBDEV_TURBO_MAX_CODE_BLOCKS) { rte_bbdev_log(ERR, "c (%u) is out of range 1 <= value <= %u", From patchwork Wed Oct 19 00:38:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118441 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 630BDA0560; Tue, 18 Oct 2022 18:43:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DD8C34281B; Tue, 18 Oct 2022 18:42:56 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id AF81140395; Tue, 18 Oct 2022 18:42:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111371; x=1697647371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QaTbNZdhqbqRUJjXYTAah0qOcYz3IFLqRt5408HO/J0=; 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Fixes: f404dfe35cc ("baseband/acc100: support 4G processing") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index bf0d7d77e7..50c1536dee 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2179,6 +2179,10 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, r = op->turbo_enc.tb_params.r; while (mbuf_total_left > 0 && r < c) { + if (unlikely(input == NULL)) { + rte_bbdev_log(ERR, "Not enough input segment"); + return -EINVAL; + } seg_total_left = rte_pktmbuf_data_len(input) - in_offset; /* Set up DMA descriptor */ desc = acc_desc(q, total_enqueued_cbs); @@ -3096,6 +3100,8 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, break; enqueued_cbs += ret; } + if (unlikely(enqueued_cbs == 0)) + return 0; /* Nothing to enqueue */ acc_dma_enqueue(q, enqueued_cbs, &q_data->queue_stats); @@ -3624,6 +3630,8 @@ acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, for (i = 0; i < dequeue_num; ++i) { op = acc_op_tail(q, dequeued_cbs); + if (unlikely(op == NULL)) + break; if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs, &aq_dequeued); @@ -3669,6 +3677,8 @@ acc100_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, for (i = 0; i < dequeue_num; ++i) { op = (q->ring_addr + ((q->sw_ring_tail + dequeued_cbs) & q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(op == NULL)) + break; if (op->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) ret = dequeue_dec_one_op_tb(q, &ops[i], dequeued_cbs, &aq_dequeued); From patchwork Wed Oct 19 00:38:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118442 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EBD25A0560; Tue, 18 Oct 2022 18:43:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC87B42836; Tue, 18 Oct 2022 18:42:57 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 83D1040395; Tue, 18 Oct 2022 18:42:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111371; x=1697647371; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2UzBxeCWNMmpPXIwGdL1T4E1AwQdCA6xAblNN6EfJ8o=; b=TwDFUjYEsnjClU4JaNCqlJvMhGxtkHAeU4zo3lt42PEthzcL+mOpKixI FbmAOF2SMo1LDZdjYfQYm3PSEIQWTHGMfd2y5h+cGdRR/qgk7UTKRW08H APl9aM8SDUq0LsGEuscHvkSDtyK2enezZfCxY023HYGebwfh0fs6MHnqt TdRH6DZVWPYSUTZVmytPRJUq4EYo9jDgWf/xOEIrJ10n/hIuY9SjscIfy sUmr1yzbrA5ob+WcueOArLFxSFUeF/4KOvQU3STlphDnADk8m1U//dRKr MMya+z9HU6Ra46SSr16alKN2NSEWtwSeNUnAKITSUCfsyKW3lLRT582qj w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192050" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192050" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836030" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836030" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:50 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 07/30] baseband/acc100: enforce additional check on FCW Date: Tue, 18 Oct 2022 17:38:55 -0700 Message-Id: <20221019003918.257506-8-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enforce additional check on Frame Control Word validity and add stronger alignment for decompression mode. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc100_pmd.h | 1 + drivers/baseband/acc/acc_common.h | 1 + drivers/baseband/acc/rte_acc100_pmd.c | 71 ++++++++++++++++++++++----- 3 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index 9486e98521..eb6349c85a 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -87,6 +87,7 @@ #define ACC100_HARQ_DDR (512 * 1) #define ACC100_PRQ_DDR_VER 0x10092020 #define ACC100_DDR_TRAINING_MAX (5000) +#define ACC100_HARQ_ALIGN_COMP 256 struct acc100_registry_addr { unsigned int dma_ring_dl5g_hi; diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 6f141c95ce..97d10b8b40 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -120,6 +120,7 @@ #define ACC_ALGO_SPA 0 #define ACC_ALGO_MSA 1 +#define ACC_HARQ_ALIGN_64B 64 /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 50c1536dee..1c83d591e3 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1039,6 +1039,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, uint16_t harq_index; uint32_t l; bool harq_prun = false; + uint32_t max_hc_in; fcw->qm = op->ldpc_dec.q_m; fcw->nfiller = op->ldpc_dec.n_filler; @@ -1088,13 +1089,22 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) harq_in_length = harq_in_length * 8 / 6; - harq_in_length = RTE_ALIGN(harq_in_length, 64); - if ((harq_layout[harq_index].offset > 0) & harq_prun) { + + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B); + + /* Stronger alignment requirement when in decompression mode */ + if (fcw->hcin_decomp_mode > 0) + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP); + + if ((harq_layout[harq_index].offset > 0) && harq_prun) { rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); fcw->hcin_size0 = harq_layout[harq_index].size0; fcw->hcin_offset = harq_layout[harq_index].offset; - fcw->hcin_size1 = harq_in_length - - harq_layout[harq_index].offset; + fcw->hcin_size1 = harq_in_length - harq_layout[harq_index].offset; } else { fcw->hcin_size0 = harq_in_length; fcw->hcin_offset = 0; @@ -1106,6 +1116,21 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcin_size1 = 0; } + /* Enforce additional check on FCW validity */ + max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC_HARQ_ALIGN_64B); + if ((fcw->hcin_size0 > max_hc_in) || + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || + ((fcw->hcin_size0 > fcw->hcin_offset) && + (fcw->hcin_size1 != 0))) { + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", + fcw->hcin_size0, fcw->hcin_size1, + fcw->hcin_offset, + fcw->ncb, fcw->nfiller); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + fcw->hcin_en = 0; + } + fcw->itmax = op->ldpc_dec.iter_max; fcw->itstop = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); @@ -1130,15 +1155,27 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, if (fcw->hcout_en > 0) { parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; - k0_p = (fcw->k0 > parity_offset) ? - fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; - l = k0_p + fcw->rm_e; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); harq_out_length = (uint16_t) fcw->hcin_size0; - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; - if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && - harq_prun) { + harq_out_length = RTE_MAX(harq_out_length, l); + + /* Stronger alignment when in compression mode */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC_HARQ_ALIGN_64B); + + /* Stronger alignment when in compression mode enforced again */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + if ((k0_p > fcw->hcin_size0 + ACC_HARQ_OFFSET_THRESHOLD) && harq_prun) { fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; fcw->hcout_offset = k0_p & 0xFFC0; fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; @@ -1147,6 +1184,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, fcw->hcout_size1 = 0; fcw->hcout_offset = 0; } + + if (fcw->hcout_size0 == 0) { + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", + fcw->hcout_size0); + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + fcw->hcout_en = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { @@ -1187,6 +1232,10 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, /* Disable HARQ input in that case to carry forward */ op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; } + if (unlikely(fcw->rm_e == 0)) { + rte_bbdev_log(WARNING, "Null E input provided"); + fcw->rm_e = 2; + } fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); From patchwork Wed Oct 19 00:38:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118443 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1CF9A0560; Tue, 18 Oct 2022 18:43:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C4BFD42B6D; Tue, 18 Oct 2022 18:42:58 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id BDF574114E; Tue, 18 Oct 2022 18:42:51 +0200 (CEST) DKIM-Signature: v=1; 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d="scan'208";a="803836038" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:50 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 08/30] baseband/acc100: allocate ring/queue mem when NULL Date: Tue, 18 Oct 2022 17:38:56 -0700 Message-Id: <20221019003918.257506-9-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allocate info ring, tail pointers and HARQ layout memory for a device only if it hasn't already been allocated. Fixes: 06531464151 ("baseband/acc100: support interrupt") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc/rte_acc100_pmd.c | 30 ++++++++++++++++++--------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 1c83d591e3..00d02ce90d 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -408,9 +408,9 @@ allocate_info_ring(struct rte_bbdev *dev) reg_addr = &vf_reg_addr; /* Allocate InfoRing */ d->info_ring = rte_zmalloc_socket("Info Ring", - ACC_INFO_RING_NUM_ENTRIES * - sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, - dev->data->socket_id); + ACC_INFO_RING_NUM_ENTRIES * + sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, + dev->data->socket_id); if (d->info_ring == NULL) { rte_bbdev_log(ERR, "Failed to allocate Info Ring for %s:%u", @@ -499,7 +499,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) acc_reg_write(d, reg_addr->ring_size, value); /* Configure tail pointer for use when SDONE enabled */ - d->tail_ptrs = rte_zmalloc_socket( + if (d->tail_ptrs == NULL) + d->tail_ptrs = rte_zmalloc_socket( dev->device->driver->name, ACC100_NUM_QGRPS * ACC100_NUM_AQS * sizeof(uint32_t), RTE_CACHE_LINE_SIZE, socket_id); @@ -507,8 +508,8 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) rte_bbdev_log(ERR, "Failed to allocate tail ptr for %s:%u", dev->device->driver->name, dev->data->dev_id); - rte_free(d->sw_rings); - return -ENOMEM; + ret = -ENOMEM; + goto free_sw_rings; } d->tail_ptr_iova = rte_malloc_virt2iova(d->tail_ptrs); @@ -531,15 +532,16 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) /* Continue */ } - d->harq_layout = rte_zmalloc_socket("HARQ Layout", + if (d->harq_layout == NULL) + d->harq_layout = rte_zmalloc_socket("HARQ Layout", ACC_HARQ_LAYOUT * sizeof(*d->harq_layout), RTE_CACHE_LINE_SIZE, dev->data->socket_id); if (d->harq_layout == NULL) { rte_bbdev_log(ERR, "Failed to allocate harq_layout for %s:%u", dev->device->driver->name, dev->data->dev_id); - rte_free(d->sw_rings); - return -ENOMEM; + ret = -ENOMEM; + goto free_tail_ptrs; } /* Mark as configured properly */ @@ -548,8 +550,16 @@ acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) rte_bbdev_log_debug( "ACC100 (%s) configured sw_rings = %p, sw_rings_iova = %#" PRIx64, dev->data->name, d->sw_rings, d->sw_rings_iova); - return 0; + +free_tail_ptrs: + rte_free(d->tail_ptrs); + d->tail_ptrs = NULL; +free_sw_rings: + rte_free(d->sw_rings_base); + d->sw_rings = NULL; + + return ret; } static int From patchwork Wed Oct 19 00:38:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118444 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5C9BA0560; Tue, 18 Oct 2022 18:43:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AD06542B74; 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18 Oct 2022 09:42:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836045" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836045" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:51 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 09/30] baseband/acc100: reduce input length for CRC24B Date: Tue, 18 Oct 2022 17:38:57 -0700 Message-Id: <20221019003918.257506-10-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Input length should be reduced only for CRC24B. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 00d02ce90d..b79a251e9f 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1443,8 +1443,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c; in_length_in_bits = K - enc->n_filler; - if ((enc->op_flags & RTE_BBDEV_LDPC_CRC_24A_ATTACH) || - (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH) in_length_in_bits -= 24; in_length_in_bytes = in_length_in_bits >> 3; From patchwork Wed Oct 19 00:38:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118445 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4F16A0560; Tue, 18 Oct 2022 18:43:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C309142B7E; Tue, 18 Oct 2022 18:43:00 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id C461C4114E; Tue, 18 Oct 2022 18:42:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111373; x=1697647373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ujuWBLN0H5zGviO91IjuIlvt/+F8FmYVJjE8wCPqksA=; b=SZJ6jhLJDzilQCm2U7bsKdz3OzMDNb8rn/fgLzNeT0U0CzZa1qZVrD6H yllSHXisr0OaaT246tLk7hRJ3LOr5rQxcZkxP+34y0PZc9mDk25lIZoqY HWrbmNRPA8ddw8oGHOKpqcNv4aUfCCOr/nvY9PdiA5U9UX/hRn2TK1Axq npBE6UaJyakZF/ExvRPEOvRSvFATtWl2yX3EKvhQ8hv/FCX47s9qnMZJz mn6PevYb2k6rOVd+8kyyo4TdwRTq6uKVohCF4wdcGCIdfMi/xBd9t2+0N 7Cm19+bAhpwZCuFKC8i3xu1FEJC07E03o/6WWNzwejQO5TKc2MSd4lYn5 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192064" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192064" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836054" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836054" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:51 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 10/30] baseband/acc100: fix clearing PF IR outside handler Date: Tue, 18 Oct 2022 17:38:58 -0700 Message-Id: <20221019003918.257506-11-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Clearing of PF info ring outside of handler may cause interrupt to be missed. A condition in the ACC100 PMD implementation may cause an interrupt functional handler call to be missed due to related bit being cleared when checking PF info ring status. Fixes: 06531464151 ("baseband/acc100: support interrupt") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index b79a251e9f..f892b402ca 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -262,11 +262,12 @@ acc100_check_ir(struct acc_device *acc100_dev) while (ring_data->valid) { if ((ring_data->int_nb < ACC100_PF_INT_DMA_DL_DESC_IRQ) || ( ring_data->int_nb > - ACC100_PF_INT_DMA_DL5G_DESC_IRQ)) + ACC100_PF_INT_DMA_DL5G_DESC_IRQ)) { rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x", ring_data->int_nb, ring_data->detailed_info); - /* Initialize Info Ring entry and move forward */ - ring_data->val = 0; + /* Initialize Info Ring entry and move forward */ + ring_data->val = 0; + } info_ring_head++; ring_data = acc100_dev->info_ring + (info_ring_head & ACC_INFO_RING_MASK); From patchwork Wed Oct 19 00:38:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118446 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EAAD2A0560; Tue, 18 Oct 2022 18:43:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C6A3B42B83; Tue, 18 Oct 2022 18:43:01 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 3DFF041181; Tue, 18 Oct 2022 18:42:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111373; x=1697647373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AOUugWPLW1jcCvWlG9KWHtVR8djuEYnvB/v+CZymxSA=; b=Sl2hFpNIGwNO9P5fUHdTwER+CavIl9OVW56X9dvBKQeIL85qLMJcdPVG sfZkfHXMHK0qvbvEB1TKCutPbhH2zicfXX5xjqPFlhRRd4MnjC3mcEKcw cf9YA2wmRFMAWJEtcrPnrGXSXXq6/F+PdQH2oaOr9pA91g23hfOuxX+I5 JfbNaBJffcWNkWaxlLhU7TFzsXTzdFlYfL216x7W/u1j1JEQNz0upWtE+ 7I1Uu/jT+uqRfuVDyw23l7AjX19tTKQjjBPIHrsFlx8M0OKr2DYdKLXvH dVM8W0TlzU7o0a2dFY4N7CR5DjelMYuorYC5ixxUhkPOf0AV18NZjw7he w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192066" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192066" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836060" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836060" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:52 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 11/30] baseband/acc100: set device min alignment to 1 Date: Tue, 18 Oct 2022 17:38:59 -0700 Message-Id: <20221019003918.257506-12-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Historical mistakes, there should be no 64B alignment requirement for the buffer being processed. Any 1B alignment is sufficient. Fixes: 9200ffa5cd5 ("baseband/acc100: add info get function") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index f892b402ca..8d11699c0c 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -938,7 +938,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, d->acc_conf.q_ul_4g.num_qgroups - 1; dev_info->default_queue_conf = default_queue_conf; dev_info->cpu_flag_reqs = NULL; - dev_info->min_alignment = 64; + dev_info->min_alignment = 1; dev_info->capabilities = bbdev_capabilities; #ifdef ACC100_EXT_MEM dev_info->harq_buffer_size = d->ddr_size; From patchwork Wed Oct 19 00:39:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118447 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 72BC9A0560; Tue, 18 Oct 2022 18:44:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA68B42B8C; Tue, 18 Oct 2022 18:43:02 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 2BAB341181; Tue, 18 Oct 2022 18:42:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111374; x=1697647374; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IjyRO+P/e55J8AQhK95/uasSwshK7ltM5zR8uRzQSV8=; b=nCvzlaLrvuqTRdIBecb9X2ANmz1/axFm/Ytsq1TBbhXoJ8eG3A4vOLnY vf0JV227+bNuxAC0imdU2Y5vJpzuluH0nSiDoxcKOOgPpa5pBY0n0ChKa Wch5KyySQRZyDcnlN63wdcxqqTnqxKsFxjbBIXIDOXE1ekswjaLNlv9NU vTZia3XIvkX8WcklOVWC3j8aQBIlwEAluOGMKmRx1pJ8QZ687EU/NRUfK wg/GMjetUHakOnh0Hsm++ANEVwMU7l3LSB5sWaUATSB4g4FairvkVEX78 ny4BCRoXbrX0aAF3sFLlzrQ6TuHi5J5TKDuyRQwJZnicEhDXmze+bH8SS w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192071" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192071" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836066" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836066" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:52 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 12/30] baseband/acc100: add protection for NULL HARQ input Date: Tue, 18 Oct 2022 17:39:00 -0700 Message-Id: <20221019003918.257506-13-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org It is possible to cause an invalid HW operation in case the user provides the BBDEV API and HARQ operation with input enabled and zero input. Adding protection for that case. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 8d11699c0c..ed4a08ea60 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1067,6 +1067,14 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, op->ldpc_dec.tb_params.ea : op->ldpc_dec.tb_params.eb; + if (unlikely(check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + (op->ldpc_dec.harq_combined_input.length == 0))) { + rte_bbdev_log(WARNING, "Null HARQ input size provided"); + /* Disable HARQ input in that case to carry forward. */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + fcw->hcin_en = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE); fcw->hcout_en = check_bit(op->ldpc_dec.op_flags, From patchwork Wed Oct 19 00:39:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118448 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81BCCA0560; Tue, 18 Oct 2022 18:44:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 086884281E; Tue, 18 Oct 2022 18:43:04 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 7588C4069C; Tue, 18 Oct 2022 18:42:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111374; x=1697647374; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fVgQ7vyhP5ePm3Pa4uuOB5FQ7pYwSKyMcHdUhgcUVag=; b=EwEqHjhOa7FoUQerAMZD9NZRxmV8HiZGqHXTJfgcvfaSYq4Nu0dv1jJ1 k3VSzS2Z3c2qNP8JE09dEExq7zxLhRMFt5KiGsrqUHeEOxWcq4JhlrPTU w1FHh6GDdyB5SwJwJNCi7Pc8Q38tGrN3tYyepMvAISzIYzv1e2Req4JZ6 TKThovrciypl6rvA/sluIJjoVj0rWizA+CXWaMm4GG3EIoYK0zSYeoapP 95J+ySt/Ly8jXKxgaFaOB1JBsyBYnahQ972u2qGF3y5d2YBMWvnA1xTS1 X7EHWyRvbDcyq2J+TubdxqCZXgDHaWNKhKORnXKh1Bbti0cMw9PAxBKT8 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192076" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192076" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836070" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836070" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:53 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v4 13/30] baseband/acc100: reset pointer after rte_free Date: Tue, 18 Oct 2022 17:39:01 -0700 Message-Id: <20221019003918.257506-14-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Set local pointer to NULL after rte_free. This needs to be set explicitly since logic may check for null pointers. Fixes: 060e7672930 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index ed4a08ea60..13eefaad80 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -618,6 +618,9 @@ acc100_dev_close(struct rte_bbdev *dev) rte_free(d->info_ring); rte_free(d->sw_rings_base); d->sw_rings_base = NULL; + d->tail_ptrs = NULL; + d->info_ring = NULL; + d->harq_layout = NULL; } /* Ensure all in flight HW transactions are completed */ usleep(ACC_LONG_WAIT); From patchwork Wed Oct 19 00:39:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118449 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14648A0560; Tue, 18 Oct 2022 18:44:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 392AF42BAB; Tue, 18 Oct 2022 18:43:05 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 12F8841181 for ; Tue, 18 Oct 2022 18:42:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111375; x=1697647375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QLxzpdwherFogAVJIj+DuJN0YnjpJpTlRQ4Gwrxi7zE=; b=C52ncvHqvxKNH/wYRkse3ClcWyhUXGzyoby5V5n5BuaEeXyLspU0UqUk D+oK5q+sm+pG26tw7PXyYnIj0r0V/tVs8OvodXHpyOw6Q9GVHsZL87LLL PVPCdcbLmlIFEYon1KDJyt6iCveqtG8X/W7oFMiphicdxC4KxLxGFxGh9 vXrXF8vfwJkzuJsrBnKY7Srk4bQIn9G6D2IORlNXW08Ml58kLsM8ovTfB BO7Y3Px8/3nyAYbP029c+W68/PeO1cV22fmdF3I+5dsGYScxlb+dmFa5o 44zji4laPEoiUCthL35DPrxUsTMUyeRTINUsi4Jnyh7hjn8YxySQKH3ww g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192081" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192081" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836075" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836075" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:54 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 14/30] baseband/acc100: fix debug print for LDPC FCW Date: Tue, 18 Oct 2022 17:39:02 -0700 Message-Id: <20221019003918.257506-15-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Print full size of FCW LDPC structure on debug messages. This is just a cosmetic fix, no need to fix on previous code base. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 13eefaad80..fc2fbe5511 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2756,7 +2756,7 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, #ifdef RTE_LIBRTE_BBDEV_DEBUG rte_memdump(stderr, "FCW", &desc->req.fcw_ld, - sizeof(desc->req.fcw_ld) - 8); + sizeof(desc->req.fcw_ld)); rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); #endif From patchwork Wed Oct 19 00:39:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118450 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54F3BA0560; Tue, 18 Oct 2022 18:44:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2160142BB0; Tue, 18 Oct 2022 18:43:06 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 6B9224281B for ; Tue, 18 Oct 2022 18:42:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111375; x=1697647375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OBJWEpiSae9mkfRxOX3MgWBU3+l0mQfwqbKDDTD63QM=; b=KhyFbXqKyOZoF+ShAmi2MZjtkDJGpU9ou0j50N+zdMedCL85Gs78XhS8 glrcn8VS17hhGy4p9f2ixCLyqQodIiNuVzKrn+Llix1p72hPJqwYzlW43 1nMImm749VAZh88Uhy5j0HvUMIlXyB8CjoTm/I3zrWKSF25u8bz1NAOL2 3GmDAFT/jRgqheTerEfukijfdn01NRRuBlhsh6SnjfTqZZyyS+Vg7PJWv cDr01a+vpk+6GEILCFwpauN9480tfQmc2207NEcp4BTHhFvbKowLqz0gx kZvFkjRQ0F/M3DV0cyrwZrQFr4UkKN74Lpge1hbJ6TbiOfL9jn+LibvBq A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192086" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192086" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836081" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836081" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:54 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 15/30] baseband/acc100: add enqueue status Date: Tue, 18 Oct 2022 17:39:03 -0700 Message-Id: <20221019003918.257506-16-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add enqueue status as part of rte_bbdev_queue_data. This is a new feature to update queue status and indicate the reason why a previous enqueue may or may not have consumed all requested operations. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 56 ++++++++++++++++++++------- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index fc2fbe5511..ca92ae906f 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2968,13 +2968,17 @@ acc100_enqueue_enc_cb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { /* Check if there are available space for further processing */ - if (unlikely(avail - 1 < 0)) + if (unlikely(avail - 1 < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= 1; ret = enqueue_enc_one_op_cb(q, ops[i], i); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } } if (unlikely(i == 0)) @@ -3006,20 +3010,26 @@ acc100_enqueue_ldpc_enc_cb(struct rte_bbdev_queue_data *q_data, int16_t enq, left = num; while (left > 0) { - if (unlikely(avail < 1)) + if (unlikely(avail < 1)) { + acc_enqueue_ring_full(q_data); break; + } avail--; enq = RTE_MIN(left, ACC_MUX_5GDL_DESC); if (check_mux(&ops[i], enq)) { ret = enqueue_ldpc_enc_n_op_cb(q, &ops[i], desc_idx, enq); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } i += enq; } else { ret = enqueue_ldpc_enc_one_op_cb(q, ops[i], desc_idx); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } i++; } desc_idx++; @@ -3057,13 +3067,17 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { cbs_in_tb = get_num_cbs_in_tb_enc(&ops[i]->turbo_enc); /* Check if there are available space for further processing */ - if (unlikely(avail - cbs_in_tb < 0)) + if (unlikely(avail - cbs_in_tb < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= cbs_in_tb; ret = enqueue_enc_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } enqueued_cbs += ret; } if (unlikely(enqueued_cbs == 0)) @@ -3120,13 +3134,17 @@ acc100_enqueue_dec_cb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { /* Check if there are available space for further processing */ - if (unlikely(avail - 1 < 0)) + if (unlikely(avail - 1 < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= 1; ret = enqueue_dec_one_op_cb(q, ops[i], i); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } } if (unlikely(i == 0)) @@ -3166,8 +3184,10 @@ acc100_enqueue_ldpc_dec_tb(struct rte_bbdev_queue_data *q_data, ret = enqueue_ldpc_dec_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } enqueued_cbs += ret; } if (unlikely(enqueued_cbs == 0)) @@ -3194,8 +3214,10 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, bool same_op = false; for (i = 0; i < num; ++i) { /* Check if there are available space for further processing */ - if (unlikely(avail < 1)) + if (unlikely(avail < 1)) { + acc_enqueue_ring_full(q_data); break; + } avail -= 1; if (i > 0) @@ -3208,8 +3230,10 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e, same_op); ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } } if (unlikely(i == 0)) @@ -3244,13 +3268,17 @@ acc100_enqueue_dec_tb(struct rte_bbdev_queue_data *q_data, for (i = 0; i < num; ++i) { cbs_in_tb = get_num_cbs_in_tb_dec(&ops[i]->turbo_dec); /* Check if there are available space for further processing */ - if (unlikely(avail - cbs_in_tb < 0)) + if (unlikely(avail - cbs_in_tb < 0)) { + acc_enqueue_ring_full(q_data); break; + } avail -= cbs_in_tb; ret = enqueue_dec_one_op_tb(q, ops[i], enqueued_cbs, cbs_in_tb); - if (ret < 0) + if (ret < 0) { + acc_enqueue_invalid(q_data); break; + } enqueued_cbs += ret; } From patchwork Wed Oct 19 00:39:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118451 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC84EA0560; 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a="368192090" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192090" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836089" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836089" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:55 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 16/30] baseband/acc100: add scatter-gather support Date: Tue, 18 Oct 2022 17:39:04 -0700 Message-Id: <20221019003918.257506-17-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add flag to support scatter-gather for the mbuf Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 38 ++++++++++++++++++--------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index ca92ae906f..0921e9a44d 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1363,6 +1363,8 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, * Store information about device capabilities * @param next_triplet * Index for ACC100 DMA Descriptor triplet + * @param scattergather + * Flag to support scatter-gather for the mbuf * * @return * Returns index of next triplet on success, other value if lengths of @@ -1372,12 +1374,16 @@ acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, static inline int acc100_dma_fill_blk_type_in(struct acc_dma_req_desc *desc, struct rte_mbuf **input, uint32_t *offset, uint32_t cb_len, - uint32_t *seg_total_left, int next_triplet) + uint32_t *seg_total_left, int next_triplet, + bool scattergather) { uint32_t part_len; struct rte_mbuf *m = *input; - part_len = (*seg_total_left < cb_len) ? *seg_total_left : cb_len; + if (scattergather) + part_len = (*seg_total_left < cb_len) ? *seg_total_left : cb_len; + else + part_len = cb_len; cb_len -= part_len; *seg_total_left -= part_len; @@ -1468,7 +1474,7 @@ acc100_dma_desc_le_fill(struct rte_bbdev_enc_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, - pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet); + pad_le_in(in_length_in_bytes, q), seg_total_left, next_triplet, false); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -1556,7 +1562,9 @@ acc100_dma_desc_td_fill(struct rte_bbdev_dec_op *op, } next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, kw, - seg_total_left, next_triplet); + seg_total_left, next_triplet, + check_bit(op->turbo_dec.op_flags, + RTE_BBDEV_TURBO_DEC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, "Mismatch between data to process and mbuf data length in bbdev_op: %p", @@ -1658,7 +1666,9 @@ acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, next_triplet = acc100_dma_fill_blk_type_in(desc, input, in_offset, input_length, - seg_total_left, next_triplet); + seg_total_left, next_triplet, + check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)); if (unlikely(next_triplet < 0)) { rte_bbdev_log(ERR, @@ -2726,10 +2736,9 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, fcw = &desc->req.fcw_ld; q->d->fcw_ld_fill(op, fcw, harq_layout); - /* Special handling when overusing mbuf */ - if (fcw->rm_e < ACC_MAX_E_MBUF) - seg_total_left = rte_pktmbuf_data_len(input) - - in_offset; + /* Special handling when using mbuf or not */ + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)) + seg_total_left = rte_pktmbuf_data_len(input) - in_offset; else seg_total_left = fcw->rm_e; @@ -2804,9 +2813,10 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, r = op->ldpc_dec.tb_params.r; while (mbuf_total_left > 0 && r < c) { - - seg_total_left = rte_pktmbuf_data_len(input) - in_offset; - + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DEC_SCATTER_GATHER)) + seg_total_left = rte_pktmbuf_data_len(input) - in_offset; + else + seg_total_left = op->ldpc_dec.input.length; /* Set up DMA descriptor */ desc = acc_desc(q, total_enqueued_cbs); desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset; @@ -2831,7 +2841,9 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); #endif - if (seg_total_left == 0) { + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_DEC_SCATTER_GATHER) + && (seg_total_left == 0)) { /* Go to the next mbuf */ input = input->next; in_offset = 0; From patchwork Wed Oct 19 00:39:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118452 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 11DC2A0560; Tue, 18 Oct 2022 18:44:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D8EB742B90; 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18 Oct 2022 09:42:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836093" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836093" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:55 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 17/30] baseband/acc100: add HARQ index helper function Date: Tue, 18 Oct 2022 17:39:05 -0700 Message-Id: <20221019003918.257506-18-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor code to use the HARQ index helper function and make harq_idx uint32. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 36 +++++++++++++-------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 0921e9a44d..d0c98ced32 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1050,7 +1050,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, union acc_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; - uint16_t harq_index; + uint32_t harq_index; uint32_t l; bool harq_prun = false; uint32_t max_hc_in; @@ -1098,8 +1098,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION); fcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION); - harq_index = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; + harq_index = hq_index(op->ldpc_dec.harq_combined_output.offset); #ifdef ACC100_EXT_MEM /* Limit cases when HARQ pruning is valid */ harq_prun = ((op->ldpc_dec.harq_combined_output.offset % @@ -1777,20 +1776,17 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, *h_out_length = desc->data_ptrs[next_triplet].blen; next_triplet++; - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { - desc->data_ptrs[next_triplet].address = - op->ldpc_dec.harq_combined_output.offset; + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + struct rte_bbdev_dec_op *prev_op; + uint32_t harq_idx, prev_harq_idx; + desc->data_ptrs[next_triplet].address = op->ldpc_dec.harq_combined_output.offset; /* Adjust based on previous operation */ - struct rte_bbdev_dec_op *prev_op = desc->op_addr; + prev_op = desc->op_addr; op->ldpc_dec.harq_combined_output.length = prev_op->ldpc_dec.harq_combined_output.length; - int16_t hq_idx = op->ldpc_dec.harq_combined_output.offset / - ACC_HARQ_OFFSET; - int16_t prev_hq_idx = - prev_op->ldpc_dec.harq_combined_output.offset - / ACC_HARQ_OFFSET; - harq_layout[hq_idx].val = harq_layout[prev_hq_idx].val; + harq_idx = hq_index(op->ldpc_dec.harq_combined_output.offset); + prev_harq_idx = hq_index(prev_op->ldpc_dec.harq_combined_output.offset); + harq_layout[harq_idx].val = harq_layout[prev_harq_idx].val; #ifndef ACC100_EXT_MEM struct rte_bbdev_op_data ho = op->ldpc_dec.harq_combined_output; @@ -2534,6 +2530,9 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *hq_output_head, *hq_output; uint16_t harq_dma_length_in, harq_dma_length_out; uint16_t harq_in_length = op->ldpc_dec.harq_combined_input.length; + bool ddr_mem_in; + union acc_harq_layout_data *harq_layout; + uint32_t harq_index; if (harq_in_length == 0) { rte_bbdev_log(ERR, "Loopback of invalid null size\n"); @@ -2553,13 +2552,12 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, } harq_dma_length_out = harq_dma_length_in; - bool ddr_mem_in = check_bit(op->ldpc_dec.op_flags, + ddr_mem_in = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE); - union acc_harq_layout_data *harq_layout = q->d->harq_layout; - uint16_t harq_index = (ddr_mem_in ? + harq_layout = q->d->harq_layout; + harq_index = hq_index(ddr_mem_in ? op->ldpc_dec.harq_combined_input.offset : - op->ldpc_dec.harq_combined_output.offset) - / ACC_HARQ_OFFSET; + op->ldpc_dec.harq_combined_output.offset); desc = acc_desc(q, total_enqueued_cbs); fcw = &desc->req.fcw_ld; From patchwork Wed Oct 19 00:39:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118453 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D58EAA0560; Tue, 18 Oct 2022 18:44:42 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C46DF42BB9; Tue, 18 Oct 2022 18:43:08 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 1B4CD4281E for ; Tue, 18 Oct 2022 18:42:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111377; x=1697647377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OVTyyLqgxNkb/jRlrUoqzvwni9fxozFng/bfnrWWetk=; b=PiY+c69ymtqEG7v7cUPSdLzEhSyI0e4yD0AD2aCn+xS1E+IEwvo+uuTG 6mDyXPlrCPv5th+ISc9/sQtUQzIO1gKxLkjv5e7C1jftUVcxWn2BwmNtr jLdv1s7NNPjfbcQE+/ZQxNOHC10p9sAmzuWs6MBLiaGuoUf8WnOcOYrox PVYzQc5hRm4OtQZ/Jvio6EfCNvrTtCFNiyTXJ1z8HOUaJGTdqpo+URvH8 ezu1Zy42vPGgB58NQg4HMaVPxQ3xIrL1uVnib6fLUIYW40z9F2FBQDbEG ONi0CvEpLz1QQo1g34DGskWU5lz4/ywscnSSMux//YADD2pFpeWl+eqUc g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192100" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192100" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836098" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836098" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:56 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 18/30] baseband/acc100: enable input validation by default Date: Tue, 18 Oct 2022 17:39:06 -0700 Message-Id: <20221019003918.257506-19-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable validation functions by default and provide a new flag RTE_LIBRTE_SKIP_VALIDATE if the user wants to run without validating input to save cycles. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 36 +++++++++++++-------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index d0c98ced32..c75a426d38 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1800,7 +1800,7 @@ acc100_dma_desc_ld_update(struct rte_bbdev_dec_op *op, desc->op_addr = op; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo encoder parameters */ static inline int validate_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) @@ -2063,10 +2063,10 @@ enqueue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, seg_total_left; struct rte_mbuf *input, *output_head, *output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo encoder validation failed"); + rte_bbdev_log(ERR, "Turbo encoder validation rejected"); return -EINVAL; } #endif @@ -2115,10 +2115,10 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, uint16_t in_length_in_bytes; struct rte_bbdev_op_ldpc_enc *enc = &ops[0]->ldpc_enc; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_enc_op(ops[0], q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -2175,10 +2175,10 @@ enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, seg_total_left; struct rte_mbuf *input, *output_head, *output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -2231,10 +2231,10 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_idx, current_enqueued_cbs = 0; uint64_t fcw_offset; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo encoder validation failed"); + rte_bbdev_log(ERR, "Turbo encoder validation rejected"); return -EINVAL; } #endif @@ -2305,7 +2305,7 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int validate_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) @@ -2463,10 +2463,10 @@ enqueue_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, struct rte_mbuf *input, *h_output_head, *h_output, *s_output_head, *s_output; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo decoder validation failed"); + rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; } #endif @@ -2686,10 +2686,10 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, return ret; } -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC decoder validation failed"); + rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } #endif @@ -2787,10 +2787,10 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, uint64_t fcw_offset; union acc_harq_layout_data *harq_layout; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_ldpc_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC decoder validation failed"); + rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } #endif @@ -2879,10 +2879,10 @@ enqueue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, uint16_t desc_idx, current_enqueued_cbs = 0; uint64_t fcw_offset; -#ifdef RTE_LIBRTE_BBDEV_DEBUG +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ if (validate_dec_op(op, q) == -1) { - rte_bbdev_log(ERR, "Turbo decoder validation failed"); + rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; } #endif From patchwork Wed Oct 19 00:39:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118454 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 73A70A0560; Tue, 18 Oct 2022 18:44:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0571E42BA0; Tue, 18 Oct 2022 18:43:10 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 723F44161A for ; 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a="803836104" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836104" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:56 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 19/30] baseband/acc100: added LDPC transport block support Date: Tue, 18 Oct 2022 17:39:07 -0700 Message-Id: <20221019003918.257506-20-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added LDPC enqueue functions to handle transport blocks. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 164 +++++++++++++++++++++++++- 1 file changed, 163 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index c75a426d38..580780c274 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2164,6 +2164,56 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, return num; } +/* Enqueue one encode operations for ACC100 device for a partial TB + * all codes blocks have same configuration multiplexed on the same descriptor. + */ +static inline void +enqueue_ldpc_enc_part_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, + uint16_t total_enqueued_descs, int16_t num_cbs, uint32_t e, + uint16_t in_len_bytes, uint32_t out_len_bytes, uint32_t *in_offset, + uint32_t *out_offset) +{ + union acc_dma_desc *desc = NULL; + struct rte_mbuf *output_head, *output; + int i, next_triplet; + struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; + uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs) & q->sw_ring_wrap_mask); + + desc = q->ring_addr + desc_idx; + acc_fcw_le_fill(op, &desc->req.fcw_le, num_cbs, e); + + /* This could be done at polling. */ + acc_header_init(&desc->req); + desc->req.numCBs = num_cbs; + + desc->req.m2dlen = 1 + num_cbs; + desc->req.d2mlen = num_cbs; + next_triplet = 1; + + for (i = 0; i < num_cbs; i++) { + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset(enc->input.data, *in_offset); + *in_offset += in_len_bytes; + desc->req.data_ptrs[next_triplet].blen = in_len_bytes; + next_triplet++; + desc->req.data_ptrs[next_triplet].address = + rte_pktmbuf_iova_offset(enc->output.data, *out_offset); + *out_offset += out_len_bytes; + desc->req.data_ptrs[next_triplet].blen = out_len_bytes; + next_triplet++; + enc->output.length += out_len_bytes; + output_head = output = enc->output.data; + mbuf_append(output_head, output, out_len_bytes); + } + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + rte_memdump(stderr, "FCW", &desc->req.fcw_le, + sizeof(desc->req.fcw_le) - 8); + rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc)); +#endif + +} + /* Enqueue one encode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, @@ -2305,6 +2355,76 @@ enqueue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, return current_enqueued_cbs; } +/* Enqueue one encode operations for ACC100 device in TB mode. + * returns the number of descs used. + */ +static inline int +enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, + uint16_t enq_descs, uint8_t cbs_in_tb) +{ +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE + if (validate_ldpc_enc_op(op, q) == -1) { + rte_bbdev_log(ERR, "LDPC encoder validation failed"); + return -EINVAL; + } +#endif + uint8_t num_a, num_b; + uint16_t desc_idx; + uint8_t r = op->ldpc_enc.tb_params.r; + uint8_t cab = op->ldpc_enc.tb_params.cab; + union acc_dma_desc *desc; + uint16_t init_enq_descs = enq_descs; + uint16_t input_len_B = ((op->ldpc_enc.basegraph == 1 ? 22 : 10) * + op->ldpc_enc.z_c - op->ldpc_enc.n_filler) >> 3; + uint32_t in_offset = 0, out_offset = 0; + uint16_t return_descs; + + if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + input_len_B -= 3; + + if (r < cab) { + num_a = cab - r; + num_b = cbs_in_tb - cab; + } else { + num_a = 0; + num_b = cbs_in_tb - r; + } + + while (num_a > 0) { + uint32_t e = op->ldpc_enc.tb_params.ea; + uint32_t out_len_bytes = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_a, ACC_MUX_5GDL_DESC); + num_a -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_bytes, &in_offset, &out_offset); + enq_descs++; + } + while (num_b > 0) { + uint32_t e = op->ldpc_enc.tb_params.eb; + uint32_t out_len_bytes = (e + 7) >> 3; + uint8_t enq = RTE_MIN(num_b, ACC_MUX_5GDL_DESC); + num_b -= enq; + enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B, + out_len_bytes, &in_offset, &out_offset); + enq_descs++; + } + + return_descs = enq_descs - init_enq_descs; + /* Keep total number of CBs in first TB. */ + desc_idx = ((q->sw_ring_head + init_enq_descs) & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.cbs_in_tb = return_descs; /** Actual number of descriptors. */ + desc->req.op_addr = op; + + /* Set SDone on last CB descriptor for TB mode. */ + desc_idx = ((q->sw_ring_head + enq_descs - 1) & q->sw_ring_wrap_mask); + desc = q->ring_addr + desc_idx; + desc->req.sdone_enable = 1; + desc->req.irq_enable = q->irq_enable; + desc->req.op_addr = op; + return return_descs; +} + #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validates turbo decoder parameters */ static inline int @@ -2881,6 +3001,10 @@ enqueue_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE /* Validate op structure */ + if (cbs_in_tb == 0) { + rte_bbdev_log(ERR, "Turbo decoder invalid number of CBs"); + return -EINVAL; + } if (validate_dec_op(op, q) == -1) { rte_bbdev_log(ERR, "Turbo decoder validation rejected"); return -EINVAL; @@ -3102,6 +3226,44 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, return i; } +/* Enqueue LDPC encode operations for ACC100 device in TB mode. */ +static uint16_t +acc100_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data, + struct rte_bbdev_enc_op **ops, uint16_t num) +{ + struct acc_queue *q = q_data->queue_private; + int32_t avail = acc_ring_avail_enq(q); + uint16_t i, enqueued_descs = 0; + uint8_t cbs_in_tb; + int descs_used; + + for (i = 0; i < num; ++i) { + cbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc); + /* Check if there are available space for further processing. */ + if (unlikely(avail - cbs_in_tb < 0)) { + acc_enqueue_ring_full(q_data); + break; + } + descs_used = enqueue_ldpc_enc_one_op_tb(q, ops[i], enqueued_descs, cbs_in_tb); + if (descs_used < 0) { + acc_enqueue_invalid(q_data); + break; + } + enqueued_descs += descs_used; + avail -= descs_used; + } + if (unlikely(enqueued_descs == 0)) + return 0; /* Nothing to enqueue. */ + + acc_dma_enqueue(q, enqueued_descs, &q_data->queue_stats); + + /* Update stats. */ + q_data->queue_stats.enqueued_count += i; + q_data->queue_stats.enqueue_err_count += num - i; + + return i; +} + /* Enqueue encode operations for ACC100 device. */ static uint16_t acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data, @@ -3125,7 +3287,7 @@ acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - return acc100_enqueue_enc_tb(q_data, ops, num); + return acc100_enqueue_ldpc_enc_tb(q_data, ops, num); else return acc100_enqueue_ldpc_enc_cb(q_data, ops, num); } From patchwork Wed Oct 19 00:39:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118455 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0FF8AA0560; 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a="368192107" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192107" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836111" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836111" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:57 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 20/30] baseband/acc100: update validate LDPC enc/dec Date: Tue, 18 Oct 2022 17:39:08 -0700 Message-Id: <20221019003918.257506-21-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update validate functions to check for valid LDPC parameters to avoid any HW issues. Adding protection for null corner case and for HARQ inbound size out of range. HARQ input size from application may be invalid and causing HW issue. Add checks to ensure that if HARQ is invalid, set to some valid size to ensure HW issues do not occur. Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc_common.h | 1 + drivers/baseband/acc/rte_acc100_pmd.c | 285 +++++++++++++++++++++++--- 2 files changed, 255 insertions(+), 31 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index 97d10b8b40..eae7eab4e9 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -121,6 +121,7 @@ #define ACC_ALGO_SPA 0 #define ACC_ALGO_MSA 1 #define ACC_HARQ_ALIGN_64B 64 +#define ACC_MAX_ZC 384 /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 580780c274..94863d7afd 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1953,14 +1953,11 @@ static inline int validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) { struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc; + int K, N, q_m, crc24; if (!validate_op_required(q)) return 0; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); - return -1; - } if (ldpc_enc->input.data == NULL) { rte_bbdev_log(ERR, "Invalid input pointer"); return -1; @@ -1969,17 +1966,12 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) rte_bbdev_log(ERR, "Invalid output pointer"); return -1; } - if (ldpc_enc->input.length > - RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { - rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", - ldpc_enc->input.length, - RTE_BBDEV_LDPC_MAX_CB_SIZE); + if (ldpc_enc->input.length == 0) { + rte_bbdev_log(ERR, "CB size (%u) is null", ldpc_enc->input.length); return -1; } if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) { - rte_bbdev_log(ERR, - "BG (%u) is out of range 1 <= value <= 2", - ldpc_enc->basegraph); + rte_bbdev_log(ERR, "BG (%u) is out of range 1 <= value <= 2", ldpc_enc->basegraph); return -1; } if (ldpc_enc->rv_index > 3) { @@ -1994,13 +1986,89 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op, struct acc_queue *q) ldpc_enc->code_block_mode); return -1; } - int K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; - if (ldpc_enc->n_filler >= K) { - rte_bbdev_log(ERR, - "K and F are not compatible %u %u", - K, ldpc_enc->n_filler); + if (ldpc_enc->z_c > ACC_MAX_ZC) { + rte_bbdev_log(ERR, "Zc (%u) is out of range", ldpc_enc->z_c); + return -1; + } + + K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; + N = (ldpc_enc->basegraph == 1 ? ACC_N_ZC_1 : ACC_N_ZC_2) * ldpc_enc->z_c; + q_m = ldpc_enc->q_m; + crc24 = 0; + + if (check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_CRC_24A_ATTACH) || + check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + crc24 = 24; + if ((K - ldpc_enc->n_filler) % 8 > 0) { + rte_bbdev_log(ERR, "K - F not byte aligned %u", K - ldpc_enc->n_filler); + return -1; + } + if (ldpc_enc->n_filler > (K - 2 * ldpc_enc->z_c)) { + rte_bbdev_log(ERR, "K - F invalid %u %u", K, ldpc_enc->n_filler); + return -1; + } + if ((ldpc_enc->n_cb > N) || (ldpc_enc->n_cb <= K)) { + rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", ldpc_enc->n_cb, K, N); return -1; } + if (!check_bit(op->ldpc_enc.op_flags, + RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) && + ((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) + || (q_m > 8))) { + rte_bbdev_log(ERR, "Qm (%u) is out of range", ldpc_enc->q_m); + return -1; + } + if (ldpc_enc->code_block_mode == RTE_BBDEV_CODE_BLOCK) { + if (ldpc_enc->cb_params.e == 0) { + rte_bbdev_log(ERR, "E is null"); + return -1; + } + if (q_m > 0) { + if (ldpc_enc->cb_params.e % q_m > 0) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + } + if ((ldpc_enc->z_c <= 11) && (ldpc_enc->cb_params.e > 3456)) { + rte_bbdev_log(ERR, "E too large for small block"); + return -1; + } + if (ldpc_enc->input.length > + RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { + rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", + ldpc_enc->input.length, + RTE_BBDEV_LDPC_MAX_CB_SIZE); + return -1; + } + if (K < (int) (ldpc_enc->input.length * 8 + ldpc_enc->n_filler) + crc24) { + rte_bbdev_log(ERR, + "K and F not matching input size %u %u %u", + K, ldpc_enc->n_filler, + ldpc_enc->input.length); + return -1; + } + } else { + if ((ldpc_enc->tb_params.c == 0) || + (ldpc_enc->tb_params.ea == 0) || + (ldpc_enc->tb_params.eb == 0)) { + rte_bbdev_log(ERR, "TB parameter is null"); + return -1; + } + if (q_m > 0) { + if ((ldpc_enc->tb_params.ea % q_m > 0) || + (ldpc_enc->tb_params.eb % q_m > 0)) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + } + if ((ldpc_enc->z_c <= 11) && (RTE_MAX(ldpc_enc->tb_params.ea, + ldpc_enc->tb_params.eb) > 3456)) { + rte_bbdev_log(ERR, "E too large for small block"); + return -1; + } + } return 0; } @@ -2009,24 +2077,30 @@ static inline int validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) { struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec; + int K, N, q_m; + uint32_t min_harq_input; if (!validate_op_required(q)) return 0; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); + if (ldpc_dec->input.data == NULL) { + rte_bbdev_log(ERR, "Invalid input pointer"); + return -1; + } + if (ldpc_dec->hard_output.data == NULL) { + rte_bbdev_log(ERR, "Invalid output pointer"); + return -1; + } + if (ldpc_dec->input.length == 0) { + rte_bbdev_log(ERR, "input is null"); return -1; } if ((ldpc_dec->basegraph > 2) || (ldpc_dec->basegraph == 0)) { - rte_bbdev_log(ERR, - "BG (%u) is out of range 1 <= value <= 2", - ldpc_dec->basegraph); + rte_bbdev_log(ERR, "BG (%u) is out of range 1 <= value <= 2", ldpc_dec->basegraph); return -1; } if (ldpc_dec->iter_max == 0) { - rte_bbdev_log(ERR, - "iter_max (%u) is equal to 0", - ldpc_dec->iter_max); + rte_bbdev_log(ERR, "iter_max (%u) is equal to 0", ldpc_dec->iter_max); return -1; } if (ldpc_dec->rv_index > 3) { @@ -2041,13 +2115,162 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op, struct acc_queue *q) ldpc_dec->code_block_mode); return -1; } - int K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; - if (ldpc_dec->n_filler >= K) { - rte_bbdev_log(ERR, - "K and F are not compatible %u %u", - K, ldpc_dec->n_filler); + /* Check Zc is valid value. */ + if ((ldpc_dec->z_c > ACC_MAX_ZC) || (ldpc_dec->z_c < 2)) { + rte_bbdev_log(ERR, "Zc (%u) is out of range", ldpc_dec->z_c); + return -1; + } + if (ldpc_dec->z_c > 256) { + if ((ldpc_dec->z_c % 32) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 128) { + if ((ldpc_dec->z_c % 16) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 64) { + if ((ldpc_dec->z_c % 8) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 32) { + if ((ldpc_dec->z_c % 4) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } else if (ldpc_dec->z_c > 16) { + if ((ldpc_dec->z_c % 2) != 0) { + rte_bbdev_log(ERR, "Invalid Zc %d", ldpc_dec->z_c); + return -1; + } + } + + K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; + N = (ldpc_dec->basegraph == 1 ? ACC_N_ZC_1 : ACC_N_ZC_2) * ldpc_dec->z_c; + q_m = ldpc_dec->q_m; + + if (ldpc_dec->n_filler >= K - 2 * ldpc_dec->z_c) { + rte_bbdev_log(ERR, "K and F are not compatible %u %u", K, ldpc_dec->n_filler); + return -1; + } + if ((ldpc_dec->n_cb > N) || (ldpc_dec->n_cb <= K)) { + rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", ldpc_dec->n_cb, K, N); + return -1; + } + if (((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) + || (q_m > 8))) { + rte_bbdev_log(ERR, "Qm (%u) is out of range", ldpc_dec->q_m); + return -1; + } + if (ldpc_dec->code_block_mode == RTE_BBDEV_CODE_BLOCK) { + if (ldpc_dec->cb_params.e == 0) { + rte_bbdev_log(ERR, "E is null"); + return -1; + } + if (ldpc_dec->cb_params.e % q_m > 0) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + if (ldpc_dec->cb_params.e > 512 * ldpc_dec->z_c) { + rte_bbdev_log(ERR, "E too high"); + return -1; + } + } else { + if ((ldpc_dec->tb_params.c == 0) || + (ldpc_dec->tb_params.ea == 0) || + (ldpc_dec->tb_params.eb == 0)) { + rte_bbdev_log(ERR, "TB parameter is null"); + return -1; + } + if ((ldpc_dec->tb_params.ea % q_m > 0) || + (ldpc_dec->tb_params.eb % q_m > 0)) { + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); + return -1; + } + if ((ldpc_dec->tb_params.ea > 512 * ldpc_dec->z_c) || + (ldpc_dec->tb_params.eb > 512 * ldpc_dec->z_c)) { + rte_bbdev_log(ERR, "E too high"); + return -1; + } + } + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DECODE_BYPASS)) { + rte_bbdev_log(ERR, "Avoid LDPC Decode bypass"); + return -1; + } + + /* Avoid HARQ compression for small block size */ + if ((check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) && (K < 2048)) + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; + + min_harq_input = check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION) ? 256 : 64; + if (check_bit(op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) && + ldpc_dec->harq_combined_input.length < + min_harq_input) { + rte_bbdev_log(ERR, "HARQ input size is too small %d < %d", + ldpc_dec->harq_combined_input.length, + min_harq_input); return -1; } + + /* Enforce in-range HARQ input size */ + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + uint32_t max_harq_input = RTE_ALIGN_CEIL(ldpc_dec->n_cb - ldpc_dec->n_filler, 64); + + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION)) + max_harq_input = max_harq_input * 3 / 4; + + if (ldpc_dec->harq_combined_input.length > max_harq_input) { + rte_bbdev_log(ERR, + "HARQ input size out of range %d > %d, Ncb %d F %d K %d N %d", + ldpc_dec->harq_combined_input.length, + max_harq_input, ldpc_dec->n_cb, + ldpc_dec->n_filler, K, N); + /* Fallback to flush HARQ combine */ + ldpc_dec->harq_combined_input.length = 0; + + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + } + } + +#ifdef ACC100_EXT_MEM + /* Enforce in-range HARQ offset */ + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { + if ((op->ldpc_dec.harq_combined_input.offset >> 10) >= q->d->ddr_size) { + rte_bbdev_log(ERR, + "HARQin offset out of range %d > %d", + op->ldpc_dec.harq_combined_input.offset, + q->d->ddr_size); + return -1; + } + if ((op->ldpc_dec.harq_combined_input.offset & 0x3FF) > 0) { + rte_bbdev_log(ERR, + "HARQin offset not aligned on 1kB %d", + op->ldpc_dec.harq_combined_input.offset); + return -1; + } + } + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { + if ((op->ldpc_dec.harq_combined_output.offset >> 10) >= q->d->ddr_size) { + rte_bbdev_log(ERR, + "HARQout offset out of range %d > %d", + op->ldpc_dec.harq_combined_output.offset, + q->d->ddr_size); + return -1; + } + if ((op->ldpc_dec.harq_combined_output.offset & 0x3FF) > 0) { + rte_bbdev_log(ERR, + "HARQout offset not aligned on 1kB %d", + op->ldpc_dec.harq_combined_output.offset); + return -1; + } + } +#endif + return 0; } #endif @@ -2685,7 +2908,7 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, memset(fcw, 0, sizeof(struct acc_fcw_ld)); fcw->FCWversion = ACC_FCW_VER; fcw->qm = 2; - fcw->Zc = 384; + fcw->Zc = ACC_MAX_ZC; if (harq_in_length < 16 * ACC_N_ZC_1) fcw->Zc = 16; fcw->ncb = fcw->Zc * ACC_N_ZC_1; From patchwork Wed Oct 19 00:39:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118456 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 92780A0560; Tue, 18 Oct 2022 18:44:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA65642B7D; Tue, 18 Oct 2022 18:43:11 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id A1A2A42829 for ; Tue, 18 Oct 2022 18:42:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111378; x=1697647378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vx3mMM5n3WyzFyLFegciQ/ibPW0GfX/YeMCAlQTTZf8=; b=PKawweFgp7VZ8VrJX/UBe8+TTfv5HpH9Ecf1LFxEuwr4eRgKhkvZW5AD ei85STpIuJxdkFV5HcbiMIPKorcda5YDnSLFATCs82t/3ambLH+/vteAk AQWP+zylApjCUQZjZ5GIxxqJHruComhPWceM4fY4taPVJ3lf63Jw+sCgb LFQDnKTF2h2QZcr94JlyNeU/pTSBo/Jaunk7mRvR6SaorDfUew0PssV5a QqV26+mw62huNmykVcu5uMNYaY5KN6f90i1UNXXTXfsVwS171i9XL9xns 52BeHig3p1XkSc/I56SpZ6Nkdz4G/iGU/sDYHSZOJeULvNeN8bdxUxkLb Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192115" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192115" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836120" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836120" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:57 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 21/30] baseband/acc100: implement configurable queue depth Date: Tue, 18 Oct 2022 17:39:09 -0700 Message-Id: <20221019003918.257506-22-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement new feature to make queue depth configurable based on decode or encode mode. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 94863d7afd..a734be8553 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -776,9 +776,15 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F; q->aq_id = q_idx & 0xF; - q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ? - (1 << d->acc_conf.q_ul_4g.aq_depth_log2) : - (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + q->aq_depth = 0; + if (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_TURBO_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_4g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_DEC) + q->aq_depth = (1 << d->acc_conf.q_ul_5g.aq_depth_log2); + else if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) + q->aq_depth = (1 << d->acc_conf.q_dl_5g.aq_depth_log2); q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base, queue_offset(d->pf_device, From patchwork Wed Oct 19 00:39:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118457 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DC601A0560; Tue, 18 Oct 2022 18:45:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8CF6042BC5; Tue, 18 Oct 2022 18:43:12 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 0FA454161A for ; Tue, 18 Oct 2022 18:42:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111379; x=1697647379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Sk7ibhp6Waz1pS+sfnRESBiRcUuM6Jbxdy2qX8akelw=; b=AaBBFpA8LD6BKCIuQP/gEbBzZChqSXDvsU2yt6d7Y/KSPPcwTA6WfTMo +TOkOt5pzkoKcJsSkasHE27GHsdhiD4+C5/Iwcuk7dT0NVhi8uqGWczmm GlvCGaWHdZD61fNoCru8vCiLE3LFVsTh7SGh1eusU9+iKydzjWSMDP5rg bwUL0tm0xwqzc4ooT6jWq0q4RXsjYA17y7WlutP5tXS6XGJQTfxY3Teh+ GqB2779wLpcRQhio6BZFMRjwINNe6jk3nZizWumtpQRLsCDY2Rpn1I9wQ qem1mgipOrZqRGkeemMdT54W8IdueuVJtA97Ky83XvfQmTxQ6DDtZY4hY g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192122" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192122" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836128" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836128" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:58 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 22/30] baseband/acc100: add queue stop operation Date: Tue, 18 Oct 2022 17:39:10 -0700 Message-Id: <20221019003918.257506-23-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Implement new feature to stop queue operation. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index a734be8553..7d392bfba7 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -799,6 +799,65 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, return 0; } +static inline void +acc100_print_op(struct rte_bbdev_dec_op *op, enum rte_bbdev_op_type op_type, + uint16_t index) +{ + if (op == NULL) + return; + if (op_type == RTE_BBDEV_OP_LDPC_DEC) + rte_bbdev_log(DEBUG, + " Op 5GUL %d %d %d %d %d %d %d %d %d %d %d %d", + index, + op->ldpc_dec.basegraph, op->ldpc_dec.z_c, + op->ldpc_dec.n_cb, op->ldpc_dec.q_m, + op->ldpc_dec.n_filler, op->ldpc_dec.cb_params.e, + op->ldpc_dec.op_flags, op->ldpc_dec.rv_index, + op->ldpc_dec.iter_max, op->ldpc_dec.iter_count, + op->ldpc_dec.harq_combined_input.length + ); + else if (op_type == RTE_BBDEV_OP_LDPC_ENC) { + struct rte_bbdev_enc_op *op_dl = (struct rte_bbdev_enc_op *) op; + rte_bbdev_log(DEBUG, + " Op 5GDL %d %d %d %d %d %d %d %d %d", + index, + op_dl->ldpc_enc.basegraph, op_dl->ldpc_enc.z_c, + op_dl->ldpc_enc.n_cb, op_dl->ldpc_enc.q_m, + op_dl->ldpc_enc.n_filler, op_dl->ldpc_enc.cb_params.e, + op_dl->ldpc_enc.op_flags, op_dl->ldpc_enc.rv_index + ); + } +} + +static int +acc100_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct acc_queue *q; + struct rte_bbdev_dec_op *op; + uint16_t i; + + q = dev->data->queues[queue_id].queue_private; + rte_bbdev_log(INFO, "Queue Stop %d H/T/D %d %d %x OpType %d", + queue_id, q->sw_ring_head, q->sw_ring_tail, + q->sw_ring_depth, q->op_type); + for (i = 0; i < q->sw_ring_depth; ++i) { + op = (q->ring_addr + i)->req.op_addr; + acc100_print_op(op, q->op_type, i); + } + /* ignore all operations in flight and clear counters */ + q->sw_ring_tail = q->sw_ring_head; + q->aq_enqueued = 0; + q->aq_dequeued = 0; + dev->data->queues[queue_id].queue_stats.enqueued_count = 0; + dev->data->queues[queue_id].queue_stats.dequeued_count = 0; + dev->data->queues[queue_id].queue_stats.enqueue_err_count = 0; + dev->data->queues[queue_id].queue_stats.dequeue_err_count = 0; + dev->data->queues[queue_id].queue_stats.enqueue_warn_count = 0; + dev->data->queues[queue_id].queue_stats.dequeue_warn_count = 0; + + return 0; +} + /* Release ACC100 queue */ static int acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) @@ -991,6 +1050,7 @@ static const struct rte_bbdev_ops acc100_bbdev_ops = { .info_get = acc100_dev_info_get, .queue_setup = acc100_queue_setup, .queue_release = acc100_queue_release, + .queue_stop = acc100_queue_stop, .queue_intr_enable = acc100_queue_intr_enable, .queue_intr_disable = acc100_queue_intr_disable }; From patchwork Wed Oct 19 00:39:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118458 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF3EBA0560; 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a="368192127" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192127" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836138" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836138" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:58 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 23/30] baseband/acc100: update uplink CB input length Date: Tue, 18 Oct 2022 17:39:11 -0700 Message-Id: <20221019003918.257506-24-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use the FCW E parameter for rate matching as the code block input length. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 7d392bfba7..c94fe14439 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -1713,7 +1713,7 @@ acc100_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, crc24_overlap = 24; /* Compute some LDPC BG lengths */ - input_length = dec->cb_params.e; + input_length = fcw->rm_e; if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_LLR_COMPRESSION)) input_length = (input_length * 3 + 3) / 4; From patchwork Wed Oct 19 00:39:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118459 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4DBADA0560; Tue, 18 Oct 2022 18:45:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A86742BCE; Tue, 18 Oct 2022 18:43:14 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 2492942685 for ; Tue, 18 Oct 2022 18:42:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111380; x=1697647380; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZzQ4rLku7w4+c+PUHsN692mqahBjH2LCLeOyItsNRao=; b=b1mAcnCJGFpYYG7tbVK91+j1B24yKkBIB0I8CEcGuW9XU0lr7BUKo8MF koYyv3D+LsN5z/h5wRh0hFJFDke91kKi3eZ3+0KPWJDUU03z1CjJeaiRu szbmMrJHo45qzU7gFXtqNd3i+XZIYfaiBRg8u3+3DDOz6pdS59N6ZdtyJ TrKWGvLGgKZbrvDvdNdeUy593z+kGgadZ+64h7kRFaOf2Ar4adqXIT5bl ct8D7BLXi/EFC5iMmOEN7i4Sk7iab3mjxOWrYV2FHUt1XEuuLgPBMMLpi SLtCfI5CvlVQRqqYOGm16UQG8o1IJfpAc078zwuyglkwuZenNXReV+8Ij g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192132" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192132" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:42:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836143" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836143" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:59 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 24/30] baseband/acc100: update log messages Date: Tue, 18 Oct 2022 17:39:12 -0700 Message-Id: <20221019003918.257506-25-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add extra values for some log messages. No functional impact. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index c94fe14439..e00a636d9f 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -979,6 +979,7 @@ acc100_dev_info_get(struct rte_bbdev *dev, /* Read and save the populated config from ACC100 registers */ fetch_acc100_config(dev); + /* Check the status of device */ dev_info->device_status = RTE_BBDEV_DEV_NOT_SUPPORTED; /* Expose number of queues */ @@ -2653,7 +2654,7 @@ enqueue_ldpc_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op *op, { #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE if (validate_ldpc_enc_op(op, q) == -1) { - rte_bbdev_log(ERR, "LDPC encoder validation failed"); + rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } #endif @@ -3876,8 +3877,9 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, - rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", + desc, rsp.val, + cb_idx, cbs_in_tb); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0); @@ -3973,6 +3975,7 @@ dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data, return -1; rsp.val = atom_desc.rsp.val; + rte_bbdev_log_debug("Resp. desc %p: %x\n", desc, rsp.val); /* Dequeue */ op = desc->req.op_addr; From patchwork Wed Oct 19 00:39:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118460 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19F59A0560; Tue, 18 Oct 2022 18:45:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0263A42BD1; Tue, 18 Oct 2022 18:43:15 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 8F8CB42B78 for ; Tue, 18 Oct 2022 18:43:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111380; x=1697647380; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2U1oHyMhSlw/pnUFA9uIU6DYUvdyui4TQeN3daQFszM=; b=JYLbpvCgtbA1OPo5a8kWfgpzKgtyr+7Fv88QbqmO6oNfCyLC4cV6tm9Z mr72cY+A3Y/mYnKz2EXthbd7VDHZeBdSeFvjCSwDj6mV6LnGdbvPLKJS/ n+HDBmeXXu3tj5DX5FYti36jF33YYnuwV/NXqldX+i4aILjcB31XSbp3k Vv/SjGBfYSsBHUndBsY/0asyhPfYkHi+VRlkWpP/pSeudieoVfqYmqMa+ ZtEk+rF8lJwd3alz9XxsR5MDgPNpMx0PDjP0rtgc9+MmX0YUNk8Tycy4u Otd+x8XYQBnV/HCSUP7ikXOBbJSkzO0vjLLoJbNwZSgzEc+rbAWUU/aOk w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192134" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192134" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:43:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836147" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836147" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:42:59 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 25/30] baseband/acc100: store FCW from first CB descriptor Date: Tue, 18 Oct 2022 17:39:13 -0700 Message-Id: <20221019003918.257506-26-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the descriptor from the first code block from a transport block. Copy the LDPC FCW from the first descriptor into the rest of the CBs in that TB. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index e00a636d9f..ed5ee63950 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -3188,6 +3188,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, uint16_t total_enqueued_cbs, uint8_t cbs_in_tb) { union acc_dma_desc *desc = NULL; + union acc_dma_desc *desc_first = NULL; int ret; uint8_t r, c; uint32_t in_offset, h_out_offset, @@ -3207,6 +3208,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, desc_idx = acc_desc_idx(q, total_enqueued_cbs); desc = q->ring_addr + desc_idx; + desc_first = desc; fcw_offset = (desc_idx << 8) + ACC_DESC_FCW_OFFSET; harq_layout = q->d->harq_layout; q->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout); @@ -3229,6 +3231,7 @@ enqueue_ldpc_dec_one_op_tb(struct acc_queue *q, struct rte_bbdev_dec_op *op, desc = acc_desc(q, total_enqueued_cbs); desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset; desc->req.data_ptrs[0].blen = ACC_FCW_LD_BLEN; + rte_memcpy(&desc->req.fcw_ld, &desc_first->req.fcw_ld, ACC_FCW_LD_BLEN); ret = acc100_dma_desc_ld_fill(op, &desc->req, &input, h_output, &in_offset, &h_out_offset, &h_out_length, From patchwork Wed Oct 19 00:39:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118461 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C6EA7A0560; Tue, 18 Oct 2022 18:45:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D210242BD5; Tue, 18 Oct 2022 18:43:15 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 1029B42B78 for ; Tue, 18 Oct 2022 18:43:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111381; x=1697647381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qz+vYOu7DrCCOIiLYmIkt50aBcSRuzjoo7mQoXM1rTY=; b=j6aKwmOWGfo+gPA/Jiu5qVrEKl5AYseld+cA+Oh641JZnCEhkTVBfl8G LN6YaIt2GUV10VWEfvCcGf5B8twi0+ucphDI8xO+h7kadw1zOp8TEACNq VvMntE3/FXbb2RU20lYVPIEjcIb3SOXu7xbJshUVLSD0/lxWbsTAGcWEm Pu1/EvyMFUhBQzHoPwOqOcjQw6BHsXPTkfrT3lTU616NK8S7vSDfpK6Df 8fU8uBpDBtapuItWyf1g0lpDphZ9eoe0EotDa0bR9+jM50ZIxZ9gf/N9k j4L90pYP9NFGM+L8id4+PeyH67DQAeFP+OqaxgSJ3PdSLozSbrnOt+pYR w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192139" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192139" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:43:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836157" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836157" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:43:00 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 26/30] baseband/acc100: update device info Date: Tue, 18 Oct 2022 17:39:14 -0700 Message-Id: <20221019003918.257506-27-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove unused capabilities, use dummy operation as start count for number of queues. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/rte_acc100_pmd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index ed5ee63950..45783a7a78 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -885,7 +885,6 @@ acc100_dev_info_get(struct rte_bbdev *dev, { struct acc_device *d = dev->data->dev_private; int i; - static const struct rte_bbdev_op_cap bbdev_capabilities[] = { { .type = RTE_BBDEV_OP_TURBO_DEC, @@ -897,7 +896,6 @@ acc100_dev_info_get(struct rte_bbdev *dev, RTE_BBDEV_TURBO_EARLY_TERMINATION | RTE_BBDEV_TURBO_DEC_INTERRUPTS | RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN | - RTE_BBDEV_TURBO_MAP_DEC | RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP | RTE_BBDEV_TURBO_DEC_CRC_24B_DROP | RTE_BBDEV_TURBO_DEC_SCATTER_GATHER, @@ -992,12 +990,13 @@ acc100_dev_info_get(struct rte_bbdev *dev, d->acc_conf.q_ul_5g.num_qgroups; dev_info->num_queues[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_aqs_per_groups * d->acc_conf.q_dl_5g.num_qgroups; + dev_info->num_queues[RTE_BBDEV_OP_FFT] = 0; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_DEC] = d->acc_conf.q_ul_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_TURBO_ENC] = d->acc_conf.q_dl_4g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_DEC] = d->acc_conf.q_ul_5g.num_qgroups; dev_info->queue_priority[RTE_BBDEV_OP_LDPC_ENC] = d->acc_conf.q_dl_5g.num_qgroups; dev_info->max_num_queues = 0; - for (i = RTE_BBDEV_OP_TURBO_DEC; i <= RTE_BBDEV_OP_LDPC_ENC; i++) + for (i = RTE_BBDEV_OP_NONE; i <= RTE_BBDEV_OP_LDPC_ENC; i++) dev_info->max_num_queues += dev_info->num_queues[i]; dev_info->queue_size_lim = ACC_MAX_QUEUE_DEPTH; dev_info->hardware_accelerated = true; From patchwork Wed Oct 19 00:39:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118463 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 01FA5A0560; Tue, 18 Oct 2022 18:45:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 78D4042BDD; Tue, 18 Oct 2022 18:43:17 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 2327B42B88 for ; Tue, 18 Oct 2022 18:43:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111382; x=1697647382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PQLfmJnMN3Uf+y+xhVFwgJiRtckp53c/+SoP+P8+36U=; b=L/a7NCoHgLSL2Q89lrbnkyEgY6ubyn2NEtr0AkkFCKbx5l+FeEhBo71b B0VqQUGFT4nnAxLdFYdkLGRQE3wvJuiWxaqyHbSp3egKL5v8unit+HL2s rmtvoOmqtSUcNNgrQ/ulj0m0rAxOrOK0qSiIPmK/FrAfEt67zmTSAgcyt wrpYoKUBE9LGmpdeEbJljE7NWFzEDAgpYaN1hWQrs+q5ad96PzUB+VBAA U13iRDvO7vuw68uPJFS4OeeX1d612+R2wgX/WLoooFgqLaDyuqcVeIywm wYgNPO7IUwvJnf45Vu/SiFP/iOcTW9jWauomBZxlj60pA6E4PiJymUWC2 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192141" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192141" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:43:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836169" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836169" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:43:00 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 27/30] baseband/acc100: add ring companion address Date: Tue, 18 Oct 2022 17:39:15 -0700 Message-Id: <20221019003918.257506-28-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Store the virtual address of companion ring as part of queue information. Use this address to calculate the op address. Signed-off-by: Hernan Vargas --- drivers/baseband/acc/rte_acc100_pmd.c | 179 +++++++++++++++++--------- 1 file changed, 116 insertions(+), 63 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 45783a7a78..87756839ef 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -676,6 +676,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, struct acc_device *d = dev->data->dev_private; struct acc_queue *q; int16_t q_idx; + int ret; if (d == NULL) { rte_bbdev_log(ERR, "Undefined device"); @@ -734,8 +735,8 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, RTE_CACHE_LINE_SIZE, conf->socket); if (q->lb_in == NULL) { rte_bbdev_log(ERR, "Failed to allocate lb_in memory"); - rte_free(q); - return -ENOMEM; + ret = -ENOMEM; + goto free_q; } q->lb_in_addr_iova = rte_malloc_virt2iova(q->lb_in); q->lb_out = rte_zmalloc_socket(dev->device->driver->name, @@ -743,11 +744,18 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, RTE_CACHE_LINE_SIZE, conf->socket); if (q->lb_out == NULL) { rte_bbdev_log(ERR, "Failed to allocate lb_out memory"); - rte_free(q->lb_in); - rte_free(q); - return -ENOMEM; + ret = -ENOMEM; + goto free_lb_in; } q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out); + q->companion_ring_addr = rte_zmalloc_socket(dev->device->driver->name, + d->sw_ring_max_depth * sizeof(*q->companion_ring_addr), + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->companion_ring_addr == NULL) { + rte_bbdev_log(ERR, "Failed to allocate companion_ring memory"); + ret = -ENOMEM; + goto free_lb_out; + } /* * Software queue ring wraps synchronously with the HW when it reaches @@ -767,10 +775,8 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q_idx = acc100_find_free_queue_idx(dev, conf); if (q_idx == -1) { - rte_free(q->lb_in); - rte_free(q->lb_out); - rte_free(q); - return -1; + ret = -EINVAL; + goto free_companion_ring_addr; } q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; @@ -797,6 +803,21 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, dev->data->queues[queue_id].queue_private = q; return 0; + +free_companion_ring_addr: + rte_free(q->companion_ring_addr); + q->companion_ring_addr = NULL; +free_lb_out: + rte_free(q->lb_out); + q->lb_out = NULL; +free_lb_in: + rte_free(q->lb_in); + q->lb_in = NULL; +free_q: + rte_free(q); + q = NULL; + + return ret; } static inline void @@ -869,6 +890,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) /* Mark the Queue as un-assigned */ d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF - (uint64_t) (1 << q->aq_id)); + rte_free(q->companion_ring_addr); rte_free(q->lb_in); rte_free(q->lb_out); rte_free(q); @@ -2395,7 +2417,7 @@ enqueue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op *op, /* Enqueue one encode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, - uint16_t total_enqueued_cbs, int16_t num) + uint16_t total_enqueued_descs, int16_t num) { union acc_dma_desc *desc = NULL; uint32_t out_length; @@ -2412,7 +2434,7 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, } #endif - desc = acc_desc(q, total_enqueued_cbs); + desc = acc_desc(q, total_enqueued_descs); acc_fcw_le_fill(ops[0], &desc->req.fcw_le, num, 0); /** This could be done at polling */ @@ -2442,6 +2464,11 @@ enqueue_ldpc_enc_n_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ops, } desc->req.op_addr = ops[0]; + /* Keep track of pointers even when multiplexed in single descriptor */ + struct acc_ptrs *context_ptrs = q->companion_ring_addr + + acc_desc_idx(q, total_enqueued_descs); + for (i = 0; i < num; i++) + context_ptrs->ptr[i].op_addr = ops[i]; #ifdef RTE_LIBRTE_BBDEV_DEBUG rte_memdump(stderr, "FCW", &desc->req.fcw_le, @@ -3790,7 +3817,8 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, /* Dequeue one encode operations from ACC100 device in CB mode */ static inline int dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, - uint16_t total_dequeued_cbs, uint32_t *aq_dequeued) + uint16_t *dequeued_ops, uint32_t *aq_dequeued, + uint16_t *dequeued_descs) { union acc_dma_desc *desc, atom_desc; union acc_dma_rsp_desc rsp; @@ -3798,7 +3826,7 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, int i; uint16_t desc_idx; - desc_idx = acc_desc_idx_tail(q, total_dequeued_cbs); + desc_idx = acc_desc_idx_tail(q, *dequeued_descs); desc = q->ring_addr + desc_idx; atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); @@ -3808,7 +3836,7 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, return -1; rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x", desc, rsp.val); + rte_bbdev_log_debug("Resp. desc %p: %x num %d\n", desc, rsp.val, desc->req.numCBs); /* Dequeue */ op = desc->req.op_addr; @@ -3828,27 +3856,35 @@ dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, desc->rsp.add_info_0 = 0; /*Reserved bits */ desc->rsp.add_info_1 = 0; /*Reserved bits */ - /* Flag that the muxing cause loss of opaque data */ - op->opaque_data = (void *)-1; - for (i = 0 ; i < desc->req.numCBs; i++) - ref_op[i] = op; + ref_op[0] = op; + struct acc_ptrs *context_ptrs = q->companion_ring_addr + desc_idx; + for (i = 1 ; i < desc->req.numCBs; i++) + ref_op[i] = context_ptrs->ptr[i].op_addr; + + /* One CB (op) was successfully dequeued */ + /* One op was successfully dequeued */ + (*dequeued_descs)++; + *dequeued_ops += desc->req.numCBs; /* One CB (op) was successfully dequeued */ return desc->req.numCBs; } -/* Dequeue one encode operations from ACC100 device in TB mode */ +/* Dequeue one LDPC encode operations from ACC100 device in TB mode + * That operation may cover multiple descriptors + */ static inline int dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, - uint16_t total_dequeued_cbs, uint32_t *aq_dequeued) + uint16_t *dequeued_ops, uint32_t *aq_dequeued, + uint16_t *dequeued_descs) { union acc_dma_desc *desc, *last_desc, atom_desc; union acc_dma_rsp_desc rsp; struct rte_bbdev_enc_op *op; uint8_t i = 0; - uint16_t current_dequeued_cbs = 0, cbs_in_tb; + uint16_t current_dequeued_descs = 0, descs_in_tb; - desc = acc_desc_tail(q, total_dequeued_cbs); + desc = acc_desc_tail(q, *dequeued_descs); atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); @@ -3857,9 +3893,9 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, return -1; /* Get number of CBs in dequeued TB */ - cbs_in_tb = desc->req.cbs_in_tb; + descs_in_tb = desc->req.cbs_in_tb; /* Get last CB */ - last_desc = acc_desc_tail(q, total_dequeued_cbs + cbs_in_tb - 1); + last_desc = acc_desc_tail(q, *dequeued_descs + descs_in_tb - 1); /* Check if last CB in TB is ready to dequeue (and thus * the whole TB) - checking sdone bit. If not return. */ @@ -3874,14 +3910,13 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, /* Clearing status, it will be set based on response */ op->status = 0; - while (i < cbs_in_tb) { - desc = acc_desc_tail(q, total_dequeued_cbs); + while (i < descs_in_tb) { + desc = acc_desc_tail(q, *dequeued_descs); atom_desc.atom_hdr = __atomic_load_n((uint64_t *)desc, __ATOMIC_RELAXED); rsp.val = atom_desc.rsp.val; - rte_bbdev_log_debug("Resp. desc %p: %x r %d c %d\n", - desc, rsp.val, - cb_idx, cbs_in_tb); + rte_bbdev_log_debug("Resp. desc %p: %x descs %d cbs %d\n", + desc, rsp.val, descs_in_tb, desc->req.numCBs); op->status |= ((rsp.input_err) ? (1 << RTE_BBDEV_DATA_ERROR) : 0); @@ -3895,14 +3930,15 @@ dequeue_enc_one_op_tb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, desc->rsp.val = ACC_DMA_DESC_TYPE; desc->rsp.add_info_0 = 0; desc->rsp.add_info_1 = 0; - total_dequeued_cbs++; - current_dequeued_cbs++; + (*dequeued_descs)++; + current_dequeued_descs++; i++; } *ref_op = op; - return current_dequeued_cbs; + (*dequeued_ops)++; + return current_dequeued_descs; } /* Dequeue one decode operation from ACC100 device in CB mode */ @@ -4092,12 +4128,12 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { struct acc_queue *q = q_data->queue_private; - uint16_t dequeue_num; uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; - uint16_t i, dequeued_cbs = 0; + uint16_t i, dequeued_ops = 0, dequeued_descs = 0; + int ret, cbm; struct rte_bbdev_enc_op *op; - int ret; + if (avail == 0) return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG @@ -4106,30 +4142,36 @@ acc100_dequeue_enc(struct rte_bbdev_queue_data *q_data, return 0; } #endif + op = (q->ring_addr + (q->sw_ring_tail & + q->sw_ring_wrap_mask))->req.op_addr; + if (unlikely(ops == NULL || op == NULL)) + return 0; + cbm = op->turbo_enc.code_block_mode; - dequeue_num = (avail < num) ? avail : num; - - for (i = 0; i < dequeue_num; ++i) { - op = acc_op_tail(q, dequeued_cbs); - if (op->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) - ret = dequeue_enc_one_op_tb(q, &ops[i], dequeued_cbs, - &aq_dequeued); + for (i = 0; i < num; i++) { + if (cbm == RTE_BBDEV_TRANSPORT_BLOCK) + ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); else - ret = dequeue_enc_one_op_cb(q, &ops[i], dequeued_cbs, - &aq_dequeued); + ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); if (ret < 0) break; - dequeued_cbs += ret; + + if (dequeued_ops >= num) + break; } q->aq_dequeued += aq_dequeued; - q->sw_ring_tail += dequeued_cbs; + q->sw_ring_tail += dequeued_descs; /* Update enqueue stats */ - q_data->queue_stats.dequeued_count += i; + q_data->queue_stats.dequeued_count += dequeued_ops; - return i; + return dequeued_ops; } /* Dequeue LDPC encode operations from ACC100 device. */ @@ -4140,24 +4182,36 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct acc_queue *q = q_data->queue_private; uint32_t avail = acc_ring_avail_deq(q); uint32_t aq_dequeued = 0; - uint16_t dequeue_num, i, dequeued_cbs = 0, dequeued_descs = 0; - int ret; + uint16_t i, dequeued_ops = 0, dequeued_descs = 0; + int ret, cbm; + struct rte_bbdev_enc_op *op; + union acc_dma_desc *desc; + if (q == NULL) + return 0; #ifdef RTE_LIBRTE_BBDEV_DEBUG - if (unlikely(ops == 0 && q == NULL)) + if (unlikely(ops == 0)) return 0; #endif - - dequeue_num = RTE_MIN(avail, num); - - for (i = 0; i < dequeue_num; i++) { - ret = dequeue_enc_one_op_cb(q, &ops[dequeued_cbs], - dequeued_descs, &aq_dequeued); + desc = q->ring_addr + (q->sw_ring_tail & q->sw_ring_wrap_mask); + if (unlikely(desc == NULL)) + return 0; + op = desc->req.op_addr; + if (unlikely(ops == NULL || op == NULL)) + return 0; + cbm = op->ldpc_enc.code_block_mode; + for (i = 0; i < avail; i++) { + if (cbm == RTE_BBDEV_TRANSPORT_BLOCK) + ret = dequeue_enc_one_op_tb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); + else + ret = dequeue_enc_one_op_cb(q, &ops[dequeued_ops], + &dequeued_ops, &aq_dequeued, + &dequeued_descs); if (ret < 0) break; - dequeued_cbs += ret; - dequeued_descs++; - if (dequeued_cbs >= num) + if (dequeued_ops >= num) break; } @@ -4165,12 +4219,11 @@ acc100_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, q->sw_ring_tail += dequeued_descs; /* Update enqueue stats */ - q_data->queue_stats.dequeued_count += dequeued_cbs; + q_data->queue_stats.dequeued_count += dequeued_ops; - return dequeued_cbs; + return dequeued_ops; } - /* Dequeue decode operations from ACC100 device. */ static uint16_t acc100_dequeue_dec(struct rte_bbdev_queue_data *q_data, From patchwork Wed Oct 19 00:39:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118462 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 45A59A0560; Tue, 18 Oct 2022 18:45:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A5D5C42BD9; Tue, 18 Oct 2022 18:43:16 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 4793D42B8A for ; Tue, 18 Oct 2022 18:43:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111382; x=1697647382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4/T1jB/HclBLbblWNTV1Q/aw7CporqYrKIydu6ym0+8=; b=Er4dYvep7Re4cVX43M6lqmB1/dt8f7djoSKlm7aCIxR3RLgsrS017O5l UdqGsaEz3FBnR4rrslHneA8AlPaJN7EhVshTw82gSctNiXGTibIfQnCb6 cg5saJ4lZWjpRkn9l2KJTo35cnRvAX6TKtBG39+MXvPjvhEsr0Th7cvRl WHfFc0RfIto6YfTM7MUY+cjV15YMG1bb/GQA+pDDjlHcbn1amST80IoKb ZrZgrNV3p7NAtBMA5LHBkr4g78AWfVYdcw5conQp2IpVZDbJNVb3DXoW7 XUfOiVOS/K6xHj33m87jEdBlMCOtTRJU+eeY/OhQOhUN9SNEXvII0H3+p Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192144" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192144" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:43:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836175" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836175" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:43:01 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 28/30] baseband/acc100: add workaround for deRM corner cases Date: Tue, 18 Oct 2022 17:39:16 -0700 Message-Id: <20221019003918.257506-29-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add function to support de-ratematch pre-processing for SW corner cases. Some specific 5GUL FEC corner cases may cause unintended back pressure and in some cases potential stability issue on the ACC100. To be able to avoid completly such potential issue, the PMD can preempt such code block configuration so that to process the first level deRM in SW using the SDK libraries prior to running the rest of the FEC decoding in HW using an amended code block configuration. In case meson build system doesn't find such SDK libraries, the fall method is to run in HW as is with a warning. Signed-off-by: Hernan Vargas --- drivers/baseband/acc/acc_common.h | 8 ++ drivers/baseband/acc/meson.build | 21 +++++ drivers/baseband/acc/rte_acc100_pmd.c | 108 +++++++++++++++++++++++++- 3 files changed, 134 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h index eae7eab4e9..5e8972b40a 100644 --- a/drivers/baseband/acc/acc_common.h +++ b/drivers/baseband/acc/acc_common.h @@ -123,6 +123,14 @@ #define ACC_HARQ_ALIGN_64B 64 #define ACC_MAX_ZC 384 +/* De-ratematch code rate limitation when padding is required */ +#define ACC_LIM_03 2 /* 0.03 */ +#define ACC_LIM_09 6 /* 0.09 */ +#define ACC_LIM_14 9 /* 0.14 */ +#define ACC_LIM_21 14 /* 0.21 */ +#define ACC_LIM_31 20 /* 0.31 */ +#define ACC_MAX_E (128 * 1024 - 2) + /* Helper macro for logging */ #define rte_acc_log(level, fmt, ...) \ rte_log(RTE_LOG_ ## level, RTE_LOG_NOTICE, fmt "\n", \ diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build index 77c393b533..a5fc4fed01 100644 --- a/drivers/baseband/acc/meson.build +++ b/drivers/baseband/acc/meson.build @@ -1,6 +1,27 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2020 Intel Corporation +# Check for FlexRAN SDK libraries +dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false) + +if dep_dec5g.found() + ext_deps += cc.find_library('libstdc++', required: true) + ext_deps += cc.find_library('libirc', required: true) + ext_deps += cc.find_library('libimf', required: true) + ext_deps += cc.find_library('libipps', required: true) + ext_deps += cc.find_library('libsvml', required: true) + ext_deps += dep_dec5g + ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true) + ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true) + ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true) + ext_deps += dependency('flexran_sdk_turbo', required: true) + ext_deps += dependency('flexran_sdk_crc', required: true) + ext_deps += dependency('flexran_sdk_rate_matching', required: true) + ext_deps += dependency('flexran_sdk_common', required: true) + cflags += ['-DRTE_BBDEV_SDK_AVX2'] + cflags += ['-DRTE_BBDEV_SDK_AVX512'] +endif + deps += ['bbdev', 'bus_pci'] sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c') diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 87756839ef..0c2454995a 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -25,6 +25,10 @@ #include "acc101_pmd.h" #include "acc200_cfg.h" +#ifdef RTE_BBDEV_SDK_AVX512 +#include +#endif + #ifdef RTE_LIBRTE_BBDEV_DEBUG RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG); #else @@ -756,6 +760,14 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, ret = -ENOMEM; goto free_lb_out; } + q->derm_buffer = rte_zmalloc_socket(dev->device->driver->name, + RTE_BBDEV_TURBO_MAX_CB_SIZE * 10, + RTE_CACHE_LINE_SIZE, conf->socket); + if (q->derm_buffer == NULL) { + rte_bbdev_log(ERR, "Failed to allocate derm_buffer memory"); + ret = -ENOMEM; + goto free_companion_ring_addr; + } /* * Software queue ring wraps synchronously with the HW when it reaches @@ -776,7 +788,7 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q_idx = acc100_find_free_queue_idx(dev, conf); if (q_idx == -1) { ret = -EINVAL; - goto free_companion_ring_addr; + goto free_derm_buffer; } q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF; @@ -804,6 +816,9 @@ acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, dev->data->queues[queue_id].queue_private = q; return 0; +free_derm_buffer: + rte_free(q->derm_buffer); + q->derm_buffer = NULL; free_companion_ring_addr: rte_free(q->companion_ring_addr); q->companion_ring_addr = NULL; @@ -890,6 +905,7 @@ acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id) /* Mark the Queue as un-assigned */ d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFFFFFFFFFF - (uint64_t) (1 << q->aq_id)); + rte_free(q->derm_buffer); rte_free(q->companion_ring_addr); rte_free(q->lb_in); rte_free(q->lb_out); @@ -3110,10 +3126,44 @@ harq_loopback(struct acc_queue *q, struct rte_bbdev_dec_op *op, return 1; } +/** Assess whether a work around is required for the deRM corner cases */ +static inline bool +derm_workaround_required(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc_queue *q) +{ + if (!is_acc100(q)) + return false; + int32_t e = ldpc_dec->cb_params.e; + int q_m = ldpc_dec->q_m; + int z_c = ldpc_dec->z_c; + int K = (ldpc_dec->basegraph == 1 ? ACC_K_ZC_1 : ACC_K_ZC_2) + * z_c; + + bool required = false; + if (ldpc_dec->basegraph == 1) { + if ((q_m == 4) && (z_c >= 320) && (e * ACC_LIM_31 > K * 64)) + required = true; + else if ((e * ACC_LIM_21 > K * 64)) + required = true; + } else { + if (q_m <= 2) { + if ((z_c >= 208) && (e * ACC_LIM_09 > K * 64)) + required = true; + else if ((z_c < 208) && (e * ACC_LIM_03 > K * 64)) + required = true; + } else if (e * ACC_LIM_14 > K * 64) + required = true; + } + if (required) + rte_bbdev_log(INFO, "Running deRM pre-processing in SW"); + + return required; +} + /** Enqueue one decode operations for ACC100 device in CB mode */ static inline int enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, - uint16_t total_enqueued_cbs, bool same_op) + uint16_t total_enqueued_cbs, bool same_op, + struct rte_bbdev_queue_data *q_data) { int ret; if (unlikely(check_bit(op->ldpc_dec.op_flags, @@ -3167,6 +3217,58 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op, } else { struct acc_fcw_ld *fcw; uint32_t seg_total_left; + + if (derm_workaround_required(&op->ldpc_dec, q)) { + #ifdef RTE_BBDEV_SDK_AVX512 + struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec; + struct bblib_rate_dematching_5gnr_request derm_req; + struct bblib_rate_dematching_5gnr_response derm_resp; + uint8_t *in; + + /* Checking input size is matching with E */ + if (dec->input.data->data_len < dec->cb_params.e) { + rte_bbdev_log(ERR, "deRM: Input size mismatch"); + return -EFAULT; + } + /* Run first deRM processing in SW */ + in = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t *, in_offset); + derm_req.p_in = (int8_t *) in; + derm_req.p_harq = (int8_t *) q->derm_buffer; + derm_req.base_graph = dec->basegraph; + derm_req.zc = dec->z_c; + derm_req.ncb = dec->n_cb; + derm_req.e = dec->cb_params.e; + if (derm_req.e > ACC_MAX_E) { + rte_bbdev_log(WARNING, + "deRM: E %d > %d max", + derm_req.e, ACC_MAX_E); + derm_req.e = ACC_MAX_E; + } + derm_req.k0 = 0; /* Actual output from SDK */ + derm_req.isretx = false; + derm_req.rvid = dec->rv_index; + derm_req.modulation_order = dec->q_m; + derm_req.start_null_index = + (dec->basegraph == 1 ? 22 : 10) + * dec->z_c - 2 * dec->z_c + - dec->n_filler; + derm_req.num_of_null = dec->n_filler; + bblib_rate_dematching_5gnr(&derm_req, &derm_resp); + /* Force back the HW DeRM */ + dec->q_m = 1; + dec->cb_params.e = dec->n_cb - dec->n_filler; + dec->rv_index = 0; + rte_memcpy(in, q->derm_buffer, dec->cb_params.e); + /* Capture counter when pre-processing is used */ + q_data->queue_stats.enqueue_warn_count++; + #else + RTE_SET_USED(q_data); + rte_bbdev_log(WARNING, + "Corner case may require deRM pre-processing in SDK" + ); + #endif + } + fcw = &desc->req.fcw_ld; q->d->fcw_ld_fill(op, fcw, harq_layout); @@ -3720,7 +3822,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data, ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m, ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e, same_op); - ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op); + ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data); if (ret < 0) { acc_enqueue_invalid(q_data); break; From patchwork Wed Oct 19 00:39:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118464 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77D24A0560; Tue, 18 Oct 2022 18:45:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4962D42B73; Tue, 18 Oct 2022 18:43:18 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 14BFB42B8A for ; Tue, 18 Oct 2022 18:43:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111383; x=1697647383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tPBOkEwKOXMhl3og3EQSQuZyO6z/sJsxMw/bY++NRfI=; b=NWsplGOsmHjR2TUb/N+lZdlqwcEoI0nw6y7SZg3EC1EveuEBrBdBFhfb InwbZrO4ZzFnBxZtUsvLVuSxHyDD7zX7POjpClgm52F4XTHgbbTgL0uie lBPm0cIpj7mDNSZEDv+r2sEX6TfcgkvTHLo2trpFMKI7Vp+YuHC8+uQZJ cxObktOnCVmVqSMsXgS7I8/Iu0TLJGcHaFFoe1BSxQHT6ktNuc2pmU8vF WmY8cec0cbpQEP1g93uHGZmUgALW4fDPCKwrVEHsTOmC9mPOAF4omDy/T qtJw43qc87mHif08+ZWkNNRjCY9WjQDTBjy1yq9P4QM5cg/U1jnq4jb9C Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192148" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192148" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:43:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836181" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836181" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:43:01 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 29/30] baseband/acc100: configure PMON control registers Date: Tue, 18 Oct 2022 17:39:17 -0700 Message-Id: <20221019003918.257506-30-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable performance monitor control registers. Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc/acc100_pmd.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/baseband/acc/acc100_pmd.h b/drivers/baseband/acc/acc100_pmd.h index eb6349c85a..8c0aec5ed8 100644 --- a/drivers/baseband/acc/acc100_pmd.h +++ b/drivers/baseband/acc/acc100_pmd.h @@ -115,6 +115,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -144,6 +146,8 @@ static const struct acc100_registry_addr pf_reg_addr = { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure holding registry addresses for VF */ From patchwork Wed Oct 19 00:39:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hernan Vargas X-Patchwork-Id: 118465 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 31019A0560; Tue, 18 Oct 2022 18:45:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 16D7642BE6; Tue, 18 Oct 2022 18:43:19 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 860394281E for ; Tue, 18 Oct 2022 18:43:03 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666111383; x=1697647383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=y18+KviydKHpTY5WkgROwCnKqvMAg5n42IATb4aEzq4=; b=TYY98yAZUfuDbMp2a/44p7IDJhB255R+FMA9KtG8NZu8hOXKiQfnT6BW 6VSk5Vj6CzSLpNPWgNWN7EABBGzsIOXD6Cwi1OoxqD9thvzqHvO/uBBMd okm9C0qDGitMvDZ70cjV2fkTEFt+nBHNKGRur069Woxoh/PM5+TkOn0JH CR8kM/Mwvn89mjDE6AemestnWg5KNZ3lMd6h/FHb0gTyEX8n+ia+h7sZv n+yZ26P9yW/TCmpsAObfPycyNHHHLB+f+C8gPP7FiXzGhbaAux26hrqCR CiVRZVczLETgB89UqKybpBzE83wQHcEcIEJjQ9QqreV7kEqo4CTnUrPZW Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="368192153" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368192153" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 09:43:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="803836197" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="803836197" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga005.jf.intel.com with ESMTP; 18 Oct 2022 09:43:02 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 30/30] baseband/acc100: update guide docs Date: Tue, 18 Oct 2022 17:39:18 -0700 Message-Id: <20221019003918.257506-31-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221019003918.257506-1-hernan.vargas@intel.com> References: <20221019003918.257506-1-hernan.vargas@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add new flags ACC100_EXT_MEM and RTE_LIBRTE_BBDEV_SKIP_VALIDATE to the documentation. Signed-off-by: Hernan Vargas --- doc/guides/bbdevs/acc100.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst index 8b29b92a9d..b0ac2526de 100644 --- a/doc/guides/bbdevs/acc100.rst +++ b/doc/guides/bbdevs/acc100.rst @@ -65,6 +65,15 @@ ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities: - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity +* PMD Specific build flags: + The ACC100 PMD includes some optional build flags which may be used for troubleshooting. + Recommended build configuration is for these to be kept as default. + - ``ACC100_EXT_MEM`` : default option with memory external to CPU on the PCie card DDR itself. + Alternative build option will use CPU memory (not recommended). + - ``RTE_LIBRTE_BBDEV_SKIP_VALIDATE`` : option to skip API input validation. + Recommended value is to keep the validation enable by default as a protection for negative + scenarios at a cost of some cycles spent to enforce these checks. + Installation ------------