From patchwork Tue Oct 25 15:46:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 119109 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A2F5FA054A; Tue, 25 Oct 2022 17:46:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 61A2D42C1F; Tue, 25 Oct 2022 17:46:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9C0B042C1D for ; Tue, 25 Oct 2022 17:46:56 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29P94bNc029975 for ; Tue, 25 Oct 2022 08:46:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=tT/ai6qI0rDR4ovPATIKd8Ndc+CpG6j9kQNVY+izgko=; b=aGFkGn8L1MUEildB910V04YGZvUK8KUL7jZ8f6pFVxGbzTZnsd7VIAVJub3qSZXnLml2 5NDnnnq0ApuovT6bsTdJ5cr8l6qY9IRKYEGwg58Iia9nwhTPwwigmUq2AVri+VArS3qH LW4E2SEeB7epKQqJcgo4bH7vZi0VL0Fzu/o5LIp3VqY/P+n+vzIpr8mKgxsoXZls1dBJ JKZSdTZQnbfbBEDtEr5DW7HiZxGktG25yTCZAx6L1fGTFyAYHcI6a1BcuWtbvEgRuXGt BzHsMqQXgQoyVjs/rUede1zUmrDlRQE4LDhQd9oj76IT+5GrDVzmPyCXCfQvT9t9E2no Vg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kcg1musf5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 25 Oct 2022 08:46:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Oct 2022 08:46:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 25 Oct 2022 08:46:53 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.28.161.88]) by maili.marvell.com (Postfix) with ESMTP id 9CE813F7082; Tue, 25 Oct 2022 08:46:50 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Subject: [PATCH] event/cnxk: fix incorrect mbuf offset calculation Date: Tue, 25 Oct 2022 21:16:53 +0530 Message-ID: <20221025154653.10482-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xAnU6f8di4CPs2TZBpy6WpDS7eMhx0Ps X-Proofpoint-GUID: xAnU6f8di4CPs2TZBpy6WpDS7eMhx0Ps X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-25_09,2022-10-25_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Fix incorrect mbuf offset calculation when HEADROOM exceeds 128B while processing event vectors. Fixes: 7fbbc981d54f("event/cnxk: support vectorized Rx event fast path") Signed-off-by: Pavan Nikhilesh Change-Id: I1c33c8a5cce29c3ea7eb0411f4e1bedf42053167 --- drivers/net/cnxk/cn10k_rx.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 4e22ceda02..721127dddd 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -1203,9 +1203,11 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, mbuf23 = vqsubq_u64(mbuf23, data_off); } else { mbuf01 = - vsubq_u64(vld1q_u64((uint64_t *)cq0), data_off); - mbuf23 = vsubq_u64(vld1q_u64((uint64_t *)(cq0 + 16)), - data_off); + vsubq_u64(vld1q_u64((uint64_t *)cq0), + vdupq_n_u64(sizeof(struct rte_mbuf))); + mbuf23 = + vsubq_u64(vld1q_u64((uint64_t *)(cq0 + 16)), + vdupq_n_u64(sizeof(struct rte_mbuf))); } /* Move mbufs to scalar registers for future use */