From patchwork Wed Oct 26 10:23:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 119154 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CC25AA04FD; Wed, 26 Oct 2022 12:25:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2567F42B73; Wed, 26 Oct 2022 12:25:09 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id A104840041 for ; Wed, 26 Oct 2022 12:25:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666779905; x=1698315905; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HI54bn3HhaA7a4Q73qwZN7LSoxPsH1icn2wtfLsVyMs=; b=jrHhMd3rOQ0cw4siC2M81z0t9DXvIxDQysPTGZ56PRsTlyaCwvM0vvvD sEcVycnOZt4DZTcPJkR6FOvooIWGuOPykjN+eStbdHgEkkvgapS+DviEi q7eqynDxhmnqDMQIWSYVmJNBqoYhxqZ9+gQLJWept3F8BvSuxah3lDi/T /UpStqkIP7meWUmGLRDZSdi9SOEdtljQHP62RwEY6EIA+/ktgsWrYyOWA lvGchkwMKrY3H2NYXSR+L6p2CCvWGT4zY6HeY3QulOyYtRvgapvNTwpm4 BxLC3oa23XW/EMbb4jGIbRwBqmcXzqUGftAoUyI8HrtfFUAds0HPUUxNA g==; X-IronPort-AV: E=McAfee;i="6500,9779,10511"; a="306641136" X-IronPort-AV: E=Sophos;i="5.95,214,1661842800"; d="scan'208";a="306641136" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2022 03:25:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10511"; a="700875116" X-IronPort-AV: E=Sophos;i="5.95,214,1661842800"; d="scan'208";a="700875116" Received: from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104]) by fmsmga004.fm.intel.com with ESMTP; 26 Oct 2022 03:25:02 -0700 From: Junfeng Guo To: qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@xilinx.com, beilei.xing@intel.com Cc: dev@dpdk.org, xiaoyun.li@intel.com, awogbemila@google.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, stephen@networkplumber.org, chenbo.xia@intel.com, helin.zhang@intel.com, Junfeng Guo Subject: [PATCH v2] net/gve: fix meson build failure on non-Linux platforms Date: Wed, 26 Oct 2022 18:23:21 +0800 Message-Id: <20221026102321.260886-1-junfeng.guo@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221026084244.22083-1-junfeng.guo@intel.com> References: <20221026084244.22083-1-junfeng.guo@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Meson build may fail on FreeBSD with gcc and clang, due to missing the header file linux/pci_regs.h on non-Linux platform. Thus, in this patch, we removed the file include and added the used Macros derived from linux/pci_regs.h. Fixes: 3047a5ac8e66 ("net/gve: add support for device initialization") Signed-off-by: Junfeng Guo Tested-by: Daxue Gao --- drivers/net/gve/gve_ethdev.c | 1 - drivers/net/gve/gve_ethdev.h | 13 +++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c index b0f7b98daa..18c879b8d1 100644 --- a/drivers/net/gve/gve_ethdev.c +++ b/drivers/net/gve/gve_ethdev.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2022 Intel Corporation */ -#include #include "gve_ethdev.h" #include "base/gve_adminq.h" diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h index 36b334c36b..f6cac3ff2b 100644 --- a/drivers/net/gve/gve_ethdev.h +++ b/drivers/net/gve/gve_ethdev.h @@ -11,6 +11,19 @@ #include "base/gve.h" +/* + * Following macros are derived from linux/pci_regs.h, however, + * we can't simply include that header here, as there is no such + * file for non-Linux platform. + */ +#define PCI_CFG_SPACE_SIZE 256 +#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ +#define PCI_STD_HEADER_SIZEOF 64 +#define PCI_CAP_SIZEOF 4 +#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ +#define PCI_MSIX_FLAGS 2 /* Message Control */ +#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ + #define GVE_DEFAULT_RX_FREE_THRESH 512 #define GVE_DEFAULT_TX_FREE_THRESH 256 #define GVE_TX_MAX_FREE_SZ 512