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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000B8EB.mail.protection.outlook.com (10.167.241.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Thu, 10 Nov 2022 13:05:53 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Thu, 10 Nov 2022 05:05:41 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 10 Nov 2022 05:05:39 -0800 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko Subject: [PATCH] common/mlx5: fix DevX register read error severity Date: Thu, 10 Nov 2022 15:05:20 +0200 Message-ID: <20221110130520.15275-1-getelson@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EB:EE_|BL1PR12MB5128:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f26c797-c79b-44d3-0cf7-08dac31c4cc1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2022 13:05:53.9629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f26c797-c79b-44d3-0cf7-08dac31c4cc1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5128 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org PMD attempt to read HW UTC counter properties can fail because the feature has no support in port FW or mlx5 kernel module. In that case PMD still can produce correct time-stamps if it runs on core with nanosecond time resolution. Fixes: b0067860959d ("common/mlx5: update log for DevX general command failure") Cc: stable@dpdk.org Signed-off-by: Gregory Etelson Acked-by: Matan Azrad Reported-by: David Marchand Acked-by: David Marchand --- drivers/common/mlx5/mlx5_devx_cmds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 05b9429c7f..59cebb530f 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -111,7 +111,7 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, MLX5_ST_SZ_BYTES(access_register_out) + sizeof(uint32_t) * dw_cnt); if (rc || MLX5_FW_STATUS(out)) { - DEVX_DRV_LOG(ERR, out, "read access", "NIC register", reg_id); + DEVX_DRV_LOG(DEBUG, out, "read access", "NIC register", reg_id); return MLX5_DEVX_ERR_RC(rc); } memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],