From patchwork Fri Nov 25 02:51:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Ke1X" X-Patchwork-Id: 120142 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1351BA0032; Fri, 25 Nov 2022 04:05:48 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0571B40156; Fri, 25 Nov 2022 04:05:48 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id C7BD440150 for ; Fri, 25 Nov 2022 04:05:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669345547; x=1700881547; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=PFfX7zKb94fyn0r0CdBun2UdGDD8izOaI7jmGVG3DgY=; b=MOLUAulNpTE1YtZnt9ncHGymfEWgv1jytRFOOZbY5D1XY4t9CyfIsPHa znAgXUHRLrMw9khtPtzDzSy3lPRJrK8DoOAyY6u01/MxiH/HxdFMA0+R4 pn5ewBL18xuJVQabWpR26SvhGiLbvX5FgVV3U56Ul7FkIKj6uqMB6JQXQ bCGc7/50AacYNnM1STCin5wWumP+hPyzkQpiww5YfrifDtME0Mhewc0wL weOWkwh2MbYunNeisplewCRkB1PX0nzigggyRvcAfrEuaVau6Mg2TvE2a RTbjFxasQLapIWGxNgktX7zVxxamuj703Y1YJVIi8c1rTH1mDoXW3EYsW Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="315555480" X-IronPort-AV: E=Sophos;i="5.96,192,1665471600"; d="scan'208";a="315555480" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2022 19:05:45 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10541"; a="644656596" X-IronPort-AV: E=Sophos;i="5.96,192,1665471600"; d="scan'208";a="644656596" Received: from unknown (HELO localhost.localdomain) ([10.239.252.104]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Nov 2022 19:05:43 -0800 From: Ke Zhang To: qi.z.zhang@intel.com, yuying.zhang@intel.com, dev@dpdk.org Cc: "ke1x.zhang" Subject: [PATCH] net/ice: add devargs for disabling mac filter Date: Fri, 25 Nov 2022 10:51:24 +0800 Message-Id: <20221125025124.805466-1-ke1x.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: "ke1x.zhang" This patch adds support to disable mac filter which will be used by ice driver when setting dpdk_devargs config field in the TRex config file. Mac filter is not disabled in default. Signed-off-by: ke1x.zhang --- drivers/net/ice/ice_ethdev.c | 13 +++++++++++++ drivers/net/ice/ice_ethdev.h | 1 + drivers/net/ice/ice_generic_flow.c | 15 +++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 0bc739daf0..0c9f66eb88 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -28,6 +28,7 @@ /* devargs */ #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" +#define ICE_MAC_FILTER_DISABLE "mac-filter-disable" #define ICE_PROTO_XTR_ARG "proto_xtr" #define ICE_FIELD_OFFS_ARG "field_offs" #define ICE_FIELD_NAME_ARG "field_name" @@ -49,6 +50,7 @@ static const char * const ice_valid_args[] = { ICE_HW_DEBUG_MASK_ARG, ICE_ONE_PPS_OUT_ARG, ICE_RX_LOW_LATENCY_ARG, + ICE_MAC_FILTER_DISABLE, NULL }; @@ -962,8 +964,13 @@ ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr) struct ice_mac_filter *f; struct LIST_HEAD_TYPE list_head; struct ice_hw *hw = ICE_VSI_TO_HW(vsi); + struct ice_adapter *ad = (struct ice_adapter *)hw->back; int ret = 0; + if (ad->devargs.mac_filter_disable == 1) { + PMD_DRV_LOG(ERR, "This MAC filter is disabled."); + return 0; + } /* If it's added and configured, return */ f = ice_find_mac_filter(vsi, mac_addr); if (f) { @@ -2075,6 +2082,11 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) if (ret) goto bail; + ret = rte_kvargs_process(kvlist, ICE_MAC_FILTER_DISABLE, + &parse_bool, &ad->devargs.mac_filter_disable); + if (ret) + goto bail; + ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG, &parse_u64, &ad->hw.debug_mask); if (ret) @@ -6050,6 +6062,7 @@ RTE_PMD_REGISTER_PARAM_STRING(net_ice, ICE_PROTO_XTR_ARG "=[queue:]" ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>" + ICE_MAC_FILTER_DISABLE "=<0|1>" ICE_RX_LOW_LATENCY_ARG "=<0|1>"); RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE); diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index c8311be179..0350c6584a 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -563,6 +563,7 @@ struct ice_devargs { int safe_mode_support; uint8_t proto_xtr_dflt; int pipe_mode_support; + int mac_filter_disable; uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; uint8_t pin_idx; uint8_t pps_out_ena; diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c index d496c28dec..bca38f5a52 100644 --- a/drivers/net/ice/ice_generic_flow.c +++ b/drivers/net/ice/ice_generic_flow.c @@ -2464,6 +2464,8 @@ ice_flow_create(struct rte_eth_dev *dev, struct rte_flow_error *error) { struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); + struct ice_adapter *ad = + ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); struct rte_flow *flow = NULL; int ret; struct ice_flow_engine *engine = NULL; @@ -2476,6 +2478,14 @@ ice_flow_create(struct rte_eth_dev *dev, return flow; } + if (ad->devargs.mac_filter_disable == 1) { + if ((pattern[0].type == RTE_FLOW_ITEM_TYPE_ANY) + && (actions[0].type == RTE_FLOW_ACTION_TYPE_DROP)) { + flow->rule = NULL; + return flow; + } + } + rte_spinlock_lock(&pf->flow_ops_lock); ret = ice_flow_process_filter(dev, flow, attr, pattern, actions, @@ -2506,6 +2516,11 @@ ice_flow_destroy(struct rte_eth_dev *dev, ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private); int ret = 0; + if ((ad->devargs.mac_filter_disable == 1) + && (flow->rule == NULL)) { + return 0; + } + if (!flow || !flow->engine || !flow->engine->destroy) { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE,