From patchwork Thu Dec 1 04:07:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 120398 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2F5AAA00C2; Thu, 1 Dec 2022 05:07:13 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 17D0E40A7F; Thu, 1 Dec 2022 05:07:13 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 47CD740693 for ; Thu, 1 Dec 2022 05:07:11 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B127248014892 for ; Wed, 30 Nov 2022 20:07:10 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ir9uyyfHOZYPm9t9WV3pRn6nveq4lbgK0OtFJm0gcsM=; b=Pe188fNjbpT2X5mVrXnTTd7eD+lNZcgve62yTD9wZEMNcUZaDHnqGJj1iBh5pJqSu00O xahTZMpDed4j2rcCvoUr6cbq80tdHi6Z/2Ck6eXc+t5GEUhiPMt1lBvy98ma2tkWzNDQ Ky1lQWZ+8uK1ceASlga/CC1EX0I6fb3q/QaTQomyaRLYTeC8NC2/nFqhTvk6pG4C/fYb Q+DBf5MMjpjwI+CjtOqo5DVj/xLxP9ztPXpoamoXnH18nrQhtmEjwKBLjHSvP4z7N+5+ r1VfcWp8+0mGXB2xJPgLAyAHmQWsMJqyEC6qk3qmyesurvL97PzmowzABBycxarzsGH4 zQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3m6k710abj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 30 Nov 2022 20:07:10 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 30 Nov 2022 20:07:08 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 30 Nov 2022 20:07:08 -0800 Received: from satheeshpaullabpc.. (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 91D045B6926; Wed, 30 Nov 2022 20:07:06 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Subject: [dpdk-dev] [PATCH] common/cnxk: mask LA ltype for second pass for cnxk Date: Thu, 1 Dec 2022 09:37:03 +0530 Message-ID: <20221201040703.2977551-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mP4EwUn_IBhBauA6m3ckQUbvG0rrW6EI X-Proofpoint-GUID: mP4EwUn_IBhBauA6m3ckQUbvG0rrW6EI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-01_02,2022-11-30_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kiran Kumar K While installing flow rule, if user provide item type as RTE_FLOW_ITEM_TYPE_ETH, it should be applied to both first and second pass. Adding changes to mask the ltype to match both. Signed-off-by: Kiran Kumar K Reviewed-by: Satheesh Paul --- drivers/common/cnxk/roc_npc_mcam.c | 29 +++++++++++++++++++++++------ drivers/common/cnxk/roc_npc_parse.c | 1 + drivers/common/cnxk/roc_npc_priv.h | 1 + 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index a725cabc57..526a6d1579 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -551,6 +551,8 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, struct idev_cfg *idev; uint16_t pf_func = 0; uint16_t ctr = ~(0); + uint32_t la_offset; + uint64_t mask; int rc, idx; int entry; @@ -617,17 +619,32 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow, flow->npc_action &= ~(GENMASK(19, 4)); flow->npc_action |= (uint64_t)pf_func << 4; - npc_mcam_set_channel(flow, req, inl_dev->channel, - inl_dev->chan_mask, false); + npc_mcam_set_channel(flow, req, inl_dev->channel, inl_dev->chan_mask, + false); } else if (npc->is_sdp_link) { - npc_mcam_set_channel(flow, req, npc->sdp_channel, - npc->sdp_channel_mask, + npc_mcam_set_channel(flow, req, npc->sdp_channel, npc->sdp_channel_mask, pst->is_second_pass_rule); } else { - npc_mcam_set_channel(flow, req, npc->channel, - (BIT_ULL(12) - 1), + npc_mcam_set_channel(flow, req, npc->channel, (BIT_ULL(12) - 1), pst->is_second_pass_rule); } + /* Always match both 1st pass and 2nd pass ltypes for all rules */ + if (!pst->is_second_pass_rule && pst->has_eth_type) { + la_offset = __builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] & + ((1ULL << 9 /* LA offset */) - 1)); + la_offset *= 4; + + mask = ~((0xfULL << la_offset)); + /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */ + req->entry_data.kw[0] &= mask; + req->entry_data.kw_mask[0] &= mask; + req->entry_data.kw[0] |= (0x2ULL << la_offset); + req->entry_data.kw_mask[0] |= (0x7ULL << la_offset); + flow->mcam_data[0] &= mask; + flow->mcam_mask[0] &= mask; + flow->mcam_data[0] |= (0x2ULL << la_offset); + flow->mcam_mask[0] |= (0x7ULL << la_offset); + } } else { uint16_t pf_func = (flow->npc_action >> 4) & 0xffff; diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c index ff00c746d6..947e1ec53d 100644 --- a/drivers/common/cnxk/roc_npc_parse.c +++ b/drivers/common/cnxk/roc_npc_parse.c @@ -193,6 +193,7 @@ npc_parse_la(struct npc_parse_state *pst) if (pst->pattern->type != ROC_NPC_ITEM_TYPE_ETH) return 0; + pst->has_eth_type = true; eth_item = pst->pattern->spec; lid = NPC_LID_LA; diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h index 1a597280d1..09a727b13e 100644 --- a/drivers/common/cnxk/roc_npc_priv.h +++ b/drivers/common/cnxk/roc_npc_priv.h @@ -196,6 +196,7 @@ struct npc_parse_state { bool set_vlan_ltype_mask; bool set_ipv6ext_ltype_mask; bool is_second_pass_rule; + bool has_eth_type; }; enum npc_kpu_parser_flag {