From patchwork Wed Dec 14 16:34:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Power, Ciara" X-Patchwork-Id: 120892 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0795BA0543; Wed, 14 Dec 2022 17:34:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E25D24021D; Wed, 14 Dec 2022 17:34:15 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 2C81F400D6 for ; Wed, 14 Dec 2022 17:34:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671035654; x=1702571654; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=87gpwV9qyDvY41hc1rpxonnzZ2K0K22m36oiYfBRIIE=; b=P5CA+kc5o67sS87pSEijza+Al1EEE+dmRB/EQWp7x36lyrD6dq8JaX3G VgwTwEt4dR//Tou2vr59X8lNHgWfXKgc9hDXwUgmwQoH516+ZnusQAlNt RcCOqN9EMqOf7e72PbdGcA1L9UKzFzAoo5y5viK1hg6EreMwIBhSr+3X1 Oo8rLYrFzWYYdglmgZJ0soTq1HERcfeSQ9jMBFXtlgz5R/GGMakjlO90H u78vMv+8ZWHDBBxGc9TmdwhtC6ytvlyc+6yZatISpNXp3sTRX5eFHT3Ym urVI2i7EEUCQLiP1NfJdJyuOMoBcO8N4zEQYDZI1qOoc23sp7/u851xTS Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10561"; a="345527344" X-IronPort-AV: E=Sophos;i="5.96,244,1665471600"; d="scan'208";a="345527344" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2022 08:34:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10561"; a="737754965" X-IronPort-AV: E=Sophos;i="5.96,244,1665471600"; d="scan'208";a="737754965" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.219]) by FMSMGA003.fm.intel.com with ESMTP; 14 Dec 2022 08:34:08 -0800 From: Ciara Power To: Kai Ji Cc: dev@dpdk.org, arkadiuszx.kusztal@intel.com, Ciara Power Subject: [PATCH] crypto/qat: enable asymmetric crypto on gen3 device Date: Wed, 14 Dec 2022 16:34:06 +0000 Message-Id: <20221214163406.76060-1-ciara.power@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit enables asymmetric crypto in generation three devices. Signed-off-by: Ciara Power Acked-by: Kai Ji --- doc/guides/cryptodevs/qat.rst | 3 ++- doc/guides/rel_notes/release_23_03.rst | 3 +++ drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 12 ++++++++---- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index d1e64475c4..80952ae2fe 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -168,6 +168,7 @@ poll mode crypto driver support for the following hardware accelerator devices: * ``Intel QuickAssist Technology C62x`` * ``Intel QuickAssist Technology C3xxx`` * ``Intel QuickAssist Technology D15xx`` +* ``Intel QuickAssist Technology C4xxx`` * ``Intel QuickAssist Technology 4xxx`` * ``Intel QuickAssist Technology 401xxx`` @@ -391,7 +392,7 @@ to see the full table) +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ - | Yes | No | No | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 | + | Yes | Yes | No | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 | +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ | Yes | Yes | No | 4 | 4xxx | linux/5.11+ | qat_4xxx | 4xxx | 4940 | 4 | 4941 | 16 | +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index b8c5b68d6c..922e414394 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -55,6 +55,9 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Intel QuickAssist Technology (QAT) crypto driver.** + + * Added Asymmetric Crypto support for GEN3. Removed Items ------------- diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 7f00f6097d..6dc485d365 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -725,8 +725,12 @@ RTE_INIT(qat_sym_crypto_gen3_init) RTE_INIT(qat_asym_crypto_gen3_init) { - qat_asym_gen_dev_ops[QAT_GEN3].cryptodev_ops = NULL; - qat_asym_gen_dev_ops[QAT_GEN3].get_capabilities = NULL; - qat_asym_gen_dev_ops[QAT_GEN3].get_feature_flags = NULL; - qat_asym_gen_dev_ops[QAT_GEN3].set_session = NULL; + qat_asym_gen_dev_ops[QAT_GEN3].cryptodev_ops = + &qat_asym_crypto_ops_gen1; + qat_asym_gen_dev_ops[QAT_GEN3].get_capabilities = + qat_asym_crypto_cap_get_gen1; + qat_asym_gen_dev_ops[QAT_GEN3].get_feature_flags = + qat_asym_crypto_feature_flags_get_gen1; + qat_asym_gen_dev_ops[QAT_GEN3].set_session = + qat_asym_crypto_set_session_gen1; }