From patchwork Wed Dec 21 13:21:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 121234 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41F6BA034C; Wed, 21 Dec 2022 14:21:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 25C8B40A7F; Wed, 21 Dec 2022 14:21:52 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8E97040A7A for ; Wed, 21 Dec 2022 14:21:50 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BLABi9Z017593; Wed, 21 Dec 2022 05:21:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=5VIDgowfYfLVv5DwGGW+pGArVUTb3hJG/ioR+OUCPWU=; b=C5cX3VGZu6TaxvgmwQQ9kQuzdm+02tnURXBitRglQPly4+iJIVxMtCQfVZ+buc7GGHqc PP2XLkD5ccmVB2qdPLiMHmK3hqySIWmGPDQu9+w3KHgQlxXlNZb9V+Rg358vOpG8Y2ha dRaulyaYcm3PV/8+abgej28012BBZkLa2Ep0bDkcPzFsMjH0mdXCyxbd3MOk0aKZVU7Z 1sEZJxoibn5X40oF8qUECF1elZF/NUIh7MZDasBxJ3fQu3D0x7jqzbJsKCprr9QHayBT hp7K3eLdlzOWWJ3vDBMWhWGUyOFyMHvswnhl0qVwx4V77ZfeE303Le39+Qa/e91NR0ou 2Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mksuxads3-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Dec 2022 05:21:49 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 21 Dec 2022 05:21:48 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 21 Dec 2022 05:21:48 -0800 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id B7D483F7070; Wed, 21 Dec 2022 05:21:45 -0800 (PST) From: Srujana Challa To: , CC: , , , , , Subject: [PATCH 1/4] common/cnxk: add CPT HW error callback register functions Date: Wed, 21 Dec 2022 18:51:39 +0530 Message-ID: <20221221132142.2732040-1-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: oHp5srH45mY3N2CW9hG1qLmv1YdYpTY6 X-Proofpoint-ORIG-GUID: oHp5srH45mY3N2CW9hG1qLmv1YdYpTY6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_07,2022-12-21_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds functions to register callback API to report CPT_MISC_INT to the driver. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_cpt.c | 31 +++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 8 +++++++- drivers/common/cnxk/version.map | 2 ++ 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index fb97ec89b2..bf0d1cff9c 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -25,6 +25,11 @@ #define CPT_LF_DEFAULT_NB_DESC 1024 #define CPT_LF_FC_MIN_THRESHOLD 32 +static struct cpt_int_cb { + roc_cpt_int_misc_cb_t cb; + void *cb_args; +} int_cb; + static void cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb) { @@ -57,6 +62,9 @@ cpt_lf_misc_irq(void *param) /* Clear interrupt */ plt_write64(intr, lf->rbase + CPT_LF_MISC_INT); + + if (int_cb.cb != NULL) + int_cb.cb(lf, int_cb.cb_args); } static int @@ -1079,3 +1087,26 @@ roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, return 0; } + +void +roc_cpt_int_misc_cb_register(roc_cpt_int_misc_cb_t cb, void *args) +{ + if (int_cb.cb != NULL) + return; + + int_cb.cb = cb; + int_cb.cb_args = args; +} + +int +roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb, void *args) +{ + if (int_cb.cb == NULL) + return 0; + if (int_cb.cb != cb || int_cb.cb_args != args) + return -EINVAL; + + int_cb.cb = NULL; + int_cb.cb_args = NULL; + return 0; +} diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index bc9cc19edd..ac8be1b475 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -131,7 +131,7 @@ struct roc_cpt { union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES]; uint8_t eng_grp[CPT_MAX_ENG_TYPES]; uint8_t cpt_revision; - + void *opaque; #define ROC_CPT_MEM_SZ (6 * 1024) uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; @@ -144,6 +144,9 @@ struct roc_cpt_rxc_time_cfg { uint16_t zombie_thres; }; +/* CPT MISC interrupt callback */ +typedef void (*roc_cpt_int_misc_cb_t)(struct roc_cpt_lf *lf, void *args); + int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg); int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt); @@ -174,4 +177,7 @@ int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, void __roc_api roc_cpt_parse_hdr_dump(const struct cpt_parse_hdr_s *cpth); int __roc_api roc_cpt_ctx_write(struct roc_cpt_lf *lf, void *sa_dptr, void *sa_cptr, uint16_t sa_len); + +void __roc_api roc_cpt_int_misc_cb_register(roc_cpt_int_misc_cb_t cb, void *args); +int __roc_api roc_cpt_int_misc_cb_unregister(roc_cpt_int_misc_cb_t cb, void *args); #endif /* _ROC_CPT_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 17f0ec6b48..d6d96dd3eb 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -78,6 +78,8 @@ INTERNAL { roc_cpt_parse_hdr_dump; roc_cpt_rxc_time_cfg; roc_cpt_ctx_write; + roc_cpt_int_misc_cb_register; + roc_cpt_int_misc_cb_unregister; roc_dpi_configure; roc_dpi_dev_fini; roc_dpi_dev_init; From patchwork Wed Dec 21 13:21:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 121235 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B5133A034C; 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Wed, 21 Dec 2022 05:21:52 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 21 Dec 2022 05:21:51 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 21 Dec 2022 05:21:51 -0800 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id 9E0ED3F7071; Wed, 21 Dec 2022 05:21:48 -0800 (PST) From: Srujana Challa To: , CC: , , , , , Subject: [PATCH 2/4] crypto/cnxk: add callback to report CPT HW error Date: Wed, 21 Dec 2022 18:51:40 +0530 Message-ID: <20221221132142.2732040-2-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221132142.2732040-1-schalla@marvell.com> References: <20221221132142.2732040-1-schalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 9XQnxm8N_9aMQUCizv1WJE6RXJFieG0F X-Proofpoint-ORIG-GUID: 9XQnxm8N_9aMQUCizv1WJE6RXJFieG0F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_07,2022-12-21_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds and register callback to report CPT MISC error interrupts to the application using rte_cryptodev_pmd_callback_process. Signed-off-by: Srujana Challa --- drivers/crypto/cnxk/cnxk_cryptodev.c | 12 ++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev.h | 1 + drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 8 ++++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.c b/drivers/crypto/cnxk/cnxk_cryptodev.c index 35635f7831..fee272d425 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include "roc_cpt.h" @@ -56,3 +57,14 @@ cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt) return 0; } + +void +cnxk_cpt_int_misc_cb(struct roc_cpt_lf *lf, __rte_unused void *args) +{ + struct roc_cpt *roc_cpt = lf->roc_cpt; + + if (roc_cpt == NULL) + return; + + rte_cryptodev_pmd_callback_process(roc_cpt->opaque, RTE_CRYPTODEV_EVENT_ERROR); +} diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index 48bd6e144c..fcb1c48b5a 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -31,5 +31,6 @@ struct cnxk_cpt_vf { uint64_t cnxk_cpt_default_ff_get(void); int cnxk_cpt_eng_grp_add(struct roc_cpt *roc_cpt); int cnxk_cpt_parse_devargs(struct rte_devargs *devargs, struct cnxk_cpt_vf *vf); +void cnxk_cpt_int_misc_cb(struct roc_cpt_lf *lf, void *args); #endif /* _CNXK_CRYPTODEV_H_ */ diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index a9c42205e6..91c7a686c2 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -91,6 +91,9 @@ cnxk_cpt_dev_config(struct rte_cryptodev *dev, return ret; } } + roc_cpt->opaque = dev; + /* Register callback to handle CPT_MISC_INT */ + roc_cpt_int_misc_cb_register(cnxk_cpt_int_misc_cb, NULL); return 0; } @@ -150,6 +153,11 @@ cnxk_cpt_dev_close(struct rte_cryptodev *dev) roc_ae_ec_grp_put(); } + ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL); + if (ret < 0) { + plt_err("Could not unregister CPT_MISC_INT cb"); + return ret; + } roc_cpt_dev_clear(&vf->cpt); return 0; From patchwork Wed Dec 21 13:21:41 2022 Content-Type: text/plain; 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Wed, 21 Dec 2022 05:21:51 -0800 (PST) From: Srujana Challa To: , CC: , , , , , Subject: [PATCH 3/4] cryptodev: introduce query API for error interrupt event Date: Wed, 21 Dec 2022 18:51:41 +0530 Message-ID: <20221221132142.2732040-3-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221132142.2732040-1-schalla@marvell.com> References: <20221221132142.2732040-1-schalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: yVmNWJcn-D6ctXP5wU_mwbBTbfmyLv1r X-Proofpoint-ORIG-GUID: yVmNWJcn-D6ctXP5wU_mwbBTbfmyLv1r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_07,2022-12-21_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org An event RTE_CRYPTODEV_EVENT_ERROR gets fired when crypto PMD receives an error interrupt. This patch adds query function for the application, to get more info about the event. Signed-off-by: Srujana Challa Acked-by: Akhil Goyal --- lib/cryptodev/cryptodev_pmd.h | 9 +++++++++ lib/cryptodev/rte_cryptodev.c | 19 +++++++++++++++++++ lib/cryptodev/rte_cryptodev.h | 19 +++++++++++++++++++ lib/cryptodev/version.map | 3 +++ 4 files changed, 50 insertions(+) diff --git a/lib/cryptodev/cryptodev_pmd.h b/lib/cryptodev/cryptodev_pmd.h index 0020102eb7..0dfad9e24f 100644 --- a/lib/cryptodev/cryptodev_pmd.h +++ b/lib/cryptodev/cryptodev_pmd.h @@ -451,6 +451,13 @@ typedef int (*cryptodev_session_event_mdata_set_t)( enum rte_crypto_op_sess_type sess_type, void *ev_mdata); +/** + * @internal Query queue pair error interrupt event. + * @see rte_cryptodev_queue_pair_event_error_query() + */ +typedef int (*cryptodev_queue_pair_event_error_query_t)(struct rte_cryptodev *dev, + uint16_t qp_id); + /** Crypto device operations function pointer table */ struct rte_cryptodev_ops { cryptodev_configure_t dev_configure; /**< Configure device. */ @@ -497,6 +504,8 @@ struct rte_cryptodev_ops { }; cryptodev_session_event_mdata_set_t session_ev_mdata_set; /**< Set a Crypto or Security session even meta data. */ + cryptodev_queue_pair_event_error_query_t queue_pair_event_error_query; + /**< Query queue error interrupt event */ }; diff --git a/lib/cryptodev/rte_cryptodev.c b/lib/cryptodev/rte_cryptodev.c index 2165a0688c..89ff66d2ba 100644 --- a/lib/cryptodev/rte_cryptodev.c +++ b/lib/cryptodev/rte_cryptodev.c @@ -1863,6 +1863,25 @@ rte_cryptodev_pmd_callback_process(struct rte_cryptodev *dev, rte_spinlock_unlock(&rte_cryptodev_cb_lock); } +int +rte_cryptodev_queue_pair_event_error_query(uint8_t dev_id, uint16_t qp_id) +{ + struct rte_cryptodev *dev; + + if (!rte_cryptodev_is_valid_dev(dev_id)) { + CDEV_LOG_ERR("Invalid dev_id=%" PRIu8, dev_id); + return -EINVAL; + } + dev = &rte_crypto_devices[dev_id]; + + if (qp_id >= dev->data->nb_queue_pairs) + return -EINVAL; + if (*dev->dev_ops->queue_pair_event_error_query == NULL) + return -ENOTSUP; + + return dev->dev_ops->queue_pair_event_error_query(dev, qp_id); +} + struct rte_mempool * rte_cryptodev_sym_session_pool_create(const char *name, uint32_t nb_elts, uint32_t elt_size, uint32_t cache_size, uint16_t user_data_size, diff --git a/lib/cryptodev/rte_cryptodev.h b/lib/cryptodev/rte_cryptodev.h index 86d792e2e7..5f11a538fb 100644 --- a/lib/cryptodev/rte_cryptodev.h +++ b/lib/cryptodev/rte_cryptodev.h @@ -871,6 +871,25 @@ rte_cryptodev_callback_unregister(uint8_t dev_id, enum rte_cryptodev_event_type event, rte_cryptodev_cb_fn cb_fn, void *cb_arg); +/** + * @warning + * @b EXPERIMENTAL: this API may change without prior notice. + * + * Query a cryptodev queue pair if there are pending RTE_CRYPTODEV_EVENT_ERROR + * events. + * + * @param dev_id The device identifier. + * @param qp_id Queue pair index to be queried. + * + * @return + * - 1 if requested queue has a pending event. + * - 0 if no pending event is found. + * - a negative value on failure + */ +__rte_experimental +int +rte_cryptodev_queue_pair_event_error_query(uint8_t dev_id, uint16_t qp_id); + struct rte_cryptodev_callback; /** Structure to keep track of registered callbacks */ diff --git a/lib/cryptodev/version.map b/lib/cryptodev/version.map index 00c99fb45c..214c91a06f 100644 --- a/lib/cryptodev/version.map +++ b/lib/cryptodev/version.map @@ -150,6 +150,9 @@ EXPERIMENTAL { __rte_cryptodev_trace_sym_session_get_user_data; __rte_cryptodev_trace_sym_session_set_user_data; __rte_cryptodev_trace_count; + + # added in 23.03 + rte_cryptodev_queue_pair_event_error_query; }; INTERNAL { From patchwork Wed Dec 21 13:21:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 121237 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8EBD7A034C; Wed, 21 Dec 2022 14:22:07 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A756A42D1A; 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Wed, 21 Dec 2022 05:21:58 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 21 Dec 2022 05:21:56 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Wed, 21 Dec 2022 05:21:56 -0800 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id 69E063F7075; Wed, 21 Dec 2022 05:21:54 -0800 (PST) From: Srujana Challa To: , CC: , , , , , Subject: [PATCH 4/4] crypto/cnxk: add error interrupt event query handler Date: Wed, 21 Dec 2022 18:51:42 +0530 Message-ID: <20221221132142.2732040-4-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221132142.2732040-1-schalla@marvell.com> References: <20221221132142.2732040-1-schalla@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: wnZiJ5djXgeKsOcLcyhClHEBc5wxCssw X-Proofpoint-ORIG-GUID: wnZiJ5djXgeKsOcLcyhClHEBc5wxCssw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-21_07,2022-12-21_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds RTE_CRYPTODEV_EVENT_ERROR query handler for cn9k/cn10k PMD. The query handler finds the next queue pair ID with pending error interrupt event if any, starting from the given queue pair index, for the device. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_cpt.c | 4 +++- drivers/common/cnxk/roc_cpt.h | 1 + drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 1 + drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 1 + drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 15 +++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 1 + 6 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index bf0d1cff9c..fd7a40d6e4 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -63,8 +63,10 @@ cpt_lf_misc_irq(void *param) /* Clear interrupt */ plt_write64(intr, lf->rbase + CPT_LF_MISC_INT); - if (int_cb.cb != NULL) + if (int_cb.cb != NULL) { + lf->error_event_pending = 1; int_cb.cb(lf, int_cb.cb_args); + } } static int diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index ac8be1b475..e9ce4cb831 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -119,6 +119,7 @@ struct roc_cpt_lf { uint64_t io_addr; uint8_t *iq_vaddr; struct roc_nix *inl_outb_nix; + uint8_t error_event_pending; } __plt_cache_aligned; struct roc_cpt { diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 7dad370047..009d26d433 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -1082,4 +1082,5 @@ struct rte_cryptodev_ops cn10k_cpt_ops = { /* Event crypto ops */ .session_ev_mdata_set = cn10k_cpt_crypto_adapter_ev_mdata_set, + .queue_pair_event_error_query = cnxk_cpt_queue_pair_event_error_query, }; diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 04c004bc7a..a86d45a40c 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -759,5 +759,6 @@ struct rte_cryptodev_ops cn9k_cpt_ops = { /* Event crypto ops */ .session_ev_mdata_set = cn9k_cpt_crypto_adapter_ev_mdata_set, + .queue_pair_event_error_query = cnxk_cpt_queue_pair_event_error_query, }; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 91c7a686c2..d8cbe5cd74 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -806,3 +806,18 @@ cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp) plt_print(""); roc_cpt_afs_print(qp->lf.roc_cpt); } + +int +cnxk_cpt_queue_pair_event_error_query(struct rte_cryptodev *dev, uint16_t qp_id) +{ + struct cnxk_cpt_vf *vf = dev->data->dev_private; + struct roc_cpt *roc_cpt = &vf->cpt; + struct roc_cpt_lf *lf; + + lf = roc_cpt->lf[qp_id]; + if (lf && lf->error_event_pending) { + lf->error_event_pending = 0; + return 1; + } + return 0; +} diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index 13c90444d6..2b25cfe1c4 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -128,6 +128,7 @@ int cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xform, struct rte_cryptodev_asym_session *sess); void cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp); +int cnxk_cpt_queue_pair_event_error_query(struct rte_cryptodev *dev, uint16_t qp_id); static __rte_always_inline void pending_queue_advance(uint64_t *index, const uint64_t mask)