From patchwork Wed Jan 18 06:00:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122237 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CCD342409; Wed, 18 Jan 2023 07:04:17 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 26F67427EE; Wed, 18 Jan 2023 07:04:14 +0100 (CET) Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by mails.dpdk.org (Postfix) with ESMTP id 7153D410EE; Wed, 18 Jan 2023 07:04:10 +0100 (CET) X-QQ-mid: bizesmtp69t1674021847trwiuu1l Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:06 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: ChPCFoAbo1rnppeSQR2aV34zcDRHYtJd+OmOJvWfMi8N12X7kISyG9hWHh7YP wiCF+pNrnDByaTNYAVYcdG8sQ9oqiie1i0oPg04xbsROeImHsAZh/pbNMW+/5CagP/9W1JT xDkzK2TmD84XV3qKYtBnD7Hbqzt0oNJ7q45wWRigfUIFw5xwAe6XP89vgcHbu3A0MO0JryO 8mNoTSSpqZvhdUAlXhlBRuit1+MXN0H25PChwNuUkCorjN7XuYnBi1J8PisgRIM2vEzBCyW UsSl1PE8CWLDJkD63HBu/huCKA+rLZRPw9MOa8L0mdiac83kX6qZ1KB7aKqKn7F8N7e9daa +s8gQZlbdE8twI5bRbAgtjihfgdsTJ4zS5Cec6cnYl/1ScJtgRXne1S5HKTXTwKQyGyCtmj X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 1/8] net/txgbe: fix Rx buffer size in configure register Date: Wed, 18 Jan 2023 14:00:32 +0800 Message-Id: <20230118060039.3074016-2-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When round up buffer size to 1K, to configure the register, hardware will receive packets exceeding the buffer size in LRO mode. It will cause a segment fault in the receive function. Fixes: be797cbf4582 ("net/txgbe: add Rx and Tx init") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_rxtx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index ac1bba08a3..ae70ca3beb 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -4382,7 +4382,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev) */ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM); - buf_size = ROUND_UP(buf_size, 0x1 << 10); + buf_size = ROUND_DOWN(buf_size, 0x1 << 10); srrctl |= TXGBE_RXCFG_PKTLEN(buf_size); wr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl); From patchwork Wed Jan 18 06:00:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122238 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44E5442409; Wed, 18 Jan 2023 07:04:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 272C842D16; Wed, 18 Jan 2023 07:04:17 +0100 (CET) Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by mails.dpdk.org (Postfix) with ESMTP id D6B3F42D16; Wed, 18 Jan 2023 07:04:14 +0100 (CET) X-QQ-mid: bizesmtp69t1674021850tl63fk71 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:09 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: Fc2LLDWeHZ8Hq5YWVDdNwz6ZNN0GkRR1n0wfqZlrbG4aa2Refq1EGjyhmAIKk AAdr/L8Eufs2VqdO71tkErntGBaG2ZSkbAdMaKdk4YpqpgBm/OnZb2oGJa617CxdAkID8Vq 2lBeJ6StcS9kdbLST2+NA4g8f+3NGgQuOgS5EL4ddj0pWlWnmaIUgPSoiG1lODFNRsP3b+L m+4RT8UdG5Qs2niWKG28EE9Q9vUrcJbztZjpss0hwfW1e9TwxQ3OdZtxVC5NhLPf0jxxVBE ZQnjD5aaXpijNd5aL3x32s672rTQ+smY3IY7sfh9xf5WzxcYHSluzbUkRX/yKnhIE1ZJIDK XntPE2/ZfZxNrod7oegE7CRfM9gmF0D5ZpbubYCD3gMqEUIv0viNCx1CfNG+lwkjCQK8ICr X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 2/8] net/txgbe: fix default signal quality value for KX/KX4 Date: Wed, 18 Jan 2023 14:00:33 +0800 Message-Id: <20230118060039.3074016-3-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On old firmware versions, the default value of signal quality(TX_EQ) is configured by the driver. Fix it for KX/KX4 mode. Fixes: 01c3cf5c85a7 ("net/txgbe: add autoneg control read and write") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_phy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 9f46d5bdb0..87935abdaa 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -1693,9 +1693,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg) wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { value = (0x1804 & ~0x3F3F); + value |= 40 << 8; wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); - value = (0x50 & ~0x7F) | 40 | (1 << 6); + value = (0x50 & ~0x7F) | (1 << 6); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } out: @@ -1907,10 +1908,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw, value |= hw->phy.ffe_post | (1 << 6); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) { - value = (0x1804 & ~0x3F3F) | (24 << 8) | 4; + value = (0x1804 & ~0x3F3F) | (40 << 8); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value); - value = (0x50 & ~0x7F) | 16 | (1 << 6); + value = (0x50 & ~0x7F) | (1 << 6); wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value); } out: From patchwork Wed Jan 18 06:00:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122239 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4A7E142409; Wed, 18 Jan 2023 07:04:32 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9310A42D4E; Wed, 18 Jan 2023 07:04:18 +0100 (CET) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id 0093242D35; Wed, 18 Jan 2023 07:04:15 +0100 (CET) X-QQ-mid: bizesmtp69t1674021852t6wg7v1l Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:11 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: 0laiA9+vjABOz2ECRTmjyjlbW838IdP1OOks+Z/GkQ8pfuDVF9O80UccJgXC4 hc5IqFJcbyGB+LEJvZv1KfjF7xeXU2lGlAO9DTnbyMoEe97EX8UvfiIFbFJhQdTIVFRhvsQ EhhJUMp1HKE/BLGCoXRUbL4SRBFweqaX1MXUq0uYga3NA0+/RtheDxGytqTA6/pXA/xB4xh 3hs6zB/OazelUnck9WpQdBjYgm4tUegc+R2NlrLgM5lZpsRxImOMQw7+F/VbxuY0pujBOu4 MAXD78yAGGEzbyBfZhUWtQH2o9I2KJPwlObsoX86ISumQOtarrbFIWLpT7Zrppex7EXRr53 98AlUTcVoZhtaz3W4rreXrlMWokL0Cf2q1yizUz6LwDhtzgP8sybBsj57DYTUIcAcv4FCg8 X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 3/8] net/txgbe: fix packet type to parse from offload flags Date: Wed, 18 Jan 2023 14:00:34 +0800 Message-Id: <20230118060039.3074016-4-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In some external applications, developers may fill in wrong packet_type in rte_mbuf for transmission. It will result in Tx ring hang when Tx checksum offload is on. So change it to parse from ol_flags. Fixes: ca46fcd753b1 ("net/txgbe: support Tx with hardware offload") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_rxtx.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c index ae70ca3beb..e91aaf60ef 100644 --- a/drivers/net/txgbe/txgbe_rxtx.c +++ b/drivers/net/txgbe/txgbe_rxtx.c @@ -516,20 +516,21 @@ tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags) return cmdtype; } -static inline uint8_t -tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) +static inline uint32_t +tx_desc_ol_flags_to_ptype(uint64_t oflags) { + uint32_t ptype; bool tun; - if (ptype) - return txgbe_encode_ptype(ptype); - /* Only support flags in TXGBE_TX_OFFLOAD_MASK */ tun = !!(oflags & RTE_MBUF_F_TX_TUNNEL_MASK); /* L2 level */ ptype = RTE_PTYPE_L2_ETHER; if (oflags & RTE_MBUF_F_TX_VLAN) + ptype |= (tun ? RTE_PTYPE_INNER_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER_VLAN); + + if (oflags & RTE_MBUF_F_TX_QINQ) //tun + qinq is not supported ptype |= RTE_PTYPE_L2_ETHER_VLAN; /* L3 level */ @@ -587,6 +588,14 @@ tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) break; } + return ptype; +} + +static inline uint8_t +tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) +{ + ptype = tx_desc_ol_flags_to_ptype(oflags); + return txgbe_encode_ptype(ptype); } From patchwork Wed Jan 18 06:00:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122240 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13A7F42409; Wed, 18 Jan 2023 07:04:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C19C742D47; Wed, 18 Jan 2023 07:04:21 +0100 (CET) Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by mails.dpdk.org (Postfix) with ESMTP id 119C242D3D; Wed, 18 Jan 2023 07:04:17 +0100 (CET) X-QQ-mid: bizesmtp69t1674021855tod274mi Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:14 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: eeGIu46hDGhIV7yDxmj+W/7zZ4Tz9Rv7h51IMJvSLUgdlpTtQEGgPZW2+acIG pIaP615ekUE39y+eAERq4sPMxa6c8fluCPvND/HnLcFonyzIFHyZFmWKdte8zpMxSgvneEB sMth1i/NvSmS+mX0i7YXcn+IkO3RQ5JjHfhp2NpeiZLNexVwwBwkOS35b0i+7Vytx3DrvLL WAUwCSy/OZimhPHxN+Ax7Bp6Z4l5FscXp2mJ/LbqxtwpBMoSXaqnhmudYBUC/TYABJ3OvAX /b0CG+/WGlDdH2LNOpzE9eSFijVPvT0Vaei0oTURi21IVl9inzWjKSA6n97EnpmD+4I7BW6 ZvaiFlnoziRgDYo2fI94zoJEFh35jje0QCX8fDOj+Gd64xeoinR0m+S25qnz9lh3UOTjJFU BOw1rv1qIjk= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 4/8] net/ngbe: fix packet type to parse from offload flags Date: Wed, 18 Jan 2023 14:00:35 +0800 Message-Id: <20230118060039.3074016-5-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In some external applications, developers may fill in wrong packet_type in rte_mbuf for transmission. It will result in Tx ring hang when Tx checksum offload is on. So change it to parse from ol_flags. And remove redundant tunnel type since the NIC does not support it. Fixes: 9f3206140274 ("net/ngbe: support TSO") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/ngbe_rxtx.c | 87 +++++++++--------------------------- 1 file changed, 20 insertions(+), 67 deletions(-) diff --git a/drivers/net/ngbe/ngbe_rxtx.c b/drivers/net/ngbe/ngbe_rxtx.c index 9fd24fa444..09312cf40d 100644 --- a/drivers/net/ngbe/ngbe_rxtx.c +++ b/drivers/net/ngbe/ngbe_rxtx.c @@ -24,15 +24,11 @@ /* Bit Mask to indicate what bits required for building Tx context */ static const u64 NGBE_TX_OFFLOAD_MASK = (RTE_MBUF_F_TX_IP_CKSUM | - RTE_MBUF_F_TX_OUTER_IPV6 | - RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_IPV6 | RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_L4_MASK | RTE_MBUF_F_TX_TCP_SEG | - RTE_MBUF_F_TX_TUNNEL_MASK | - RTE_MBUF_F_TX_OUTER_IP_CKSUM | NGBE_TX_IEEE1588_TMST); #define NGBE_TX_OFFLOAD_NOTSUP_MASK \ @@ -333,34 +329,15 @@ ngbe_set_xmit_ctx(struct ngbe_tx_queue *txq, } vlan_macip_lens = NGBE_TXD_IPLEN(tx_offload.l3_len >> 1); - - if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) { - tx_offload_mask.outer_tun_len |= ~0; - tx_offload_mask.outer_l2_len |= ~0; - tx_offload_mask.outer_l3_len |= ~0; - tx_offload_mask.l2_len |= ~0; - tunnel_seed = NGBE_TXD_ETUNLEN(tx_offload.outer_tun_len >> 1); - tunnel_seed |= NGBE_TXD_EIPLEN(tx_offload.outer_l3_len >> 2); - - switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) { - case RTE_MBUF_F_TX_TUNNEL_IPIP: - /* for non UDP / GRE tunneling, set to 0b */ - break; - default: - PMD_TX_LOG(ERR, "Tunnel type not supported"); - return; - } - vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.outer_l2_len); - } else { - tunnel_seed = 0; - vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.l2_len); - } + vlan_macip_lens |= NGBE_TXD_MACLEN(tx_offload.l2_len); if (ol_flags & RTE_MBUF_F_TX_VLAN) { tx_offload_mask.vlan_tci |= ~0; vlan_macip_lens |= NGBE_TXD_VLAN(tx_offload.vlan_tci); } + tunnel_seed = 0; + txq->ctx_cache[ctx_idx].flags = ol_flags; txq->ctx_cache[ctx_idx].tx_offload.data[0] = tx_offload_mask.data[0] & tx_offload.data[0]; @@ -449,16 +426,10 @@ tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags) return cmdtype; } -static inline uint8_t -tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) +static inline uint32_t +tx_desc_ol_flags_to_ptype(uint64_t oflags) { - bool tun; - - if (ptype) - return ngbe_encode_ptype(ptype); - - /* Only support flags in NGBE_TX_OFFLOAD_MASK */ - tun = !!(oflags & RTE_MBUF_F_TX_TUNNEL_MASK); + uint32_t ptype; /* L2 level */ ptype = RTE_PTYPE_L2_ETHER; @@ -466,41 +437,34 @@ tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) ptype |= RTE_PTYPE_L2_ETHER_VLAN; /* L3 level */ - if (oflags & (RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IP_CKSUM)) - ptype |= RTE_PTYPE_L3_IPV4; - else if (oflags & (RTE_MBUF_F_TX_OUTER_IPV6)) - ptype |= RTE_PTYPE_L3_IPV6; - if (oflags & (RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM)) - ptype |= (tun ? RTE_PTYPE_INNER_L3_IPV4 : RTE_PTYPE_L3_IPV4); + ptype |= RTE_PTYPE_L3_IPV4; else if (oflags & (RTE_MBUF_F_TX_IPV6)) - ptype |= (tun ? RTE_PTYPE_INNER_L3_IPV6 : RTE_PTYPE_L3_IPV6); + ptype |= RTE_PTYPE_L3_IPV6; /* L4 level */ switch (oflags & (RTE_MBUF_F_TX_L4_MASK)) { case RTE_MBUF_F_TX_TCP_CKSUM: - ptype |= (tun ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP); + ptype |= RTE_PTYPE_L4_TCP; break; case RTE_MBUF_F_TX_UDP_CKSUM: - ptype |= (tun ? RTE_PTYPE_INNER_L4_UDP : RTE_PTYPE_L4_UDP); + ptype |= RTE_PTYPE_L4_UDP; break; case RTE_MBUF_F_TX_SCTP_CKSUM: - ptype |= (tun ? RTE_PTYPE_INNER_L4_SCTP : RTE_PTYPE_L4_SCTP); + ptype |= RTE_PTYPE_L4_SCTP; break; } if (oflags & RTE_MBUF_F_TX_TCP_SEG) - ptype |= (tun ? RTE_PTYPE_INNER_L4_TCP : RTE_PTYPE_L4_TCP); - - /* Tunnel */ - switch (oflags & RTE_MBUF_F_TX_TUNNEL_MASK) { - case RTE_MBUF_F_TX_TUNNEL_IPIP: - case RTE_MBUF_F_TX_TUNNEL_IP: - ptype |= RTE_PTYPE_L2_ETHER | - RTE_PTYPE_L3_IPV4 | - RTE_PTYPE_TUNNEL_IP; - break; - } + ptype |= RTE_PTYPE_L4_TCP; + + return ptype; +} + +static inline uint8_t +tx_desc_ol_flags_to_ptid(uint64_t oflags, uint32_t ptype) +{ + ptype = tx_desc_ol_flags_to_ptype(oflags); return ngbe_encode_ptype(ptype); } @@ -629,9 +593,6 @@ ngbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, tx_offload.l4_len = tx_pkt->l4_len; tx_offload.vlan_tci = tx_pkt->vlan_tci; tx_offload.tso_segsz = tx_pkt->tso_segsz; - tx_offload.outer_l2_len = tx_pkt->outer_l2_len; - tx_offload.outer_l3_len = tx_pkt->outer_l3_len; - tx_offload.outer_tun_len = 0; /* If new context need be built or reuse the exist ctx*/ ctx = what_ctx_update(txq, tx_ol_req, tx_offload); @@ -752,10 +713,6 @@ ngbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, */ pkt_len -= (tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len); - pkt_len -= - (tx_pkt->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) - ? tx_offload.outer_l2_len + - tx_offload.outer_l3_len : 0; } /* @@ -1939,12 +1896,8 @@ ngbe_get_tx_port_offloads(struct rte_eth_dev *dev) RTE_ETH_TX_OFFLOAD_UDP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | - RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_UDP_TSO | - RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO | - RTE_ETH_TX_OFFLOAD_IP_TNL_TSO | - RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS; if (hw->is_pf) From patchwork Wed Jan 18 06:00:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122241 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0AEE42409; Wed, 18 Jan 2023 07:04:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3D7642D54; Wed, 18 Jan 2023 07:04:23 +0100 (CET) Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by mails.dpdk.org (Postfix) with ESMTP id EA76742D59; Wed, 18 Jan 2023 07:04:20 +0100 (CET) X-QQ-mid: bizesmtp69t1674021857tdpi4o0m Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:16 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: FVl8EHhfVR7uhbB1A9ra2Qpk4/PxebGUOEhy4y3z18OFkrpES4q+J1UumQihH 0/ev6kf+9O0A2LAkMXcUf6SJGoN4KhcNOUTNEEGnbWRr6d/XY8OJODHTWAqsDX4x6n8bjuI W5c30UDg5jfbLLxa0f0MQPsFAPSRN7LdSjpSI44D+saW9QVKGTH3WEW1o9x1ff94FCwwpLH mLnWvTWLWG23yJn03hlEO5y8cKSpc5m/JIXHDq4pqiciL/RX2yV9VUBcmASy19TRmv1aVjy BwYNKo8t/C2dBSwAcspC9B6W5DFxIXXHzBWc4Wj51OvAIyRW7zjToHFlYM3KdMv9Ff1rg4i I+ib8q4PITWPGQaP5myhHcz2TXq77UBH/wjP050F/3Un4wvgCj9XmtImG2kGy8BwE+WwXGG X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH 5/8] net/ngbe: add spinlock protection on YT PHY Date: Wed, 18 Jan 2023 14:00:36 +0800 Message-Id: <20230118060039.3074016-6-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For yt8521s/yt8531s PHY, if other registers are accessing between reads/writes of ext field registers, the value of ext filed registers will get weird for unknown reasons. So it's protected when all of ext field registers accessing. Fixes: 44e97550ca68 ("net/ngbe: identify and reset PHY") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_phy_yt.c | 36 +++++++++++++++++++++++++++++ drivers/net/ngbe/base/ngbe_type.h | 1 + 2 files changed, 37 insertions(+) diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index c88946f7c3..726d6c8ef5 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -100,11 +100,15 @@ s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw, s32 ngbe_init_phy_yt(struct ngbe_hw *hw) { + rte_spinlock_init(&hw->phy_lock); + + rte_spinlock_lock(&hw->phy_lock); /* close sds area register */ ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); /* enable interrupts */ ngbe_write_phy_reg_mdi(hw, YT_INTR, 0, YT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK); + rte_spinlock_unlock(&hw->phy_lock); hw->phy.set_phy_power(hw, false); @@ -123,7 +127,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, hw->phy.autoneg_advertised = 0; /* check chip_mode first */ + rte_spinlock_lock(&hw->phy_lock); ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(0)) { /* UTP to rgmii */ if (!hw->mac.autoneg) { @@ -146,11 +152,14 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); goto skip_an; } + rte_spinlock_lock(&hw->phy_lock); /*disable 100/10base-T Self-negotiation ability*/ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | @@ -189,6 +198,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); skip_an: hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) { @@ -199,6 +209,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value = YT_RGMII_CONF1_RXDELAY | YT_RGMII_CONF1_TXDELAY_FE | YT_RGMII_CONF1_TXDELAY; + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value); value = YT_CHIP_MODE_SEL(1) | YT_CHIP_SW_LDO_EN | @@ -225,17 +236,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, value = YT_BCR_RESET | YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1; hw->phy.write_reg(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) { hw->phy.set_phy_power(hw, true); + rte_spinlock_lock(&hw->phy_lock); hw->phy.read_reg(hw, YT_SPST, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); if (value & YT_SPST_LINK) { /* fiber up */ hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; } else { /* utp up */ + rte_spinlock_lock(&hw->phy_lock); /*disable 100/10base-T Self-negotiation ability*/ ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | @@ -279,10 +294,12 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET; ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); } } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; + rte_spinlock_lock(&hw->phy_lock); ngbe_read_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, &value); value |= YT_RGMII_CONF1_MODE; ngbe_write_phy_reg_ext_yt(hw, YT_RGMII_CONF1, 0, value); @@ -297,6 +314,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value); value &= ~YT_SMI_PHY_SW_RST; ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value); + rte_spinlock_unlock(&hw->phy_lock); hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(5)) { @@ -320,7 +338,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; + rte_spinlock_lock(&hw->phy_lock); hw->phy.write_reg(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); goto skip_an_sr; } @@ -339,19 +359,23 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; + rte_spinlock_lock(&hw->phy_lock); hw->phy.write_reg(hw, YT_BCR, 0, value); /* software reset to make the above configuration take effect */ hw->phy.read_reg(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; hw->phy.write_reg(hw, 0x0, 0, value); + rte_spinlock_unlock(&hw->phy_lock); skip_an_sr: hw->phy.set_phy_power(hw, true); } + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); return 0; } @@ -366,6 +390,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw) hw->phy.type != ngbe_phy_yt8521s_sfi) return NGBE_ERR_PHY_TYPE; + rte_spinlock_lock(&hw->phy_lock); /* check chip_mode first */ ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &ctrl); if (ctrl & YT_CHIP_MODE_MASK) { @@ -395,6 +420,7 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw) msleep(1); } } + rte_spinlock_unlock(&hw->phy_lock); if (i == YT_PHY_RST_WAIT_PERIOD) { DEBUGOUT("PHY reset polling failed to complete."); @@ -409,7 +435,9 @@ s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit) u16 value; s32 status = 0; + rte_spinlock_lock(&hw->phy_lock); status = hw->phy.read_reg(hw, YT_ANA, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); value &= YT_FANA_PAUSE_MASK; *pause_bit = (u8)(value >> 7); @@ -421,7 +449,9 @@ s32 ngbe_get_phy_lp_advertised_pause_yt(struct ngbe_hw *hw, u8 *pause_bit) u16 value; s32 status = 0; + rte_spinlock_lock(&hw->phy_lock); status = hw->phy.read_reg(hw, YT_LPAR, 0, &value); + rte_spinlock_unlock(&hw->phy_lock); value &= YT_FLPAR_PAUSE_MASK; *pause_bit = (u8)(value >> 7); @@ -433,10 +463,12 @@ s32 ngbe_set_phy_pause_adv_yt(struct ngbe_hw *hw, u16 pause_bit) u16 value; s32 status = 0; + rte_spinlock_lock(&hw->phy_lock); status = hw->phy.read_reg(hw, YT_ANA, 0, &value); value &= ~YT_FANA_PAUSE_MASK; value |= pause_bit; status = hw->phy.write_reg(hw, YT_ANA, 0, value); + rte_spinlock_unlock(&hw->phy_lock); return status; } @@ -453,6 +485,7 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw, /* Initialize speed and link to default case */ *link_up = false; *speed = NGBE_LINK_SPEED_UNKNOWN; + rte_spinlock_lock(&hw->phy_lock); ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0); ngbe_read_phy_reg_mdi(hw, YT_INTR_STATUS, 0, &insr); @@ -472,6 +505,7 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw, *link_up = true; } + rte_spinlock_unlock(&hw->phy_lock); if (*link_up) { if (phy_speed == YT_SPST_SPEED_1000M) *speed = NGBE_LINK_SPEED_1GB_FULL; @@ -488,6 +522,7 @@ s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on) { u16 value = 0; + rte_spinlock_lock(&hw->phy_lock); /* power down/up in fiber mode */ hw->phy.read_reg(hw, YT_BCR, 0, &value); if (on) @@ -504,6 +539,7 @@ s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on) else value |= YT_BCR_PWDN; ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); + rte_spinlock_unlock(&hw->phy_lock); return 0; } diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h index aa5c41146c..05804eeab7 100644 --- a/drivers/net/ngbe/base/ngbe_type.h +++ b/drivers/net/ngbe/base/ngbe_type.h @@ -433,6 +433,7 @@ struct ngbe_hw { bool gpio_ctl; u32 led_conf; bool init_phy; + rte_spinlock_t phy_lock; struct { u64 rx_qp_packets; u64 tx_qp_packets; From patchwork Wed Jan 18 06:00:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122242 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9B06C42409; Wed, 18 Jan 2023 07:04:52 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 011F142D61; Wed, 18 Jan 2023 07:04:26 +0100 (CET) Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by mails.dpdk.org (Postfix) with ESMTP id A86CE410EE for ; Wed, 18 Jan 2023 07:04:23 +0100 (CET) X-QQ-mid: bizesmtp69t1674021860tuy4n9ip Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:19 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: LE7C6P2vL8TajNKXovkCZOvmcKTJY7kR5zlPxlsNR2CKtQoQqMPbzQigqUrNj LOpzLg1Is9OyJT9hPJ/7OhV1NhfVTPaS4Qbmk7DlQWB8t8ZQ9lb99fV9srsOUDUJzVkVc/j EDBROiHFaQX7dD0v1570vGEgEQ0hvLa0adNnGAMtHXofZrlSU7pScDJO6e5Skr5K4RdHT2M 0PhfksCWidnglIx+E0DqhhJGTJePDPJwoZA5P/BdvsK5LKv5K1kDmr4OYjEPbjazgqDG7Mo 8JoYPmEZMEMLqMwDKtTWTn2AQZiowByE/8NoSDQDBxdC4xxR29fzRpIowQ+lF2e4ejSQE2W uqqhz4j10FmI+nVwxQC274HQ9nmJyq104OeAR56by/M811mfzldY6yN/roOCEphsOJI+72N X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 6/8] net/ngbe: add chip overheat support Date: Wed, 18 Jan 2023 14:00:37 +0800 Message-Id: <20230118060039.3074016-7-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to handle overheat interrupt. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_23_03.rst | 4 ++++ drivers/net/ngbe/ngbe_ethdev.c | 32 +++++++++++++++++++++++++- drivers/net/ngbe/ngbe_ethdev.h | 1 + 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index b8c5b68d6c..9c61bdbdcb 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -55,6 +55,10 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated Wangxun ngbe driver.** + + * Added chip overheat detection support. + Removed Items ------------- diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c index afdb3ad41f..c32d954769 100644 --- a/drivers/net/ngbe/ngbe_ethdev.c +++ b/drivers/net/ngbe/ngbe_ethdev.c @@ -947,7 +947,7 @@ ngbe_dev_phy_intr_setup(struct rte_eth_dev *dev) else wr32(hw, NGBE_GPIOINTPOL, NGBE_GPIOINTPOL_ACT(3)); - intr->mask_misc |= NGBE_ICRMISC_GPIO; + intr->mask_misc |= NGBE_ICRMISC_GPIO | NGBE_ICRMISC_HEAT; } /* @@ -1869,6 +1869,28 @@ ngbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +ngbe_dev_overheat(struct rte_eth_dev *dev) +{ + struct ngbe_hw *hw = ngbe_dev_hw(dev); + s32 temp_state; + + temp_state = hw->mac.check_overtemp(hw); + if (!temp_state) + return; + + if (temp_state == NGBE_ERR_UNDERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been started again, " + "since the temperature has been back to normal state."); + wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, NGBE_PBRXCTL_ENA); + ngbe_dev_set_link_up(dev); + } else if (temp_state == NGBE_ERR_OVERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been stopped because it has over heated."); + wr32m(hw, NGBE_PBRXCTL, NGBE_PBRXCTL_ENA, 0); + ngbe_dev_set_link_down(dev); + } +} + void ngbe_dev_setup_link_alarm_handler(void *param) { @@ -2167,6 +2189,9 @@ ngbe_dev_interrupt_get_status(struct rte_eth_dev *dev) if (eicr & NGBE_ICRMISC_GPIO) intr->flags |= NGBE_FLAG_NEED_LINK_UPDATE; + if (eicr & NGBE_ICRMISC_HEAT) + intr->flags |= NGBE_FLAG_OVERHEAT; + ((u32 *)hw->isb_mem)[NGBE_ISB_MISC] = 0; return 0; @@ -2243,6 +2268,11 @@ ngbe_dev_interrupt_action(struct rte_eth_dev *dev) RTE_ETH_EVENT_INTR_LSC, NULL); } + if (intr->flags & NGBE_FLAG_OVERHEAT) { + ngbe_dev_overheat(dev); + intr->flags &= ~NGBE_FLAG_OVERHEAT; + } + PMD_DRV_LOG(DEBUG, "enable intr immediately"); ngbe_enable_intr(dev); diff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h index 8d500fd38c..330f476f6f 100644 --- a/drivers/net/ngbe/ngbe_ethdev.h +++ b/drivers/net/ngbe/ngbe_ethdev.h @@ -17,6 +17,7 @@ #define NGBE_FLAG_PHY_INTERRUPT ((uint32_t)(1 << 2)) #define NGBE_FLAG_MACSEC ((uint32_t)(1 << 3)) #define NGBE_FLAG_NEED_LINK_CONFIG ((uint32_t)(1 << 4)) +#define NGBE_FLAG_OVERHEAT ((uint32_t)(1 << 5)) #define NGBE_VFTA_SIZE 128 #define NGBE_HKEY_MAX_INDEX 10 From patchwork Wed Jan 18 06:00:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122243 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4D92642409; Wed, 18 Jan 2023 07:05:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B344442D72; Wed, 18 Jan 2023 07:04:27 +0100 (CET) Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by mails.dpdk.org (Postfix) with ESMTP id 377F742D5D for ; Wed, 18 Jan 2023 07:04:25 +0100 (CET) X-QQ-mid: bizesmtp69t1674021862tjxdprzp Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:21 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: zT6n3Y95oi1+rq8Ek0pbP/r74sQBcI+XAL+XtzhAc2/SmyuiAGMjazL+gW8zM 2r4Qe+xl7mhyBQBT8nkxz2q+MsoiuYV0lIwE072AbeaTP7XcCMlPuR6YGWE06hb9A9a6rsw VVHkZF2mmSEumYcOhdZeDuCIA3Jw5gIi05YCpSFz9bj6jgVqfFMm5ch/Pa76J6nGdZnSsTQ sutIfJ/u0Rn3b+IqhlOvH7xJ2tjYLFOeLGwJvhW019yINd6/VMzHGutM/JrmKYcDg9EI/9z wMZukDNUWSwMWe6pnhJtWKqjvib4fbPmgzhYhXBLSazwmWod6+pONWILjf0GPJPo0cP0fbU o2Mp40iQCa/k7noqlQ4yNGqSMZKdR9ovbGmGYlwPFPZ8t/Z5EOtvwwjsYQEPq63h07E0Lyo X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 7/8] net/txgbe: add chip overheat support Date: Wed, 18 Jan 2023 14:00:38 +0800 Message-Id: <20230118060039.3074016-8-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to handle overheat interrupt. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_23_03.rst | 4 ++++ drivers/net/txgbe/base/txgbe_hw.c | 1 + drivers/net/txgbe/base/txgbe_phy.c | 22 ++++++++++++++++++ drivers/net/txgbe/base/txgbe_phy.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 31 ++++++++++++++++++++++++++ drivers/net/txgbe/txgbe_ethdev.h | 1 + 6 files changed, 60 insertions(+) diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index 9c61bdbdcb..e64cb2d974 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -59,6 +59,10 @@ New Features * Added chip overheat detection support. +* **Updated Wangxun txgbe driver.** + + * Added chip overheat detection support. + Removed Items ------------- diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 8966453a03..e7c9754d26 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2684,6 +2684,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw) phy->identify_sfp = txgbe_identify_module; phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked; phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked; + phy->check_overtemp = txgbe_check_overtemp; phy->reset = txgbe_reset_phy; /* MAC */ diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c index 87935abdaa..f4cadcc510 100644 --- a/drivers/net/txgbe/base/txgbe_phy.c +++ b/drivers/net/txgbe/base/txgbe_phy.c @@ -1363,6 +1363,28 @@ static void txgbe_i2c_stop(struct txgbe_hw *hw) wr32(hw, TXGBE_I2CENA, 0); } +/** + * txgbe_check_overtemp - Checks if an overtemp occurred. + * @hw: pointer to hardware structure + * + * Checks if the temp alarm status was triggered due to overtemp + **/ +s32 txgbe_check_overtemp(struct txgbe_hw *hw) +{ + s32 status = 0; + u32 ts_state; + + /* Check that the temp alarm status was triggered */ + ts_state = rd32(hw, TXGBE_TS_ALARM_ST); + + if (ts_state & TXGBE_TS_ALARM_ST_DALARM) + status = TXGBE_ERR_UNDERTEMP; + else if (ts_state & TXGBE_TS_ALARM_ST_ALARM) + status = TXGBE_ERR_OVERTEMP; + + return status; +} + static void txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw) { diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h index 5093d83b97..4dfe18930c 100644 --- a/drivers/net/txgbe/base/txgbe_phy.h +++ b/drivers/net/txgbe/base/txgbe_phy.h @@ -447,6 +447,7 @@ s32 txgbe_identify_module(struct txgbe_hw *hw); s32 txgbe_identify_sfp_module(struct txgbe_hw *hw); s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw); +s32 txgbe_check_overtemp(struct txgbe_hw *hw); s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset, u8 dev_addr, u8 *data); s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset, diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 86ef979b29..ce7cf2506d 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -1542,6 +1542,7 @@ txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) wr32(hw, TXGBE_GPIOINTEN, gpie); intr->mask_misc |= TXGBE_ICRMISC_GPIO; intr->mask_misc |= TXGBE_ICRMISC_ANDONE; + intr->mask_misc |= TXGBE_ICRMISC_HEAT; } int @@ -2672,6 +2673,28 @@ txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +txgbe_dev_overheat(struct rte_eth_dev *dev) +{ + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + s32 temp_state; + + temp_state = hw->phy.check_overtemp(hw); + if (!temp_state) + return; + + if (temp_state == TXGBE_ERR_UNDERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been started again, " + "since the temperature has been back to normal state."); + wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA); + txgbe_dev_set_link_up(dev); + } else if (temp_state == TXGBE_ERR_OVERTEMP) { + PMD_DRV_LOG(CRIT, "Network adapter has been stopped because it has over heated."); + wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0); + txgbe_dev_set_link_down(dev); + } +} + void txgbe_dev_setup_link_alarm_handler(void *param) { @@ -2974,6 +2997,9 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, if (eicr & TXGBE_ICRMISC_GPIO) intr->flags |= TXGBE_FLAG_PHY_INTERRUPT; + if (eicr & TXGBE_ICRMISC_HEAT) + intr->flags |= TXGBE_FLAG_OVERHEAT; + return 0; } @@ -3086,6 +3112,11 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev, } } + if (intr->flags & TXGBE_FLAG_OVERHEAT) { + txgbe_dev_overheat(dev); + intr->flags &= ~TXGBE_FLAG_OVERHEAT; + } + PMD_DRV_LOG(DEBUG, "enable intr immediately"); txgbe_enable_intr(dev); rte_intr_enable(intr_handle); diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h index 6a18865e23..c59b6370bb 100644 --- a/drivers/net/txgbe/txgbe_ethdev.h +++ b/drivers/net/txgbe/txgbe_ethdev.h @@ -30,6 +30,7 @@ #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3) #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5) +#define TXGBE_FLAG_OVERHEAT (uint32_t)(1 << 6) /* * Defines that were not part of txgbe_type.h as they are not used by the From patchwork Wed Jan 18 06:00:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 122244 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F29F42409; Wed, 18 Jan 2023 07:05:06 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4A3142D60; Wed, 18 Jan 2023 07:04:31 +0100 (CET) Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by mails.dpdk.org (Postfix) with ESMTP id 1EB4142D71 for ; Wed, 18 Jan 2023 07:04:28 +0100 (CET) X-QQ-mid: bizesmtp69t1674021865t1310co1 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 18 Jan 2023 14:04:24 +0800 (CST) X-QQ-SSF: 01400000000000H0X000B00A0000000 X-QQ-FEAT: +ynUkgUhZJlFH+htGERKrP83cl3TwIflyqICxEIgIK4pPQyTCpydmMc/9A2g7 S4jsems3CbzElParTAQdTUiDMLhJU6NMyTC7KqL9pO/+csKlpDuI1dv+Fzkj1nPxQLI4cMR Bl4aJj/Nkle3bi3KAXcmic4Rpi6AEu7WudhN/3zxaYfsazykEkKE9V81Kzt0Z1lDttkN66G W5pjiKdVG6gh7js33XD96Ojlc44My33DFWYzKeLafY2MUcUc4WQY2YVib+NKTGDjXI7qQRc LJNqvFTKtd+p+6Wo6F/sGL2U+1vuyWAtnrreUQ3LYvvOo+93IUWUJI2V5j51DO/OgBCql1w V+FwQ5E8JX8t0gB6vteJPoetpfa4FJm/UGP//CJGPRIcuVaKPEOqTNV5VRDXv3K6znpRTiv X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu Subject: [PATCH 8/8] net/txgbe: add SFP hot-plug identification support Date: Wed, 18 Jan 2023 14:00:39 +0800 Message-Id: <20230118060039.3074016-9-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230118060039.3074016-1-jiawenwu@trustnetic.com> References: <20230118060039.3074016-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvr:qybglogicsvr5 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to identify the new SFP/SFP+ module when the device is started. Signed-off-by: Jiawen Wu --- doc/guides/rel_notes/release_23_03.rst | 1 + drivers/net/txgbe/base/txgbe_regs.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 70 +++++++++++++++++++++++--- 3 files changed, 65 insertions(+), 7 deletions(-) diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index e64cb2d974..3c43b75ac0 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -62,6 +62,7 @@ New Features * **Updated Wangxun txgbe driver.** * Added chip overheat detection support. + * Added SFP hot-plug identification support. Removed Items diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 911bb6e04e..bc2854b01a 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1579,6 +1579,7 @@ enum txgbe_5tuple_protocol { #define TXGBE_GPIOINTMASK 0x014834 #define TXGBE_GPIOINTTYPE 0x014838 #define TXGBE_GPIOINTSTAT 0x014840 +#define TXGBE_GPIORAWINTSTAT 0x014844 #define TXGBE_GPIOEOI 0x01484C diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index ce7cf2506d..a502618bc5 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -114,6 +114,7 @@ static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *handle); static void txgbe_dev_interrupt_handler(void *param); +static void txgbe_dev_detect_sfp(void *param); static void txgbe_dev_interrupt_delayed_handler(void *param); static void txgbe_configure_msix(struct rte_eth_dev *dev); @@ -1535,11 +1536,20 @@ txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) { struct txgbe_hw *hw = TXGBE_DEV_HW(dev); struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); + u8 device_type = hw->subsystem_device_id & 0xF0; uint32_t gpie; - gpie = rd32(hw, TXGBE_GPIOINTEN); - gpie |= TXGBE_GPIOBIT_6; - wr32(hw, TXGBE_GPIOINTEN, gpie); + if (device_type != TXGBE_DEV_ID_MAC_XAUI && + device_type != TXGBE_DEV_ID_MAC_SGMII) { + gpie = rd32(hw, TXGBE_GPIOINTEN); + gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6; + wr32(hw, TXGBE_GPIOINTEN, gpie); + + gpie = rd32(hw, TXGBE_GPIOINTTYPE); + gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6; + wr32(hw, TXGBE_GPIOINTTYPE, gpie); + } + intr->mask_misc |= TXGBE_ICRMISC_GPIO; intr->mask_misc |= TXGBE_ICRMISC_ANDONE; intr->mask_misc |= TXGBE_ICRMISC_HEAT; @@ -1648,6 +1658,7 @@ txgbe_dev_start(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); /* Stop the link setup handler before resetting the HW. */ + rte_eal_alarm_cancel(txgbe_dev_detect_sfp, dev); rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); /* disable uio/vfio intr/eventfd mapping */ @@ -1880,6 +1891,7 @@ txgbe_dev_stop(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); + rte_eal_alarm_cancel(txgbe_dev_detect_sfp, dev); rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev); /* disable interrupts */ @@ -2673,6 +2685,51 @@ txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +txgbe_dev_detect_sfp(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + s32 err; + + err = hw->phy.identify_sfp(hw); + if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) { + PMD_DRV_LOG(ERR, "Unsupported SFP+ module type was detected."); + } else if (err == TXGBE_ERR_SFP_NOT_PRESENT) { + PMD_DRV_LOG(INFO, "SFP not present."); + } else if (err == 0) { + hw->mac.setup_sfp(hw); + PMD_DRV_LOG(INFO, "detected SFP+: %d\n", hw->phy.sfp_type); + txgbe_dev_setup_link_alarm_handler(dev); + txgbe_dev_link_update(dev, 0); + } +} + +static void +txgbe_dev_sfp_event(struct rte_eth_dev *dev) +{ + struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev); + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + u32 reg; + + wr32(hw, TXGBE_GPIOINTMASK, 0xFF); + reg = rd32(hw, TXGBE_GPIORAWINTSTAT); + if (reg & TXGBE_GPIOBIT_2) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2); + rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev); + } + if (reg & TXGBE_GPIOBIT_3) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_3); + intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; + } + if (reg & TXGBE_GPIOBIT_6) { + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_6); + intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE; + } + + wr32(hw, TXGBE_GPIOINTMASK, 0); +} + static void txgbe_dev_overheat(struct rte_eth_dev *dev) { @@ -2972,9 +3029,6 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX) wr32(hw, TXGBE_PX_INTA, 1); - /* clear all cause mask */ - txgbe_disable_intr(hw); - /* read-on-clear nic registers here */ eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC]; PMD_DRV_LOG(DEBUG, "eicr %x", eicr); @@ -3000,6 +3054,8 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev, if (eicr & TXGBE_ICRMISC_HEAT) intr->flags |= TXGBE_FLAG_OVERHEAT; + ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC] = 0; + return 0; } @@ -3064,7 +3120,7 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev, } if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) { - hw->phy.handle_lasi(hw); + txgbe_dev_sfp_event(dev); intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT; }