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Wed, 1 Feb 2023 07:35:38 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Ashish Gupta" , Fan Zhang , Kai Ji , Thomas Monjalon , , , Subject: [PATCH v2 1/2] compressdev: fix end of comp PMD list macro conflict Date: Wed, 1 Feb 2023 17:35:30 +0200 Message-ID: <20230201153531.912219-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201153531.912219-1-michaelba@nvidia.com> References: <20230101134720.1709991-1-michaelba@nvidia.com> <20230201153531.912219-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT096:EE_|CY8PR12MB8242:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e4209e4-6014-4e56-f8ff-08db0469ffee X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AfspWeU8ZGa2ovsc8RpoACkmKYd8heWemVfPJkr8xwGbdByOmxoHubJEo35TalLvP14ImzupxnmqBqRm8pjUlhbqjlGjtzYJT02hYTScHagOFem1pRyK8s9SpAQs1PbaABKct7dCke8ytQDUPFAGyYmHDGGWNjclocvo48XIPiIEfd2D2SAnHUo527pmGyNOGvDf8RYqRwkchYSzH2iCG3c3PIyZOZA/4SK84IwsB/z1UB1fenHhBig+qwsthCWKc/HhqNuskv5dRyDY8wQMW90txDaEcsfiIDU+JPcbRZq2bPlaOr9cS2Bluyf0jEkj5X5fWnIoRbEEPBi+7T61khH8+PYXImtsMEF2o1hLgWhn+c+7xPMwh43qegp/xh1xozVT5tZNOKuWtIEA2saV+g5KkCtUXcle+6Vx3u6yLh6oWBUh/DofbzaAWSIs0sVb/hcs/VGyPrACQwGpyQ7GHv7MbjasnCFmai6cykJ1iQ+6afbvHcxW9iWM81/Dq0Y4YVBha2Vvj/MHCp2rwQNYRHeZb/w/OL9Ry8LQSzILYsCyY1WL4DzrbM6dURTFYfmW36uktQfxCkB7ZVW68Ota9yquMeo4GZWrYhXI5kn0lqyu4A9OlKlmDSzsL/PHHV7o50W/NdwN4V0N1SrBD32tsRHIijRRhtf82/oOqmSQ2gR7eyQWKPyrv/oWy3GQ0O9JVzmPtKicxCVQowneHSnha8PL/dmb5Ykqrnw+StV47JZbcDET9cGKjBG3tbi+V/aU X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(136003)(346002)(376002)(396003)(451199018)(36840700001)(40470700004)(46966006)(40460700003)(1076003)(36756003)(478600001)(40480700001)(55016003)(2906002)(7696005)(54906003)(5660300002)(6666004)(86362001)(316002)(36860700001)(336012)(426003)(83380400001)(70586007)(4326008)(6916009)(70206006)(47076005)(6286002)(186003)(356005)(26005)(41300700001)(82740400003)(7636003)(2616005)(8936002)(82310400005)(8676002)(141333003)(181643002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2023 15:35:51.3423 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e4209e4-6014-4e56-f8ff-08db0469ffee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8242 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The "rte_compressdev_info_get()" function retrieves the contextual information of a device. The output structure "dev_info" contains a list of devices supported capabilities for each supported algorithm. In this function description, it says the element after the last valid element has op field set to "RTE_COMP_ALGO_LIST_END". On the other hand, when this function used by "rte_compressdev_capability_get()" function, it uses "RTE_COMP_ALGO_UNSPECIFIED" as end of list as same as the "RTE_COMP_END_OF_CAPABILITIES_LIST()". The mlx5 and qat PMDs use "RTE_COMP_ALGO_LIST_END" as the end of capabilities list. When "rte_compressdev_capability_get()" function is called with unsupported algorithm, it might read memory out of bound. This patch change the "rte_compressdev_info_get()" function description to say using "RTE_COMP_ALGO_UNSPECIFIED" as the end of capabilities list. In addition, it moves both mlx5 and qat PMDs to use "RTE_COMP_ALGO_UNSPECIFIED" through "RTE_COMP_END_OF_CAPABILITIES_LIST()" macro. Fixes: 5d432f364078 ("compressdev: add device capabilities") Fixes: 2d148597ce76 ("compress/qat: add gen-specific implementation") Fixes: 384bac8d6555 ("compress/mlx5: add supported capabilities") Cc: fiona.trahe@intel.com Cc: roy.fan.zhang@intel.com Cc: matan@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/compress/mlx5/mlx5_compress.c | 4 +--- drivers/compress/qat/dev/qat_comp_pmd_gen1.c | 2 +- drivers/compress/qat/dev/qat_comp_pmd_gen4.c | 2 +- lib/compressdev/rte_compressdev.h | 2 +- 4 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index fb2bda9745..459e4b5e8a 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -96,9 +96,7 @@ static const struct rte_compressdev_capabilities mlx5_caps[] = { RTE_COMP_FF_HUFFMAN_DYNAMIC, .window_size = {.min = 10, .max = 15, .increment = 1}, }, - { - .algo = RTE_COMP_ALGO_LIST_END, - } + RTE_COMP_END_OF_CAPABILITIES_LIST() }; static void diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen1.c b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c index 12d9d89072..3a8484eef1 100644 --- a/drivers/compress/qat/dev/qat_comp_pmd_gen1.c +++ b/drivers/compress/qat/dev/qat_comp_pmd_gen1.c @@ -26,7 +26,7 @@ const struct rte_compressdev_capabilities qat_gen1_comp_capabilities[] = { RTE_COMP_FF_OOP_LB_IN_SGL_OUT | RTE_COMP_FF_STATEFUL_DECOMPRESSION, .window_size = {.min = 15, .max = 15, .increment = 0} }, - {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } }; + RTE_COMP_END_OF_CAPABILITIES_LIST() }; static int qat_comp_dev_config_gen1(struct rte_compressdev *dev, diff --git a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c index 79b2ceb414..05906f13e0 100644 --- a/drivers/compress/qat/dev/qat_comp_pmd_gen4.c +++ b/drivers/compress/qat/dev/qat_comp_pmd_gen4.c @@ -25,7 +25,7 @@ qat_gen4_comp_capabilities[] = { RTE_COMP_FF_OOP_SGL_IN_LB_OUT | RTE_COMP_FF_OOP_LB_IN_SGL_OUT, .window_size = {.min = 15, .max = 15, .increment = 0} }, - {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } }; + RTE_COMP_END_OF_CAPABILITIES_LIST() }; static int qat_comp_dev_config_gen4(struct rte_compressdev *dev, diff --git a/lib/compressdev/rte_compressdev.h b/lib/compressdev/rte_compressdev.h index 42bda9fc79..7eb5c58798 100644 --- a/lib/compressdev/rte_compressdev.h +++ b/lib/compressdev/rte_compressdev.h @@ -353,7 +353,7 @@ rte_compressdev_stats_reset(uint8_t dev_id); * @note The capabilities field of dev_info is set to point to the first * element of an array of struct rte_compressdev_capabilities. * The element after the last valid element has it's op field set to - * RTE_COMP_ALGO_LIST_END. + * RTE_COMP_ALGO_UNSPECIFIED. */ __rte_experimental void From patchwork Wed Feb 1 15:35:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 122874 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B877241BA0; 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Wed, 1 Feb 2023 07:35:43 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 1 Feb 2023 07:35:43 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36 via Frontend Transport; Wed, 1 Feb 2023 07:35:41 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Ashish Gupta" , Fan Zhang , Kai Ji , Thomas Monjalon Subject: [PATCH v2 2/2] compressdev: remove useless list end enums Date: Wed, 1 Feb 2023 17:35:31 +0200 Message-ID: <20230201153531.912219-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201153531.912219-1-michaelba@nvidia.com> References: <20230101134720.1709991-1-michaelba@nvidia.com> <20230201153531.912219-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C982:EE_|SN7PR12MB6689:EE_ X-MS-Office365-Filtering-Correlation-Id: 21fdd2ae-b5ff-4e02-2749-08db046a01f6 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2023 15:35:54.7917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21fdd2ae-b5ff-4e02-2749-08db046a01f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C982.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6689 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The both "RTE_COMP_ALGO_LIST_END" and "RTE_COMP_HASH_ALGO_LIST_END" are useless. This patch removes them from the library. Signed-off-by: Michael Baum --- lib/compressdev/rte_comp.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/compressdev/rte_comp.h b/lib/compressdev/rte_comp.h index a8f398b57b..5bd711fda1 100644 --- a/lib/compressdev/rte_comp.h +++ b/lib/compressdev/rte_comp.h @@ -109,7 +109,6 @@ enum rte_comp_algorithm { /**< LZS compression algorithm * https://tools.ietf.org/html/rfc2395 */ - RTE_COMP_ALGO_LIST_END }; /** Compression Hash Algorithms */ @@ -120,7 +119,6 @@ enum rte_comp_hash_algorithm { /**< SHA1 hash algorithm */ RTE_COMP_HASH_ALGO_SHA2_256, /**< SHA256 hash algorithm of SHA2 family */ - RTE_COMP_HASH_ALGO_LIST_END }; /**< Compression Level.