From patchwork Mon Apr 10 06:47:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 125869 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 279534290A; Mon, 10 Apr 2023 08:47:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B0E1C40DDC; Mon, 10 Apr 2023 08:47:39 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 4E30840A81 for ; Mon, 10 Apr 2023 08:47:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681109258; x=1712645258; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=D3vjzqt9p4vq7+YJj+ajJrbt2nnnBKmO2UDnmMVKjlk=; b=YmSZhyH37zZiM4VfH2MZyWzDmibIgZMGUDNa9VhWGQvElXsWFTe361E2 zrmKT3L2wCy7mPwbmY8gUCoiIIhU2NoHg2i+k9w9EBwT9ekFEfwE5cysO QblVXEaY6nHDlnfWB8TYdIWg22HOXmTMy4b9v7Sj+rdZI/uSyMSle4TL6 WZFmeIlxck/OHpkcc8883udiWkCmYWTDk6pfWDgVLO2KkzFiptSPQ98+h ibsZPl9kTJ1elRKQv8PLSdXSQZsvDX3UIj7q3PKUSmdQRvvLTuVPxGdJA g2GWUKQh9ZwK+vIMwUI1W6hWFmRIBds52Bap4lnJUmttrC6DFYk92fm8S A==; X-IronPort-AV: E=McAfee;i="6600,9927,10675"; a="408435783" X-IronPort-AV: E=Sophos;i="5.98,333,1673942400"; d="scan'208";a="408435783" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2023 23:47:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10675"; a="831841851" X-IronPort-AV: E=Sophos;i="5.98,333,1673942400"; d="scan'208";a="831841851" Received: from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104]) by fmsmga001.fm.intel.com with ESMTP; 09 Apr 2023 23:47:34 -0700 From: Junfeng Guo To: qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com, beilei.xing@intel.com Cc: dev@dpdk.org, Junfeng Guo , Rushil Gupta , Joshua Washington , Jeroen de Borst Subject: [PATCH] net/gve: add struct members and typedefs for DQO Date: Mon, 10 Apr 2023 14:47:24 +0800 Message-Id: <20230410064724.2094392-1-junfeng.guo@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add struct members for gve_tx_queue and gve_rx_queue. Add typedefs for little endians. Signed-off-by: Junfeng Guo Signed-off-by: Rushil Gupta Signed-off-by: Joshua Washington Signed-off-by: Jeroen de Borst --- .mailmap | 1 + drivers/net/gve/base/gve_osdep.h | 4 ++++ drivers/net/gve/gve_ethdev.h | 9 +++++++++ 3 files changed, 14 insertions(+) diff --git a/.mailmap b/.mailmap index 0859104404..10e1392cd8 100644 --- a/.mailmap +++ b/.mailmap @@ -590,6 +590,7 @@ Jens Freimann Jeremy Plsek Jeremy Spewock Jerin Jacob +Jeroen de Borst Jerome Jutteau Jerry Hao OS Jerry Lilijun diff --git a/drivers/net/gve/base/gve_osdep.h b/drivers/net/gve/base/gve_osdep.h index 7cb73002f4..abf3d379ae 100644 --- a/drivers/net/gve/base/gve_osdep.h +++ b/drivers/net/gve/base/gve_osdep.h @@ -35,6 +35,10 @@ typedef rte_be16_t __be16; typedef rte_be32_t __be32; typedef rte_be64_t __be64; +typedef rte_le16_t __le16; +typedef rte_le32_t __le32; +typedef rte_le64_t __le64; + typedef rte_iova_t dma_addr_t; #define ETH_MIN_MTU RTE_ETHER_MIN_MTU diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h index 42a02cf5d4..0b825113f6 100644 --- a/drivers/net/gve/gve_ethdev.h +++ b/drivers/net/gve/gve_ethdev.h @@ -11,6 +11,9 @@ #include "base/gve.h" +/* TODO: this is a workaround to ensure that Tx complq is enough */ +#define DQO_TX_MULTIPLIER 4 + /* * Following macros are derived from linux/pci_regs.h, however, * we can't simply include that header here, as there is no such @@ -124,6 +127,9 @@ struct gve_tx_queue { const struct rte_memzone *qres_mz; struct gve_queue_resources *qres; + /* newly added for DQO */ + uint64_t compl_ring_phys_addr; + /* Only valid for DQO_RDA queue format */ struct gve_tx_queue *complq; @@ -164,6 +170,9 @@ struct gve_rx_queue { uint16_t ntfy_id; uint16_t rx_buf_len; + /* newly added for DQO */ + uint64_t compl_ring_phys_addr; + /* Only valid for DQO_RDA queue format */ struct gve_rx_queue *bufq;