From patchwork Thu Apr 13 09:44:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126003 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7E8342931; Thu, 13 Apr 2023 11:50:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9CE8D41138; Thu, 13 Apr 2023 11:50:15 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 2D65E4021F for ; Thu, 13 Apr 2023 11:50:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379411; x=1712915411; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=373QxvP2q6x+nCTNvD2s+xR0zLnz5dw4sHp/J63RI2Y=; b=iovAosGh0uAecF/7ftoOqFo58kUWA9KxbTkmyVSqL5c3BhdkvveXvBtT tD4AutWjJtZR8o4eirzwOfu/fQ5hjmDxl81NprV67WR8ltptAlQipkAw1 NgxXB0G4al83WwWer9lPyvoB9s9jkj0ogkfyscOsRF+y0sIOG1xMqGShx eH/SKWqASWEjWDE/pnK/fmb96N5vCu7P5+0MZb5dRvd+yZx3ScMYSirAQ jUzsykbI0hQYxjbKw2+/dZF+6t+FGNEdS6TCvQKksqvzlka2mSKj7QyWf WdOV26derZerXG0b+0vMT2cTVA1k3WV6K9EAi4Zc6YyN3e2cX31LuMCT0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290344" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290344" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699239" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699239" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:07 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Jie Wang Subject: [PATCH 01/18] common/idpf: support flow subscription Date: Thu, 13 Apr 2023 05:44:45 -0400 Message-Id: <20230413094502.1714755-2-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org VF is able to subscribe a flow from PF by VIRTCHNL_FLOW_SUBSCRIBE. PF is expected to offload a rule to hardware which will redirect the packet that matching the required pattern to this VF. Only a flow with dst mac address as PF's mac address can be subscribed. VIRTCHNL_VF_OFFLOAD_FSUB_PF is used for Flow subscription capability negotiation and only a trusted VF can be granted with this capability. A flow can be unsubscribed by VIRTCHNL_FLOW_UNSUBSCRIBE. Signed-off-by: Jie Wang Signed-off-by: Qi Zhang Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl.h | 102 +++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 3 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h index ea798e3971..3008802c4a 100644 --- a/drivers/common/idpf/base/virtchnl.h +++ b/drivers/common/idpf/base/virtchnl.h @@ -182,6 +182,8 @@ enum virtchnl_ops { VIRTCHNL_OP_MAP_QUEUE_VECTOR = 111, VIRTCHNL_OP_CONFIG_QUEUE_BW = 112, VIRTCHNL_OP_CONFIG_QUANTA = 113, + VIRTCHNL_OP_FLOW_SUBSCRIBE = 114, + VIRTCHNL_OP_FLOW_UNSUBSCRIBE = 115, VIRTCHNL_OP_MAX, }; @@ -298,6 +300,10 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode) return "VIRTCHNL_OP_DISABLE_QUEUES_V2"; case VIRTCHNL_OP_MAP_QUEUE_VECTOR: return "VIRTCHNL_OP_MAP_QUEUE_VECTOR"; + case VIRTCHNL_OP_FLOW_SUBSCRIBE: + return "VIRTCHNL_OP_FLOW_SUBSCRIBE"; + case VIRTCHNL_OP_FLOW_UNSUBSCRIBE: + return "VIRTCHNL_OP_FLOW_UNSUBSCRIBE"; case VIRTCHNL_OP_MAX: return "VIRTCHNL_OP_MAX"; default: @@ -434,6 +440,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource); /* BIT(8) is reserved */ #define VIRTCHNL_VF_LARGE_NUM_QPAIRS BIT(9) #define VIRTCHNL_VF_OFFLOAD_CRC BIT(10) +#define VIRTCHNL_VF_OFFLOAD_FSUB_PF BIT(14) #define VIRTCHNL_VF_OFFLOAD_VLAN_V2 BIT(15) #define VIRTCHNL_VF_OFFLOAD_VLAN BIT(16) #define VIRTCHNL_VF_OFFLOAD_RX_POLLING BIT(17) @@ -1451,6 +1458,7 @@ enum virtchnl_vfr_states { }; #define VIRTCHNL_MAX_NUM_PROTO_HDRS 32 +#define VIRTCHNL_MAX_NUM_PROTO_HDRS_W_MSK 16 #define VIRTCHNL_MAX_SIZE_RAW_PACKET 1024 #define PROTO_HDR_SHIFT 5 #define PROTO_HDR_FIELD_START(proto_hdr_type) \ @@ -1643,6 +1651,22 @@ struct virtchnl_proto_hdr { VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_proto_hdr); +struct virtchnl_proto_hdr_w_msk { + /* see enum virtchnl_proto_hdr_type */ + s32 type; + u32 pad; + /** + * binary buffer in network order for specific header type. + * For example, if type = VIRTCHNL_PROTO_HDR_IPV4, a IPv4 + * header is expected to be copied into the buffer. + */ + u8 buffer_spec[64]; + /* binary buffer for bit-mask applied to specific header type */ + u8 buffer_mask[64]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(136, virtchnl_proto_hdr_w_msk); + struct virtchnl_proto_hdrs { u8 tunnel_level; /** @@ -1655,12 +1679,18 @@ struct virtchnl_proto_hdrs { */ int count; /** - * number of proto layers, must < VIRTCHNL_MAX_NUM_PROTO_HDRS - * must be 0 for a raw packet request. + * count must <= + * VIRTCHNL_MAX_NUM_PROTO_HDRS + VIRTCHNL_MAX_NUM_PROTO_HDRS_W_MSK + * count = 0 : select raw + * 1 < count <= VIRTCHNL_MAX_NUM_PROTO_HDRS : select proto_hdr + * count > VIRTCHNL_MAX_NUM_PROTO_HDRS : select proto_hdr_w_msk + * last valid index = count - VIRTCHNL_MAX_NUM_PROTO_HDRS */ union { struct virtchnl_proto_hdr proto_hdr[VIRTCHNL_MAX_NUM_PROTO_HDRS]; + struct virtchnl_proto_hdr_w_msk + proto_hdr_w_msk[VIRTCHNL_MAX_NUM_PROTO_HDRS_W_MSK]; struct { u16 pkt_len; u8 spec[VIRTCHNL_MAX_SIZE_RAW_PACKET]; @@ -1681,7 +1711,7 @@ struct virtchnl_rss_cfg { VIRTCHNL_CHECK_STRUCT_LEN(2444, virtchnl_rss_cfg); -/* action configuration for FDIR */ +/* action configuration for FDIR and FSUB */ struct virtchnl_filter_action { /* see enum virtchnl_action type */ s32 type; @@ -1799,6 +1829,66 @@ struct virtchnl_fdir_del { VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_fdir_del); +/* Status returned to VF after VF requests FSUB commands + * VIRTCHNL_FSUB_SUCCESS + * VF FLOW related request is successfully done by PF + * The request can be OP_FLOW_SUBSCRIBE/UNSUBSCRIBE. + * + * VIRTCHNL_FSUB_FAILURE_RULE_NORESOURCE + * OP_FLOW_SUBSCRIBE request is failed due to no Hardware resource. + * + * VIRTCHNL_FSUB_FAILURE_RULE_EXIST + * OP_FLOW_SUBSCRIBE request is failed due to the rule is already existed. + * + * VIRTCHNL_FSUB_FAILURE_RULE_NONEXIST + * OP_FLOW_UNSUBSCRIBE request is failed due to this rule doesn't exist. + * + * VIRTCHNL_FSUB_FAILURE_RULE_INVALID + * OP_FLOW_SUBSCRIBE request is failed due to parameters validation + * or HW doesn't support. + */ +enum virtchnl_fsub_prgm_status { + VIRTCHNL_FSUB_SUCCESS = 0, + VIRTCHNL_FSUB_FAILURE_RULE_NORESOURCE, + VIRTCHNL_FSUB_FAILURE_RULE_EXIST, + VIRTCHNL_FSUB_FAILURE_RULE_NONEXIST, + VIRTCHNL_FSUB_FAILURE_RULE_INVALID, +}; + +/* VIRTCHNL_OP_FLOW_SUBSCRIBE + * VF sends this request to PF by filling out vsi_id, + * validate_only, priority, proto_hdrs and actions. + * PF will return flow_id + * if the request is successfully done and return status to VF. + */ +struct virtchnl_flow_sub { + u16 vsi_id; /* INPUT */ + u8 validate_only; /* INPUT */ + /* 0 is the highest priority; INPUT */ + u8 priority; + u32 flow_id; /* OUTPUT */ + struct virtchnl_proto_hdrs proto_hdrs; /* INPUT */ + struct virtchnl_filter_action_set actions; /* INPUT */ + /* see enum virtchnl_fsub_prgm_status; OUTPUT */ + s32 status; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(2616, virtchnl_flow_sub); + +/* VIRTCHNL_OP_FLOW_UNSUBSCRIBE + * VF sends this request to PF by filling out vsi_id + * and flow_id. PF will return status to VF. + */ +struct virtchnl_flow_unsub { + u16 vsi_id; /* INPUT */ + u16 pad; + u32 flow_id; /* INPUT */ + /* see enum virtchnl_fsub_prgm_status; OUTPUT */ + s32 status; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_flow_unsub); + /* VIRTCHNL_OP_GET_QOS_CAPS * VF sends this message to get its QoS Caps, such as * TC number, Arbiter and Bandwidth. @@ -2731,6 +2821,12 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, case VIRTCHNL_OP_DEL_FDIR_FILTER: valid_len = sizeof(struct virtchnl_fdir_del); break; + case VIRTCHNL_OP_FLOW_SUBSCRIBE: + valid_len = sizeof(struct virtchnl_flow_sub); + break; + case VIRTCHNL_OP_FLOW_UNSUBSCRIBE: + valid_len = sizeof(struct virtchnl_flow_unsub); + break; case VIRTCHNL_OP_GET_QOS_CAPS: break; case VIRTCHNL_OP_CONFIG_QUEUE_TC_MAP: From patchwork Thu Apr 13 09:44:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126004 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8C3BD42931; Thu, 13 Apr 2023 11:50:24 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D841E42B7E; Thu, 13 Apr 2023 11:50:16 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 35F52410F9; Thu, 13 Apr 2023 11:50:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379414; x=1712915414; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VQXRouaK+IKPG/RNj7a4FchRTe4L3XqOPsszmvYTy6E=; b=DrKBIJ1hT96lYNtLi0/+X9cL4r5QZz2j151PgEXJrZGspKlBE9FlkraI +NrV0TIREc42SQd1edg+nOdBpNcP4v5R15353OqpGM6+dyVAXpwuoPyD7 quIt8i9EWLoPuzR5uBPEHwsbolKD1S4f4/vQ3RA9f/eV3GR551+yilE+N kWl5mab9RpPpJWKh3/qGtQzehRdTfA/ro4Y4XdDC7MyxohxyElkgZjVi/ IFcd+hLGsN505+lTblOVCkHyqqrm/P84Xfom6mOPT9S0oNV3FaGh3hBBV 1/Whga1YhzgRpkou1CV+ualn6ATehNkIHD+Wd1cmHANHp01k/TJFzrtvK Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290359" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290359" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699245" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699245" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:10 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Charles Stoll Subject: [PATCH 02/18] common/idpf: fix ctlq message send and receive Date: Thu, 13 Apr 2023 05:44:46 -0400 Message-Id: <20230413094502.1714755-3-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes the ctlq send and receive functions to not cast the cookie field to a u64 before programming. By doing a cast, it can cause endianness issues as LE will swap the lower 32 and higher 32 bits whereas BE will not. By treating this field as two 32 bit values, both BE and LE will place the retval and opcode in the correct location. Since this field is now being treated as two 32 bit values, the cfg.data section must also be split into a data high and data low. Macros to easily pack and read these fields have also been added. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Charles Stoll Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 3af81e5a64..8e4d3ee54f 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -311,18 +311,14 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, for (i = 0; i < num_q_msg; i++) { struct idpf_ctlq_msg *msg = &q_msg[i]; - u64 msg_cookie; desc = IDPF_CTLQ_DESC(cq, cq->next_to_use); desc->opcode = CPU_TO_LE16(msg->opcode); desc->pfid_vfid = CPU_TO_LE16(msg->func_id); - msg_cookie = *(u64 *)&msg->cookie; - desc->cookie_high = - CPU_TO_LE32(IDPF_HI_DWORD(msg_cookie)); - desc->cookie_low = - CPU_TO_LE32(IDPF_LO_DWORD(msg_cookie)); + desc->cookie_high = CPU_TO_LE32(msg->cookie.mbx.chnl_opcode); + desc->cookie_low = CPU_TO_LE32(msg->cookie.mbx.chnl_retval); desc->flags = CPU_TO_LE16((msg->host_id & IDPF_HOST_ID_MASK) << IDPF_CTLQ_FLAG_HOST_ID_S); @@ -620,8 +616,6 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, num_to_clean = *num_q_msg; for (i = 0; i < num_to_clean; i++) { - u64 msg_cookie; - /* Fetch next descriptor and check if marked as done */ desc = IDPF_CTLQ_DESC(cq, ntc); flags = LE16_TO_CPU(desc->flags); @@ -639,10 +633,8 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, if (flags & IDPF_CTLQ_FLAG_ERR) ret_code = -EBADMSG; - msg_cookie = (u64)LE32_TO_CPU(desc->cookie_high) << 32; - msg_cookie |= (u64)LE32_TO_CPU(desc->cookie_low); - idpf_memcpy(&q_msg[i].cookie, &msg_cookie, sizeof(u64), - IDPF_NONDMA_TO_NONDMA); + q_msg[i].cookie.mbx.chnl_opcode = LE32_TO_CPU(desc->cookie_high); + q_msg[i].cookie.mbx.chnl_retval = LE32_TO_CPU(desc->cookie_low); q_msg[i].opcode = LE16_TO_CPU(desc->opcode); q_msg[i].data_len = LE16_TO_CPU(desc->datalen); From patchwork Thu Apr 13 09:44:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126005 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2E30742931; Thu, 13 Apr 2023 11:50:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7EA1142D12; Thu, 13 Apr 2023 11:50:18 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 46E614021F; Thu, 13 Apr 2023 11:50:15 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379415; x=1712915415; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FLOzSIp7OeQRV7sspPldHGbBKpUSnbSBjVpl2JmpW0Y=; b=IhkdFVloaPCeGMiZmcWtcvott72SM3dJdJjVAV7UvMbKELRRbtIEvzJR EFZSsdTHoMehN4UfOl50g50NFgwKvcXeCm+18dJSX91R959HTQ1dbNdeB b0wMyBzRj4PeWjr4IBagTJR+kIobyv2LB9Yat9B4k+Wze24FEiA4cy6M+ 6u6yY8OUGA71ziHZNAikEETfUEUo6SrT5A/jf3qWdnzaJ0U8Yw7CO6GmG 4W4hTli10nN1LmmkFLkAd6dT+3EIL4inDVcaCGW8oWBx5n5kRI0VFo5XG sKPdltqkwdkEF5gfbigtQC2iHTGxNVmCldROzXevyOhqxuzCwIRYr/e1s g==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290373" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290373" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699252" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699252" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:12 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Priyalee Kushwaha Subject: [PATCH 03/18] common/idpf: fix ITR register definitions for AVF Date: Thu, 13 Apr 2023 05:44:47 -0400 Message-Id: <20230413094502.1714755-4-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix ITR register definitions for AVF1.0 and AVF2.0 Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Priyalee Kushwaha Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_lan_pf_regs.h | 9 +++++++-- drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 ++++++++++++----- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 3df2347bd7..7f731ec3d6 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -77,8 +77,13 @@ #define PF_GLINT_DYN_CTL_WB_ON_ITR_M BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S) #define PF_GLINT_DYN_CTL_INTENA_MSK_S 31 #define PF_GLINT_DYN_CTL_INTENA_MSK_M BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S) -#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start)) -#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) * 0x1000)) +/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is + * spacing b/w itrn registers of the same vector. + */ +#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */ +#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 #define PF_GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S) diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 9cd4f757d9..13c5c5a7da 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -90,11 +90,18 @@ #define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S) #define VF_INT_DYN_CTLN_INTENA_MSK_S 31 #define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S) -#define VF_INT_ITR0(_i) (0x00004C00 + ((_i) * 4)) -#define VF_INT_ITRN_V2(_i, _reg_start) ((_reg_start) + (((_i)) * 4)) -#define VF_INT_ITRN(_i, _INT) (0x00002800 + ((_i) * 4) + ((_INT) * 0x40)) -#define VF_INT_ITRN_64(_i, _INT) (0x00002C00 + ((_i) * 4) + ((_INT) * 0x100)) -#define VF_INT_ITRN_2K(_i, _INT) (0x00072000 + ((_i) * 4) + ((_INT) * 0x100)) +/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing + * b/w itrn registers of the same vector + */ +#define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4)) +#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \ + ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing))) +/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */ +#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40)) +/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */ +#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100)) +/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */ +#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 #define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S) From patchwork Thu Apr 13 09:44:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126006 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B212F42931; Thu, 13 Apr 2023 11:50:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9BE1442D1A; Thu, 13 Apr 2023 11:50:19 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 587114114B for ; Thu, 13 Apr 2023 11:50:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379417; x=1712915417; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AcPd/43caLnE6wVp3OdqTJotit7vuunfCEQFbuk6iNA=; b=dIE1JbVOK73ppKTIYdHxE3pG65gf8g3H6DdWHIBH9uzxnVKemYQJ2fPB Eth7PfvAeMKszf4XzwXqvmQYGyEtHdKaX4439u+ittqgkDuAStC4gCUXW OHe1OEbJ6bCZCk4BHRL3myeyF3G5PyOI+3VSnWvUANxtC68PO/TdrHFN0 XDFwZ1FpKQPyXTWvntOPmjiAHT6+hY56ExGWw9eNQAM+SqdYrgOkzh1gH 9GHHXed8XbhyBLbxT+F4EhkBqJ483LgrFh8hFrFIdPL4iYYINKm+5yPA/ nGctc3DYEiPT9pBOy1GPv+c5Nwq4NQGQ72n1u1DxULRmiA9OycsBbZthp w==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290386" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290386" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699261" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699261" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:14 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH 04/18] common/idpf: remove qregion struct variables Date: Thu, 13 Apr 2023 05:44:48 -0400 Message-Id: <20230413094502.1714755-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Existing qregion variables are not well defined and cannot be used for TC related stuff. Remove them from create vport struct and add those freed bytes to a new reserved field. Add appropriate comments on how to use the dynctl and itrn register spacing variables. Only VF reference was used in get version comments where it should be PF/VF. Note: qregion variables will be added once the requirements are defined properly. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index d496f2388e..5c01734b65 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -426,13 +426,13 @@ /* VIRTCHNL2_OP_VERSION - * VF posts its version number to the CP. CP responds with its version number + * PF/VF posts its version number to the CP. CP responds with its version number * in the same format, along with a return code. - * If there is a major version mismatch, then the VF cannot operate. - * If there is a minor version mismatch, then the VF can operate but should + * If there is a major version mismatch, then the PF/VF cannot operate. + * If there is a minor version mismatch, then the PF/VF can operate but should * add a warning to the system log. * - * This version opcode MUST always be specified as == 1, regardless of other + * This version opcode MUST always be specified as == 1, regardless of other * changes in the API. The CP must always respond to this message without * error regardless of version mismatch. */ @@ -598,11 +598,7 @@ struct virtchnl2_create_vport { /* see VIRTCHNL2_TX_DESC_IDS definitions */ __le64 tx_desc_ids; -#define MAX_Q_REGIONS 16 - __le32 max_qs_per_qregion[MAX_Q_REGIONS]; - __le32 qregion_total_qs; - __le16 qregion_type; - __le16 pad2; + u8 reserved1[72]; /* see VIRTCHNL2_RSS_ALGORITHM definitions */ __le32 rss_algorithm; @@ -665,9 +661,7 @@ struct virtchnl2_txq_info { */ __le16 peer_rx_queue_id; - /* value ranges from 0 to 15 */ - __le16 qregion_id; - u8 pad[2]; + u8 pad[4]; /* Egress pasid is used for SIOV use case */ __le32 egress_pasid; @@ -734,10 +728,7 @@ struct virtchnl2_rxq_info { * if this field is set */ u8 bufq2_ena; - u8 pad2; - - /* value ranges from 0 to 15 */ - __le16 qregion_id; + u8 pad2[3]; /* Ingress pasid is used for SIOV use case */ __le32 ingress_pasid; @@ -801,9 +792,13 @@ struct virtchnl2_vector_chunk { * interrupt indices without modifying the state of the interrupt. */ __le32 dynctl_reg_start; + /* register spacing to find the next dynctl and itrn register offset + * from the provided dynctl_reg_start and itrn_reg_start respectively + */ __le32 dynctl_reg_spacing; __le32 itrn_reg_start; + /* register spacing to find the individual itrn register where n=0..2 */ __le32 itrn_reg_spacing; u8 reserved[8]; }; From patchwork Thu Apr 13 09:44:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126007 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AAEAD42931; Thu, 13 Apr 2023 11:50:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BFA0942D20; Thu, 13 Apr 2023 11:50:20 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 590E842C54 for ; Thu, 13 Apr 2023 11:50:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379419; x=1712915419; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IXY7IFhDXjIrFFog9/DbVPZLHVa/0RPEvZ2TO2r3rEk=; b=EaMNAt8kBjX6kg7WOlzGY5OgbfeQE25W6As0cJapYs9vaQcTH+/hziAI WWlo6D5winddbf91AALLBiF67nycJDGlYLk7X8tGhfFGdaszO7UzM2Bw4 wiEhnbbbAf4KLsntldDXioCz6th6Vb3CBmDU1RZa7Jh/ar09AzFsUjluq RMg1JIA9AtKcrR/gydeyT7Il7l/eCEGsYYhmn1ibJaih9EtxqW2Pb2Lbx oYRGlG0tL8LOfea1xwcpsW87Oco6wVqgHdmHJGI8j8AkqdcFCMUpzEyG2 3dkOA7BjXAwH0LfHBYegYykL8B/9cdmZUYt7RcnnW28xaIXUZxZ6mvQJx g==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290394" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290394" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699267" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699267" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:17 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH 05/18] common/idpf: move OEM capability to the last bit Date: Thu, 13 Apr 2023 05:44:49 -0400 Message-Id: <20230413094502.1714755-6-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move the existing OEM capability in VIRTCHNL2_OTHER_CAPS to the last bit. This should not break any backward compatibility as it is not used yet. And VIRTCHNL2_MEV_DEVICE is no longer upstreamed. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 5c01734b65..32d8fe8c06 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -208,11 +208,8 @@ #define VIRTCHNL2_CAP_RX_FLEX_DESC BIT(17) #define VIRTCHNL2_CAP_PTYPE BIT(18) #define VIRTCHNL2_CAP_LOOPBACK BIT(19) -#define VIRTCHNL2_CAP_OEM BIT(20) - -/* VIRTCHNL2_DEVICE_TYPE */ -/* underlying device type */ -#define VIRTCHNL2_MEV_DEVICE 0 +/* this must be the last capability */ +#define VIRTCHNL2_CAP_OEM BIT(63) /* VIRTCHNL2_TXQ_SCHED_MODE * Transmit Queue Scheduling Modes - Queue mode is the legacy mode i.e. inorder From patchwork Thu Apr 13 09:44:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126008 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 04FB342931; Thu, 13 Apr 2023 11:50:56 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E067942C76; Thu, 13 Apr 2023 11:50:23 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 867904114B for ; Thu, 13 Apr 2023 11:50:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379421; x=1712915421; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GhO87oGG11ZM1yvafwTCi0+S6V7GZh/8I+81IGbEIfg=; b=ULYDeV7baY2hyZJojWlwrP6JRDu4E3l9O7i9kuQADY6mqMyBkBG8uP8Z PYkM+zy4eQTzqTwZKot/4/6wfjdWFiXh7vPp2UIxYt1uwA0lgMRc9a0yJ KIkYEtpC0sT6A28k07mtJolrG/uYZknio6425QooqES4SbGvXHwQqsse5 36XefS+6onmQ1wb6Wref/c2hDPUBebHQzG53soqRdem9d2mIpgSGT6aI1 1ESti6WuybW50f9VkiXVylLIzuBRrVPyKQuaVB5cE4pgCXjPxtkElqb0R qjBpaDLLK5ooBlwRY+ZtQKlpbtbRHIywydM1K8+FbuIrRVk8C6IEwGECS Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290410" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290410" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699274" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699274" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:18 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH 06/18] common/idpf: modify SSO/LSO and ITR fields Date: Thu, 13 Apr 2023 05:44:50 -0400 Message-Id: <20230413094502.1714755-7-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Driver assumes minimum packet length for sso as 17 bytes but it should be a negotiated value from CP. - Similarly, the number of header buffers for lso that are supported by the device should also be a negotiated value. Add min_sso_packet_len, max_hdr_buf_per_lso to address the above. Also, the existing 'itrn_reg_spacing' should be used for spacing between ITRn registers of 2 consecutive vectors and add a new spacing field to get the spacing between ITR registers of the same vector. - ITR_IDX 2 is not used in the current code. Bring it back if there exists any use case in the future. - NO_ITR is not really a register index and it is used only in the IDPF base code, so virtchnl support is not required for that - itr_idx_map is also not used as by default driver assumes at the minimum 2 ITRs are supported by the device. If any additional ITRs are also supported, then those should be negotiated. Remove all the above said fields and mark them as reserved. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 32d8fe8c06..edf3f200b3 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -289,8 +289,6 @@ */ #define VIRTCHNL2_ITR_IDX_0 0 #define VIRTCHNL2_ITR_IDX_1 1 -#define VIRTCHNL2_ITR_IDX_2 2 -#define VIRTCHNL2_ITR_IDX_NO_ITR 3 /* VIRTCHNL2_VECTOR_LIMITS * Since PF/VF messages are limited by __le16 size, precalculate the maximum @@ -510,9 +508,7 @@ struct virtchnl2_get_capabilities { */ u8 max_sg_bufs_per_tx_pkt; - /* see VIRTCHNL2_ITR_IDX definition */ - u8 itr_idx_map; - + u8 reserved1; __le16 pad1; /* version of Control Plane that is running */ @@ -521,7 +517,12 @@ struct virtchnl2_get_capabilities { /* see VIRTCHNL2_DEVICE_TYPE definitions */ __le32 device_type; - u8 reserved[12]; + /* min packet length supported by device for single segment offload */ + u8 min_sso_packet_len; + /* max number of header buffers that can be used for an LSO */ + u8 max_hdr_buf_per_lso; + + u8 reserved[10]; }; VIRTCHNL2_CHECK_STRUCT_LEN(80, virtchnl2_get_capabilities); @@ -789,15 +790,17 @@ struct virtchnl2_vector_chunk { * interrupt indices without modifying the state of the interrupt. */ __le32 dynctl_reg_start; - /* register spacing to find the next dynctl and itrn register offset - * from the provided dynctl_reg_start and itrn_reg_start respectively - */ + /* register spacing between dynctl registers of 2 consecutive vectors */ __le32 dynctl_reg_spacing; __le32 itrn_reg_start; - /* register spacing to find the individual itrn register where n=0..2 */ + /* register spacing between itrn registers of 2 consecutive vectors */ __le32 itrn_reg_spacing; - u8 reserved[8]; + /* register spacing between itrn registers of the same vector + * where n=0..2 + */ + __le32 itrn_index_spacing; + u8 reserved[4]; }; VIRTCHNL2_CHECK_STRUCT_LEN(32, virtchnl2_vector_chunk); From patchwork Thu Apr 13 09:44:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126009 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E292242931; Thu, 13 Apr 2023 11:51:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D1EAC42D33; Thu, 13 Apr 2023 11:50:25 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id BCC504114B for ; Thu, 13 Apr 2023 11:50:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379423; x=1712915423; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=na+DY3kJkdubMbrHkHHTx9PtdNDzHvcFhNbY3+/qo3k=; b=kcH8RwPMUh7+ZXkTq1zs+1tGiXV2sJWfm5kc61Yuq7G6eNIDoZYeXK/F muhhG4gsr0Qgkjwd8NrdyBRBNPjHz1OUeGfcjSx7a+bAbbQwzwsKvvnnf 04JJTjsY1kF6I7iL/Q6gT1NINibG0XBFeZeIg0A0I1xqEZSJPf0RgOJ8b n+enu9rgBvujJULWW4N0Ugm7eIHuK87QSFSVhvwEMPD9sBIcXR3T/u1AH Bz6HP2AOPHHTkU5Mdv3vzCXsxEThE42m0GmZPjQgWKnTWC8osxRwvkm3Z vMhZlP3g8LTbW6v4VC/Gf4iuV1GDNG1m5Np6tCUovxqNrOsTwruGevS0u A==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290430" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290430" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699284" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699284" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:21 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Kazatsker Kirill , Pavan Kumar Linga Subject: [PATCH 07/18] common/idpf: add virtchnl2 error codes Date: Thu, 13 Apr 2023 05:44:51 -0400 Message-Id: <20230413094502.1714755-8-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Virtchnl2 error codes are required for meaningful failure information sharing between CP and PF/VF. Introduce the necessary error codes. New error codes were introduced removing the old ones. So the references to the old one should be modified to avoid CI build failures. Use appropriate error codes wherever necessary. Signed-off-by: Kazatsker Kirill Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 40 +++++++++++++++++++++------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index edf3f200b3..415e90358e 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -12,14 +12,34 @@ #include "virtchnl2_lan_desc.h" -/* Error Codes - * Note that many older versions of various iAVF drivers convert the reported - * status code directly into an iavf_status enumeration. For this reason, it - * is important that the values of these enumerations line up. - */ -#define VIRTCHNL2_STATUS_SUCCESS 0 -#define VIRTCHNL2_STATUS_ERR_PARAM -5 -#define VIRTCHNL2_STATUS_ERR_OPCODE_MISMATCH -38 +/* VIRTCHNL2_ERROR_CODES */ +/* success */ +#define VIRTCHNL2_STATUS_SUCCESS 0 +/* Operation not permitted, used in case of command not permitted for sender */ +#define VIRTCHNL2_STATUS_ERR_EPERM 1 +/* Bad opcode - virtchnl interface problem */ +#define VIRTCHNL2_STATUS_ERR_ESRCH 3 +/* I/O error - HW access error */ +#define VIRTCHNL2_STATUS_ERR_EIO 5 +/* No such resource - Referenced resource is not allacated */ +#define VIRTCHNL2_STATUS_ERR_ENXIO 6 +/* Permission denied - Resource is not permitted to caller */ +#define VIRTCHNL2_STATUS_ERR_EACCES 13 +/* Device or resource busy - In case shared resource is in use by others */ +#define VIRTCHNL2_STATUS_ERR_EBUSY 16 +/* Object already exists and not free */ +#define VIRTCHNL2_STATUS_ERR_EEXIST 17 +/* Invalid input argument in command */ +#define VIRTCHNL2_STATUS_ERR_EINVAL 22 +/* No space left or allocation failure */ +#define VIRTCHNL2_STATUS_ERR_ENOSPC 28 +/* Parameter out of range */ +#define VIRTCHNL2_STATUS_ERR_ERANGE 34 + +/* Op not allowed in current dev mode */ +#define VIRTCHNL2_STATUS_ERR_EMODE 200 +/* State Machine error - Command sequence problem */ +#define VIRTCHNL2_STATUS_ERR_ESM 201 /* These macros are used to generate compilation errors if a structure/union * is not exactly the correct length. It gives a divide by zero error if the @@ -1445,11 +1465,11 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 case VIRTCHNL2_OP_EVENT: case VIRTCHNL2_OP_UNKNOWN: default: - return VIRTCHNL2_STATUS_ERR_PARAM; + return VIRTCHNL2_STATUS_ERR_ESRCH; } /* few more checks */ if (err_msg_format || valid_len != msglen) - return VIRTCHNL2_STATUS_ERR_OPCODE_MISMATCH; + return VIRTCHNL2_STATUS_ERR_EINVAL; return 0; } From patchwork Thu Apr 13 09:44:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126010 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 423F842931; Thu, 13 Apr 2023 11:51:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2523642D37; Thu, 13 Apr 2023 11:50:28 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 149F942D36 for ; Thu, 13 Apr 2023 11:50:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379426; x=1712915426; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iJS8b289BbEG/ftluEVn/OUjC0eQe2qMP8SQk1HdJwY=; b=FnxWMjWWSjHukAeWRnlgFw3g1seugB90Js/lyN6dUukIeJPlXOFcnx5/ ritmvniQQv74OSjlWTl5RVgEMBO6kvgSOzMH20PH+CQ9Wpcg/XkfcPFfg GKh7R+90AGjMDSr1kIA8PFIW+ZYfucPWpIBEwj2UVqUqDWjL/1orzei2n TVTFoUQL4IJSjbN3K9BUUZZQoohYrD3k4oei7dxP2v3Lq/hwdKq73pkgI OH9o+2VmBUKCQk1xcjkMViE/jKMAMSLPADsENSi7CiD3vbSnpUKf8Qj8R QgEAHeWLsuZeZFpUKmMEffdu4G/EgyxYbxOp5F5ablW00wCIJ4qs8SF1V Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290442" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290442" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699292" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699292" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:23 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Charles Stoll Subject: [PATCH 08/18] common/idpf: swap opcode and retval location in msg struct Date: Thu, 13 Apr 2023 05:44:52 -0400 Message-Id: <20230413094502.1714755-9-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org To make the code more readable and make it clearer that the opcode goes in cookie_high and retval goes in cookie_low. Add macro definitions for filling opcode and retval. Signed-off-by: Charles Stoll Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 2 ++ drivers/common/idpf/base/idpf_controlq_api.h | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 8e4d3ee54f..8381e4000f 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -288,6 +288,8 @@ int idpf_ctlq_deinit(struct idpf_hw *hw) * send routine via the q_msg struct / control queue specific data struct. * The control queue will hold a reference to each send message until * the completion for that message has been cleaned. + * Since all q_msgs being sent are store in native endianness, these values + * must be converted to LE before being written to the hw descriptor. */ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, u16 num_q_msg, struct idpf_ctlq_msg q_msg[]) diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 32d17baadf..80be282b42 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -63,9 +63,13 @@ struct idpf_ctlq_msg { u16 status; /* when receiving a message */ }; union { +#ifndef __KERNEL__ +#define FILL_OPCODE_V1(msg, opcode) ((msg).cookie.cfg.mbx.chnl_opcode = opcode) +#define FILL_RETVAL_V1(msg, retval) ((msg).cookie.cfg.mbx.chnl_retval = retval) +#endif /* __KERNEL__ */ struct { - u32 chnl_retval; u32 chnl_opcode; + u32 chnl_retval; } mbx; } cookie; union { From patchwork Thu Apr 13 09:44:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126011 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 269BA42931; Thu, 13 Apr 2023 11:51:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E02ED42D4E; Thu, 13 Apr 2023 11:50:29 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 10AC942D17; Thu, 13 Apr 2023 11:50:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379428; x=1712915428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lXCh0dlDMSMTYHgs9Vu+Se1yJrx1nTovMiZyf5x3pY8=; b=g9dpaixEeXcj4GZmQVWEJKwN++87NS0B+brxCowe/hlj8fqDxNxbZM9l zHdThplc73Xg28HOqpHPOKfDqxWc3iTLw+8ORhOXjKTYuySA4q+kWcBTs IlwiXepnFl7jzC6Z1XZpP/WAOf3/vpXUROPXtYEcBRLersJ2UdxjgJzFC DMArBJFJI6KMpOcCnSkJ7n63G9+rF23HHvG5hVQpXwFlG3AGgri2WMCVx GiiaDSS4QVZg5Kx/fBimeZkchzXvhVfxm84PrySnGAwEh6J/f0+hUAN/8 naOJDEeF0mPuXshqChBw79P4cv+sVGwnPmEMBrndbYygVATrzJHQQw8OM Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290460" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290460" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699304" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699304" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:25 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Christopher Pau Subject: [PATCH 09/18] common/idpf: fix idpf_send_msg_to_cp prototypes Date: Thu, 13 Apr 2023 05:44:53 -0400 Message-Id: <20230413094502.1714755-10-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Virtchnl2 opcodes are no longer in the enum virtchnl_ops. So change these parameters to allow int rather that compiler enum type checking. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Christopher Pau Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 3a9fdb1878..69e3b32f85 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -146,7 +146,7 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) * is sent asynchronously, i.e. idpf_asq_send_command() does not wait for * completion before returning. */ -int idpf_send_msg_to_cp(struct idpf_hw *hw, enum virtchnl_ops v_opcode, +int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, int v_retval, u8 *msg, u16 msglen) { struct idpf_ctlq_msg ctlq_msg = { 0 }; diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index 529b62212d..3ce25e644d 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -40,6 +40,6 @@ int idpf_set_rss_key(struct idpf_hw *hw, u16 seid, int idpf_set_mac_type(struct idpf_hw *hw); int idpf_reset(struct idpf_hw *hw); -int idpf_send_msg_to_cp(struct idpf_hw *hw, enum virtchnl_ops v_opcode, +int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, int v_retval, u8 *msg, u16 msglen); #endif /* _IDPF_PROTOTYPE_H_ */ From patchwork Thu Apr 13 09:44:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126012 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9627742931; Thu, 13 Apr 2023 11:51:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7AF8D42D5E; Thu, 13 Apr 2023 11:50:32 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 9199F42D48; Thu, 13 Apr 2023 11:50:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379430; x=1712915430; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ah9vgoVDJaO1ih3yu8myzr6iCvuVkAMldnLcmp3bdvw=; b=jNgYbSg9SouRgRFJkbgVoHBDkZL+2lfllmumPGdf/MlF8RPv+tRXFlYs /NT2/jdQIJd7AtCcoFqh9sQ/FpCVsAmVl8ce7An3X4nIcxmpgBgLXrczw lVh5VUp/R5K3mH5qnGEERy9ywxcpHzHyGPhCQ7FLHplJvJD2UrilfDD/n 4fNt7ZurClvsIRNVfCBp1ww6im6cbVcIiCyKEwk1P9KGZ99YGXe/Byt1T FUFsSI030TzanSZgXRLofx8Uqn7cPzRxdly0w2S0Nr1QgxwaG5TpFxrwY CwlAPHZfrxoiWYJT0RMAR2C0+5qYyrI4Q0ng2/JvP8wOUqMIOLp/aiNQY g==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290483" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290483" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699311" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699311" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:27 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Christopher Pau Subject: [PATCH 10/18] common/idpf: fix memory leaks on ctrlq functions Date: Thu, 13 Apr 2023 05:44:54 -0400 Message-Id: <20230413094502.1714755-11-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org idpf_init_hw needs to free it's q_info. idpf_clean_arq_element needs to return buffers via post_rx_buffs Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Christopher Pau Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index 69e3b32f85..de82c3458f 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -130,6 +130,8 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) hw->mac.addr[4] = 0x03; hw->mac.addr[5] = 0x14; + idpf_free(hw, q_info); + return 0; } @@ -219,6 +221,7 @@ bool idpf_check_asq_alive(struct idpf_hw *hw) int idpf_clean_arq_element(struct idpf_hw *hw, struct idpf_arq_event_info *e, u16 *pending) { + struct idpf_dma_mem *dma_mem = NULL; struct idpf_ctlq_msg msg = { 0 }; int status; u16 msg_data_len; @@ -226,6 +229,8 @@ int idpf_clean_arq_element(struct idpf_hw *hw, *pending = 1; status = idpf_ctlq_recv(hw->arq, pending, &msg); + if (status == -ENOMSG) + goto exit; /* ctlq_msg does not align to ctlq_desc, so copy relevant data here */ e->desc.opcode = msg.opcode; @@ -240,7 +245,14 @@ int idpf_clean_arq_element(struct idpf_hw *hw, msg_data_len = msg.data_len; idpf_memcpy(e->msg_buf, msg.ctx.indirect.payload->va, msg_data_len, IDPF_DMA_TO_NONDMA); + dma_mem = msg.ctx.indirect.payload; + } else { + *pending = 0; } + + status = idpf_ctlq_post_rx_buffs(hw, hw->arq, pending, &dma_mem); + +exit: return status; } From patchwork Thu Apr 13 09:44:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126013 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81E3442931; Thu, 13 Apr 2023 11:51:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B160442D63; Thu, 13 Apr 2023 11:50:33 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 2074842D38 for ; Thu, 13 Apr 2023 11:50:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379432; x=1712915432; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d1xR7S990AdEi3exqcwT8dyyEWyM85AY8GpZU7bWuMc=; b=HqyB/xdCOcf8uTJ3tfdmKyI789a1ukHAfPnx/6BSSdHOcvTjohUw46Jk x/jPzwy1AYNtjaD7T0kr+Gxytxi/sXcVZSWYe8/MrftLP3Ev4i7RVCy4N oukp4Vxw0gK3OyOloiudRuUKK4fEY7cIm47q01t5t2/6dACnmip1dnylq VbYoZqTFETY051FJcz/HAVXVjxl3jzPxP7Sc/D2nDtVyO5EkiCHN+R5fE inzGZm1lOHF3K4pNM/Q3Nmtiz0Kle8Yx3HFclCDNi+rrbqSQQF+IkG/2m x5jYFRYXecGHQTj3R4Ak54+TaFf3NHejh4bdbkpbjHewzZhlQdj5nGhW1 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290495" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290495" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699326" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699326" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:29 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Christopher Pau Subject: [PATCH 11/18] common/idpf: allocate static buffer at initialization Date: Thu, 13 Apr 2023 05:44:55 -0400 Message-Id: <20230413094502.1714755-12-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some OSs don't allow allocating DMA memory at runtime. So create an initial static buffer at initialization to hold this data. Signed-off-by: Christopher Pau Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_common.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index de82c3458f..f4a5707272 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -6,6 +6,7 @@ #include "idpf_prototype.h" #include "virtchnl.h" +struct idpf_dma_mem send_dma_mem = { 0 }; /** * idpf_set_mac_type - Sets MAC type @@ -132,6 +133,15 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size) idpf_free(hw, q_info); + /* + * Need an initial static buffer to copy DMA memory to send + * for drivers that do not allow this allocation at runtime + */ + send_dma_mem.va = (struct idpf_dma_mem *) + idpf_alloc_dma_mem(hw, &send_dma_mem, 4096); + if (!send_dma_mem.va) + return -ENOMEM; + return 0; } @@ -152,7 +162,6 @@ int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, int v_retval, u8 *msg, u16 msglen) { struct idpf_ctlq_msg ctlq_msg = { 0 }; - struct idpf_dma_mem dma_mem = { 0 }; int status; ctlq_msg.opcode = idpf_mbq_opc_send_msg_to_pf; @@ -162,19 +171,11 @@ int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode, ctlq_msg.cookie.mbx.chnl_opcode = v_opcode; if (msglen > 0) { - dma_mem.va = (struct idpf_dma_mem *) - idpf_alloc_dma_mem(hw, &dma_mem, msglen); - if (!dma_mem.va) - return -ENOMEM; - - idpf_memcpy(dma_mem.va, msg, msglen, IDPF_NONDMA_TO_DMA); - ctlq_msg.ctx.indirect.payload = &dma_mem; + idpf_memcpy(send_dma_mem.va, msg, msglen, IDPF_NONDMA_TO_DMA); + ctlq_msg.ctx.indirect.payload = &send_dma_mem; } status = idpf_ctlq_send(hw, hw->asq, 1, &ctlq_msg); - if (dma_mem.va) - idpf_free_dma_mem(hw, &dma_mem); - return status; } @@ -262,6 +263,9 @@ int idpf_clean_arq_element(struct idpf_hw *hw, */ int idpf_deinit_hw(struct idpf_hw *hw) { + if (send_dma_mem.va) + idpf_free_dma_mem(hw, &send_dma_mem); + hw->asq = NULL; hw->arq = NULL; From patchwork Thu Apr 13 09:44:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126014 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8088E42931; Thu, 13 Apr 2023 11:51:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 178DB42D4A; Thu, 13 Apr 2023 11:50:37 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id CDEE942D17 for ; Thu, 13 Apr 2023 11:50:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379435; x=1712915435; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nftYXJRt8xSIivMQRbHgwM2xsehu6fv/EHzLlFe3dOc=; b=mGz4RgEU42pfl/h6rICFC9iMqB0AFP8u5dJ5CZFM4/ktxOfctVGjzjvC LYelmG00DmgLB7CESS/rtIqLdmfgKDu/wJTNlzqtGt2DPtksVgtITR1Do P4MUPomqGjJxZkSe4Q8p5d+0tJIJgIs6X01i+7IAg5VPdG92y47Lbqloo kes9haWXqkEIfJI5eV6BCo8Ax1+vfKwZXy0iE1jpn/+l0JeRRVCfz+bPJ 3aRY2p7Nv0Ajy6DMm/uk9Hy0gQn39ZfzWNJeBe89gf32RkbrXfpsyAkW+ fEIfb/RWYSa2ywCHxQ1QM8hsZUHyh8mqSkVwtZB3imwJZf3Pj3iotzL68 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290513" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290513" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699341" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699341" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:31 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Piotr Gardocki Subject: [PATCH 12/18] common/idpf: add SyncE support over VF Date: Thu, 13 Apr 2023 05:44:56 -0400 Message-Id: <20230413094502.1714755-13-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch enables to VF access to all SyncE related operations. Most of the opcodes in this implementation map directly to the AQ commands. Additionally there is a VIRTCHNL_OP_SYNCE_GET_HW_INFO opcode which should be used by VF to discover all hardware related details required for Synce operations. The goal of this implementation is to provide device agnostic interface to the VF, but due to the feature design the VF will get the minimum HW details via VIRTCHNL_OP_SYNCE_GET_HW_INFO opcode. Signed-off-by: Piotr Gardocki Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl.h | 582 ++++++++++++++++++++++++++++ 1 file changed, 582 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h index 3008802c4a..54d66c4913 100644 --- a/drivers/common/idpf/base/virtchnl.h +++ b/drivers/common/idpf/base/virtchnl.h @@ -184,6 +184,19 @@ enum virtchnl_ops { VIRTCHNL_OP_CONFIG_QUANTA = 113, VIRTCHNL_OP_FLOW_SUBSCRIBE = 114, VIRTCHNL_OP_FLOW_UNSUBSCRIBE = 115, + VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT = 116, + VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT = 117, + VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO = 118, + VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO = 119, + VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG = 120, + VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG = 121, + VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG = 122, + VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG = 123, + VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES = 124, + VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS = 125, + VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG = 126, + VIRTCHNL_OP_SYNCE_GET_CGU_INFO = 127, + VIRTCHNL_OP_SYNCE_GET_HW_INFO = 128, VIRTCHNL_OP_MAX, }; @@ -294,6 +307,32 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode) return "VIRTCHNL_OP_1588_PTP_SET_PIN_CFG"; case VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP: return "VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP"; + case VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT: + return "VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT"; + case VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT: + return "VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT"; + case VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO: + return "VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO"; + case VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO: + return "VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO"; + case VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG: + return "VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG"; + case VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG: + return "VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG"; + case VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG: + return "VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG"; + case VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG: + return "VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG"; + case VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES: + return "VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES"; + case VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS: + return "VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS"; + case VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG: + return "VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG"; + case VIRTCHNL_OP_SYNCE_GET_CGU_INFO: + return "VIRTCHNL_OP_SYNCE_GET_CGU_INFO"; + case VIRTCHNL_OP_SYNCE_GET_HW_INFO: + return "VIRTCHNL_OP_SYNCE_GET_HW_INFO"; case VIRTCHNL_OP_ENABLE_QUEUES_V2: return "VIRTCHNL_OP_ENABLE_QUEUES_V2"; case VIRTCHNL_OP_DISABLE_QUEUES_V2: @@ -2065,6 +2104,19 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); * VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS * VIRTCHNL_OP_1588_PTP_SET_PIN_CFG * VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP + * VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT + * VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT + * VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO + * VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO + * VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG + * VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG + * VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG + * VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG + * VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES + * VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS + * VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG + * VIRTCHNL_OP_SYNCE_GET_CGU_INFO + * VIRTCHNL_OP_SYNCE_GET_HW_INFO * * Support for offloading control of the device PTP hardware clock (PHC) is enabled * by VIRTCHNL_VF_CAP_PTP. This capability allows a VF to request that PF @@ -2085,6 +2137,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); #define VIRTCHNL_1588_PTP_CAP_WRITE_PHC BIT(3) #define VIRTCHNL_1588_PTP_CAP_PHC_REGS BIT(4) #define VIRTCHNL_1588_PTP_CAP_PIN_CFG BIT(5) +#define VIRTCHNL_1588_PTP_CAP_SYNCE BIT(6) /** * virtchnl_phc_regs @@ -2222,6 +2275,11 @@ enum virtchnl_ptp_tstamp_format { * input to timestamp external events, or as an output to cause a periodic * signal output. * + * VIRTCHNL_1588_PTP_CAP_SYNCE indicates that the VF has access to SyncE related + * capabilities. The first command the VF should issue is the + * VIRTCHNL_OP_SYNCE_GET_HW_INFO. It returns to VF all required HW details + * needed for further processing. + * * Note that in the future, additional capability flags may be added which * indicate additional extended support. All fields marked as reserved by this * header will be set to zero. VF implementations should verify this to ensure @@ -2600,6 +2658,494 @@ struct virtchnl_phc_ext_tstamp { VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_phc_ext_tstamp); +/** + * virtchnl_synce_get_phy_rec_clk_out + * @phy_output: PHY reference clock output pin + * @port_num: Port number + * @flags: PHY flags + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT. This command reads + * the mapping of the Ethernet lanes to the recovered clocks. The request is + * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability + * with PF. + * + * The VF driver sets phy_output to choose CGU pin. In response the PF driver + * sends the same structure with the same opcode. + * + * The VF driver can also set port_num to 0xFF to check if the PHY output is + * driven by the PF that sends that command. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_phy_rec_clk_out { + u8 phy_output; + u8 port_num; +#define VIRTCHNL_GET_PHY_REC_CLK_OUT_CURR_PORT 0xFF + u8 flags; +#define VIRTCHNL_GET_PHY_REC_CLK_OUT_OUT_EN BIT(0) + u8 rsvd[13]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_phy_rec_clk_out); + +/** + * virtchnl_synce_set_phy_rec_clk_out + * @phy_output: PHY reference clock output pin + * @enable: GPIO state to be applied + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT. The command maps + * any of the four Ethernet lanes (PHY Port number) onto the two recovered + * clocks (Phy output). The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver specifies either SCL or SDA pin in phy_output and whether to + * enable(1) or disable(0) the given pin in enable variable. + * In response the PF driver sends back the same structure with the same opcode. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_set_phy_rec_clk_out { + u8 phy_output; + u8 enable; + u8 rsvd[14]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_phy_rec_clk_out); + +/** + * virtchnl_synce_get_cgu_ref_prio + * @dpll_num: DPLL index + * @ref_idx: Reference pin index + * @ref_priority: Reference input priority + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO. The command reads + * the currently configured priority of the selected reference clock for a given + * DPLL block within a given Clock Controller (DPLL) node. The request is + * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability + * with PF. + * + * The VF driver should set dpll_num and ref_idx to choose the pin for which + * the ref_priority will be returned. In response the PF driver sends the same + * structure with the same opcode with ref_priority filled. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_cgu_ref_prio { + u8 dpll_num; + u8 ref_idx; + u8 ref_priority; + u8 rsvd[13]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_cgu_ref_prio); + +/** + * virtchnl_synce_set_cgu_ref_prio + * @dpll_num: DPLL index + * @ref_idx: Reference pin index + * @ref_priority: Reference input priority + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO. The command + * configures the priority of the selected Input Index within a given DPLL block + * of CCU node. The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver should set dpll_num and ref_idx to choose the pin and + * ref_priority to be applied to given pin. In response the PF driver sends the + * same structure with the same opcode. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_set_cgu_ref_prio { + u8 dpll_num; + u8 ref_idx; + u8 ref_priority; + u8 rsvd[13]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_cgu_ref_prio); + +/** + * virtchnl_synce_get_input_pin_cfg + * @freq: Frequency of the reference clock input + * @phase_delay: Phase compensation for the reference clock input + * @input_idx: CGU pin index + * @status: Status flags + * @type: Input type flags + * @flags1: First set of flags + * @flags2: Second set of flags + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG. The command reads + * the current configuration of the specified reference clock input of a given + * Clock Controller (DPLL) node. The request is acceptable only when VF + * negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver should set input_idx to choose CGU pin for which the + * configuration will be returned. In response the PF driver sends the same + * structure with the same opcode with the remaining fields filled. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_input_pin_cfg { + u32 freq; + u32 phase_delay; + u8 input_idx; + u8 status; +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_LOS BIT(0) +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_SCM_FAIL BIT(1) +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_CFM_FAIL BIT(2) +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_GST_FAIL BIT(3) +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_PFM_FAIL BIT(4) +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL BIT(6) +#define VIRTCHNL_GET_CGU_IN_CFG_STATUS_ESYNC_CAP BIT(7) + u8 type; +#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_READ_ONLY BIT(0) +#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_GPS BIT(4) +#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_EXTERNAL BIT(5) +#define VIRTCHNL_GET_CGU_IN_CFG_TYPE_PHY BIT(6) + u8 flags1; +#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP BIT(0) +#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_1PPS_SUPP BIT(2) +#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP BIT(3) +#define VIRTCHNL_GET_CGU_IN_CFG_FLG1_ANYFREQ BIT(7) + u8 flags2; +#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) +#define VIRTCHNL_GET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) + u8 rsvd[3]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_input_pin_cfg); + +/** + * virtchnl_synce_set_input_pin_cfg + * @freq: Frequency of the reference clock input + * @phase_delay: Phase compensation for the reference clock input + * @input_idx: CGU pin index + * @flags1: First set of flags + * @flags2: Second set of flags + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG. The command + * configures the specified reference clock input of a given Clock Controller + * (DPLL) node. The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver should set input_idx to choose CGU pin and the rest of fields + * according to the required configuration. In response the PF driver sends the + * same structure with the same opcode. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_set_input_pin_cfg { + u32 freq; + u32 phase_delay; + u8 input_idx; + u8 flags1; +#define VIRTCHNL_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ BIT(6) +#define VIRTCHNL_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY BIT(7) + u8 flags2; +#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_INPUT_EN BIT(5) +#define VIRTCHNL_SET_CGU_IN_CFG_FLG2_ESYNC_EN BIT(6) + u8 rsvd[5]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_input_pin_cfg); + +/** + * virtchnl_synce_get_output_pin_cfg + * @freq: Output frequency + * @src_freq: Source frequency + * @output_idx: Output pin index + * @flags: Output flags + * @src_sel: Internal DPLL source + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG. The command reads + * the current frequency, phase compensation and embedded sync configuration + * of the specified clock output of a given Clock Controller (DPLL) node. + * The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver should set output_idx to choose CGU pin and the rest of fields + * according to the required configuration. In response the PF driver sends the + * same structure with the same opcode. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_output_pin_cfg { + u32 freq; + u32 src_freq; + u8 output_idx; + u8 flags; +#define VIRTCHNL_GET_CGU_OUT_CFG_OUT_EN BIT(0) +#define VIRTCHNL_GET_CGU_OUT_CFG_ESYNC_EN BIT(1) +#define VIRTCHNL_GET_CGU_OUT_CFG_ESYNC_ABILITY BIT(2) + u8 src_sel; +#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT 0 +#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL \ + (0x1F << VIRTCHNL_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT) +#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT 5 +#define VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE \ + (0x7 << VIRTCHNL_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT) + u8 rsvd[5]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_output_pin_cfg); + +/** + * virtchnl_synce_set_output_pin_cfg + * @freq: Output frequency + * @phase_delay: Output phase compensation + * @output_idx: Output pin index + * @flags: Output flags + * @src_sel: Internal DPLL source + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG. The command + * configures the specified reference clock input of a given Clock Controller + * (DPLL) node. The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver should set output_idx to choose CGU pin and the rest of fields + * according to the required configuration. In response the PF driver sends the + * same structure with the same opcode. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_set_output_pin_cfg { + u32 freq; + u32 phase_delay; + u8 output_idx; + u8 flags; +#define VIRTCHNL_SET_CGU_OUT_CFG_OUT_EN BIT(0) +#define VIRTCHNL_SET_CGU_OUT_CFG_ESYNC_EN BIT(1) +#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_FREQ BIT(2) +#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_PHASE BIT(3) +#define VIRTCHNL_SET_CGU_OUT_CFG_UPDATE_SRC_SEL BIT(4) + u8 src_sel; +#define VIRTCHNL_SET_CGU_OUT_CFG_DPLL_SRC_SEL 0x1F + u8 rsvd[5]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_output_pin_cfg); + +/** + * virtchnl_synce_get_cgu_abilities + * @num_inputs: Number of Clock Controller inputs + * @num_outputs: Number of Clock Controller outputs + * @pps_dpll_idx: The index of a PPS DPLL block in the CCU + * @synce_dpll_idx: The index of a SyncE DPLL block in the CCU + * @max_in_freq: Maximum Input Frequency + * @max_in_phase_adj: Maximum Input Phase Adjustment + * @max_out_freq: Maximum Output Frequency + * @max_out_phase_adj: Maximum Output Phase Adjustment + * @cgu_part_num: Clock Controller Part Number + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES. The command reads + * the capabilities of the CC. If the value is not defined or cannot be + * evaluated, then it shall be 0xFF for 8-bit fields and 0xFFFFFFFF for 32-bit + * fields. The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * The VF driver sends an empty message to the PF driver. In response the PF + * driver sends the virtchnl_synce_get_cgu_abilities structure. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_cgu_abilities { + u8 num_inputs; + u8 num_outputs; + u8 pps_dpll_idx; + u8 synce_dpll_idx; + u32 max_in_freq; + u32 max_in_phase_adj; + u32 max_out_freq; + u32 max_out_phase_adj; + u8 cgu_part_num; + u8 rsvd[3]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_synce_get_cgu_abilities); + +/** + * virtchnl_synce_get_cgu_dpll_status + * @phase_offset: Phase offset in ns + * @dpll_state: DPLL state + * @dpll_num: DPLL index + * @ref_state: Reference clock state + * @eec_mode: EEC Mode - The configured clock quality level + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS. The command reads + * the selected DPLL block status within the selected CCU node. The request is + * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability + * with PF. + * + * The VF driver chooses in dpll_num which DPLL block it wants to read. + * In response the PF driver fills the remaining fields in structure and sends + * to VF with the same opcode. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_cgu_dpll_status { + s64 phase_offset; + u16 dpll_state; +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_LOCK BIT(0) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_HO BIT(1) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_HO_READY BIT(2) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_FLHIT BIT(5) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_PSLHIT BIT(7) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT 8 +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SEL \ + (0x1F << VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT 13 +#define VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE \ + (0x7 << VIRTCHNL_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT) + u8 dpll_num; + u8 ref_state; +#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_LOS BIT(0) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_SCM BIT(1) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_CFM BIT(2) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_GST BIT(3) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_PFM BIT(4) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_FAST_LOCK_EN BIT(5) +#define VIRTCHNL_GET_CGU_DPLL_STATUS_REF_SW_ESYNC BIT(6) + u8 eec_mode; +#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_1 0xA +#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_2 0xB +#define VIRTCHNL_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN 0xF + u8 rsvd[11]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_synce_get_cgu_dpll_status); + +/** + * virtchnl_synce_set_cgu_dpll_config + * @dpll_num: DPLL index + * @ref_state: Reference clock state + * @config: DPLL config + * @eec_mode: EEC Mode - The configured clock quality level + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG. The command + * configures the selected DPLL block within the selected CCU node. The request + * is acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE + * capability with PF. + * + * The VF driver chooses in dpll_num which DPLL block it wants to configure. + * The PF driver applies the given configuration and returns unchanged structure + * to the VF. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_set_cgu_dpll_config { + u8 dpll_num; + u8 ref_state; +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_LOS BIT(0) +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_SCM BIT(1) +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_CFM BIT(2) +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_GST BIT(3) +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_PFM BIT(4) +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN BIT(5) +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC BIT(6) + u8 config; +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_CLK_REF_SEL 0x1F +#define VIRTCHNL_SET_CGU_DPLL_CONFIG_MODE (0x7 << 5) + u8 eec_mode; + u8 rsvd[12]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_set_cgu_dpll_config); + +/** + * virtchnl_synce_get_cgu_info + * @cgu_id: CGU ID + * @cgu_cfg_ver: CGU config version + * @cgu_fw_ver: CGU firmware version + * @rsvd: Reserved for future extension + * + * Structure sent with VIRTCHNL_OP_SYNCE_GET_CGU_INFO. The command retrieves + * information about CCU. If parameter is unsupported, then it should contain + * 0xFFFFFFFF for 32-bit values or 0xFF for 8-bit values. The request is + * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_SYNCE capability + * with PF. + * + * The VF driver sends an empty message to the PF driver. In response the PF + * driver sends the virtchnl_synce_get_cgu_info structure. + * + * If the Admin Queue command returns an error the PF will return + * VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR with unchanged structure to VF. + */ +struct virtchnl_synce_get_cgu_info { + u32 cgu_id; + u32 cgu_cfg_ver; + u32 cgu_fw_ver; + u8 rsvd[4]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_synce_get_cgu_info); + +/** + * virtchnl_cgu_pin + * @pin_index: Pin index to use in all functions + * @name: Human readable pin name + * + * Structure used as a part of VIRTCHNL_OP_SYNCE_GET_HW_INFO request. + * The VF issues a VIRTCHNL_OP_SYNCE_GET_HW_INFO request to the PF in + * order to obtain the list of available CGU pins. + */ +struct virtchnl_cgu_pin { + u8 pin_index; + char name[63]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(64, virtchnl_cgu_pin); + +/** + * virtchnl_synce_get_hw_info + * @cgu_present: True if CGU is present + * @rclk_present: True is PHY recovered clock is present + * @c827_idx: C827 index for the current port + * @len: Length of the variable CGU pins array + * @rsvd: Reserved for future extension + * @pins: Variable length CGU pins array + * + * Variable structure sent by the PF in reply to VIRTCHNL_OP_SYNCE_GET_HW_INFO. + * The VF does not send this structure with its request of the operation. + * The request is acceptable only when VF negotiated + * VIRTCHNL_1588_PTP_CAP_SYNCE capability with PF. + * + * If this opcode returns error status the VF should assume it does not have + * access to any other SyncE commands. + */ +struct virtchnl_synce_get_hw_info { + u8 cgu_present; + u8 rclk_present; + u8 c827_idx; + u8 len; + u8 rsvd[4]; + struct virtchnl_cgu_pin pins[1]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_synce_get_hw_info); + /* Since VF messages are limited by u16 size, precalculate the maximum possible * values of nested elements in virtchnl structures that virtual channel can * possibly handle in a single message. @@ -2918,6 +3464,42 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, case VIRTCHNL_OP_1588_PTP_EXT_TIMESTAMP: valid_len = sizeof(struct virtchnl_phc_ext_tstamp); break; + case VIRTCHNL_OP_SYNCE_GET_PHY_REC_CLK_OUT: + valid_len = sizeof(struct virtchnl_synce_get_phy_rec_clk_out); + break; + case VIRTCHNL_OP_SYNCE_SET_PHY_REC_CLK_OUT: + valid_len = sizeof(struct virtchnl_synce_set_phy_rec_clk_out); + break; + case VIRTCHNL_OP_SYNCE_GET_CGU_REF_PRIO: + valid_len = sizeof(struct virtchnl_synce_get_cgu_ref_prio); + break; + case VIRTCHNL_OP_SYNCE_SET_CGU_REF_PRIO: + valid_len = sizeof(struct virtchnl_synce_set_cgu_ref_prio); + break; + case VIRTCHNL_OP_SYNCE_GET_INPUT_PIN_CFG: + valid_len = sizeof(struct virtchnl_synce_get_input_pin_cfg); + break; + case VIRTCHNL_OP_SYNCE_SET_INPUT_PIN_CFG: + valid_len = sizeof(struct virtchnl_synce_set_input_pin_cfg); + break; + case VIRTCHNL_OP_SYNCE_GET_OUTPUT_PIN_CFG: + valid_len = sizeof(struct virtchnl_synce_get_output_pin_cfg); + break; + case VIRTCHNL_OP_SYNCE_SET_OUTPUT_PIN_CFG: + valid_len = sizeof(struct virtchnl_synce_set_output_pin_cfg); + break; + case VIRTCHNL_OP_SYNCE_GET_CGU_ABILITIES: + break; + case VIRTCHNL_OP_SYNCE_GET_CGU_DPLL_STATUS: + valid_len = sizeof(struct virtchnl_synce_get_cgu_dpll_status); + break; + case VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG: + valid_len = sizeof(struct virtchnl_synce_set_cgu_dpll_config); + break; + case VIRTCHNL_OP_SYNCE_GET_CGU_INFO: + break; + case VIRTCHNL_OP_SYNCE_GET_HW_INFO: + break; case VIRTCHNL_OP_ENABLE_QUEUES_V2: case VIRTCHNL_OP_DISABLE_QUEUES_V2: valid_len = sizeof(struct virtchnl_del_ena_dis_queues); From patchwork Thu Apr 13 09:44:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126015 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCE4042931; Thu, 13 Apr 2023 11:51:49 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF4A342D3C; Thu, 13 Apr 2023 11:50:40 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 34F6342D3C for ; Thu, 13 Apr 2023 11:50:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379438; x=1712915438; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SXo7/Pjj7jQW2OleKGH8O2pr2IQLIl9HMg3yjKXI2e4=; b=TmhIw8xosvtdP+lcpvIdw+4O9U5HbRcujG8NUyGPUGlXCzTORpAZtCAb XQexYVQOpda0p3gLXG4GZqXb7a+/jmHdgD1ufNsluIbgT4f1Rd4SXX3Fk vo9rpWO31sFOU7eiAGW7g9UdnB+uC+IHUCypQEAuBjnQKxK8l1vXXrI0r XeI1hy8NUdrwozuL7sSd4/K+yVBwo2lge83y7PeSosTq88Y9sxxu/8wuW hbB/7Q6JTRi9gD/UYOKefhMPk0tO95ztqpQORJ8sZTo2k9M397Vip4UHw w47p8ffqMwBVkd949cw/O/YXteEHaIHiSPRZHhCqhja7OONWNh19p0eDk w==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290528" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290528" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699351" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699351" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:34 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Priyalee Kushwaha Subject: [PATCH 13/18] common/idpf: replace MAKEMASK to IDPF_M Date: Thu, 13 Apr 2023 05:44:57 -0400 Message-Id: <20230413094502.1714755-14-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Replace MAKEMASK to IDPF_M to avoid conflicts with MAKEMASK redefinition from various subcomponents. Signed-off-by: Priyalee Kushwaha Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.h | 3 -- drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 +++++------ drivers/common/idpf/base/idpf_lan_txrx.h | 46 +++++++++---------- drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +++---- drivers/common/idpf/base/idpf_osdep.h | 2 + drivers/common/idpf/base/idpf_type.h | 2 - drivers/common/idpf/base/virtchnl2_lan_desc.h | 28 +++++------ 7 files changed, 60 insertions(+), 63 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h index e7b0d803b3..47bffcf79f 100644 --- a/drivers/common/idpf/base/idpf_controlq.h +++ b/drivers/common/idpf/base/idpf_controlq.h @@ -97,9 +97,6 @@ struct idpf_ctlq_desc { #define IDPF_CTLQ_FLAG_VFC BIT(IDPF_CTLQ_FLAG_VFC_S) /* 0x800 */ #define IDPF_CTLQ_FLAG_BUF BIT(IDPF_CTLQ_FLAG_BUF_S) /* 0x1000 */ -/* Host ID is a special field that has 3b and not a 1b flag */ -#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S) - struct idpf_mbxq_desc { u8 pad[8]; /* CTLQ flags/opcode/len/retval fields */ u32 chnl_opcode; /* avoid confusion with desc->opcode */ diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 7f731ec3d6..1c665d1f3b 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -24,7 +24,7 @@ #define PF_FW_ARQBAH (PF_FW_BASE + 0x4) #define PF_FW_ARQLEN (PF_FW_BASE + 0x8) #define PF_FW_ARQLEN_ARQLEN_S 0 -#define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) +#define PF_FW_ARQLEN_ARQLEN_M IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S) #define PF_FW_ARQLEN_ARQVFE_S 28 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S) #define PF_FW_ARQLEN_ARQOVFL_S 29 @@ -35,14 +35,14 @@ #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) #define PF_FW_ARQH (PF_FW_BASE + 0xC) #define PF_FW_ARQH_ARQH_S 0 -#define PF_FW_ARQH_ARQH_M MAKEMASK(0x1FFF, PF_FW_ARQH_ARQH_S) +#define PF_FW_ARQH_ARQH_M IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S) #define PF_FW_ARQT (PF_FW_BASE + 0x10) #define PF_FW_ATQBAL (PF_FW_BASE + 0x14) #define PF_FW_ATQBAH (PF_FW_BASE + 0x18) #define PF_FW_ATQLEN (PF_FW_BASE + 0x1C) #define PF_FW_ATQLEN_ATQLEN_S 0 -#define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, PF_FW_ATQLEN_ATQLEN_S) +#define PF_FW_ATQLEN_ATQLEN_M IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S) #define PF_FW_ATQLEN_ATQVFE_S 28 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S) #define PF_FW_ATQLEN_ATQOVFL_S 29 @@ -53,7 +53,7 @@ #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) #define PF_FW_ATQH (PF_FW_BASE + 0x20) #define PF_FW_ATQH_ATQH_S 0 -#define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, PF_FW_ATQH_ATQH_S) +#define PF_FW_ATQH_ATQH_M IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S) #define PF_FW_ATQT (PF_FW_BASE + 0x24) /* Interrupts */ @@ -66,7 +66,7 @@ #define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2 #define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S) #define PF_GLINT_DYN_CTL_ITR_INDX_S 3 -#define PF_GLINT_DYN_CTL_ITR_INDX_M MAKEMASK(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) +#define PF_GLINT_DYN_CTL_ITR_INDX_M IDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S) #define PF_GLINT_DYN_CTL_INTERVAL_S 5 #define PF_GLINT_DYN_CTL_INTERVAL_M BIT(PF_GLINT_DYN_CTL_INTERVAL_S) #define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 @@ -86,13 +86,13 @@ #define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000)) #define PF_GLINT_ITR_MAX_INDEX 2 #define PF_GLINT_ITR_INTERVAL_S 0 -#define PF_GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S) +#define PF_GLINT_ITR_INTERVAL_M IDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S) /* Timesync registers */ #define PF_TIMESYNC_BASE 0x08404000 #define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE) #define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0 -#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M MAKEMASK(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) +#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M IDPF_M(0x3, PF_GLTSYN_CMD_SYNC_EXEC_CMD_S) #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2 #define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S) #define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4) @@ -104,23 +104,23 @@ /* Generic registers */ #define PF_INT_DIR_OICR_ENA 0x08406000 #define PF_INT_DIR_OICR_ENA_S 0 -#define PF_INT_DIR_OICR_ENA_M MAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) +#define PF_INT_DIR_OICR_ENA_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_ENA_S) #define PF_INT_DIR_OICR 0x08406004 #define PF_INT_DIR_OICR_TSYN_EVNT 0 #define PF_INT_DIR_OICR_PHY_TS_0 BIT(1) #define PF_INT_DIR_OICR_PHY_TS_1 BIT(2) #define PF_INT_DIR_OICR_CAUSE 0x08406008 #define PF_INT_DIR_OICR_CAUSE_CAUSE_S 0 -#define PF_INT_DIR_OICR_CAUSE_CAUSE_M MAKEMASK(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) +#define PF_INT_DIR_OICR_CAUSE_CAUSE_M IDPF_M(0xFFFFFFFF, PF_INT_DIR_OICR_CAUSE_CAUSE_S) #define PF_INT_PBA_CLEAR 0x0840600C #define PF_FUNC_RID 0x08406010 #define PF_FUNC_RID_FUNCTION_NUMBER_S 0 -#define PF_FUNC_RID_FUNCTION_NUMBER_M MAKEMASK(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) +#define PF_FUNC_RID_FUNCTION_NUMBER_M IDPF_M(0x7, PF_FUNC_RID_FUNCTION_NUMBER_S) #define PF_FUNC_RID_DEVICE_NUMBER_S 3 -#define PF_FUNC_RID_DEVICE_NUMBER_M MAKEMASK(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) +#define PF_FUNC_RID_DEVICE_NUMBER_M IDPF_M(0x1F, PF_FUNC_RID_DEVICE_NUMBER_S) #define PF_FUNC_RID_BUS_NUMBER_S 8 -#define PF_FUNC_RID_BUS_NUMBER_M MAKEMASK(0xFF, PF_FUNC_RID_BUS_NUMBER_S) +#define PF_FUNC_RID_BUS_NUMBER_M IDPF_M(0xFF, PF_FUNC_RID_BUS_NUMBER_S) /* Reset registers */ #define PFGEN_RTRIG 0x08407000 @@ -132,7 +132,7 @@ #define PFGEN_RTRIG_IMCR_M BIT(2) #define PFGEN_RSTAT 0x08407008 /* PFR Status */ #define PFGEN_RSTAT_PFR_STATE_S 0 -#define PFGEN_RSTAT_PFR_STATE_M MAKEMASK(0x3, PFGEN_RSTAT_PFR_STATE_S) +#define PFGEN_RSTAT_PFR_STATE_M IDPF_M(0x3, PFGEN_RSTAT_PFR_STATE_S) #define PFGEN_CTRL 0x0840700C #define PFGEN_CTRL_PFSWR BIT(0) diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 98484b267c..82742857be 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -68,9 +68,9 @@ enum idpf_rss_hash { #define IDPF_TXD_COMPLQ_GEN_M BIT_ULL(IDPF_TXD_COMPLQ_GEN_S) #define IDPF_TXD_COMPLQ_COMPL_TYPE_S 11 #define IDPF_TXD_COMPLQ_COMPL_TYPE_M \ - MAKEMASK(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) + IDPF_M(0x7UL, IDPF_TXD_COMPLQ_COMPL_TYPE_S) #define IDPF_TXD_COMPLQ_QID_S 0 -#define IDPF_TXD_COMPLQ_QID_M MAKEMASK(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) +#define IDPF_TXD_COMPLQ_QID_M IDPF_M(0x3FFUL, IDPF_TXD_COMPLQ_QID_S) /* For base mode TX descriptors */ @@ -100,29 +100,29 @@ enum idpf_rss_hash { #define IDPF_TXD_CTX_QW1_MSS_S 50 #define IDPF_TXD_CTX_QW1_MSS_M \ - MAKEMASK(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) + IDPF_M(0x3FFFULL, IDPF_TXD_CTX_QW1_MSS_S) #define IDPF_TXD_CTX_QW1_TSO_LEN_S 30 #define IDPF_TXD_CTX_QW1_TSO_LEN_M \ - MAKEMASK(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) + IDPF_M(0x3FFFFULL, IDPF_TXD_CTX_QW1_TSO_LEN_S) #define IDPF_TXD_CTX_QW1_CMD_S 4 #define IDPF_TXD_CTX_QW1_CMD_M \ - MAKEMASK(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) + IDPF_M(0xFFFUL, IDPF_TXD_CTX_QW1_CMD_S) #define IDPF_TXD_CTX_QW1_DTYPE_S 0 #define IDPF_TXD_CTX_QW1_DTYPE_M \ - MAKEMASK(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) + IDPF_M(0xFUL, IDPF_TXD_CTX_QW1_DTYPE_S) #define IDPF_TXD_QW1_L2TAG1_S 48 #define IDPF_TXD_QW1_L2TAG1_M \ - MAKEMASK(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) + IDPF_M(0xFFFFULL, IDPF_TXD_QW1_L2TAG1_S) #define IDPF_TXD_QW1_TX_BUF_SZ_S 34 #define IDPF_TXD_QW1_TX_BUF_SZ_M \ - MAKEMASK(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) + IDPF_M(0x3FFFULL, IDPF_TXD_QW1_TX_BUF_SZ_S) #define IDPF_TXD_QW1_OFFSET_S 16 #define IDPF_TXD_QW1_OFFSET_M \ - MAKEMASK(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) + IDPF_M(0x3FFFFULL, IDPF_TXD_QW1_OFFSET_S) #define IDPF_TXD_QW1_CMD_S 4 -#define IDPF_TXD_QW1_CMD_M MAKEMASK(0xFFFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_TXD_QW1_CMD_M IDPF_M(0xFFFUL, IDPF_TXD_QW1_CMD_S) #define IDPF_TXD_QW1_DTYPE_S 0 -#define IDPF_TXD_QW1_DTYPE_M MAKEMASK(0xFUL, IDPF_TXD_QW1_DTYPE_S) +#define IDPF_TXD_QW1_DTYPE_M IDPF_M(0xFUL, IDPF_TXD_QW1_DTYPE_S) /* TX Completion Descriptor Completion Types */ #define IDPF_TXD_COMPLT_ITR_FLUSH 0 @@ -173,10 +173,10 @@ enum idpf_tx_desc_len_fields { IDPF_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ }; -#define IDPF_TXD_QW1_MACLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) -#define IDPF_TXD_QW1_IPLEN_M MAKEMASK(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) -#define IDPF_TXD_QW1_L4LEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) -#define IDPF_TXD_QW1_FCLEN_M MAKEMASK(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_MACLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_MACLEN_S) +#define IDPF_TXD_QW1_IPLEN_M IDPF_M(0x7FUL, IDPF_TX_DESC_LEN_IPLEN_S) +#define IDPF_TXD_QW1_L4LEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) +#define IDPF_TXD_QW1_FCLEN_M IDPF_M(0xFUL, IDPF_TX_DESC_LEN_L4_LEN_S) enum idpf_tx_base_desc_cmd_bits { IDPF_TX_DESC_CMD_EOP = 0x0001, @@ -244,9 +244,9 @@ struct idpf_flex_tx_desc { __le16 cmd_dtype; #define IDPF_FLEX_TXD_QW1_DTYPE_S 0 #define IDPF_FLEX_TXD_QW1_DTYPE_M \ - MAKEMASK(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) + IDPF_M(0x1FUL, IDPF_FLEX_TXD_QW1_DTYPE_S) #define IDPF_FLEX_TXD_QW1_CMD_S 5 -#define IDPF_FLEX_TXD_QW1_CMD_M MAKEMASK(0x7FFUL, IDPF_TXD_QW1_CMD_S) +#define IDPF_FLEX_TXD_QW1_CMD_M IDPF_M(0x7FFUL, IDPF_TXD_QW1_CMD_S) union { /* DTYPE = IDPF_TX_DESC_DTYPE_FLEX_DATA_(0x03) */ u8 raw[4]; @@ -388,9 +388,9 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_MSS_RT_0 0 #define IDPF_TXD_FLEX_CTX_MSS_RT_M 0x3FFF #define IDPF_TXD_FLEX_CTX_FTYPE_S 14 -#define IDPF_TXD_FLEX_CTX_FTYPE_VF MAKEMASK(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) -#define IDPF_TXD_FLEX_CTX_FTYPE_PF MAKEMASK(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VF IDPF_M(0x0, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_VDEV IDPF_M(0x1, IDPF_TXD_FLEX_CTX_FTYPE_S) +#define IDPF_TXD_FLEX_CTX_FTYPE_PF IDPF_M(0x2, IDPF_TXD_FLEX_CTX_FTYPE_S) u8 hdr_len; u8 ptag; } tso; @@ -407,10 +407,10 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_PASID_M 0xFFFFF #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID_S 36 #define IDPF_TXD_FLEX_CTX_QW1_PASID_VALID \ - MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) + IDPF_M(0x1, IDPF_TXD_FLEX_CTX_PASID_VALID_S) #define IDPF_TXD_FLEX_CTX_QW1_TPH_S 37 #define IDPF_TXD_FLEX_CTX_QW1_TPH \ - MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_TPH_S) + IDPF_M(0x1, IDPF_TXD_FLEX_CTX_TPH_S) #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_S 38 #define IDPF_TXD_FLEX_CTX_QW1_PFNUM_M 0xF /* The following are only valid for DTYPE = 0x09 and DTYPE = 0x0A */ @@ -418,7 +418,7 @@ struct idpf_flex_tx_hs_ctx_desc { #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_M 0x1FFFFF #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S 63 #define IDPF_TXD_FLEX_CTX_QW1_SAIDX_VALID \ - MAKEMASK(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) + IDPF_M(0x1, IDPF_TXD_FLEX_CTX_QW1_SAIDX_VAL_S) /* The following are only valid for DTYPE = 0x0D and DTYPE = 0x0E */ #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_S 48 #define IDPF_TXD_FLEX_CTX_QW1_FLEX0_M 0xFF diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index 13c5c5a7da..c8739fae7a 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -9,7 +9,7 @@ /* Reset */ #define VFGEN_RSTAT 0x00008800 #define VFGEN_RSTAT_VFR_STATE_S 0 -#define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, VFGEN_RSTAT_VFR_STATE_S) +#define VFGEN_RSTAT_VFR_STATE_M IDPF_M(0x3, VFGEN_RSTAT_VFR_STATE_S) /* Control(VF Mailbox) Queue */ #define VF_BASE 0x00006000 @@ -18,7 +18,7 @@ #define VF_ATQBAH (VF_BASE + 0x1800) #define VF_ATQLEN (VF_BASE + 0x0800) #define VF_ATQLEN_ATQLEN_S 0 -#define VF_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, VF_ATQLEN_ATQLEN_S) +#define VF_ATQLEN_ATQLEN_M IDPF_M(0x3FF, VF_ATQLEN_ATQLEN_S) #define VF_ATQLEN_ATQVFE_S 28 #define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S) #define VF_ATQLEN_ATQOVFL_S 29 @@ -29,14 +29,14 @@ #define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S) #define VF_ATQH (VF_BASE + 0x0400) #define VF_ATQH_ATQH_S 0 -#define VF_ATQH_ATQH_M MAKEMASK(0x3FF, VF_ATQH_ATQH_S) +#define VF_ATQH_ATQH_M IDPF_M(0x3FF, VF_ATQH_ATQH_S) #define VF_ATQT (VF_BASE + 0x2400) #define VF_ARQBAL (VF_BASE + 0x0C00) #define VF_ARQBAH (VF_BASE) #define VF_ARQLEN (VF_BASE + 0x2000) #define VF_ARQLEN_ARQLEN_S 0 -#define VF_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, VF_ARQLEN_ARQLEN_S) +#define VF_ARQLEN_ARQLEN_M IDPF_M(0x3FF, VF_ARQLEN_ARQLEN_S) #define VF_ARQLEN_ARQVFE_S 28 #define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S) #define VF_ARQLEN_ARQOVFL_S 29 @@ -47,7 +47,7 @@ #define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S) #define VF_ARQH (VF_BASE + 0x1400) #define VF_ARQH_ARQH_S 0 -#define VF_ARQH_ARQH_M MAKEMASK(0x1FFF, VF_ARQH_ARQH_S) +#define VF_ARQH_ARQH_M IDPF_M(0x1FFF, VF_ARQH_ARQH_S) #define VF_ARQT (VF_BASE + 0x1000) /* Transmit queues */ @@ -69,7 +69,7 @@ #define VF_INT_DYN_CTL0_INTENA_S 0 #define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S) #define VF_INT_DYN_CTL0_ITR_INDX_S 3 -#define VF_INT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) +#define VF_INT_DYN_CTL0_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTL0_ITR_INDX_S) #define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4)) #define VF_INT_DYN_CTLN_INTENA_S 0 @@ -79,7 +79,7 @@ #define VF_INT_DYN_CTLN_SWINT_TRIG_S 2 #define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S) #define VF_INT_DYN_CTLN_ITR_INDX_S 3 -#define VF_INT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) +#define VF_INT_DYN_CTLN_ITR_INDX_M IDPF_M(0x3, VF_INT_DYN_CTLN_ITR_INDX_S) #define VF_INT_DYN_CTLN_INTERVAL_S 5 #define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S) #define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24 @@ -104,7 +104,7 @@ #define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000)) #define VF_INT_ITRN_MAX_INDEX 2 #define VF_INT_ITRN_INTERVAL_S 0 -#define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S) +#define VF_INT_ITRN_INTERVAL_M IDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S) #define VF_INT_PBA_CLEAR 0x00008900 #define VF_INT_ICR0_ENA1 0x00005000 diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 99ae9cf60a..abcf68f1a2 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -45,6 +45,8 @@ typedef struct idpf_lock idpf_lock; #define low_16_bits(x) ((x) & 0xFFFF) #define high_16_bits(x) (((x) & 0xFFFF0000) >> 16) +#define IDPF_M(m, s) ((m) << (s)) + #ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 #endif diff --git a/drivers/common/idpf/base/idpf_type.h b/drivers/common/idpf/base/idpf_type.h index 3b46536287..2a97d32a8b 100644 --- a/drivers/common/idpf/base/idpf_type.h +++ b/drivers/common/idpf/base/idpf_type.h @@ -14,8 +14,6 @@ #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) -#define MAKEMASK(m, s) ((m) << (s)) - struct idpf_eth_stats { u64 rx_bytes; /* gorc */ u64 rx_unicast; /* uprc */ diff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h index b8cb22e474..0992cefc6c 100644 --- a/drivers/common/idpf/base/virtchnl2_lan_desc.h +++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h @@ -80,19 +80,19 @@ /* For splitq virtchnl2_rx_flex_desc_adv desc members */ #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_M \ - MAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S) + IDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_RXDID_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_M \ - MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S) + IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_PTYPE_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S 10 #define VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_M \ - MAKEMASK(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S) + IDPF_M(0x3UL, VIRTCHNL2_RX_FLEX_DESC_ADV_UMBCAST_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S 12 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_M \ - MAKEMASK(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S) + IDPF_M(0xFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF0_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M \ - MAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S) + IDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S 14 #define VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M \ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S) @@ -101,7 +101,7 @@ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S 0 #define VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_M \ - MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S) + IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_HDR_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S 10 #define VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_M \ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_RSC_S) @@ -110,7 +110,7 @@ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_SPH_S) #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_S 12 #define VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M \ - MAKEMASK(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M) + IDPF_M(0x7UL, VIRTCHNL2_RX_FLEX_DESC_ADV_FF1_M) #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S 15 #define VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_M \ BIT_ULL(VIRTCHNL2_RX_FLEX_DESC_ADV_MISS_S) @@ -159,12 +159,12 @@ /* for virtchnl2_rx_flex_desc.ptype_flex_flags0 member */ #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_S 0 #define VIRTCHNL2_RX_FLEX_DESC_PTYPE_M \ - MAKEMASK(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */ + IDPF_M(0x3FFUL, VIRTCHNL2_RX_FLEX_DESC_PTYPE_S) /* 10 bits */ /* for virtchnl2_rx_flex_desc.pkt_length member */ #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S 0 #define VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M \ - MAKEMASK(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */ + IDPF_M(0x3FFFUL, VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_S) /* 14 bits */ /* VIRTCHNL2_RX_FLEX_DESC_STATUS_ERROR_0_BITS * for singleq (flex) virtchnl2_rx_flex_desc @@ -212,19 +212,19 @@ BIT_ULL(VIRTCHNL2_RX_BASE_DESC_QW1_LEN_SPH_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S 52 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_M \ - MAKEMASK(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S) + IDPF_M(0x7FFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_HBUF_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S 38 #define VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_M \ - MAKEMASK(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S) + IDPF_M(0x3FFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_LEN_PBUF_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S 30 #define VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_M \ - MAKEMASK(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S) + IDPF_M(0xFFULL, VIRTCHNL2_RX_BASE_DESC_QW1_PTYPE_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S 19 #define VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_M \ - MAKEMASK(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S) + IDPF_M(0xFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_ERROR_S) #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S 0 #define VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_M \ - MAKEMASK(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S) + IDPF_M(0x7FFFFUL, VIRTCHNL2_RX_BASE_DESC_QW1_STATUS_S) /* VIRTCHNL2_RX_BASE_DESC_STATUS_BITS * for singleq (base) virtchnl2_rx_base_desc From patchwork Thu Apr 13 09:44:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126016 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3D0D42931; Thu, 13 Apr 2023 11:51:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0645742D59; Thu, 13 Apr 2023 11:50:42 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 1961942D3C for ; Thu, 13 Apr 2023 11:50:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379440; x=1712915440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m7L71LNAcB0rGYn4mU7lHqqtE+JbNMwIEM2IZ6gd2t8=; b=O/m05/w9gaKGu8r2f7i3k9ZmAOhtyRrmrtx2ZH+9m1+3xHxjTTI9Dyro iJuKhJeb0A1pdYmaECfXqBAFD/Q/ppJvK+n00+JayicEHZDmWQwH9HpPK fq7ZZcpNr5+dTJMbrz5BqjJmcHIarIoKMzKPzRI9aA1ETLzYRxE3Baqvd 6z4Men3zJkAMsk2n+xNU/ym672qwwvgkupIaqGNRfTbSFa7vfTlt7jVxo 7n0jziw8215OtrS9El8QSIT7C/Mu+g80SFg7M6m95CKHTetRB6oJko0wQ fUTo0wGM/K6VGdJ6l8QhDun1FqfXm0UvDPptwGkPttHQIh1C9fLhZjC4U Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290548" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290548" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699363" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699363" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:36 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Jun Zhang Subject: [PATCH 14/18] common/idpf: add GNSS support over VF Date: Thu, 13 Apr 2023 05:44:58 -0400 Message-Id: <20230413094502.1714755-15-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch enables VF access to GNSS Console I2C. Most of the opcodes in this implementation map directly to the AQ commands for GNSS Console I2C Read and Write for GNSS status, configuration, and NMEA messages. Additionally there is VF and PF negotiation on GNSS Access Capability through Extended PTP Capability Exchange. VF can access GNSS Console I2C only if Extended PTP Capability exchange indicates so. Signed-off-by: Jun Zhang Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl.h | 111 ++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h index 54d66c4913..4e9cf9fdeb 100644 --- a/drivers/common/idpf/base/virtchnl.h +++ b/drivers/common/idpf/base/virtchnl.h @@ -197,6 +197,8 @@ enum virtchnl_ops { VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG = 126, VIRTCHNL_OP_SYNCE_GET_CGU_INFO = 127, VIRTCHNL_OP_SYNCE_GET_HW_INFO = 128, + VIRTCHNL_OP_GNSS_READ_I2C = 129, + VIRTCHNL_OP_GNSS_WRITE_I2C = 130, VIRTCHNL_OP_MAX, }; @@ -333,6 +335,10 @@ static inline const char *virtchnl_op_str(enum virtchnl_ops v_opcode) return "VIRTCHNL_OP_SYNCE_GET_CGU_INFO"; case VIRTCHNL_OP_SYNCE_GET_HW_INFO: return "VIRTCHNL_OP_SYNCE_GET_HW_INFO"; + case VIRTCHNL_OP_GNSS_READ_I2C: + return "VIRTCHNL_OP_GNSS_READ_I2C"; + case VIRTCHNL_OP_GNSS_WRITE_I2C: + return "VIRTCHNL_OP_GNSS_WRITE_I2C"; case VIRTCHNL_OP_ENABLE_QUEUES_V2: return "VIRTCHNL_OP_ENABLE_QUEUES_V2"; case VIRTCHNL_OP_DISABLE_QUEUES_V2: @@ -2117,6 +2123,8 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); * VIRTCHNL_OP_SYNCE_SET_CGU_DPLL_CONFIG * VIRTCHNL_OP_SYNCE_GET_CGU_INFO * VIRTCHNL_OP_SYNCE_GET_HW_INFO + * VIRTCHNL_OP_GNSS_READ_I2C + * VIRTCHNL_OP_GNSS_WRITE_I2C * * Support for offloading control of the device PTP hardware clock (PHC) is enabled * by VIRTCHNL_VF_CAP_PTP. This capability allows a VF to request that PF @@ -2138,6 +2146,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); #define VIRTCHNL_1588_PTP_CAP_PHC_REGS BIT(4) #define VIRTCHNL_1588_PTP_CAP_PIN_CFG BIT(5) #define VIRTCHNL_1588_PTP_CAP_SYNCE BIT(6) +#define VIRTCHNL_1588_PTP_CAP_GNSS BIT(7) /** * virtchnl_phc_regs @@ -2280,6 +2289,10 @@ enum virtchnl_ptp_tstamp_format { * VIRTCHNL_OP_SYNCE_GET_HW_INFO. It returns to VF all required HW details * needed for further processing. * + * VIRTCHNL_1588_PTP_CAP_GNSS indicates that the VF has access to GNSS related + * capabilities, i.e. Access onboard GNSS Module (if present) through I2C GNSS + * console for GNSS Configuration, Status, and NMEA Messages. + * * Note that in the future, additional capability flags may be added which * indicate additional extended support. All fields marked as reserved by this * header will be set to zero. VF implementations should verify this to ensure @@ -3146,6 +3159,98 @@ struct virtchnl_synce_get_hw_info { VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_synce_get_hw_info); +/** + * virtchnl_link_topo_params + * @lport_num: link port number + * @lport_num_valid: link port number validity + * @node_type_ctx: node type & context + * @index: node index + * + * Structure used as part of virtchnl_link_topo_addr with gnss I2C read or write + * request. VF sets this structure field for GNSS I2C console Node, PF passes it + * on to AdminQ. + */ +struct virtchnl_link_topo_params { + u8 lport_num; + u8 lport_num_valid; + u8 node_type_ctx; +#define VIRTCHNL_LINK_TOPO_NODE_TYPE_GPS 11 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_S 4 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_M \ + (0xF << VIRTCHNL_LINK_TOPO_NODE_CTX_S) +#define VIRTCHNL_LINK_TOPO_NODE_CTX_GLOBAL 0 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_BOARD 1 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_PORT 2 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_NODE 3 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_PROVIDED 4 +#define VIRTCHNL_LINK_TOPO_NODE_CTX_OVERRIDE 5 + u8 index; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(4, virtchnl_link_topo_params); + +/** + * virtchnl_link_topo_addr + * @topo_params: link topo parameters + * @handle: link topo handle (board type, mezzaine / lom Type) + * + * Structure used as part of virtchnl_gnss_i2c read or write request. VF sets + * this structure field for GNSS I2C console Node, PF passes it on to AdminQ. + */ +struct virtchnl_link_topo_addr { + struct virtchnl_link_topo_params topo_params; + u16 handle; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_link_topo_addr); + +/** + * virtchnl_gnss_i2c + * @topo_addr: link topo address + * @i2c_addr: gnss console I2C Address + * @i2c_params: gnss console I2C Parameters + * @i2c_bus_addr: gnss console I2C Bus Address + * @i2c_data: Data to be written to gnss module + * + * Structure sent with VIRTCHNL_OP_GNSS_READ_I2C for GNSS Console I2C Read, + * or VIRTCHNL_OP_GNSS_WRITE_I2C for GNSS Console I2C Write. The request is + * acceptable only when VF negotiated VIRTCHNL_1588_PTP_CAP_GNSS capability + * with PF. + */ +struct virtchnl_gnss_i2c { + struct virtchnl_link_topo_addr topo_addr; + u16 i2c_addr; + u8 i2c_params; +#define VIRTCHNL_I2C_DATA_SIZE_S 0 +#define VIRTCHNL_I2C_DATA_SIZE_M (0xF << VIRTCHNL_I2C_DATA_SIZE_S) +#define VIRTCHNL_I2C_ADDR_TYPE_M BIT(4) +#define VIRTCHNL_I2C_ADDR_TYPE_7BIT 0 +#define VIRTCHNL_I2C_ADDR_TYPE_10BIT VIRTCHNL_I2C_ADDR_TYPE_M +#define VIRTCHNL_I2C_DATA_OFFSET_S 5 +#define VIRTCHNL_I2C_DATA_OFFSET_M (0x3 << VIRTCHNL_I2C_DATA_OFFSET_S) +#define VIRTCHNL_I2C_USE_REPEATED_START BIT(7) + u8 rsvd; + u16 i2c_bus_addr; +#define VIRTCHNL_I2C_ADDR_7BIT_MASK 0x7F +#define VIRTCHNL_I2C_ADDR_10BIT_MASK 0x3FF + u8 i2c_data[4]; /* Used only by write command, reserved in read. */ +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_gnss_i2c); + +/** + * virtchnl_gnss_read_i2c_resp + * @i2c_data: Data returned from gnss console I2C read + * + * Structure returned by PF in response to VIRTCHNL_OP_GNSS_READ_I2C for + * GNSS Console I2C Read. + */ +struct virtchnl_gnss_read_i2c_resp { + u8 i2c_data[16]; +}; + +VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_gnss_read_i2c_resp); + /* Since VF messages are limited by u16 size, precalculate the maximum possible * values of nested elements in virtchnl structures that virtual channel can * possibly handle in a single message. @@ -3500,6 +3605,12 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode, break; case VIRTCHNL_OP_SYNCE_GET_HW_INFO: break; + case VIRTCHNL_OP_GNSS_READ_I2C: + valid_len = sizeof(struct virtchnl_gnss_i2c); + break; + case VIRTCHNL_OP_GNSS_WRITE_I2C: + valid_len = sizeof(struct virtchnl_gnss_i2c); + break; case VIRTCHNL_OP_ENABLE_QUEUES_V2: case VIRTCHNL_OP_DISABLE_QUEUES_V2: valid_len = sizeof(struct virtchnl_del_ena_dis_queues); From patchwork Thu Apr 13 09:44:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126017 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C517142931; Thu, 13 Apr 2023 11:52:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9927B42D7C; Thu, 13 Apr 2023 11:50:44 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 1946942D73 for ; Thu, 13 Apr 2023 11:50:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379442; x=1712915442; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WouZ5MZLkn3YhMvzRAOlChwCZIa7TiiCq3lLPL1CLLI=; b=g0V5S2RmdxVTuKYFrwPA84QqvcWlOp/6auno5K0erb+I+/mqwc900dS7 /mtntDVVLxc5DGQMzmJ5zzDPlCh3WE4lNzhEII4uMht5Ay93CRigZEEKf A9PIuyM0zRq7iT2jI/GTGeaPQnmgiUs88+icrgONe3WhL0fwg3jlwWxWO +jf3TISxvGoBZ5fxTdan5i3LO5XkcGJXsnmPF60PHmp1VI3F/JAzHxiKn 2v8hiQy2lY3a66DquwDGj13vwuJjuLc6dxweOpG/WNjTN6hhP1NUr1dV4 KZXsxjRPNMIIYKNmT67SxsaAvW4miiGDghSm161WDcNvMWRv6WxPX0TjR A==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290564" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290564" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699375" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699375" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:39 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , Nizan Zorea Subject: [PATCH 15/18] common/idpf: add/delete queue groups commands Date: Thu, 13 Apr 2023 05:44:59 -0400 Message-Id: <20230413094502.1714755-16-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add types for new two virtchnl commands: add & delete queue group Signed-off-by: Nizan Zorea Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 189 +++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 415e90358e..9e70e5b10e 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -95,6 +95,8 @@ #define VIRTCHNL2_OP_ADD_MAC_ADDR 535 #define VIRTCHNL2_OP_DEL_MAC_ADDR 536 #define VIRTCHNL2_OP_CONFIG_PROMISCUOUS_MODE 537 +#define VIRTCHNL2_OP_ADD_QUEUE_GROUPS 538 +#define VIRTCHNL2_OP_DEL_QUEUE_GROUPS 539 #define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0xFFFF @@ -345,6 +347,14 @@ #define VIRTCHNL2_UNICAST_PROMISC BIT(0) #define VIRTCHNL2_MULTICAST_PROMISC BIT(1) +/* VIRTCHNL2_QUEUE_GROUP_TYPE + * Type of queue groups + * 0 till 0xFF is for general use + */ +#define VIRTCHNL2_QUEUE_GROUP_DATA 1 +#define VIRTCHNL2_QUEUE_GROUP_MBX 2 +#define VIRTCHNL2_QUEUE_GROUP_CONFIG 3 + /* VIRTCHNL2_PROTO_HDR_TYPE * Protocol header type within a packet segment. A segment consists of one or * more protocol headers that make up a logical group of protocol headers. Each @@ -794,6 +804,133 @@ struct virtchnl2_add_queues { VIRTCHNL2_CHECK_STRUCT_LEN(56, virtchnl2_add_queues); +/* Queue Groups Extension */ + +struct virtchnl2_rx_queue_group_info { + /* IN/OUT, user can ask to update rss_lut size originally allocated + * by CreateVport command. New size will be returned if allocation + * suceeded, otherwise original rss_size from CreateVport will + * be returned. + */ + __le16 rss_lut_size; + /* Future extension purpose */ + u8 pad[6]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_rx_queue_group_info); + +struct virtchnl2_tx_queue_group_info { /* IN */ + /* TX TC queue group will be connected to */ + u8 tx_tc; + /* Each group can have its own priority, value 0-7, while each group + * with unique priority is strict priority. + * It can be single set of queue groups which configured with + * same priority, then they are assumed part of WFQ arbitration + * group and are expected to be assigned with weight. + */ + u8 priority; + /* Determines if queue group is expected to be Strict Priority + * according to its priority + */ + u8 is_sp; + u8 pad; + + /* Peak Info Rate Weight in case Queue Group is part of WFQ + * arbitration set. + * The weights of the groups are independent of each other. + * Possible values: 1-200 + */ + __le16 pir_weight; + /* Future extension purpose for CIR only */ + u8 cir_pad[2]; + /* Future extension purpose*/ + u8 pad2[8]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_tx_queue_group_info); + +struct virtchnl2_queue_group_id { + /* Queue group ID - depended on it's type + * Data: is an ID which is relative to Vport + * Config & Mailbox: is an ID which is relative to func. + * This ID is use in future calls, i.e. delete. + * Requested by host and assigned by Control plane. + */ + __le16 queue_group_id; + /* Functional type: see VIRTCHNL2_QUEUE_GROUP_TYPE definitions */ + __le16 queue_group_type; + u8 pad[4]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_queue_group_id); + +struct virtchnl2_queue_group_info { + /* IN */ + struct virtchnl2_queue_group_id qg_id; + /* IN, Number of queue of different types in the group. */ + __le16 num_tx_q; + __le16 num_tx_complq; + __le16 num_rx_q; + __le16 num_rx_bufq; + + struct virtchnl2_tx_queue_group_info tx_q_grp_info; + struct virtchnl2_rx_queue_group_info rx_q_grp_info; + /* Future extension purpose */ + u8 pad[40]; + struct virtchnl2_queue_reg_chunks chunks; /* OUT */ +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(120, virtchnl2_queue_group_info); + +struct virtchnl2_queue_groups { + __le16 num_queue_groups; + u8 pad[6]; + struct virtchnl2_queue_group_info groups[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(128, virtchnl2_queue_groups); + +/* VIRTCHNL2_OP_ADD_QUEUE_GROUPS + * PF sends this message to request additional transmit/receive queue groups + * beyond the ones that were assigned via CREATE_VPORT request. + * virtchnl2_add_queue_groups structure is used to specify the number of each + * type of queues. CP responds with the same structure with the actual number of + * groups and queues assigned followed by num_queue_groups and num_chunks of + * virtchnl2_queue_groups and virtchnl2_queue_chunk structures. + */ +struct virtchnl2_add_queue_groups { + /* IN, vport_id to add queue group to, same as allocated by CreateVport. + * NA for mailbox and other types not assigned to vport + */ + __le32 vport_id; + u8 pad[4]; + /* IN/OUT */ + struct virtchnl2_queue_groups qg_info; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(136, virtchnl2_add_queue_groups); + +/* VIRTCHNL2_OP_DEL_QUEUE_GROUPS + * PF sends this message to delete queue groups. + * PF sends virtchnl2_delete_queue_groups struct to specify the queue groups + * to be deleted. CP performs requested action and returns status and update + * num_queue_groups with number of successfully deleted queue groups. + */ +struct virtchnl2_delete_queue_groups { + /* IN, vport_id to delete queue group from, same as + * allocated by CreateVport. + */ + __le32 vport_id; + /* IN/OUT, Defines number of groups provided below */ + __le16 num_queue_groups; + u8 pad[2]; + + /* IN, IDs & types of Queue Groups to delete */ + struct virtchnl2_queue_group_id qg_ids[1]; +}; + +VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_delete_queue_groups); + /* Structure to specify a chunk of contiguous interrupt vectors */ struct virtchnl2_vector_chunk { __le16 start_vector_id; @@ -1243,6 +1380,10 @@ static inline const char *virtchnl2_op_str(__le32 v_opcode) return "VIRTCHNL2_OP_CREATE_ADI"; case VIRTCHNL2_OP_DESTROY_ADI: return "VIRTCHNL2_OP_DESTROY_ADI"; + case VIRTCHNL2_OP_ADD_QUEUE_GROUPS: + return "VIRTCHNL2_OP_ADD_QUEUE_GROUPS"; + case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: + return "VIRTCHNL2_OP_DEL_QUEUE_GROUPS"; default: return "Unsupported (update virtchnl2.h)"; } @@ -1373,6 +1514,54 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 sizeof(struct virtchnl2_queue_chunk); } break; + case VIRTCHNL2_OP_ADD_QUEUE_GROUPS: + valid_len = sizeof(struct virtchnl2_add_queue_groups); + if (msglen != valid_len) { + __le32 i = 0, offset = 0; + struct virtchnl2_add_queue_groups *add_queue_grp = + (struct virtchnl2_add_queue_groups *)msg; + struct virtchnl2_queue_groups *groups = &(add_queue_grp->qg_info); + struct virtchnl2_queue_group_info *grp_info; + __le32 chunk_size = sizeof(struct virtchnl2_queue_reg_chunk); + __le32 group_size = sizeof(struct virtchnl2_queue_group_info); + __le32 total_chunks_size; + + if (groups->num_queue_groups == 0) { + err_msg_format = true; + break; + } + valid_len += (groups->num_queue_groups - 1) * + sizeof(struct virtchnl2_queue_group_info); + offset = (u8 *)(&groups->groups[0]) - (u8 *)groups; + + for (i = 0; i < groups->num_queue_groups; i++) { + grp_info = (struct virtchnl2_queue_group_info *) + ((u8 *)groups + offset); + if (grp_info->chunks.num_chunks == 0) { + offset += group_size; + continue; + } + total_chunks_size = (grp_info->chunks.num_chunks - 1) * chunk_size; + offset += group_size + total_chunks_size; + valid_len += total_chunks_size; + } + } + break; + case VIRTCHNL2_OP_DEL_QUEUE_GROUPS: + valid_len = sizeof(struct virtchnl2_delete_queue_groups); + if (msglen != valid_len) { + struct virtchnl2_delete_queue_groups *del_queue_grp = + (struct virtchnl2_delete_queue_groups *)msg; + + if (del_queue_grp->num_queue_groups == 0) { + err_msg_format = true; + break; + } + + valid_len += (del_queue_grp->num_queue_groups - 1) * + sizeof(struct virtchnl2_queue_group_id); + } + break; case VIRTCHNL2_OP_MAP_QUEUE_VECTOR: case VIRTCHNL2_OP_UNMAP_QUEUE_VECTOR: valid_len = sizeof(struct virtchnl2_queue_vector_maps); From patchwork Thu Apr 13 09:45:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126018 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CE65942931; Thu, 13 Apr 2023 11:52:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D555D42D8B; Thu, 13 Apr 2023 11:50:45 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 4C98542D0E for ; Thu, 13 Apr 2023 11:50:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379444; x=1712915444; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eAM6Cws01kD4xK3/PFvH/Ake/7Q0Lm96Gu58dzqsv3M=; b=Kjpy3zecOD7LK0z+IygGKhbx2KX0Jdzl6WkeRGYu0IzuEDTKRGI8OiGP k5OsIzuipHPsBM9PiREJcuxUw5qY4bhyXy1mY+C0HsoBgW4LOe+2X/RQx H7DvogsvY9QKSB8ABEhiB+vmoJ4tExSC3+bNf31ZYhog0dE1031mp75C0 v8lPRZMJJRNR8us0odNT51mUDOqYsst07/NTJAeLIPuaLYcCHuYVRIdVF u/6A/yinALIALU8Xi9wW2Sl2HTO34ggUC+u1eSEm8zbbanro0mAVSrlHm DrR3DdsE+4WqKOBOhnVL/Dy5w1D9LgB+jBeboFEyhb9NftKkHlv2CCmfT g==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290580" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290580" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699385" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699385" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:41 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , NorbertX Ciosek Subject: [PATCH 16/18] common/idpf: add func to clean all DESCs on controlq Date: Thu, 13 Apr 2023 05:45:00 -0400 Message-Id: <20230413094502.1714755-17-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add 'idpf_ctlq_clean_sq_force' which will clean all descriptors on given control queue. It is needed in case control plane is not running and we need to do proper driver cleanup. Signed-off-by: NorbertX Ciosek Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/idpf_controlq.c | 56 ++++++++++++++++++-- drivers/common/idpf/base/idpf_controlq_api.h | 4 ++ 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 8381e4000f..9374fce71e 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -386,13 +386,15 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, } /** - * idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the - * requested queue + * __idpf_ctlq_clean_sq - helper function to reclaim descriptors on HW write + * back for the requested queue * @cq: pointer to the specific Control queue * @clean_count: (input|output) number of descriptors to clean as input, and * number of descriptors actually cleaned as output * @msg_status: (output) pointer to msg pointer array to be populated; needs * to be allocated by caller + * @force: (input) clean descriptors which were not done yet. Use with caution + * in kernel mode only * * Returns an array of message pointers associated with the cleaned * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned @@ -400,8 +402,8 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq, * to send will have a non-zero status. The caller is expected to free original * ctlq_msgs and free or reuse the DMA buffers. */ -int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, - struct idpf_ctlq_msg *msg_status[]) +static int __idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[], bool force) { struct idpf_ctlq_desc *desc; u16 i = 0, num_to_clean; @@ -425,7 +427,7 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, for (i = 0; i < num_to_clean; i++) { /* Fetch next descriptor and check if marked as done */ desc = IDPF_CTLQ_DESC(cq, ntc); - if (!(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD)) + if (!force && !(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD)) break; desc_err = LE16_TO_CPU(desc->ret_val); @@ -435,6 +437,8 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, } msg_status[i] = cq->bi.tx_msg[ntc]; + if (!msg_status[i]) + break; msg_status[i]->status = desc_err; cq->bi.tx_msg[ntc] = NULL; @@ -457,6 +461,48 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, return ret; } +/** + * idpf_ctlq_clean_sq_force - reclaim all descriptors on HW write back for the + * requested queue. Use only in kernel mode. + * @cq: pointer to the specific Control queue + * @clean_count: (input|output) number of descriptors to clean as input, and + * number of descriptors actually cleaned as output + * @msg_status: (output) pointer to msg pointer array to be populated; needs + * to be allocated by caller + * + * Returns an array of message pointers associated with the cleaned + * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned + * descriptors. The status will be returned for each; any messages that failed + * to send will have a non-zero status. The caller is expected to free original + * ctlq_msgs and free or reuse the DMA buffers. + */ +int idpf_ctlq_clean_sq_force(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[]) +{ + return __idpf_ctlq_clean_sq(cq, clean_count, msg_status, true); +} + +/** + * idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the + * requested queue + * @cq: pointer to the specific Control queue + * @clean_count: (input|output) number of descriptors to clean as input, and + * number of descriptors actually cleaned as output + * @msg_status: (output) pointer to msg pointer array to be populated; needs + * to be allocated by caller + * + * Returns an array of message pointers associated with the cleaned + * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned + * descriptors. The status will be returned for each; any messages that failed + * to send will have a non-zero status. The caller is expected to free original + * ctlq_msgs and free or reuse the DMA buffers. + */ +int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[]) +{ + return __idpf_ctlq_clean_sq(cq, clean_count, msg_status, false); +} + /** * idpf_ctlq_post_rx_buffs - post buffers to descriptor ring * @hw: pointer to hw struct diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index 80be282b42..a00faac05f 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -191,6 +191,10 @@ int idpf_ctlq_send(struct idpf_hw *hw, int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg, struct idpf_ctlq_msg *q_msg); +/* Reclaims all descriptors on HW write back */ +int idpf_ctlq_clean_sq_force(struct idpf_ctlq_info *cq, u16 *clean_count, + struct idpf_ctlq_msg *msg_status[]); + /* Reclaims send descriptors on HW write back */ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count, struct idpf_ctlq_msg *msg_status[]); From patchwork Thu Apr 13 09:45:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126019 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58E3A42931; Thu, 13 Apr 2023 11:52:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 23D4242D41; Thu, 13 Apr 2023 11:50:49 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id D6F6E42D67; Thu, 13 Apr 2023 11:50:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379447; x=1712915447; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H3/H72F1rq1ksreXrHTKATfDYUXileBJ95oYuoTZexw=; b=YlU8/SomrluqezqufVi1KsNEn1dlVV+oZmX0jHdF1FuUtJ49Ozb9ok+i BFs2u+AO+ubmEkfJ8tVXckVYQRcJ2bj3X/UbTBbGlIiKqTSKbP9LPA1KI 8ULSb9TQxOkJZrILG43k5RZid/qHyFQk3xAfnb0wpr5gzVWg9aHSazqsy 2xgnl+nG1pd9k7ubGQfQTs9KhZmFFHefTaLivOnK5UrKq5DtY8KmMhvde LemMB89qg69GkwxZKOr5I4b0+ay1Cw4mPkEP/gG51yEEKkdoeQ5aZeU+P +QfD1QJVPgWjrjhykBWqGFuughAZfomO59Vu00OuumcdZh08Hot3NrWcF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290604" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290604" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699393" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699393" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:43 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao , stable@dpdk.org, Simei Su Subject: [PATCH 17/18] common/idpf: fix cannot understand warnings Date: Thu, 13 Apr 2023 05:45:01 -0400 Message-Id: <20230413094502.1714755-18-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix cannot understand function prototype warning, it is due to missing "struct" keyword and not described parameter or member in comments. Fixes: fb4ac04e9bfa ("common/idpf: introduce common library") Cc: stable@dpdk.org Signed-off-by: Simei Su Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl.h | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h index 4e9cf9fdeb..a333a3d88c 100644 --- a/drivers/common/idpf/base/virtchnl.h +++ b/drivers/common/idpf/base/virtchnl.h @@ -2149,7 +2149,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_quanta_cfg); #define VIRTCHNL_1588_PTP_CAP_GNSS BIT(7) /** - * virtchnl_phc_regs + * struct virtchnl_phc_regs * * Structure defines how the VF should access PHC related registers. The VF * must request VIRTCHNL_1588_PTP_CAP_PHC_REGS. If the VF has access to PHC @@ -2211,7 +2211,7 @@ enum virtchnl_ptp_tstamp_format { }; /** - * virtchnl_ptp_caps + * struct virtchnl_ptp_caps * * Structure that defines the PTP capabilities available to the VF. The VF * sends VIRTCHNL_OP_1588_PTP_GET_CAPS, and must fill in the ptp_caps field @@ -2313,7 +2313,7 @@ struct virtchnl_ptp_caps { VIRTCHNL_CHECK_STRUCT_LEN(48, virtchnl_ptp_caps); /** - * virtchnl_phc_time + * struct virtchnl_phc_time * @time: PHC time in nanoseconds * @rsvd: Reserved for future extension * @@ -2339,7 +2339,7 @@ struct virtchnl_phc_time { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_time); /** - * virtchnl_phc_adj_time + * struct virtchnl_phc_adj_time * @delta: offset requested to adjust clock by * @rsvd: reserved for future extension * @@ -2359,7 +2359,7 @@ struct virtchnl_phc_adj_time { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_adj_time); /** - * virtchnl_phc_adj_freq + * struct virtchnl_phc_adj_freq * @scaled_ppm: frequency adjustment represented in scaled parts per million * @rsvd: Reserved for future extension * @@ -2388,7 +2388,7 @@ struct virtchnl_phc_adj_freq { VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_phc_adj_freq); /** - * virtchnl_phc_tx_stamp + * struct virtchnl_phc_tx_stamp * @tstamp: timestamp value * @rsvd: Reserved for future extension * @@ -2435,7 +2435,7 @@ enum virtchnl_phc_ext_ts_mode { }; /** - * virtchnl_phc_ext_ts + * struct virtchnl_phc_ext_ts * @mode: mode of external timestamp request * @rsvd: reserved for future extension * @@ -2473,13 +2473,13 @@ enum virtchnl_phc_per_out_flags { }; /** - * virtchnl_phc_per_out + * struct virtchnl_phc_per_out * @start: absolute start time (if VIRTCHNL_PHC_PER_OUT_PHASE_START unset) * @phase: phase offset to start (if VIRTCHNL_PHC_PER_OUT_PHASE_START set) * @period: time to complete a full clock cycle (low - > high -> low) * @on: length of time the signal should stay high * @flags: flags defining the periodic output operation. - * rsvd: reserved for future extension + * @rsvd: reserved for future extension * * Configuration for a periodic output signal. Used to define the signal that * should be generated on a given function. @@ -2547,7 +2547,8 @@ enum virtchnl_phc_pin_cfg_flags { }; /** - * virtchnl_phc_set_pin + * struct virtchnl_phc_set_pin + * @flags: flags defining the bits to cfg pin * @pin_index: The pin to get or set * @func: the function type the pin is assigned to * @func_index: the index of the function the pin is assigned to @@ -2591,7 +2592,7 @@ struct virtchnl_phc_set_pin { VIRTCHNL_CHECK_STRUCT_LEN(80, virtchnl_phc_set_pin); /** - * virtchnl_phc_pin + * struct virtchnl_phc_pin * @pin_index: The pin to get or set * @func: the function type the pin is assigned to * @func_index: the index of the function the pin is assigned to @@ -2618,9 +2619,10 @@ struct virtchnl_phc_pin { VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_phc_pin); /** - * virtchnl_phc_pin_cfg + * struct virtchnl_phc_get_pins * @len: length of the variable pin config array * @pins: variable length pin configuration array + * @rsvd: reserved for future extension * * Variable structure sent by the PF in reply to * VIRTCHNL_OP_1588_PTP_GET_PIN_CFGS. The VF does not send this structure with @@ -2642,7 +2644,7 @@ struct virtchnl_phc_get_pins { VIRTCHNL_CHECK_STRUCT_LEN(80, virtchnl_phc_get_pins); /** - * virtchnl_phc_ext_stamp + * struct virtchnl_phc_ext_stamp * @tstamp: timestamp value * @tstamp_rsvd: Reserved for future extension of the timestamp value. * @tstamp_format: format of the timstamp From patchwork Thu Apr 13 09:45:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 126020 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D96D742931; Thu, 13 Apr 2023 11:52:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 718E642D84; Thu, 13 Apr 2023 11:50:50 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 6C14B42D4D for ; Thu, 13 Apr 2023 11:50:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681379448; x=1712915448; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tiLFx+dvjiH+m1jxwqN9JHHF7RuEsvSZZ7WzFKhleJo=; b=IALPPKahFrnPu9kxPzc9GERcdkAKj6k8gw+eys7SeKgzX2ygTtRRT+jO Hve0pEYctigw2n3iVI1FQIey6dItTuH+a5yEdrMMDoz6w0QD088UsmaVx s4a+krUtdJNPzcT7Di4egoFdl8Ul1Z/CZDkj4PNQx1vgJYQLj6+ho1p+R DAx/02Ll3zKFyVRE9lkK07RvoHdTGDFgKyrJbkNw9r7hmNL3yQPFPRXc+ Ncp3vgX2FptyAekUL9DFWX5l9FhJf9QB92GKueWmsJ+hXjYh39DNUg622 ejnP/QY8IkcBMXSFbiQtArMzvH+siejQs6dbkcRi4nxuTSmLofsHUpbtj w==; X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="409290617" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="409290617" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 02:50:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10678"; a="778699400" X-IronPort-AV: E=Sophos;i="5.98,341,1673942400"; d="scan'208";a="778699400" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.119.244]) by FMSMGA003.fm.intel.com with ESMTP; 13 Apr 2023 02:50:46 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, Wenjing Qiao Subject: [PATCH 18/18] common/idpf: update license and README Date: Thu, 13 Apr 2023 05:45:02 -0400 Message-Id: <20230413094502.1714755-19-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413094502.1714755-1-wenjing.qiao@intel.com> References: <20230413094502.1714755-1-wenjing.qiao@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update license and README Signed-off-by: Wenjing Qiao --- .mailmap | 8 ++++++++ drivers/common/idpf/base/README | 4 ++-- drivers/common/idpf/base/idpf_alloc.h | 2 +- drivers/common/idpf/base/idpf_common.c | 2 +- drivers/common/idpf/base/idpf_controlq.c | 2 +- drivers/common/idpf/base/idpf_controlq.h | 2 +- drivers/common/idpf/base/idpf_controlq_api.h | 2 +- drivers/common/idpf/base/idpf_controlq_setup.c | 2 +- drivers/common/idpf/base/idpf_devids.h | 2 +- drivers/common/idpf/base/idpf_lan_pf_regs.h | 2 +- drivers/common/idpf/base/idpf_lan_txrx.h | 2 +- drivers/common/idpf/base/idpf_lan_vf_regs.h | 2 +- drivers/common/idpf/base/idpf_osdep.h | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- drivers/common/idpf/base/idpf_type.h | 2 +- drivers/common/idpf/base/meson.build | 2 +- drivers/common/idpf/base/siov_regs.h | 2 +- drivers/common/idpf/base/virtchnl.h | 2 +- drivers/common/idpf/base/virtchnl2.h | 2 +- drivers/common/idpf/base/virtchnl2_lan_desc.h | 2 +- drivers/common/idpf/base/virtchnl_inline_ipsec.h | 2 +- 21 files changed, 29 insertions(+), 21 deletions(-) diff --git a/.mailmap b/.mailmap index 0859104404..309b1bc69e 100644 --- a/.mailmap +++ b/.mailmap @@ -1603,3 +1603,11 @@ Ziye Yang Zoltan Kiss Zorik Machulsky Zyta Szpak +Charles Stoll +Nizan Zorea +Vinoth Kumar Chandra Mohan +NorbertX Ciosek +Pavan Kumar Linga +Jun Zhang +Priyalee Kushwaha +Kazatsker Kirill diff --git a/drivers/common/idpf/base/README b/drivers/common/idpf/base/README index 257ad6c4b1..693049c057 100644 --- a/drivers/common/idpf/base/README +++ b/drivers/common/idpf/base/README @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2022 Intel Corporation + * Copyright(c) 2021-2023 Intel Corporation */ Intel® IDPF driver ================== This directory contains source code of BSD-3-Clause idpf driver of version -2022.09.13 released by the team which develops basic drivers for Intel IPU. +2023.02.23 released by the team which develops basic drivers for Intel IPU. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below diff --git a/drivers/common/idpf/base/idpf_alloc.h b/drivers/common/idpf/base/idpf_alloc.h index bc054851b3..5cc4beb5cf 100644 --- a/drivers/common/idpf/base/idpf_alloc.h +++ b/drivers/common/idpf/base/idpf_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_ALLOC_H_ diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index f4a5707272..d0efc6be66 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "idpf_type.h" diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 9374fce71e..68aae6f321 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "idpf_controlq.h" diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h index 47bffcf79f..0fe0e94a37 100644 --- a/drivers/common/idpf/base/idpf_controlq.h +++ b/drivers/common/idpf/base/idpf_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_CONTROLQ_H_ diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index a00faac05f..ad649ab356 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_CONTROLQ_API_H_ diff --git a/drivers/common/idpf/base/idpf_controlq_setup.c b/drivers/common/idpf/base/idpf_controlq_setup.c index 3a272b1f8d..0f1b52a7e9 100644 --- a/drivers/common/idpf/base/idpf_controlq_setup.c +++ b/drivers/common/idpf/base/idpf_controlq_setup.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ diff --git a/drivers/common/idpf/base/idpf_devids.h b/drivers/common/idpf/base/idpf_devids.h index a91eb4e02a..c47762d5b7 100644 --- a/drivers/common/idpf/base/idpf_devids.h +++ b/drivers/common/idpf/base/idpf_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_DEVIDS_H_ diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h index 1c665d1f3b..8542620e01 100644 --- a/drivers/common/idpf/base/idpf_lan_pf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_LAN_PF_REGS_H_ diff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h index 82742857be..ac925736d7 100644 --- a/drivers/common/idpf/base/idpf_lan_txrx.h +++ b/drivers/common/idpf/base/idpf_lan_txrx.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_LAN_TXRX_H_ diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h index c8739fae7a..b5ff9b2cc9 100644 --- a/drivers/common/idpf/base/idpf_lan_vf_regs.h +++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_LAN_VF_REGS_H_ diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index abcf68f1a2..8a49a966ea 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_OSDEP_H_ diff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h index 3ce25e644d..1b28668863 100644 --- a/drivers/common/idpf/base/idpf_prototype.h +++ b/drivers/common/idpf/base/idpf_prototype.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_PROTOTYPE_H_ diff --git a/drivers/common/idpf/base/idpf_type.h b/drivers/common/idpf/base/idpf_type.h index 2a97d32a8b..a22d28f448 100644 --- a/drivers/common/idpf/base/idpf_type.h +++ b/drivers/common/idpf/base/idpf_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_TYPE_H_ diff --git a/drivers/common/idpf/base/meson.build b/drivers/common/idpf/base/meson.build index dc4b93c198..96d7642209 100644 --- a/drivers/common/idpf/base/meson.build +++ b/drivers/common/idpf/base/meson.build @@ -1,5 +1,5 @@ # SPDX-License-Identifier: BSD-3-Clause -# Copyright(c) 2022 Intel Corporation +# Copyright(c) 2023 Intel Corporation sources += files( 'idpf_common.c', diff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h index 3ac4f8f177..fad329601a 100644 --- a/drivers/common/idpf/base/siov_regs.h +++ b/drivers/common/idpf/base/siov_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _SIOV_REGS_H_ #define _SIOV_REGS_H_ diff --git a/drivers/common/idpf/base/virtchnl.h b/drivers/common/idpf/base/virtchnl.h index a333a3d88c..401c6518eb 100644 --- a/drivers/common/idpf/base/virtchnl.h +++ b/drivers/common/idpf/base/virtchnl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _VIRTCHNL_H_ diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 9e70e5b10e..c0a1f63b5e 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _VIRTCHNL2_H_ diff --git a/drivers/common/idpf/base/virtchnl2_lan_desc.h b/drivers/common/idpf/base/virtchnl2_lan_desc.h index 0992cefc6c..e6e782a219 100644 --- a/drivers/common/idpf/base/virtchnl2_lan_desc.h +++ b/drivers/common/idpf/base/virtchnl2_lan_desc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ /* * Copyright (C) 2019 Intel Corporation diff --git a/drivers/common/idpf/base/virtchnl_inline_ipsec.h b/drivers/common/idpf/base/virtchnl_inline_ipsec.h index e19043ac47..d2a0a5f721 100644 --- a/drivers/common/idpf/base/virtchnl_inline_ipsec.h +++ b/drivers/common/idpf/base/virtchnl_inline_ipsec.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _VIRTCHNL_INLINE_IPSEC_H_