From patchwork Thu Apr 27 06:19:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126568 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5B30342A08; Thu, 27 Apr 2023 08:37:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E556442D3C; Thu, 27 Apr 2023 08:37:49 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id F1F2D410DD for ; Thu, 27 Apr 2023 08:37:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577467; x=1714113467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ItzsL8iVrtPTT040biVYKQTbAPsDHRK2M4P3KOzopBg=; b=f183TFNHGbCleTU862K73sYFrXpVDDRFywcEBgAfb4VTi5UlxrM4LfGe MHJaQUgSbBpW89BZkHsArgT69NosLG22gqdo3UZdRr/xj9umFmjVTZ8uR RR2OTfoCNcUrK8J+q1rwEiy98ygUc4yqXBfKpRnoLvkf3K+fiEPpb+y1E PozTywRfYHgc/XpRpnxsnV2iy8TB2nuYjYQwY84Q42gDATO4iCjvRoSeC g5HeZv02QyKbhqYE2zyge29wJE/A90jpz4fuqo5JcTDwDoR4pEP09EyeP chw20CEfQyVx2P2zAkXJK7lQOuP0XEcdJ11xHfMTlUcMjco5CqI04x/sz w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324248" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324248" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845650" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845650" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:44 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang Subject: [PATCH 01/30] net/ice/base: updated copyright Date: Thu, 27 Apr 2023 06:19:32 +0000 Message-Id: <20230427062001.478032-2-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Updated copyright to 2023. Signed-off-by: Qiming Yang --- drivers/net/ice/base/README | 2 +- drivers/net/ice/base/ice_acl.c | 2 +- drivers/net/ice/base/ice_acl.h | 2 +- drivers/net/ice/base/ice_acl_ctrl.c | 2 +- drivers/net/ice/base/ice_adminq_cmd.h | 2 +- drivers/net/ice/base/ice_alloc.h | 2 +- drivers/net/ice/base/ice_bitops.h | 2 +- drivers/net/ice/base/ice_bst_tcam.c | 2 +- drivers/net/ice/base/ice_bst_tcam.h | 2 +- drivers/net/ice/base/ice_cgu_regs.h | 2 +- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_common.h | 2 +- drivers/net/ice/base/ice_controlq.c | 2 +- drivers/net/ice/base/ice_controlq.h | 2 +- drivers/net/ice/base/ice_dcb.c | 2 +- drivers/net/ice/base/ice_dcb.h | 2 +- drivers/net/ice/base/ice_ddp.c | 2 +- drivers/net/ice/base/ice_ddp.h | 2 +- drivers/net/ice/base/ice_defs.h | 2 +- drivers/net/ice/base/ice_devids.h | 2 +- drivers/net/ice/base/ice_fdir.c | 2 +- drivers/net/ice/base/ice_fdir.h | 2 +- drivers/net/ice/base/ice_flex_pipe.c | 2 +- drivers/net/ice/base/ice_flex_pipe.h | 2 +- drivers/net/ice/base/ice_flex_type.h | 2 +- drivers/net/ice/base/ice_flg_rd.c | 2 +- drivers/net/ice/base/ice_flg_rd.h | 2 +- drivers/net/ice/base/ice_flow.c | 2 +- drivers/net/ice/base/ice_flow.h | 2 +- drivers/net/ice/base/ice_hw_autogen.h | 2 +- drivers/net/ice/base/ice_imem.c | 2 +- drivers/net/ice/base/ice_imem.h | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 2 +- drivers/net/ice/base/ice_metainit.c | 2 +- drivers/net/ice/base/ice_metainit.h | 2 +- drivers/net/ice/base/ice_mk_grp.c | 2 +- drivers/net/ice/base/ice_mk_grp.h | 2 +- drivers/net/ice/base/ice_nvm.c | 2 +- drivers/net/ice/base/ice_nvm.h | 2 +- drivers/net/ice/base/ice_parser.c | 2 +- drivers/net/ice/base/ice_parser.h | 2 +- drivers/net/ice/base/ice_parser_rt.c | 2 +- drivers/net/ice/base/ice_parser_rt.h | 2 +- drivers/net/ice/base/ice_parser_util.h | 2 +- drivers/net/ice/base/ice_pg_cam.c | 2 +- drivers/net/ice/base/ice_pg_cam.h | 2 +- drivers/net/ice/base/ice_proto_grp.c | 2 +- drivers/net/ice/base/ice_proto_grp.h | 2 +- drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_ptp_consts.h | 2 +- drivers/net/ice/base/ice_ptp_hw.c | 2 +- drivers/net/ice/base/ice_ptp_hw.h | 2 +- drivers/net/ice/base/ice_ptype_mk.c | 2 +- drivers/net/ice/base/ice_ptype_mk.h | 2 +- drivers/net/ice/base/ice_sbq_cmd.h | 2 +- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_sched.h | 2 +- drivers/net/ice/base/ice_status.h | 2 +- drivers/net/ice/base/ice_switch.c | 2 +- drivers/net/ice/base/ice_switch.h | 2 +- drivers/net/ice/base/ice_tmatch.h | 2 +- drivers/net/ice/base/ice_type.h | 2 +- drivers/net/ice/base/ice_vlan_mode.c | 2 +- drivers/net/ice/base/ice_vlan_mode.h | 2 +- drivers/net/ice/base/ice_xlt_kb.c | 2 +- drivers/net/ice/base/ice_xlt_kb.h | 2 +- 66 files changed, 66 insertions(+), 66 deletions(-) diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README index 0e37a5f7a1..d3b96e0fb4 100644 --- a/drivers/net/ice/base/README +++ b/drivers/net/ice/base/README @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2020-2022 Intel Corporation + * Copyright(c) 2020-2023 Intel Corporation */ Intel® ICE driver diff --git a/drivers/net/ice/base/ice_acl.c b/drivers/net/ice/base/ice_acl.c index 23b6c608be..fd9c6d5c14 100644 --- a/drivers/net/ice/base/ice_acl.c +++ b/drivers/net/ice/base/ice_acl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_acl.h b/drivers/net/ice/base/ice_acl.h index b5f2ec04a4..ac703be0a1 100644 --- a/drivers/net/ice/base/ice_acl.h +++ b/drivers/net/ice/base/ice_acl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_ACL_H_ diff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c index 3a912f2aa0..2223a8313b 100644 --- a/drivers/net/ice/base/ice_acl_ctrl.c +++ b/drivers/net/ice/base/ice_acl_ctrl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 5a817982b4..65cba9ab37 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_ADMINQ_CMD_H_ diff --git a/drivers/net/ice/base/ice_alloc.h b/drivers/net/ice/base/ice_alloc.h index dca502ab25..6487cdc210 100644 --- a/drivers/net/ice/base/ice_alloc.h +++ b/drivers/net/ice/base/ice_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_ALLOC_H_ diff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h index c4ae2b9c8e..5384e99415 100644 --- a/drivers/net/ice/base/ice_bitops.h +++ b/drivers/net/ice/base/ice_bitops.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_BITOPS_H_ diff --git a/drivers/net/ice/base/ice_bst_tcam.c b/drivers/net/ice/base/ice_bst_tcam.c index 5cc0d12251..fbe106df60 100644 --- a/drivers/net/ice/base/ice_bst_tcam.c +++ b/drivers/net/ice/base/ice_bst_tcam.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_bst_tcam.h b/drivers/net/ice/base/ice_bst_tcam.h index 292444c919..2fb2c8421e 100644 --- a/drivers/net/ice/base/ice_bst_tcam.h +++ b/drivers/net/ice/base/ice_bst_tcam.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_BST_TCAM_H_ diff --git a/drivers/net/ice/base/ice_cgu_regs.h b/drivers/net/ice/base/ice_cgu_regs.h index 6b9a359c5b..c44bfc1846 100644 --- a/drivers/net/ice/base/ice_cgu_regs.h +++ b/drivers/net/ice/base/ice_cgu_regs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_CGU_REGS_H_ diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 1a02aad869..fa30c50ca1 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 58260afb93..e1febfb0c4 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_COMMON_H_ diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index 8971a140ef..c34407b48c 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 45fe70450e..986604ec3c 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_CONTROLQ_H_ diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index 0e604df541..2a308b02bf 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h index d010c539a6..bae033a460 100644 --- a/drivers/net/ice/base/ice_dcb.h +++ b/drivers/net/ice/base/ice_dcb.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DCB_H_ diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index d1cae48047..93ff2608d4 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_ddp.h" diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 53bbbe2a5a..4896e85b91 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DDP_H_ diff --git a/drivers/net/ice/base/ice_defs.h b/drivers/net/ice/base/ice_defs.h index 6e886f6aac..210ce6263b 100644 --- a/drivers/net/ice/base/ice_defs.h +++ b/drivers/net/ice/base/ice_defs.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DEFS_H_ diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 13a4b16402..f80789ebc5 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_DEVIDS_H_ diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 85ca29bae5..3ed2a63b68 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index f338da38c2..81ba6008e4 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FDIR_H_ diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index b6bc0062a3..f9266447d9 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index 9ba337e1fa..422d09becc 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLEX_PIPE_H_ diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 7b8f6f9049..c83479d6fa 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLEX_TYPE_H_ diff --git a/drivers/net/ice/base/ice_flg_rd.c b/drivers/net/ice/base/ice_flg_rd.c index f320958bd3..97f62e6cc4 100644 --- a/drivers/net/ice/base/ice_flg_rd.c +++ b/drivers/net/ice/base/ice_flg_rd.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flg_rd.h b/drivers/net/ice/base/ice_flg_rd.h index 8cd375f89f..c194a4f462 100644 --- a/drivers/net/ice/base/ice_flg_rd.h +++ b/drivers/net/ice/base/ice_flg_rd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLG_RD_H_ diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 3483a5ed4f..5254ee27ed 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index dba71aab74..57e8e1f1df 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_FLOW_H_ diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 6dc77bf7cb..4610cec6a7 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ /* Machine generated file. Do not edit. */ diff --git a/drivers/net/ice/base/ice_imem.c b/drivers/net/ice/base/ice_imem.c index 277311fd20..f193aaf836 100644 --- a/drivers/net/ice/base/ice_imem.c +++ b/drivers/net/ice/base/ice_imem.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_imem.h b/drivers/net/ice/base/ice_imem.h index 06d3d5a96d..0328830b94 100644 --- a/drivers/net/ice/base/ice_imem.h +++ b/drivers/net/ice/base/ice_imem.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_IMEM_H_ diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index be6d88f0ca..d816df0ff6 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_LAN_TX_RX_H_ diff --git a/drivers/net/ice/base/ice_metainit.c b/drivers/net/ice/base/ice_metainit.c index b75d68c010..1e990c9aa0 100644 --- a/drivers/net/ice/base/ice_metainit.c +++ b/drivers/net/ice/base/ice_metainit.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_metainit.h b/drivers/net/ice/base/ice_metainit.h index dad4faf4d4..440932ae30 100644 --- a/drivers/net/ice/base/ice_metainit.h +++ b/drivers/net/ice/base/ice_metainit.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_METAINIT_H_ diff --git a/drivers/net/ice/base/ice_mk_grp.c b/drivers/net/ice/base/ice_mk_grp.c index cafe51544d..9de4527b58 100644 --- a/drivers/net/ice/base/ice_mk_grp.c +++ b/drivers/net/ice/base/ice_mk_grp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_mk_grp.h b/drivers/net/ice/base/ice_mk_grp.h index 9401647ef0..161dd724cb 100644 --- a/drivers/net/ice/base/ice_mk_grp.h +++ b/drivers/net/ice/base/ice_mk_grp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_MK_GRP_H_ diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 6550dda557..cb45cb8134 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index a8cda452db..c3e61a301f 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_NVM_H_ diff --git a/drivers/net/ice/base/ice_parser.c b/drivers/net/ice/base/ice_parser.c index a1b906d369..79c97f7903 100644 --- a/drivers/net/ice/base/ice_parser.c +++ b/drivers/net/ice/base/ice_parser.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_parser.h b/drivers/net/ice/base/ice_parser.h index b4c5e7b14d..0f64584898 100644 --- a/drivers/net/ice/base/ice_parser.h +++ b/drivers/net/ice/base/ice_parser.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PARSER_H_ diff --git a/drivers/net/ice/base/ice_parser_rt.c b/drivers/net/ice/base/ice_parser_rt.c index 215e11abd2..68c0f5d7fb 100644 --- a/drivers/net/ice/base/ice_parser_rt.c +++ b/drivers/net/ice/base/ice_parser_rt.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_parser_rt.h b/drivers/net/ice/base/ice_parser_rt.h index c1e1af0059..de851643b4 100644 --- a/drivers/net/ice/base/ice_parser_rt.h +++ b/drivers/net/ice/base/ice_parser_rt.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PARSER_RT_H_ diff --git a/drivers/net/ice/base/ice_parser_util.h b/drivers/net/ice/base/ice_parser_util.h index a33d6bf11c..9949b985ee 100644 --- a/drivers/net/ice/base/ice_parser_util.h +++ b/drivers/net/ice/base/ice_parser_util.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PARSER_UTIL_H_ diff --git a/drivers/net/ice/base/ice_pg_cam.c b/drivers/net/ice/base/ice_pg_cam.c index f06a3581a0..e6324945fb 100644 --- a/drivers/net/ice/base/ice_pg_cam.c +++ b/drivers/net/ice/base/ice_pg_cam.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_pg_cam.h b/drivers/net/ice/base/ice_pg_cam.h index ac0863afb0..0412ac5ae2 100644 --- a/drivers/net/ice/base/ice_pg_cam.h +++ b/drivers/net/ice/base/ice_pg_cam.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PG_CAM_H_ diff --git a/drivers/net/ice/base/ice_proto_grp.c b/drivers/net/ice/base/ice_proto_grp.c index a9ed9e051f..94f4df0aaa 100644 --- a/drivers/net/ice/base/ice_proto_grp.c +++ b/drivers/net/ice/base/ice_proto_grp.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_proto_grp.h b/drivers/net/ice/base/ice_proto_grp.h index 762d32464b..dc6d8a32a4 100644 --- a/drivers/net/ice/base/ice_proto_grp.h +++ b/drivers/net/ice/base/ice_proto_grp.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PROTO_GRP_H_ diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index d17ab54bd3..eeaf044059 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PROTOCOL_TYPE_H_ diff --git a/drivers/net/ice/base/ice_ptp_consts.h b/drivers/net/ice/base/ice_ptp_consts.h index ddf6242d8e..546bf8ba91 100644 --- a/drivers/net/ice/base/ice_ptp_consts.h +++ b/drivers/net/ice/base/ice_ptp_consts.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PTP_CONSTS_H_ diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index a0b8af1b94..548ef5e820 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_type.h" diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 09c236e7e0..3667c9882d 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PTP_HW_H_ diff --git a/drivers/net/ice/base/ice_ptype_mk.c b/drivers/net/ice/base/ice_ptype_mk.c index 4cd8396167..6814095dbd 100644 --- a/drivers/net/ice/base/ice_ptype_mk.c +++ b/drivers/net/ice/base/ice_ptype_mk.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_ptype_mk.h b/drivers/net/ice/base/ice_ptype_mk.h index 3efe294dda..66427c6866 100644 --- a/drivers/net/ice/base/ice_ptype_mk.h +++ b/drivers/net/ice/base/ice_ptype_mk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_PTYPE_MK_H_ diff --git a/drivers/net/ice/base/ice_sbq_cmd.h b/drivers/net/ice/base/ice_sbq_cmd.h index a215303a56..4da16caf70 100644 --- a/drivers/net/ice/base/ice_sbq_cmd.h +++ b/drivers/net/ice/base/ice_sbq_cmd.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_SBQ_CMD_H_ diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index a526c8f32c..83cd152388 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_sched.h" diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 3724ef33a8..a71619ebf0 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_SCHED_H_ diff --git a/drivers/net/ice/base/ice_status.h b/drivers/net/ice/base/ice_status.h index f52121c3a3..1965347a8b 100644 --- a/drivers/net/ice/base/ice_status.h +++ b/drivers/net/ice/base/ice_status.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_STATUS_H_ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index e4eed66406..cd6237136e 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 949c94c0c3..7a12619459 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_SWITCH_H_ diff --git a/drivers/net/ice/base/ice_tmatch.h b/drivers/net/ice/base/ice_tmatch.h index e70926acd1..a2df0c4367 100644 --- a/drivers/net/ice/base/ice_tmatch.h +++ b/drivers/net/ice/base/ice_tmatch.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_TMATCH_H_ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index bfec317b57..da813c8307 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_TYPE_H_ diff --git a/drivers/net/ice/base/ice_vlan_mode.c b/drivers/net/ice/base/ice_vlan_mode.c index 74d414b3b8..7ee00df124 100644 --- a/drivers/net/ice/base/ice_vlan_mode.c +++ b/drivers/net/ice/base/ice_vlan_mode.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_vlan_mode.h b/drivers/net/ice/base/ice_vlan_mode.h index 5e3f454a25..d2380eb94b 100644 --- a/drivers/net/ice/base/ice_vlan_mode.h +++ b/drivers/net/ice/base/ice_vlan_mode.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_VLAN_MODE_H_ diff --git a/drivers/net/ice/base/ice_xlt_kb.c b/drivers/net/ice/base/ice_xlt_kb.c index 59472a08d4..b8240946b4 100644 --- a/drivers/net/ice/base/ice_xlt_kb.c +++ b/drivers/net/ice/base/ice_xlt_kb.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "ice_common.h" diff --git a/drivers/net/ice/base/ice_xlt_kb.h b/drivers/net/ice/base/ice_xlt_kb.h index f870f18ed6..0cce33142a 100644 --- a/drivers/net/ice/base/ice_xlt_kb.h +++ b/drivers/net/ice/base/ice_xlt_kb.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _ICE_XLT_KB_H_ From patchwork Thu Apr 27 06:19:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126569 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC88042A08; Thu, 27 Apr 2023 08:38:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9BE4242D48; Thu, 27 Apr 2023 08:37:52 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id E47F942D3A for ; Thu, 27 Apr 2023 08:37:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577469; x=1714113469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UA3AY1VrHGPdAMeuMmAGzERZiNlzMyX/ZysNiCfssjY=; b=k2kKQ6xR2eKKfQL/d/m3sxLSEF7XKpt99kG/SX4yEmixVJ0d6v3iO4qS FA7IrEGY5QFZzV4cYE/hNI0LI21G51Z4Cn8y1QVIXcKtXR3AQOg7iwFGp D4qwWy5qJ+DwzQgALz8UxBOXTnwVmcvphaEgOKlkZyNJw7ltw2MGr8Aef ZOtBHoNesxS4CQXpj74Kiav9C2FENCYAcos337aBnibADewCFCGrJKkr8 pHxk863G0Kk8VZ0IByKC+9JqAJ+p3ZdE8cSoEk6BGBit2y4uiTUoDi7AO FTSpyDdlL656EevcQK+9m4FyOv481Myb6wdfcguAPtHp0c4+aDw1hmbPh Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324255" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324255" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845659" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845659" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:45 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jesse Brandeburg Subject: [PATCH 02/30] net/ice/base: add flex array safe allocations Date: Thu, 27 Apr 2023 06:19:33 +0000 Message-Id: <20230427062001.478032-3-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The Linux Kernel is now requiring flex array safe allocations from drivers and the way that we used overlaid union structures was confusing or worse, breaking Klocwork as well as failing upstream builds that were checking -Warray-bounds. And refactor structure size macros. The driver used several macros to compute size of flexible arrays. These macros are just as well converted to plain code that does struct_size. Signed-off-by: Jesse Brandeburg Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 57 +++--- drivers/net/ice/base/ice_switch.c | 265 +++++++++++++------------- drivers/net/ice/base/ice_switch.h | 12 -- 3 files changed, 165 insertions(+), 169 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 65cba9ab37..69e528a8c9 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -813,12 +813,30 @@ struct ice_aqc_sw_rules { __le32 addr_low; }; +/* Add switch rule response: + * Content of return buffer is same as the input buffer. The status field and + * LUT index are updated as part of the response + */ +struct ice_aqc_sw_rules_elem_hdr { + __le16 type; /* Switch rule type, one of T_... */ +#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 +#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 +#define ICE_AQC_SW_RULES_T_LG_ACT 0x2 +#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 +#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 +#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 +#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 + __le16 status; +}; + /* Add/Update/Get/Remove lookup Rx/Tx command/response entry * This structures describes the lookup rules and associated actions. "index" * is returned as part of a response to a successful Add command, and can be * used to identify the rule for Update/Get/Remove commands. */ struct ice_sw_rule_lkup_rx_tx { + struct ice_aqc_sw_rules_elem_hdr hdr; + __le16 recipe_id; #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ @@ -866,6 +884,8 @@ struct ice_sw_rule_lkup_rx_tx { #define ICE_SINGLE_ACT_PTR 0x2 #define ICE_SINGLE_ACT_PTR_VAL_S 4 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) + /* Bit 17 should be set if pointed action includes a FWD cmd */ +#define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17) /* Bit 18 should be set to 1 */ #define ICE_SINGLE_ACT_PTR_BIT BIT(18) @@ -895,14 +915,17 @@ struct ice_sw_rule_lkup_rx_tx { * lookup-type */ __le16 hdr_len; - u8 hdr[STRUCT_HACK_VAR_LEN]; + u8 hdr_data[STRUCT_HACK_VAR_LEN]; }; +#pragma pack(1) /* Add/Update/Remove large action command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the action for Update/Get/Remove commands. */ struct ice_sw_rule_lg_act { + struct ice_aqc_sw_rules_elem_hdr hdr; + __le16 index; /* Index in large action table */ __le16 size; /* Max number of large actions */ @@ -957,16 +980,21 @@ struct ice_sw_rule_lg_act { #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ }; +#pragma pack() +#pragma pack(1) /* Add/Update/Remove VSI list command/response entry * "index" is returned as part of a response to a successful Add command, and * can be used to identify the VSI list for Update/Get/Remove commands. */ struct ice_sw_rule_vsi_list { + struct ice_aqc_sw_rules_elem_hdr hdr; + __le16 index; /* Index of VSI/Prune list */ __le16 number_vsi; __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ }; +#pragma pack() #pragma pack(1) /* Query VSI list command/response entry */ @@ -976,31 +1004,6 @@ struct ice_sw_rule_vsi_list_query { }; #pragma pack() -#pragma pack(1) -/* Add switch rule response: - * Content of return buffer is same as the input buffer. The status field and - * LUT index are updated as part of the response - */ -struct ice_aqc_sw_rules_elem { - __le16 type; /* Switch rule type, one of T_... */ -#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 -#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 -#define ICE_AQC_SW_RULES_T_LG_ACT 0x2 -#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 -#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 -#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 -#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 - __le16 status; - union { - struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; - struct ice_sw_rule_lg_act lg_act; - struct ice_sw_rule_vsi_list vsi_list; - struct ice_sw_rule_vsi_list_query vsi_list_query; - } pdata; -}; - -#pragma pack() - /* PFC Ignore (direct 0x0301) * The command and response use the same descriptor structure */ @@ -2771,7 +2774,7 @@ struct ice_aqc_move_txqs_data { }; /* Download Package (indirect 0x0C40) */ -/* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ +/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ struct ice_aqc_download_pkg { u8 flags; #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index cd6237136e..31fec80735 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -19,7 +19,7 @@ #define ICE_MPLS_ETHER_ID 0x8847 #define ICE_ETH_P_8021Q 0x8100 -/* Dummy ethernet header needed in the ice_aqc_sw_rules_elem +/* Dummy ethernet header needed in the ice_sw_rule_* * struct to configure any switch filter rules. * {DA (6 bytes), SA(6 bytes), * Ether type (2 bytes for header without VLAN tag) OR @@ -3744,7 +3744,8 @@ static void ice_fill_sw_info(struct ice_hw *hw, struct ice_fltr_info *fi) */ static void ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info, - struct ice_aqc_sw_rules_elem *s_rule, enum ice_adminq_opc opc) + struct ice_sw_rule_lkup_rx_tx *s_rule, + enum ice_adminq_opc opc) { u16 vlan_id = ICE_MAX_VLAN_ID + 1; u16 vlan_tpid = ICE_ETH_P_8021Q; @@ -3756,15 +3757,14 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info, u8 q_rgn; if (opc == ice_aqc_opc_remove_sw_rules) { - s_rule->pdata.lkup_tx_rx.act = 0; - s_rule->pdata.lkup_tx_rx.index = - CPU_TO_LE16(f_info->fltr_rule_id); - s_rule->pdata.lkup_tx_rx.hdr_len = 0; + s_rule->act = 0; + s_rule->index = CPU_TO_LE16(f_info->fltr_rule_id); + s_rule->hdr_len = 0; return; } eth_hdr_sz = sizeof(dummy_eth_header); - eth_hdr = s_rule->pdata.lkup_tx_rx.hdr; + eth_hdr = s_rule->hdr_data; /* initialize the ether header with a dummy header */ ice_memcpy(eth_hdr, dummy_eth_header, eth_hdr_sz, ICE_NONDMA_TO_NONDMA); @@ -3849,14 +3849,14 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info, break; } - s_rule->type = (f_info->flag & ICE_FLTR_RX) ? + s_rule->hdr.type = (f_info->flag & ICE_FLTR_RX) ? CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX) : CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX); /* Recipe set depending on lookup type */ - s_rule->pdata.lkup_tx_rx.recipe_id = CPU_TO_LE16(f_info->lkup_type); - s_rule->pdata.lkup_tx_rx.src = CPU_TO_LE16(f_info->src); - s_rule->pdata.lkup_tx_rx.act = CPU_TO_LE32(act); + s_rule->recipe_id = CPU_TO_LE16(f_info->lkup_type); + s_rule->src = CPU_TO_LE16(f_info->src); + s_rule->act = CPU_TO_LE32(act); if (daddr) ice_memcpy(eth_hdr + ICE_ETH_DA_OFFSET, daddr, ETH_ALEN, @@ -3871,7 +3871,7 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info, /* Create the switch rule with the final dummy Ethernet header */ if (opc != ice_aqc_opc_update_sw_rules) - s_rule->pdata.lkup_tx_rx.hdr_len = CPU_TO_LE16(eth_hdr_sz); + s_rule->hdr_len = CPU_TO_LE16(eth_hdr_sz); } /** @@ -3888,7 +3888,8 @@ static enum ice_status ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, u16 sw_marker, u16 l_id) { - struct ice_aqc_sw_rules_elem *lg_act, *rx_tx; + struct ice_sw_rule_lkup_rx_tx *rx_tx; + struct ice_sw_rule_lg_act *lg_act; /* For software marker we need 3 large actions * 1. FWD action: FWD TO VSI or VSI LIST * 2. GENERIC VALUE action to hold the profile ID @@ -3909,18 +3910,19 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, * 1. Large Action * 2. Look up Tx Rx */ - lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_lg_acts); - rules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE; - lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size); + lg_act_size = (u16)ice_struct_size(lg_act, act, num_lg_acts); + rules_size = lg_act_size + + ice_struct_size(rx_tx, hdr_data, DUMMY_ETH_HDR_LEN); + lg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size); if (!lg_act) return ICE_ERR_NO_MEMORY; - rx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size); + rx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + lg_act_size); /* Fill in the first switch rule i.e. large action */ - lg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); - lg_act->pdata.lg_act.index = CPU_TO_LE16(l_id); - lg_act->pdata.lg_act.size = CPU_TO_LE16(num_lg_acts); + lg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); + lg_act->index = CPU_TO_LE16(l_id); + lg_act->size = CPU_TO_LE16(num_lg_acts); /* First action VSI forwarding or VSI list forwarding depending on how * many VSIs @@ -3932,13 +3934,13 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, act |= (id << ICE_LG_ACT_VSI_LIST_ID_S) & ICE_LG_ACT_VSI_LIST_ID_M; if (m_ent->vsi_count > 1) act |= ICE_LG_ACT_VSI_LIST; - lg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act); + lg_act->act[0] = CPU_TO_LE32(act); /* Second action descriptor type */ act = ICE_LG_ACT_GENERIC; act |= (1 << ICE_LG_ACT_GENERIC_VALUE_S) & ICE_LG_ACT_GENERIC_VALUE_M; - lg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act); + lg_act->act[1] = CPU_TO_LE32(act); act = (ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX << ICE_LG_ACT_GENERIC_OFFSET_S) & ICE_LG_ACT_GENERIC_OFFSET_M; @@ -3948,24 +3950,22 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, act |= (sw_marker << ICE_LG_ACT_GENERIC_VALUE_S) & ICE_LG_ACT_GENERIC_VALUE_M; - lg_act->pdata.lg_act.act[2] = CPU_TO_LE32(act); + lg_act->act[2] = CPU_TO_LE32(act); /* call the fill switch rule to fill the lookup Tx Rx structure */ ice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx, ice_aqc_opc_update_sw_rules); /* Update the action to point to the large action ID */ - rx_tx->pdata.lkup_tx_rx.act = - CPU_TO_LE32(ICE_SINGLE_ACT_PTR | - ((l_id << ICE_SINGLE_ACT_PTR_VAL_S) & - ICE_SINGLE_ACT_PTR_VAL_M)); + rx_tx->act = CPU_TO_LE32(ICE_SINGLE_ACT_PTR | + ((l_id << ICE_SINGLE_ACT_PTR_VAL_S) & + ICE_SINGLE_ACT_PTR_VAL_M)); /* Use the filter rule ID of the previously created rule with single * act. Once the update happens, hardware will treat this as large * action */ - rx_tx->pdata.lkup_tx_rx.index = - CPU_TO_LE16(m_ent->fltr_info.fltr_rule_id); + rx_tx->index = CPU_TO_LE16(m_ent->fltr_info.fltr_rule_id); status = ice_aq_sw_rules(hw, lg_act, rules_size, 2, ice_aqc_opc_update_sw_rules, NULL); @@ -3989,8 +3989,8 @@ static enum ice_status ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, u16 counter_id, u16 l_id) { - struct ice_aqc_sw_rules_elem *lg_act; - struct ice_aqc_sw_rules_elem *rx_tx; + struct ice_sw_rule_lkup_rx_tx *rx_tx; + struct ice_sw_rule_lg_act *lg_act; enum ice_status status; /* 2 actions will be added while adding a large action counter */ const int num_acts = 2; @@ -4008,18 +4008,20 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, * 1. Large Action * 2. Look up Tx Rx */ - lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_acts); - rules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE; - lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size); + lg_act_size = (u16)ice_struct_size(lg_act, act, num_acts); + rules_size = lg_act_size + + ice_struct_size(rx_tx, hdr_data, DUMMY_ETH_HDR_LEN); + lg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size); if (!lg_act) return ICE_ERR_NO_MEMORY; - rx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size); + rx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + + lg_act_size); /* Fill in the first switch rule i.e. large action */ - lg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); - lg_act->pdata.lg_act.index = CPU_TO_LE16(l_id); - lg_act->pdata.lg_act.size = CPU_TO_LE16(num_acts); + lg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); + lg_act->index = CPU_TO_LE16(l_id); + lg_act->size = CPU_TO_LE16(num_acts); /* First action VSI forwarding or VSI list forwarding depending on how * many VSIs @@ -4032,13 +4034,13 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, ICE_LG_ACT_VSI_LIST_ID_M; if (m_ent->vsi_count > 1) act |= ICE_LG_ACT_VSI_LIST; - lg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act); + lg_act->act[0] = CPU_TO_LE32(act); /* Second action counter ID */ act = ICE_LG_ACT_STAT_COUNT; act |= (counter_id << ICE_LG_ACT_STAT_COUNT_S) & ICE_LG_ACT_STAT_COUNT_M; - lg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act); + lg_act->act[1] = CPU_TO_LE32(act); /* call the fill switch rule to fill the lookup Tx Rx structure */ ice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx, @@ -4046,14 +4048,14 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent, act = ICE_SINGLE_ACT_PTR; act |= (l_id << ICE_SINGLE_ACT_PTR_VAL_S) & ICE_SINGLE_ACT_PTR_VAL_M; - rx_tx->pdata.lkup_tx_rx.act = CPU_TO_LE32(act); + rx_tx->act = CPU_TO_LE32(act); /* Use the filter rule ID of the previously created rule with single * act. Once the update happens, hardware will treat this as large * action */ f_rule_id = m_ent->fltr_info.fltr_rule_id; - rx_tx->pdata.lkup_tx_rx.index = CPU_TO_LE16(f_rule_id); + rx_tx->index = CPU_TO_LE16(f_rule_id); status = ice_aq_sw_rules(hw, lg_act, rules_size, 2, ice_aqc_opc_update_sw_rules, NULL); @@ -4115,7 +4117,7 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi, u16 vsi_list_id, bool remove, enum ice_adminq_opc opc, enum ice_sw_lkup_type lkup_type) { - struct ice_aqc_sw_rules_elem *s_rule; + struct ice_sw_rule_vsi_list *s_rule; enum ice_status status; u16 s_rule_size; u16 rule_type; @@ -4140,8 +4142,8 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi, else return ICE_ERR_PARAM; - s_rule_size = (u16)ICE_SW_RULE_VSI_LIST_SIZE(num_vsi); - s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size); + s_rule_size = (u16)ice_struct_size(s_rule, vsi, num_vsi); + s_rule = (struct ice_sw_rule_vsi_list *)ice_malloc(hw, s_rule_size); if (!s_rule) return ICE_ERR_NO_MEMORY; for (i = 0; i < num_vsi; i++) { @@ -4150,13 +4152,13 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi, goto exit; } /* AQ call requires hw_vsi_id(s) */ - s_rule->pdata.vsi_list.vsi[i] = + s_rule->vsi[i] = CPU_TO_LE16(ice_get_hw_vsi_num(hw, vsi_handle_arr[i])); } - s_rule->type = CPU_TO_LE16(rule_type); - s_rule->pdata.vsi_list.number_vsi = CPU_TO_LE16(num_vsi); - s_rule->pdata.vsi_list.index = CPU_TO_LE16(vsi_list_id); + s_rule->hdr.type = CPU_TO_LE16(rule_type); + s_rule->number_vsi = CPU_TO_LE16(num_vsi); + s_rule->index = CPU_TO_LE16(vsi_list_id); status = ice_aq_sw_rules(hw, s_rule, s_rule_size, 1, opc, NULL); @@ -4205,11 +4207,12 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list, struct ice_fltr_list_entry *f_entry) { struct ice_fltr_mgmt_list_entry *fm_entry; - struct ice_aqc_sw_rules_elem *s_rule; + struct ice_sw_rule_lkup_rx_tx *s_rule; enum ice_status status; - s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE); + s_rule = (struct ice_sw_rule_lkup_rx_tx *) + ice_malloc(hw, ice_struct_size(s_rule, hdr_data, + DUMMY_ETH_HDR_LEN)); if (!s_rule) return ICE_ERR_NO_MEMORY; fm_entry = (struct ice_fltr_mgmt_list_entry *) @@ -4230,17 +4233,17 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list, ice_fill_sw_rule(hw, &fm_entry->fltr_info, s_rule, ice_aqc_opc_add_sw_rules); - status = ice_aq_sw_rules(hw, s_rule, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE, 1, - ice_aqc_opc_add_sw_rules, NULL); + status = ice_aq_sw_rules(hw, s_rule, + ice_struct_size(s_rule, hdr_data, + DUMMY_ETH_HDR_LEN), + 1, ice_aqc_opc_add_sw_rules, NULL); if (status) { ice_free(hw, fm_entry); goto ice_create_pkt_fwd_rule_exit; } - f_entry->fltr_info.fltr_rule_id = - LE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index); - fm_entry->fltr_info.fltr_rule_id = - LE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index); + f_entry->fltr_info.fltr_rule_id = LE16_TO_CPU(s_rule->index); + fm_entry->fltr_info.fltr_rule_id = LE16_TO_CPU(s_rule->index); /* The book keeping entries will get removed when base driver * calls remove filter AQ command @@ -4263,21 +4266,24 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list, static enum ice_status ice_update_pkt_fwd_rule(struct ice_hw *hw, struct ice_fltr_info *f_info) { - struct ice_aqc_sw_rules_elem *s_rule; + struct ice_sw_rule_lkup_rx_tx *s_rule; enum ice_status status; - s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE); + s_rule = (struct ice_sw_rule_lkup_rx_tx *) + ice_malloc(hw, ice_struct_size(s_rule, hdr_data, + DUMMY_ETH_HDR_LEN)); if (!s_rule) return ICE_ERR_NO_MEMORY; ice_fill_sw_rule(hw, f_info, s_rule, ice_aqc_opc_update_sw_rules); - s_rule->pdata.lkup_tx_rx.index = CPU_TO_LE16(f_info->fltr_rule_id); + s_rule->index = CPU_TO_LE16(f_info->fltr_rule_id); /* Update switch rule with new rule set to forward VSI list */ - status = ice_aq_sw_rules(hw, s_rule, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE, 1, - ice_aqc_opc_update_sw_rules, NULL); + status = ice_aq_sw_rules(hw, s_rule, + ice_struct_size(s_rule, hdr_data, + DUMMY_ETH_HDR_LEN), + 1, ice_aqc_opc_update_sw_rules, NULL); ice_free(hw, s_rule); return status; @@ -4742,10 +4748,10 @@ ice_remove_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list, if (remove_rule) { /* Remove the lookup rule */ - struct ice_aqc_sw_rules_elem *s_rule; + struct ice_sw_rule_lkup_rx_tx *s_rule; - s_rule = (struct ice_aqc_sw_rules_elem *) - ice_malloc(hw, ICE_SW_RULE_RX_TX_NO_HDR_SIZE); + s_rule = (struct ice_sw_rule_lkup_rx_tx *) + ice_malloc(hw, ice_struct_size(s_rule, hdr_data, 0)); if (!s_rule) { status = ICE_ERR_NO_MEMORY; goto exit; @@ -4755,8 +4761,8 @@ ice_remove_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list, ice_aqc_opc_remove_sw_rules); status = ice_aq_sw_rules(hw, s_rule, - ICE_SW_RULE_RX_TX_NO_HDR_SIZE, 1, - ice_aqc_opc_remove_sw_rules, NULL); + ice_struct_size(s_rule, hdr_data, 0), + 1, ice_aqc_opc_remove_sw_rules, NULL); /* Remove a book keeping from the list */ ice_free(hw, s_rule); @@ -4872,7 +4878,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, struct ice_switch_info *sw, u8 lport) { struct ice_sw_recipe *recp_list = &sw->recp_list[ICE_SW_LKUP_MAC]; - struct ice_aqc_sw_rules_elem *s_rule, *r_iter; + struct ice_sw_rule_lkup_rx_tx *s_rule, *r_iter; struct ice_fltr_list_entry *m_list_itr; struct LIST_HEAD_TYPE *rule_head; u16 total_elem_left, s_rule_size; @@ -4933,8 +4939,8 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, } /* Allocate switch rule buffer for the bulk update for unicast */ - s_rule_size = ICE_SW_RULE_RX_TX_ETH_HDR_SIZE; - s_rule = (struct ice_aqc_sw_rules_elem *) + s_rule_size = ice_struct_size(s_rule, hdr_data, DUMMY_ETH_HDR_LEN); + s_rule = (struct ice_sw_rule_lkup_rx_tx *) ice_calloc(hw, num_unicast, s_rule_size); if (!s_rule) { status = ICE_ERR_NO_MEMORY; @@ -4950,7 +4956,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, if (IS_UNICAST_ETHER_ADDR(mac_addr)) { ice_fill_sw_rule(hw, &m_list_itr->fltr_info, r_iter, ice_aqc_opc_add_sw_rules); - r_iter = (struct ice_aqc_sw_rules_elem *) + r_iter = (struct ice_sw_rule_lkup_rx_tx *) ((u8 *)r_iter + s_rule_size); } } @@ -4960,7 +4966,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, /* Call AQ switch rule in AQ_MAX chunk */ for (total_elem_left = num_unicast; total_elem_left > 0; total_elem_left -= elem_sent) { - struct ice_aqc_sw_rules_elem *entry = r_iter; + struct ice_sw_rule_lkup_rx_tx *entry = r_iter; elem_sent = MIN_T(u8, total_elem_left, (ICE_AQ_MAX_BUF_LEN / s_rule_size)); @@ -4969,7 +4975,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, NULL); if (status) goto ice_add_mac_exit; - r_iter = (struct ice_aqc_sw_rules_elem *) + r_iter = (struct ice_sw_rule_lkup_rx_tx *) ((u8 *)r_iter + (elem_sent * s_rule_size)); } @@ -4983,7 +4989,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, if (IS_UNICAST_ETHER_ADDR(mac_addr)) { f_info->fltr_rule_id = - LE16_TO_CPU(r_iter->pdata.lkup_tx_rx.index); + LE16_TO_CPU(r_iter->index); f_info->fltr_act = ICE_FWD_TO_VSI; /* Create an entry to track this MAC address */ fm_entry = (struct ice_fltr_mgmt_list_entry *) @@ -4999,7 +5005,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list, */ LIST_ADD(&fm_entry->list_entry, rule_head); - r_iter = (struct ice_aqc_sw_rules_elem *) + r_iter = (struct ice_sw_rule_lkup_rx_tx *) ((u8 *)r_iter + s_rule_size); } } @@ -8521,7 +8527,7 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, */ static enum ice_status ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, - struct ice_aqc_sw_rules_elem *s_rule, + struct ice_sw_rule_lkup_rx_tx *s_rule, const u8 *dummy_pkt, u16 pkt_len, const struct ice_dummy_pkt_offsets *offsets) { @@ -8531,7 +8537,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, /* Start with a packet with a pre-defined/dummy content. Then, fill * in the header values to be looked up or matched. */ - pkt = s_rule->pdata.lkup_tx_rx.hdr; + pkt = s_rule->hdr_data; ice_memcpy(pkt, dummy_pkt, pkt_len, ICE_NONDMA_TO_NONDMA); @@ -8636,7 +8642,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, ((u16 *)&lkups[i].m_u)[j]); } - s_rule->pdata.lkup_tx_rx.hdr_len = CPU_TO_LE16(pkt_len); + s_rule->hdr_len = CPU_TO_LE16(pkt_len); return ICE_SUCCESS; } @@ -8922,15 +8928,15 @@ ice_set_lg_action_entry(u8 act_type, union lg_act_entry *lg_entry) * Fill a large action to hold software marker and link the lookup rule * with an action pointing to this larger action */ -static struct ice_aqc_sw_rules_elem * +static struct ice_sw_rule_lg_act * ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id, u16 lkup_rule_sz, u16 lg_act_size, u16 num_lg_acts, - struct ice_aqc_sw_rules_elem *s_rule) + struct ice_sw_rule_lkup_rx_tx *s_rule) { - struct ice_aqc_sw_rules_elem *rx_tx, *lg_act; + struct ice_sw_rule_lkup_rx_tx *rx_tx; const u16 offset_generic_md_word_0 = 0; const u16 offset_generic_md_word_1 = 1; - enum ice_status status = ICE_SUCCESS; + struct ice_sw_rule_lg_act *lg_act; union lg_act_entry lg_e_lo; union lg_act_entry lg_e_hi; const u8 priority = 0x3; @@ -8939,19 +8945,19 @@ ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id, /* For software marker we need 2 large actions for 32 bit mark id */ rules_size = lg_act_size + lkup_rule_sz; - lg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size); + lg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size); if (!lg_act) return NULL; - rx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size); + rx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + lg_act_size); ice_memcpy(rx_tx, s_rule, lkup_rule_sz, ICE_NONDMA_TO_NONDMA); ice_free(hw, s_rule); s_rule = NULL; - lg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); - lg_act->pdata.lg_act.index = CPU_TO_LE16(l_id); - lg_act->pdata.lg_act.size = CPU_TO_LE16(num_lg_acts); + lg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT); + lg_act->index = CPU_TO_LE16(l_id); + lg_act->size = CPU_TO_LE16(num_lg_acts); /* GENERIC VALUE action to hold the software marker ID low 16 bits */ /* and set in meta data index 4 by default. */ @@ -8959,7 +8965,7 @@ ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id, lg_e_lo.generic_act.offset = offset_generic_md_word_0; lg_e_lo.generic_act.priority = priority; act = ice_set_lg_action_entry(ICE_LG_ACT_GENERIC, &lg_e_lo); - lg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act); + lg_act->act[0] = CPU_TO_LE32(act); if (num_lg_acts == 1) return lg_act; @@ -8971,7 +8977,7 @@ ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id, lg_e_hi.generic_act.offset = offset_generic_md_word_1; lg_e_hi.generic_act.priority = priority; act = ice_set_lg_action_entry(ICE_LG_ACT_GENERIC, &lg_e_hi); - lg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act); + lg_act->act[1] = CPU_TO_LE32(act); return lg_act; } @@ -9000,11 +9006,12 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, struct ice_rule_query_data *added_entry) { struct ice_adv_fltr_mgmt_list_entry *m_entry, *adv_fltr = NULL; - u16 lg_act_size, lg_act_id = ICE_INVAL_LG_ACT_INDEX; + u16 lg_act_sz, lg_act_id = ICE_INVAL_LG_ACT_INDEX; u16 rid = 0, i, pkt_len, rule_buf_sz, vsi_handle; const struct ice_dummy_pkt_offsets *pkt_offsets; - struct ice_aqc_sw_rules_elem *s_rule = NULL; - struct ice_aqc_sw_rules_elem *rx_tx; + struct ice_sw_rule_lg_act *lg_rule = NULL; + struct ice_sw_rule_lkup_rx_tx *s_rule = NULL; + struct ice_sw_rule_lkup_rx_tx *rx_tx; struct LIST_HEAD_TYPE *rule_head; struct ice_switch_info *sw; u16 nb_lg_acts_mark = 1; @@ -9093,8 +9100,8 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, } return status; } - rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE + pkt_len; - s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rule_buf_sz); + rule_buf_sz = ice_struct_size(s_rule, hdr_data, 0) + pkt_len; + s_rule = (struct ice_sw_rule_lkup_rx_tx *)ice_malloc(hw, rule_buf_sz); if (!s_rule) return ICE_ERR_NO_MEMORY; if (!rinfo->flags_info.act_valid) @@ -9145,24 +9152,23 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, goto err_ice_add_adv_rule; } - /* set the rule LOOKUP type based on caller specified 'RX' + /* Set the rule LOOKUP type based on caller specified 'Rx' * instead of hardcoding it to be either LOOKUP_TX/RX * - * for 'RX' set the source to be the port number - * for 'TX' set the source to be the source HW VSI number (determined + * for 'Rx' set the source to be the port number + * for 'Tx' set the source to be the source HW VSI number (determined * by caller) */ if (rinfo->rx) { - s_rule->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX); - s_rule->pdata.lkup_tx_rx.src = - CPU_TO_LE16(hw->port_info->lport); + s_rule->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX); + s_rule->src = CPU_TO_LE16(hw->port_info->lport); } else { - s_rule->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX); - s_rule->pdata.lkup_tx_rx.src = CPU_TO_LE16(rinfo->sw_act.src); + s_rule->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX); + s_rule->src = CPU_TO_LE16(rinfo->sw_act.src); } - s_rule->pdata.lkup_tx_rx.recipe_id = CPU_TO_LE16(rid); - s_rule->pdata.lkup_tx_rx.act = CPU_TO_LE32(act); + s_rule->recipe_id = CPU_TO_LE16(rid); + s_rule->act = CPU_TO_LE32(act); status = ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt, pkt_len, pkt_offsets); @@ -9172,7 +9178,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, if (rinfo->tun_type != ICE_NON_TUN && rinfo->tun_type != ICE_SW_TUN_AND_NON_TUN) { status = ice_fill_adv_packet_tun(hw, rinfo->tun_type, - s_rule->pdata.lkup_tx_rx.hdr, + s_rule->hdr_data, pkt_offsets); if (status) goto err_ice_add_adv_rule; @@ -9180,18 +9186,19 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, rx_tx = s_rule; if (rinfo->sw_act.fltr_act == ICE_SET_MARK) { - lg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(nb_lg_acts_mark); - s_rule = ice_fill_sw_marker_lg_act(hw, rinfo->sw_act.markid, - lg_act_id, rule_buf_sz, - lg_act_size, nb_lg_acts_mark, - s_rule); - if (!s_rule) + lg_act_sz = (u16)ice_struct_size(lg_rule, act, nb_lg_acts_mark); + lg_rule = ice_fill_sw_marker_lg_act(hw, rinfo->sw_act.markid, + lg_act_id, rule_buf_sz, + lg_act_sz, nb_lg_acts_mark, + s_rule); + if (!lg_rule) goto err_ice_add_adv_rule; - rule_buf_sz += lg_act_size; + s_rule = (struct ice_sw_rule_lkup_rx_tx *)lg_rule; + rule_buf_sz += lg_act_sz; num_rules += 1; - rx_tx = (struct ice_aqc_sw_rules_elem *) - ((u8 *)s_rule + lg_act_size); + rx_tx = (struct ice_sw_rule_lkup_rx_tx *) + ((u8 *)s_rule + lg_act_sz); } status = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule, @@ -9221,7 +9228,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, adv_fltr->lkups_cnt = lkups_cnt; adv_fltr->rule_info = *rinfo; adv_fltr->rule_info.fltr_rule_id = - LE16_TO_CPU(rx_tx->pdata.lkup_tx_rx.index); + LE16_TO_CPU(rx_tx->index); adv_fltr->rule_info.lg_id = LE16_TO_CPU(lg_act_id); sw = hw->switch_info; sw->recp_list[rid].adv_rule = true; @@ -9363,9 +9370,9 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, { struct ice_adv_fltr_mgmt_list_entry *list_elem; struct ice_prot_lkup_ext lkup_exts; + bool remove_rule = false; struct ice_lock *rule_lock; /* Lock to protect filter rule list */ enum ice_status status = ICE_SUCCESS; - bool remove_rule = false; u16 i, rid, vsi_handle; ice_memset(&lkup_exts, 0, sizeof(lkup_exts), ICE_NONDMA_MEM); @@ -9416,23 +9423,21 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, } ice_release_lock(rule_lock); if (remove_rule) { - struct ice_aqc_sw_rules_elem *s_rule; + struct ice_sw_rule_lkup_rx_tx *s_rule; u16 rule_buf_sz; if (rinfo->sw_act.fltr_act == ICE_SET_MARK) ice_free_sw_marker_lg(hw, list_elem->rule_info.lg_id, rinfo->sw_act.markid); - rule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE; - s_rule = (struct ice_aqc_sw_rules_elem *) + rule_buf_sz = ice_struct_size(s_rule, hdr_data, 0); + s_rule = (struct ice_sw_rule_lkup_rx_tx *) ice_malloc(hw, rule_buf_sz); if (!s_rule) return ICE_ERR_NO_MEMORY; - s_rule->pdata.lkup_tx_rx.act = 0; - s_rule->pdata.lkup_tx_rx.index = - CPU_TO_LE16(list_elem->rule_info.fltr_rule_id); - s_rule->pdata.lkup_tx_rx.hdr_len = 0; - status = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule, - rule_buf_sz, 1, + s_rule->act = 0; + s_rule->index = CPU_TO_LE16(list_elem->rule_info.fltr_rule_id); + s_rule->hdr_len = 0; + status = ice_aq_sw_rules(hw, s_rule, rule_buf_sz, 1, ice_aqc_opc_remove_sw_rules, NULL); if (status == ICE_SUCCESS || status == ICE_ERR_DOES_NOT_EXIST) { struct ice_switch_info *sw = hw->switch_info; @@ -9488,20 +9493,20 @@ ice_rem_adv_rule_by_id(struct ice_hw *hw, /** * ice_rem_adv_rule_for_vsi - removes existing advanced switch rules for a - * given VSI handle + * given VSI handle * @hw: pointer to the hardware structure * @vsi_handle: VSI handle for which we are supposed to remove all the rules. * * This function is used to remove all the rules for a given VSI and as soon * as removing a rule fails, it will return immediately with the error code, - * else it will return ICE_SUCCESS + * else it will return success. */ enum ice_status ice_rem_adv_rule_for_vsi(struct ice_hw *hw, u16 vsi_handle) { struct ice_adv_fltr_mgmt_list_entry *list_itr, *tmp_entry; struct ice_vsi_list_map_info *map_info; - struct LIST_HEAD_TYPE *list_head; struct ice_adv_rule_info rinfo; + struct LIST_HEAD_TYPE *list_head; struct ice_switch_info *sw; enum ice_status status; u8 rid; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 7a12619459..c55ef19a8c 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -71,18 +71,6 @@ #define ICE_PROFID_IPV6_PFCP_SESSION 82 #define DUMMY_ETH_HDR_LEN 16 -#define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \ - (offsetof(struct ice_aqc_sw_rules_elem, pdata.lkup_tx_rx.hdr) + \ - (DUMMY_ETH_HDR_LEN * \ - sizeof(((struct ice_sw_rule_lkup_rx_tx *)0)->hdr[0]))) -#define ICE_SW_RULE_RX_TX_NO_HDR_SIZE \ - (offsetof(struct ice_aqc_sw_rules_elem, pdata.lkup_tx_rx.hdr)) -#define ICE_SW_RULE_LG_ACT_SIZE(n) \ - (offsetof(struct ice_aqc_sw_rules_elem, pdata.lg_act.act) + \ - ((n) * sizeof(((struct ice_sw_rule_lg_act *)0)->act[0]))) -#define ICE_SW_RULE_VSI_LIST_SIZE(n) \ - (offsetof(struct ice_aqc_sw_rules_elem, pdata.vsi_list.vsi) + \ - ((n) * sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi[0]))) /* Worst case buffer length for ice_aqc_opc_get_res_alloc */ #define ICE_MAX_RES_TYPES 0x80 From patchwork Thu Apr 27 06:19:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126570 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93B7942A08; Thu, 27 Apr 2023 08:38:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CF1E142D53; Thu, 27 Apr 2023 08:37:53 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 28C5A42D48 for ; Thu, 27 Apr 2023 08:37:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577471; x=1714113471; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kZiEtGOE2kAA0eZWGi0MeUpPXuvYwhLwQRD2HoTXCsM=; b=JvfY3pQ30EpKvd7V6baburgnfWcV5kycCsiIjNX2JNFJ7TxBG9mEnfRF /fIefv+3fqBpRndwhBE3OuWmkyhJo7fQYv49fdHOLZw9mCrSsZ2Uddfbc +r7MAENIy6osuEd52WwlbfRMCNygawyX+7XXhuE8slomvfXAlX7uNPfS5 +DvjntzEKaAfl7JKSiQb9mgzN3cWM/NETaqWkPavCTajoKJMyLUthP7VE 5GASJZsGt62fglyXDFhvWcrIuTIwyE/QPqf/e/aRT4KtRI3ts6zWTd0R6 SQ98s383kTaFb7dlzGDKbuQXgpSxzqOHOojJze6uWAtALZjTO/INuYKy7 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324260" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324260" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845665" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845665" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:47 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jacob Keller Subject: [PATCH 03/30] net/ice/base: remove unnecessary control queue array Date: Thu, 27 Apr 2023 06:19:34 +0000 Message-Id: <20230427062001.478032-4-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The driver allocates a cmd_buf array in addition to the desc_buf array. This array stores an ice_sq_cd command details structure for each entry in the control queue ring. And improve debug print for control queue messages. Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_controlq.c | 107 +++++++++++++++------------- drivers/net/ice/base/ice_controlq.h | 3 - 2 files changed, 56 insertions(+), 54 deletions(-) diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c index c34407b48c..acd6ad249b 100644 --- a/drivers/net/ice/base/ice_controlq.c +++ b/drivers/net/ice/base/ice_controlq.c @@ -101,13 +101,6 @@ ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq) if (!cq->sq.desc_buf.va) return ICE_ERR_NO_MEMORY; - cq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries, - sizeof(struct ice_sq_cd)); - if (!cq->sq.cmd_buf) { - ice_free_dma_mem(hw, &cq->sq.desc_buf); - return ICE_ERR_NO_MEMORY; - } - return ICE_SUCCESS; } @@ -176,7 +169,7 @@ ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq) if (cq->rq_buf_size > ICE_AQ_LG_BUF) desc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB); desc->opcode = 0; - /* This is in accordance with Admin queue design, there is no + /* This is in accordance with control queue design, there is no * register for buffer size configuration */ desc->datalen = CPU_TO_LE16(bi->size); @@ -309,9 +302,6 @@ do { \ ice_free_dma_mem((hw), \ &(qi)->ring.r.ring##_bi[i]); \ } \ - /* free the buffer info list */ \ - if ((qi)->ring.cmd_buf) \ - ice_free(hw, (qi)->ring.cmd_buf); \ /* free DMA head */ \ ice_free(hw, (qi)->ring.dma_head); \ } while (0) @@ -379,11 +369,11 @@ static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq) } /** - * ice_init_rq - initialize ARQ + * ice_init_rq - initialize receive side of a control queue * @hw: pointer to the hardware structure * @cq: pointer to the specific Control queue * - * The main initialization routine for the Admin Receive (Event) Queue. + * The main initialization routine for Receive side of a control queue. * Prior to calling this function, the driver *MUST* set the following fields * in the cq->structure: * - cq->num_rq_entries @@ -441,7 +431,7 @@ static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq) } /** - * ice_shutdown_sq - shutdown the Control ATQ + * ice_shutdown_sq - shutdown the transmit side of a control queue * @hw: pointer to the hardware structure * @cq: pointer to the specific Control queue * @@ -461,7 +451,7 @@ ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq) goto shutdown_sq_out; } - /* Stop firmware AdminQ processing */ + /* Stop processing of the control queue */ wr32(hw, cq->sq.head, 0); wr32(hw, cq->sq.tail, 0); wr32(hw, cq->sq.len, 0); @@ -834,7 +824,7 @@ void ice_destroy_all_ctrlq(struct ice_hw *hw) } /** - * ice_clean_sq - cleans Admin send queue (ATQ) + * ice_clean_sq - cleans send side of a control queue * @hw: pointer to the hardware structure * @cq: pointer to the specific Control queue * @@ -844,21 +834,17 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq) { struct ice_ctl_q_ring *sq = &cq->sq; u16 ntc = sq->next_to_clean; - struct ice_sq_cd *details; struct ice_aq_desc *desc; desc = ICE_CTL_Q_DESC(*sq, ntc); - details = ICE_CTL_Q_DETAILS(*sq, ntc); while (rd32(hw, cq->sq.head) != ntc) { ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head)); ice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM); - ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM); ntc++; if (ntc == sq->count) ntc = 0; desc = ICE_CTL_Q_DESC(*sq, ntc); - details = ICE_CTL_Q_DETAILS(*sq, ntc); } sq->next_to_clean = ntc; @@ -866,16 +852,42 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq) return ICE_CTL_Q_DESC_UNUSED(sq); } +/** + * ice_ctl_q_str - Convert control queue type to string + * @qtype: the control queue type + * + * Returns: A string name for the given control queue type. + */ +static const char *ice_ctl_q_str(enum ice_ctl_q qtype) +{ + switch (qtype) { + case ICE_CTL_Q_UNKNOWN: + return "Unknown CQ"; + case ICE_CTL_Q_ADMIN: + return "AQ"; + case ICE_CTL_Q_MAILBOX: + return "MBXQ"; + case ICE_CTL_Q_SB: + return "SBQ"; + default: + return "Unrecognized CQ"; + } +} + /** * ice_debug_cq * @hw: pointer to the hardware structure + * @cq: pointer to the specific Control queue * @desc: pointer to control queue descriptor * @buf: pointer to command buffer * @buf_len: max length of buf + * @response: true if this is the writeback response * * Dumps debug log about control command with descriptor contents. */ -static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len) +static void +ice_debug_cq(struct ice_hw *hw, struct ice_ctl_q_info *cq, + void *desc, void *buf, u16 buf_len, bool response) { struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; u16 datalen, flags; @@ -889,7 +901,8 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len) datalen = LE16_TO_CPU(cq_desc->datalen); flags = LE16_TO_CPU(cq_desc->flags); - ice_debug(hw, ICE_DBG_AQ_DESC, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", + ice_debug(hw, ICE_DBG_AQ_DESC, "%s %s: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", + ice_ctl_q_str(cq->qtype), response ? "Response" : "Command", LE16_TO_CPU(cq_desc->opcode), flags, datalen, LE16_TO_CPU(cq_desc->retval)); ice_debug(hw, ICE_DBG_AQ_DESC, "\tcookie (h,l) 0x%08X 0x%08X\n", @@ -914,23 +927,23 @@ static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len) } /** - * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ) + * ice_sq_done - check if the last send on a control queue has completed * @hw: pointer to the HW struct * @cq: pointer to the specific Control queue * - * Returns true if the firmware has processed all descriptors on the - * admin send queue. Returns false if there are still requests pending. + * Returns: true if all the descriptors on the send side of a control queue + * are finished processing, false otherwise. */ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq) { - /* AQ designers suggest use of head for better + /* control queue designers suggest use of head for better * timing reliability than DD bit */ return rd32(hw, cq->sq.head) == cq->sq.next_to_use; } /** - * ice_sq_send_cmd_nolock - send command to Control Queue (ATQ) + * ice_sq_send_cmd_nolock - send command to a control queue * @hw: pointer to the HW struct * @cq: pointer to the specific Control queue * @desc: prefilled descriptor describing the command (non DMA mem) @@ -938,8 +951,9 @@ static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq) * @buf_size: size of buffer for indirect commands (or 0 for direct commands) * @cd: pointer to command details structure * - * This is the main send command routine for the ATQ. It runs the queue, - * cleans the queue, etc. + * This is the main send command routine for a control queue. It prepares the + * command into a descriptor, bumps the send queue tail, waits for the command + * to complete, captures status and data for the command, etc. */ enum ice_status ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, @@ -950,7 +964,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, struct ice_aq_desc *desc_on_ring; bool cmd_completed = false; enum ice_status status = ICE_SUCCESS; - struct ice_sq_cd *details; u32 total_delay = 0; u16 retval = 0; u32 val = 0; @@ -993,12 +1006,6 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, goto sq_send_command_error; } - details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use); - if (cd) - *details = *cd; - else - ice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM); - /* Call clean and check queue available function to reclaim the * descriptors that were processed by FW/MBX; the function returns the * number of desc available. The clean function called here could be @@ -1035,8 +1042,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, /* Debug desc and buffer */ ice_debug(hw, ICE_DBG_AQ_DESC, "ATQ: Control Send queue desc and buffer:\n"); - - ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size); + ice_debug_cq(hw, cq, (void *)desc_on_ring, buf, buf_size, false); (cq->sq.next_to_use)++; if (cq->sq.next_to_use == cq->sq.count) @@ -1084,13 +1090,12 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, } ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n"); - - ice_debug_cq(hw, (void *)desc, buf, buf_size); + ice_debug_cq(hw, cq, (void *)desc, buf, buf_size, true); /* save writeback AQ if requested */ - if (details->wb_desc) - ice_memcpy(details->wb_desc, desc_on_ring, - sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA); + if (cd && cd->wb_desc) + ice_memcpy(cd->wb_desc, desc_on_ring, + sizeof(*cd->wb_desc), ICE_DMA_TO_NONDMA); /* update the error if time out occurred */ if (!cmd_completed) { @@ -1109,7 +1114,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, } /** - * ice_sq_send_cmd - send command to Control Queue (ATQ) + * ice_sq_send_cmd - send command to a control queue * @hw: pointer to the HW struct * @cq: pointer to the specific Control queue * @desc: prefilled descriptor describing the command @@ -1117,8 +1122,9 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, * @buf_size: size of buffer for indirect commands (or 0 for direct commands) * @cd: pointer to command details structure * - * This is the main send command routine for the ATQ. It runs the queue, - * cleans the queue, etc. + * Main command for the transmit side of a control queue. It puts the command + * on the queue, bumps the tail, waits for processing of the command, captures + * command status and results, etc. */ enum ice_status ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, @@ -1160,9 +1166,9 @@ void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode) * @e: event info from the receive descriptor, includes any buffers * @pending: number of events that could be left to process * - * This function cleans one Admin Receive Queue element and returns - * the contents through e. It can also return how many events are - * left to process through 'pending'. + * Clean one element from the receive side of a control queue. On return 'e' + * contains contents of the message, and 'pending' contains the number of + * events left to process. */ enum ice_status ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, @@ -1218,8 +1224,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, e->msg_len, ICE_DMA_TO_NONDMA); ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n"); - - ice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size); + ice_debug_cq(hw, cq, (void *)desc, e->msg_buf, cq->rq_buf_size, true); /* Restore the original datalen and buffer address in the desc, * FW updates datalen to indicate the event message size diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h index 986604ec3c..5c60469693 100644 --- a/drivers/net/ice/base/ice_controlq.h +++ b/drivers/net/ice/base/ice_controlq.h @@ -43,7 +43,6 @@ enum ice_ctl_q { struct ice_ctl_q_ring { void *dma_head; /* Virtual address to DMA head */ struct ice_dma_mem desc_buf; /* descriptor ring memory */ - void *cmd_buf; /* command buffer memory */ union { struct ice_dma_mem *sq_bi; @@ -73,8 +72,6 @@ struct ice_sq_cd { struct ice_aq_desc *wb_desc; }; -#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) - /* rq event information */ struct ice_rq_event_info { struct ice_aq_desc desc; From patchwork Thu Apr 27 06:19:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126571 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C735A42A08; Thu, 27 Apr 2023 08:38:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09D2C42D5E; Thu, 27 Apr 2023 08:37:55 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id EC3DF42D2D for ; Thu, 27 Apr 2023 08:37:52 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577473; x=1714113473; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gWentlx+9rzeM7saZOVSLmbcup++26Q6uwOVK0rP5aE=; b=XuCBpqA86Pw89qaNgQ/K1UGI5tJrmMeBb5chROGrhB73wESOq8Kx8ySe +S60M5LF+G7wBBDOYizN1xdrC6zbMix4QeA5NCCuwevGHAO9qX1unFBiO gxzJ4dx47fSWwIkZ2YzEuQMmntWu6OMyfnbUk58zoj94usoofmy94QLaY KVEkvHUTqQsnhr63S+sA6bZN5gZ4oMXDoEDtXrvCO8OwwaJACkHNdlOvH M3elux7LT9uaw6+Ent4pJt8mT1fDJrkwjsgK31tFeREhMOy6bU86CFQHw iLHhlKD6g3aKS7JCU13V/yZoSvo5gCjfUlSfTizIAzImyuLgRugSpCxId w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324269" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324269" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845673" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845673" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:49 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Ashish Shah Subject: [PATCH 04/30] net/ice/base: update flow seg fields to declared bitmaps Date: Thu, 27 Apr 2023 06:19:35 +0000 Message-Id: <20230427062001.478032-5-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org ice_flow_seg_info fields match and range are being used with bit operations but not declared as bitmaps. This can cause issues when casting values greater than 32. This change is to declare them as proper bitmaps so that the bitmap operations can function as intended. Signed-off-by: Ashish Shah Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_flow.c | 74 +++++++++++++++++++++++---------- drivers/net/ice/base/ice_flow.h | 6 ++- 2 files changed, 56 insertions(+), 24 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 5254ee27ed..8db394471c 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -1132,6 +1132,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); } + if ((hdrs & ICE_FLOW_SEG_HDR_IPV4) && (hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) { src = i ? @@ -1371,7 +1372,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw, */ static enum ice_status ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, - u8 seg, enum ice_flow_field fld, u64 match) + u8 seg, enum ice_flow_field fld, ice_bitmap_t *match) { enum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX; u8 fv_words = (u8)hw->blk[params->blk].es.fvw; @@ -1420,7 +1421,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, /* If the sibling field is also included, that field's * mask needs to be included. */ - if (match & BIT(sib)) + if (ice_is_bit_set(match, sib)) sib_mask = ice_flds_info[sib].mask; break; case ICE_FLOW_FIELD_IDX_IPV6_TTL: @@ -1451,7 +1452,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, /* If the sibling field is also included, that field's * mask needs to be included. */ - if (match & BIT(sib)) + if (ice_is_bit_set(match, sib)) sib_mask = ice_flds_info[sib].mask; break; case ICE_FLOW_FIELD_IDX_IPV4_SA: @@ -1722,15 +1723,16 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw, } for (i = 0; i < params->prof->segs_cnt; i++) { - u64 match = params->prof->segs[i].match; + ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX); enum ice_flow_field j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&match, - ICE_FLOW_FIELD_IDX_MAX) { + ice_cp_bitmap(match, params->prof->segs[i].match, + ICE_FLOW_FIELD_IDX_MAX); + ice_for_each_set_bit(j, match, ICE_FLOW_FIELD_IDX_MAX) { status = ice_flow_xtract_fld(hw, params, i, j, match); if (status) return status; - ice_clear_bit(j, (ice_bitmap_t *)&match); + ice_clear_bit(j, match); } /* Process raw matching bytes */ @@ -1789,7 +1791,7 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params) struct ice_flow_seg_info *seg = ¶ms->prof->segs[i]; u16 j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match, + ice_for_each_set_bit(j, seg->match, (u16)ICE_FLOW_FIELD_IDX_MAX) { struct ice_flow_fld_info *fld = &seg->fields[j]; @@ -1932,7 +1934,10 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk, for (i = 0; i < segs_cnt; i++) if (segs[i].hdrs != p->segs[i].hdrs || ((conds & ICE_FLOW_FIND_PROF_CHK_FLDS) && - segs[i].match != p->segs[i].match)) + (ice_cmp_bitmap(segs[i].match, + p->segs[i].match, + ICE_FLOW_FIELD_IDX_MAX) == + false))) break; /* A match is found if all segments are matched */ @@ -2432,7 +2437,7 @@ ice_flow_acl_set_xtrct_seq(struct ice_hw *hw, struct ice_flow_prof *prof) struct ice_flow_seg_info *seg = &prof->segs[i]; u16 j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match, + ice_for_each_set_bit(j, seg->match, ICE_FLOW_FIELD_IDX_MAX) { info = &seg->fields[j]; @@ -2601,7 +2606,8 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16 dest_vsi_handle, idx = i; params->es[idx].prot_id = prof->fv[i].proto_id; params->es[idx].off = prof->fv[i].offset; - params->mask[idx] = CPU_TO_BE16(prof->fv[i].msk); + params->mask[idx] = (((prof->fv[i].msk) << 8) & 0xff00) | + (((prof->fv[i].msk) >> 8) & 0x00ff); } switch (prof->flags) { @@ -3002,7 +3008,7 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof, struct ice_flow_seg_info *seg = &prof->segs[i]; u16 j; - ice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match, + ice_for_each_set_bit(j, seg->match, (u16)ICE_FLOW_FIELD_IDX_MAX) { struct ice_flow_fld_info *info = &seg->fields[j]; @@ -3534,7 +3540,7 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk, if (entry_h == ICE_FLOW_ENTRY_HANDLE_INVAL) return ICE_ERR_PARAM; - entry = ICE_FLOW_ENTRY_PTR((intptr_t)entry_h); + entry = ICE_FLOW_ENTRY_PTR(entry_h); /* Retain the pointer to the flow profile as the entry will be freed */ prof = entry->prof; @@ -3576,11 +3582,9 @@ ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld, enum ice_flow_fld_match_type field_type, u16 val_loc, u16 mask_loc, u16 last_loc) { - u64 bit = BIT_ULL(fld); - - seg->match |= bit; + ice_set_bit(fld, seg->match); if (field_type == ICE_FLOW_FLD_TYPE_RANGE) - seg->range |= bit; + ice_set_bit(fld, seg->range); seg->fields[fld].type = field_type; seg->fields[fld].src.val = val_loc; @@ -3741,7 +3745,7 @@ enum ice_status ice_flow_rem_vsi_prof(struct ice_hw *hw, enum ice_block blk, u16 } #define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \ -(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_ETH_NON_IP | ICE_FLOW_SEG_HDR_VLAN) +(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \ (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6) @@ -3856,6 +3860,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) const enum ice_block blk = ICE_BLK_RSS; struct ice_flow_prof *p, *t; enum ice_status status = ICE_SUCCESS; + u16 vsig; if (!ice_is_vsi_valid(hw, vsi_handle)) return ICE_ERR_PARAM; @@ -3865,7 +3870,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) ice_acquire_lock(&hw->rss_locks); LIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof, - l_entry) + l_entry) { + int ret; + + /* check if vsig is already removed */ + ret = ice_vsig_find_vsi(hw, blk, + ice_get_hw_vsi_num(hw, vsi_handle), + &vsig); + if (!ret && !vsig) + break; + if (ice_is_bit_set(p->vsis, vsi_handle)) { status = ice_flow_disassoc_prof(hw, blk, p, vsi_handle); if (status) @@ -3877,6 +3891,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle) break; } } + } ice_release_lock(&hw->rss_locks); return status; @@ -3918,6 +3933,14 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) { enum ice_rss_cfg_hdr_type hdr_type; struct ice_rss_cfg *r, *tmp; + u64 seg_match = 0; + u16 i; + + /* convert match bitmap to u64 for hash field comparison */ + ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match, + ICE_FLOW_FIELD_IDX_MAX) { + seg_match |= 1ULL << i; + } /* Search for RSS hash fields associated to the VSI that match the * hash configurations associated to the flow profile. If found @@ -3926,7 +3949,7 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) hdr_type = ice_get_rss_hdr_type(prof); LIST_FOR_EACH_ENTRY_SAFE(r, tmp, &hw->rss_list_head, ice_rss_cfg, l_entry) - if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match && + if (r->hash.hash_flds == seg_match && r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs && r->hash.hdr_type == hdr_type) { ice_clear_bit(vsi_handle, r->vsis); @@ -3951,11 +3974,18 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) { enum ice_rss_cfg_hdr_type hdr_type; struct ice_rss_cfg *r, *rss_cfg; + u64 seg_match = 0; + u16 i; + + ice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match, + ICE_FLOW_FIELD_IDX_MAX) { + seg_match |= 1ULL << i; + } hdr_type = ice_get_rss_hdr_type(prof); LIST_FOR_EACH_ENTRY(r, &hw->rss_list_head, ice_rss_cfg, l_entry) - if (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match && + if (r->hash.hash_flds == seg_match && r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs && r->hash.hdr_type == hdr_type) { ice_set_bit(vsi_handle, r->vsis); @@ -3966,7 +3996,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof) if (!rss_cfg) return ICE_ERR_NO_MEMORY; - rss_cfg->hash.hash_flds = prof->segs[prof->segs_cnt - 1].match; + rss_cfg->hash.hash_flds = seg_match; rss_cfg->hash.addl_hdrs = prof->segs[prof->segs_cnt - 1].hdrs; rss_cfg->hash.hdr_type = hdr_type; rss_cfg->hash.symm = prof->cfg.symm; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 57e8e1f1df..1415f5ba87 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -452,8 +452,10 @@ struct ice_flow_seg_fld_raw { struct ice_flow_seg_info { u32 hdrs; /* Bitmask indicating protocol headers present */ - u64 match; /* Bitmask indicating header fields to be matched */ - u64 range; /* Bitmask indicating header fields matched as ranges */ + /* Bitmask indicating header fields to be matched */ + ice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX); + /* Bitmask indicating header fields matched as ranges */ + ice_declare_bitmap(range, ICE_FLOW_FIELD_IDX_MAX); struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX]; From patchwork Thu Apr 27 06:19:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126572 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85B3542A08; Thu, 27 Apr 2023 08:38:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A011042D75; Thu, 27 Apr 2023 08:37:57 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id D002542D59 for ; Thu, 27 Apr 2023 08:37:54 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577475; x=1714113475; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uCTGDlcQsj3vl0XcKoIBX0oM0jE4InE+k7FZrga8oiA=; b=LegkXi2ovp0lN1peNNMVyt37+M6QaS0nr8OEK8gX1IeCxBvvtJMhlgv3 6g77MmH2tbuCuYKQEmLdTSEbuWyeD/gaK27iOgSg8ZM9m1oPlp/4vZcXm nSFe0Di9QO3guYcGlKFamiu56DhoUh9ApBjzAiNP6r8WeDRXQbHeGgyNb Sd7MobYZlkEZc55+WToCJoIBe/CjTvL0Q8pR7TXgt8csyrPuKZ76+nMS+ /2MTfU6QlFQNX/mrDpCNAeW/PfM833v6k4Gbk9mAkc4kLvRtZJaj50vcy YVoVF6+njyqEWo7ELljYd2dN3QV5ljgh8pd1i06JVJfUc44/B4ESxjzx3 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324279" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324279" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845680" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845680" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:51 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Paul Greenwalt , Przemek Kitszel Subject: [PATCH 05/30] net/ice/base: clean up RSS LUT and fix media type Date: Thu, 27 Apr 2023 06:19:36 +0000 Message-Id: <20230427062001.478032-6-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Refactor __ice_aq_get_set_rss_lut(): - get variant: - make use params->lut_size only as a size of params->lut; - return LUT size via params->lut_size; - set: remove option to set RSS LUT smaller than available (eg forbid PF LUT sized 512); - both: clean up code. - fix get media type and add the media type ICE_MEDIA_NONE. Signed-off-by: Paul Greenwalt Signed-off-by: Przemek Kitszel Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 30 ++- drivers/net/ice/base/ice_common.c | 366 +++++++++++--------------- drivers/net/ice/base/ice_common.h | 1 + drivers/net/ice/base/ice_type.h | 94 ++++++- 4 files changed, 275 insertions(+), 216 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 69e528a8c9..8731f35022 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1401,7 +1401,18 @@ struct ice_aqc_get_phy_caps { #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) -#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 +#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) +#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) +#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) +#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) +#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) +#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) +#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) +#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) +#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13) +#define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14) +#define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15) +#define ICE_PHY_TYPE_HIGH_MAX_INDEX 15 struct ice_aqc_get_phy_caps_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ @@ -2191,6 +2202,19 @@ struct ice_aqc_get_set_rss_keys { u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; }; +enum ice_lut_type { + ICE_LUT_VSI = 0, + ICE_LUT_PF = 1, + ICE_LUT_GLOBAL = 2, + ICE_LUT_TYPE_MASK = 3 +}; + +enum ice_lut_size { + ICE_LUT_VSI_SIZE = 64, + ICE_LUT_GLOBAL_SIZE = 512, + ICE_LUT_PF_SIZE = 2048, +}; + /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ struct ice_aqc_get_set_rss_lut { #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) @@ -2199,7 +2223,7 @@ struct ice_aqc_get_set_rss_lut { __le16 vsi_id; #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ - (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) + (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 @@ -2207,7 +2231,7 @@ struct ice_aqc_get_set_rss_lut { #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ - (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) + (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index fa30c50ca1..006ffa802c 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -341,6 +341,93 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, return ICE_SUCCESS; } +/** + * ice_phy_maps_to_media + * @phy_type_low: PHY type low bits + * @phy_type_high: PHY type high bits + * @media_mask_low: media type PHY type low bitmask + * @media_mask_high: media type PHY type high bitmask + * + * Return true if PHY type [low|high] bits are only of media type PHY types + * [low|high] bitmask. + */ +static bool +ice_phy_maps_to_media(u64 phy_type_low, u64 phy_type_high, + u64 media_mask_low, u64 media_mask_high) +{ + /* check if a PHY type exist for media type */ + if (!(phy_type_low & media_mask_low || + phy_type_high & media_mask_high)) + return false; + + /* check that PHY types are only of media type */ + if (!(phy_type_low & ~media_mask_low) && + !(phy_type_high & ~media_mask_high)) + return true; + + return false; +} + +/** + * ice_set_media_type - Sets media type + * @pi: port information structure + * + * Set ice_port_info PHY media type based on PHY type. This should be called + * from Get PHY caps with media. + */ +static void ice_set_media_type(struct ice_port_info *pi) +{ + enum ice_media_type *media_type; + u64 phy_type_high, phy_type_low; + + phy_type_high = pi->phy.phy_type_high; + phy_type_low = pi->phy.phy_type_low; + media_type = &pi->phy.media_type; + + /* if no media, then media type is NONE */ + if (!(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE)) + *media_type = ICE_MEDIA_NONE; + /* else if PHY types are only BASE-T, then media type is BASET */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_BASET_PHY_TYPE_LOW_M, 0)) + *media_type = ICE_MEDIA_BASET; + /* else if any PHY type is BACKPLANE, then media type is BACKPLANE */ + else if (phy_type_low & ICE_MEDIA_BP_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_BP_PHY_TYPE_HIGH_M) + *media_type = ICE_MEDIA_BACKPLANE; + /* else if PHY types are only optical, or optical and C2M, then media + * type is FIBER + */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_OPT_PHY_TYPE_LOW_M, + ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) || + ((phy_type_low & ICE_MEDIA_OPT_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_OPT_PHY_TYPE_HIGH_M) && + (phy_type_low & ICE_MEDIA_C2M_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M))) + *media_type = ICE_MEDIA_FIBER; + /* else if PHY types are only DA, or DA and C2C, then media type DA */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_DAC_PHY_TYPE_LOW_M, + ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) || + ((phy_type_low & ICE_MEDIA_DAC_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_DAC_PHY_TYPE_HIGH_M) && + (phy_type_low & ICE_MEDIA_C2C_PHY_TYPE_LOW_M || + phy_type_high & ICE_MEDIA_C2C_PHY_TYPE_HIGH_M))) + *media_type = ICE_MEDIA_DA; + /* else if PHY types are only C2M or only C2C, then media is AUI */ + else if (ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_C2M_PHY_TYPE_LOW_M, + ICE_MEDIA_C2M_PHY_TYPE_HIGH_M) || + ice_phy_maps_to_media(phy_type_low, phy_type_high, + ICE_MEDIA_C2C_PHY_TYPE_LOW_M, + ICE_MEDIA_C2C_PHY_TYPE_HIGH_M)) + *media_type = ICE_MEDIA_AUI; + + else + *media_type = ICE_MEDIA_UNKNOWN; +} + /** * ice_aq_get_phy_caps - returns PHY capabilities * @pi: port information structure @@ -425,6 +512,9 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, sizeof(pi->phy.link_info.module_type), ICE_NONDMA_TO_NONDMA); + ice_set_media_type(pi); + ice_debug(hw, ICE_DBG_LINK, "%s: media_type = 0x%x\n", prefix, + pi->phy.media_type); } return status; @@ -530,155 +620,6 @@ ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, return ICE_ERR_DOES_NOT_EXIST; } -/** - * ice_is_media_cage_present - * @pi: port information structure - * - * Returns true if media cage is present, else false. If no cage, then - * media type is backplane or BASE-T. - */ -static bool ice_is_media_cage_present(struct ice_port_info *pi) -{ - struct ice_aqc_get_link_topo *cmd; - struct ice_aq_desc desc; - - cmd = &desc.params.get_link_topo; - - ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); - - cmd->addr.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << - ICE_AQC_LINK_TOPO_NODE_CTX_S); - - /* set node type */ - cmd->addr.topo_params.node_type_ctx |= - (ICE_AQC_LINK_TOPO_NODE_TYPE_M & - ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE); - - /* Node type cage can be used to determine if cage is present. If AQC - * returns error (ENOENT), then no cage present. If no cage present then - * connection type is backplane or BASE-T. - */ - return ice_aq_get_netlist_node(pi->hw, cmd, NULL, NULL); -} - -/** - * ice_get_media_type - Gets media type - * @pi: port information structure - */ -static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) -{ - struct ice_link_status *hw_link_info; - - if (!pi) - return ICE_MEDIA_UNKNOWN; - - hw_link_info = &pi->phy.link_info; - if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) - /* If more than one media type is selected, report unknown */ - return ICE_MEDIA_UNKNOWN; - - if (hw_link_info->phy_type_low) { - /* 1G SGMII is a special case where some DA cable PHYs - * may show this as an option when it really shouldn't - * be since SGMII is meant to be between a MAC and a PHY - * in a backplane. Try to detect this case and handle it - */ - if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && - (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == - ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || - hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == - ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) - return ICE_MEDIA_DA; - - switch (hw_link_info->phy_type_low) { - case ICE_PHY_TYPE_LOW_1000BASE_SX: - case ICE_PHY_TYPE_LOW_1000BASE_LX: - case ICE_PHY_TYPE_LOW_10GBASE_SR: - case ICE_PHY_TYPE_LOW_10GBASE_LR: - case ICE_PHY_TYPE_LOW_25GBASE_SR: - case ICE_PHY_TYPE_LOW_25GBASE_LR: - case ICE_PHY_TYPE_LOW_40GBASE_SR4: - case ICE_PHY_TYPE_LOW_40GBASE_LR4: - case ICE_PHY_TYPE_LOW_50GBASE_SR2: - case ICE_PHY_TYPE_LOW_50GBASE_LR2: - case ICE_PHY_TYPE_LOW_50GBASE_SR: - case ICE_PHY_TYPE_LOW_50GBASE_FR: - case ICE_PHY_TYPE_LOW_50GBASE_LR: - case ICE_PHY_TYPE_LOW_100GBASE_SR4: - case ICE_PHY_TYPE_LOW_100GBASE_LR4: - case ICE_PHY_TYPE_LOW_100GBASE_SR2: - case ICE_PHY_TYPE_LOW_100GBASE_DR: - return ICE_MEDIA_FIBER; - case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: - case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: - case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: - case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: - case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: - case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: - case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: - case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: - return ICE_MEDIA_FIBER; - case ICE_PHY_TYPE_LOW_100BASE_TX: - case ICE_PHY_TYPE_LOW_1000BASE_T: - case ICE_PHY_TYPE_LOW_2500BASE_T: - case ICE_PHY_TYPE_LOW_5GBASE_T: - case ICE_PHY_TYPE_LOW_10GBASE_T: - case ICE_PHY_TYPE_LOW_25GBASE_T: - return ICE_MEDIA_BASET; - case ICE_PHY_TYPE_LOW_10G_SFI_DA: - case ICE_PHY_TYPE_LOW_25GBASE_CR: - case ICE_PHY_TYPE_LOW_25GBASE_CR_S: - case ICE_PHY_TYPE_LOW_25GBASE_CR1: - case ICE_PHY_TYPE_LOW_40GBASE_CR4: - case ICE_PHY_TYPE_LOW_50GBASE_CR2: - case ICE_PHY_TYPE_LOW_50GBASE_CP: - case ICE_PHY_TYPE_LOW_100GBASE_CR4: - case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: - case ICE_PHY_TYPE_LOW_100GBASE_CP2: - return ICE_MEDIA_DA; - case ICE_PHY_TYPE_LOW_25G_AUI_C2C: - case ICE_PHY_TYPE_LOW_40G_XLAUI: - case ICE_PHY_TYPE_LOW_50G_LAUI2: - case ICE_PHY_TYPE_LOW_50G_AUI2: - case ICE_PHY_TYPE_LOW_50G_AUI1: - case ICE_PHY_TYPE_LOW_100G_AUI4: - case ICE_PHY_TYPE_LOW_100G_CAUI4: - if (ice_is_media_cage_present(pi)) - return ICE_MEDIA_AUI; - /* fall-through */ - case ICE_PHY_TYPE_LOW_1000BASE_KX: - case ICE_PHY_TYPE_LOW_2500BASE_KX: - case ICE_PHY_TYPE_LOW_2500BASE_X: - case ICE_PHY_TYPE_LOW_5GBASE_KR: - case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: - case ICE_PHY_TYPE_LOW_10G_SFI_C2C: - case ICE_PHY_TYPE_LOW_25GBASE_KR: - case ICE_PHY_TYPE_LOW_25GBASE_KR1: - case ICE_PHY_TYPE_LOW_25GBASE_KR_S: - case ICE_PHY_TYPE_LOW_40GBASE_KR4: - case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: - case ICE_PHY_TYPE_LOW_50GBASE_KR2: - case ICE_PHY_TYPE_LOW_100GBASE_KR4: - case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: - return ICE_MEDIA_BACKPLANE; - } - } else { - switch (hw_link_info->phy_type_high) { - case ICE_PHY_TYPE_HIGH_100G_AUI2: - case ICE_PHY_TYPE_HIGH_100G_CAUI2: - if (ice_is_media_cage_present(pi)) - return ICE_MEDIA_AUI; - /* fall-through */ - case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: - return ICE_MEDIA_BACKPLANE; - case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: - case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: - return ICE_MEDIA_FIBER; - } - } - return ICE_MEDIA_UNKNOWN; -} /** * ice_aq_get_link_info @@ -696,7 +637,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, struct ice_aqc_get_link_status_data link_data = { 0 }; struct ice_aqc_get_link_status *resp; struct ice_link_status *li_old, *li; - enum ice_media_type *hw_media_type; struct ice_fc_info *hw_fc_info; bool tx_pause, rx_pause; struct ice_aq_desc desc; @@ -708,7 +648,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, return ICE_ERR_PARAM; hw = pi->hw; li_old = &pi->phy.link_info_old; - hw_media_type = &pi->phy.media_type; li = &pi->phy.link_info; hw_fc_info = &pi->fc; @@ -730,7 +669,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, li->link_speed = LE16_TO_CPU(link_data.link_speed); li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); - *hw_media_type = ice_get_media_type(pi); li->link_info = link_data.link_info; li->link_cfg_err = link_data.link_cfg_err; li->an_info = link_data.an_info; @@ -761,7 +699,6 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, (unsigned long long)li->phy_type_low); ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", (unsigned long long)li->phy_type_high); - ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); @@ -4087,6 +4024,51 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw, return ICE_SUCCESS; } +static u16 ice_lut_type_to_size(u16 lut_type) +{ + switch (lut_type) { + case ICE_LUT_VSI: + return ICE_LUT_VSI_SIZE; + case ICE_LUT_GLOBAL: + return ICE_LUT_GLOBAL_SIZE; + case ICE_LUT_PF: + return ICE_LUT_PF_SIZE; + default: + return 0; + } +} + +static u16 ice_lut_size_to_flag(u16 lut_size) +{ + u16 f = 0; + + switch (lut_size) { + case ICE_LUT_GLOBAL_SIZE: + f = ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG; + break; + case ICE_LUT_PF_SIZE: + f = ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG; + break; + default: + break; + } + return f << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S; +} + +int ice_lut_size_to_type(int lut_size) +{ + switch (lut_size) { + case ICE_LUT_VSI_SIZE: + return ICE_LUT_VSI; + case ICE_LUT_GLOBAL_SIZE: + return ICE_LUT_GLOBAL; + case ICE_LUT_PF_SIZE: + return ICE_LUT_PF; + default: + return -1; + } +} + /** * __ice_aq_get_set_rss_lut * @hw: pointer to the hardware structure @@ -4098,7 +4080,7 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw, static enum ice_status __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) { - u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; + u16 flags, vsi_id, lut_type, lut_size, glob_lut_idx = 0, vsi_handle; struct ice_aqc_get_set_rss_lut *cmd_resp; struct ice_aq_desc desc; enum ice_status status; @@ -4109,16 +4091,22 @@ __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params vsi_handle = params->vsi_handle; lut = params->lut; + lut_type = params->lut_type; + lut_size = ice_lut_type_to_size(lut_type); + cmd_resp = &desc.params.get_set_rss_lut; + if (lut_type == ICE_LUT_GLOBAL) + glob_lut_idx = params->global_lut_id; - if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) + if (!lut || !lut_size || !ice_is_vsi_valid(hw, vsi_handle)) return ICE_ERR_PARAM; - lut_size = params->lut_size; - lut_type = params->lut_type; - glob_lut_idx = params->global_lut_id; - vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); + if (lut_size > params->lut_size) + return ICE_ERR_INVAL_SIZE; - cmd_resp = &desc.params.get_set_rss_lut; + if (set && lut_size != params->lut_size) + return ICE_ERR_PARAM; + + vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); if (set) { ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); @@ -4132,61 +4120,15 @@ __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | ICE_AQC_GSET_RSS_LUT_VSI_VALID); - switch (lut_type) { - case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: - case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: - case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: - flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & - ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); - break; - default: - status = ICE_ERR_PARAM; - goto ice_aq_get_set_rss_lut_exit; - } - - if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { - flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & - ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); - - if (!set) - goto ice_aq_get_set_rss_lut_send; - } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { - if (!set) - goto ice_aq_get_set_rss_lut_send; - } else { - goto ice_aq_get_set_rss_lut_send; - } - - /* LUT size is only valid for Global and PF table types */ - switch (lut_size) { - case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: - flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << - ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & - ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; - break; - case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: - flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << - ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & - ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; - break; - case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: - if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { - flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << - ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & - ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; - break; - } - /* fall-through */ - default: - status = ICE_ERR_PARAM; - goto ice_aq_get_set_rss_lut_exit; - } + flags = ice_lut_size_to_flag(lut_size) | + ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & + ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M) | + ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & + ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); -ice_aq_get_set_rss_lut_send: cmd_resp->flags = CPU_TO_LE16(flags); status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); - -ice_aq_get_set_rss_lut_exit: + params->lut_size = LE16_TO_CPU(desc.datalen); return status; } diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index e1febfb0c4..f612ce7c52 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -100,6 +100,7 @@ ice_write_tx_drbell_q_ctx(struct ice_hw *hw, struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, u32 tx_drbell_q_index); +int ice_lut_size_to_type(int lut_size); enum ice_status ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); enum ice_status diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index da813c8307..3249e359de 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -210,7 +210,8 @@ enum ice_mac_type { /* Media Types */ enum ice_media_type { - ICE_MEDIA_UNKNOWN = 0, + ICE_MEDIA_NONE = 0, + ICE_MEDIA_UNKNOWN, ICE_MEDIA_FIBER, ICE_MEDIA_BASET, ICE_MEDIA_BACKPLANE, @@ -218,6 +219,97 @@ enum ice_media_type { ICE_MEDIA_AUI, }; +#define ICE_MEDIA_BASET_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100BASE_TX | \ + ICE_PHY_TYPE_LOW_1000BASE_T | \ + ICE_PHY_TYPE_LOW_2500BASE_T | \ + ICE_PHY_TYPE_LOW_5GBASE_T | \ + ICE_PHY_TYPE_LOW_10GBASE_T | \ + ICE_PHY_TYPE_LOW_25GBASE_T) + +#define ICE_MEDIA_C2M_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC | \ + ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC | \ + ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC | \ + ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC | \ + ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC | \ + ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC | \ + ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC | \ + ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) + +#define ICE_MEDIA_C2M_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC | \ + ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC | \ + ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC | \ + ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC) + +#define ICE_MEDIA_OPT_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_SX | \ + ICE_PHY_TYPE_LOW_1000BASE_LX | \ + ICE_PHY_TYPE_LOW_10GBASE_SR | \ + ICE_PHY_TYPE_LOW_10GBASE_LR | \ + ICE_PHY_TYPE_LOW_25GBASE_SR | \ + ICE_PHY_TYPE_LOW_25GBASE_LR | \ + ICE_PHY_TYPE_LOW_40GBASE_SR4 | \ + ICE_PHY_TYPE_LOW_40GBASE_LR4 | \ + ICE_PHY_TYPE_LOW_50GBASE_SR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_LR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_SR | \ + ICE_PHY_TYPE_LOW_50GBASE_LR | \ + ICE_PHY_TYPE_LOW_100GBASE_SR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_LR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_SR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_FR | \ + ICE_PHY_TYPE_LOW_100GBASE_DR) + +#define ICE_MEDIA_OPT_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_200G_SR4 | \ + ICE_PHY_TYPE_HIGH_200G_LR4 | \ + ICE_PHY_TYPE_HIGH_200G_FR4 | \ + ICE_PHY_TYPE_HIGH_200G_DR4 | \ + ICE_PHY_TYPE_HIGH_400GBASE_FR8) + +#define ICE_MEDIA_BP_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_1000BASE_KX | \ + ICE_PHY_TYPE_LOW_2500BASE_KX | \ + ICE_PHY_TYPE_LOW_5GBASE_KR | \ + ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 | \ + ICE_PHY_TYPE_LOW_25GBASE_KR | \ + ICE_PHY_TYPE_LOW_25GBASE_KR_S | \ + ICE_PHY_TYPE_LOW_25GBASE_KR1 | \ + ICE_PHY_TYPE_LOW_40GBASE_KR4 | \ + ICE_PHY_TYPE_LOW_50GBASE_KR2 | \ + ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 | \ + ICE_PHY_TYPE_LOW_100GBASE_KR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) + +#define ICE_MEDIA_BP_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 | \ + ICE_PHY_TYPE_HIGH_200G_KR4_PAM4) + +#define ICE_MEDIA_DAC_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_10G_SFI_DA | \ + ICE_PHY_TYPE_LOW_25GBASE_CR | \ + ICE_PHY_TYPE_LOW_25GBASE_CR_S | \ + ICE_PHY_TYPE_LOW_25GBASE_CR1 | \ + ICE_PHY_TYPE_LOW_40GBASE_CR4 | \ + ICE_PHY_TYPE_LOW_50GBASE_CR2 | \ + ICE_PHY_TYPE_LOW_100GBASE_CR4 | \ + ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 | \ + ICE_PHY_TYPE_LOW_50GBASE_CP | \ + ICE_PHY_TYPE_LOW_100GBASE_CP2) + +#define ICE_MEDIA_DAC_PHY_TYPE_HIGH_M ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 + +#define ICE_MEDIA_C2C_PHY_TYPE_LOW_M (ICE_PHY_TYPE_LOW_100M_SGMII | \ + ICE_PHY_TYPE_LOW_1G_SGMII | \ + ICE_PHY_TYPE_LOW_2500BASE_X | \ + ICE_PHY_TYPE_LOW_10G_SFI_C2C | \ + ICE_PHY_TYPE_LOW_25G_AUI_C2C | \ + ICE_PHY_TYPE_LOW_40G_XLAUI | \ + ICE_PHY_TYPE_LOW_50G_LAUI2 | \ + ICE_PHY_TYPE_LOW_50G_AUI2 | \ + ICE_PHY_TYPE_LOW_50G_AUI1 | \ + ICE_PHY_TYPE_LOW_100G_CAUI4 | \ + ICE_PHY_TYPE_LOW_100G_AUI4) + +#define ICE_MEDIA_C2C_PHY_TYPE_HIGH_M (ICE_PHY_TYPE_HIGH_100G_CAUI2 | \ + ICE_PHY_TYPE_HIGH_100G_AUI2 | \ + ICE_PHY_TYPE_HIGH_200G_AUI4 | \ + ICE_PHY_TYPE_HIGH_200G_AUI8) + /* Software VSI types. */ enum ice_vsi_type { ICE_VSI_PF = 0, From patchwork Thu Apr 27 06:19:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126573 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0E3C42A08; Thu, 27 Apr 2023 08:38:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 342BD42D6C; Thu, 27 Apr 2023 08:37:59 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 6851542D46 for ; Thu, 27 Apr 2023 08:37:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577476; x=1714113476; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pADcOzUlbE8snxSSeTZx+QfLpkAHximSLLEIHUADapQ=; b=OoZfeMUvWlWJzCvJj1dtkqAWBFkvhivNQRBnQcXGgBPtJXp2Z9XOv1yP v/KaljhAPtbVVkmCTJZ6rVVJyvd4G4guT8fDz/gJ0HCea04ADqCa/fbrp awOmg0hhq25qa1vbgrB4qKyL2dzQsP737E7IzzokUk7N0YAT4F1QlnIak 2Wreu/jnVQ5xGSthc037gKb6RQAaLYIgaPPCNkb5qAC05KSssQjdf+V0H HkyLKvBxYRz0jkZFIDcbbR8eGmkHUe0eDa5NOKQGsQ6VND6MieNwQcddd dKQeWQoRGeGU4djCkDgIRgwzdGu/km2/EIUJBu7wS4rjft6mg61qJ+Ye4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324282" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324282" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845689" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845689" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:53 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Zhirun Yan Subject: [PATCH 06/30] net/ice/base: add ability to set markid via switch filter Date: Thu, 27 Apr 2023 06:19:37 +0000 Message-Id: <20230427062001.478032-7-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Support to add large action to set 32 bits markid via switch filter. For OVS-DPDK VXLAN acceleration solution, switch markid will be used for mega flow match for decap. For one ptype, the pattern may have different fields as follow: eth / ipv4 src / udp dst eth / ipv4 dst src / udp dst FDIR will have conflict with the same profile id. So we could chose switch to set markid. Signed-off-by: Zhirun Yan Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 17 ++++++++++- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_switch.c | 48 +++++++++++++++++++++++++++---- drivers/net/ice/base/ice_switch.h | 26 +++++++++-------- drivers/net/ice/base/ice_type.h | 3 ++ 5 files changed, 77 insertions(+), 19 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 006ffa802c..5bd40ece78 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2369,6 +2369,11 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, true : false; ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, caps->nvm_unified_update); + caps->netlist_auth = + (number & ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT) ? + true : false; + ice_debug(hw, ICE_DBG_INIT, "%s: netlist_auth = %d\n", prefix, + caps->netlist_auth); break; case ICE_AQC_CAPS_MAX_MTU: caps->max_mtu = number; @@ -3814,6 +3819,7 @@ enum ice_status ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, struct ice_sq_cd *cd) { + enum ice_status status = ICE_ERR_AQ_ERROR; struct ice_aqc_restart_an *cmd; struct ice_aq_desc desc; @@ -3828,7 +3834,16 @@ ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, else cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; - return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); + status = ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); + if (status) + return status; + + if (ena_link) + pi->phy.curr_user_phy_cfg.caps |= ICE_AQC_PHY_EN_LINK; + else + pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK; + + return ICE_SUCCESS; } /** diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 83cd152388..e3a638dcdd 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1057,11 +1057,11 @@ ice_sched_add_nodes_to_layer(struct ice_port_info *pi, u32 *first_teid_ptr = first_node_teid; u16 new_num_nodes = num_nodes; enum ice_status status = ICE_SUCCESS; + u32 temp; *num_nodes_added = 0; while (*num_nodes_added < num_nodes) { u16 max_child_nodes, num_added = 0; - u32 temp; status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent, layer, new_num_nodes, diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 31fec80735..dd4cc38114 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -2520,7 +2520,7 @@ ice_free_sw_marker_lg(struct ice_hw *hw, u16 marker_lg_id, u32 sw_marker) return ICE_ERR_NO_MEMORY; sw_buf->num_elems = CPU_TO_LE16(num_elems); - if (sw_marker == (sw_marker & 0xFFFF)) + if (sw_marker <= 0xFFFF) sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_1); else sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_2); @@ -4299,9 +4299,9 @@ enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw) { struct ice_fltr_mgmt_list_entry *fm_entry; enum ice_status status = ICE_SUCCESS; + struct ice_switch_info *sw = NULL; struct LIST_HEAD_TYPE *rule_head; struct ice_lock *rule_lock; /* Lock to protect filter rule list */ - struct ice_switch_info *sw; sw = hw->switch_info; rule_lock = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rule_lock; @@ -5545,7 +5545,7 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set, u8 direction) { struct ice_fltr_list_entry f_list_entry; - struct ice_sw_recipe *recp_list; + struct ice_sw_recipe *recp_list = NULL; struct ice_fltr_info f_info; struct ice_hw *hw = pi->hw; enum ice_status status; @@ -8698,6 +8698,36 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type, return ICE_ERR_CFG; } +/** + * ice_fill_adv_packet_vlan - fill dummy packet with VLAN tag type + * @vlan_type: VLAN tag type + * @pkt: dummy packet to fill in + * @offsets: offset info for the dummy packet + */ +static enum ice_status +ice_fill_adv_packet_vlan(u16 vlan_type, u8 *pkt, + const struct ice_dummy_pkt_offsets *offsets) +{ + u16 i; + + /* Find VLAN header and insert VLAN TPID */ + for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) { + if (offsets[i].type == ICE_VLAN_OFOS || + offsets[i].type == ICE_VLAN_EX) { + struct ice_vlan_hdr *hdr; + u16 offset; + + offset = offsets[i].offset; + hdr = (struct ice_vlan_hdr *)&pkt[offset]; + hdr->type = CPU_TO_BE16(vlan_type); + + return ICE_SUCCESS; + } + } + + return ICE_ERR_CFG; +} + /** * ice_find_adv_rule_entry - Search a rule entry * @hw: pointer to the hardware structure @@ -9131,7 +9161,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, ICE_SINGLE_ACT_Q_REGION_M; break; case ICE_SET_MARK: - if (rinfo->sw_act.markid != (rinfo->sw_act.markid & 0xFFFF)) + if (rinfo->sw_act.markid > 0xFFFF) nb_lg_acts_mark += 1; /* Allocate a hardware table entry to hold large act. */ status = ice_alloc_res_lg_act(hw, &lg_act_id, nb_lg_acts_mark); @@ -9184,6 +9214,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, goto err_ice_add_adv_rule; } + if (rinfo->vlan_type != 0 && ice_is_dvm_ena(hw)) { + status = ice_fill_adv_packet_vlan(rinfo->vlan_type, + s_rule->hdr_data, + pkt_offsets); + if (status) + goto err_ice_add_adv_rule; + } + rx_tx = s_rule; if (rinfo->sw_act.fltr_act == ICE_SET_MARK) { lg_act_sz = (u16)ice_struct_size(lg_rule, act, nb_lg_acts_mark); @@ -9752,7 +9790,7 @@ enum ice_status ice_replay_vsi_all_fltr(struct ice_hw *hw, struct ice_port_info *pi, u16 vsi_handle) { - struct ice_switch_info *sw; + struct ice_switch_info *sw = NULL; enum ice_status status; u8 i; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index c55ef19a8c..49bd535c79 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -207,19 +207,19 @@ struct ice_adv_lkup_elem { union ice_prot_hdr m_u; /* Mask of header values to match */ }; -struct lg_entry_vsi_fwd { +struct entry_vsi_fwd { u16 vsi_list; u8 list; u8 valid; }; -struct lg_entry_to_q { +struct entry_to_q { u16 q_idx; u8 q_region_sz; u8 q_pri; }; -struct lg_entry_prune { +struct entry_prune { u16 vsi_list; u8 list; u8 egr; @@ -227,28 +227,29 @@ struct lg_entry_prune { u8 prune_t; }; -struct lg_entry_mirror { +struct entry_mirror { u16 mirror_vsi; }; -struct lg_entry_generic_act { +struct entry_generic_act { u16 generic_value; u8 offset; u8 priority; }; -struct lg_entry_statistics { +struct entry_statistics { u8 counter_idx; }; union lg_act_entry { - struct lg_entry_vsi_fwd vsi_fwd; - struct lg_entry_to_q to_q; - struct lg_entry_prune prune; - struct lg_entry_mirror mirror; - struct lg_entry_generic_act generic_act; - struct lg_entry_statistics statistics; + struct entry_vsi_fwd vsi_fwd; + struct entry_to_q to_q; + struct entry_prune prune; + struct entry_mirror mirror; + struct entry_generic_act generic_act; + struct entry_statistics statistics; }; + struct ice_prof_type_entry { u16 prof_id; enum ice_sw_tunnel_type type; @@ -301,6 +302,7 @@ struct ice_adv_rule_info { u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */ u16 fltr_rule_id; u16 lg_id; + u16 vlan_type; struct ice_adv_rule_flags_info flags_info; }; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 3249e359de..b2df99e472 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -693,9 +693,11 @@ struct ice_hw_common_caps { bool sec_rev_disabled; bool update_disabled; bool nvm_unified_update; + bool netlist_auth; #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) +#define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5) /* PCIe reset avoidance */ bool pcie_reset_avoidance; /* false: not supported, true: supported */ /* Post update reset restriction */ @@ -1458,6 +1460,7 @@ enum ice_sw_fwd_act_type { ICE_FWD_TO_QGRP, ICE_SET_MARK, ICE_DROP_PACKET, + ICE_LG_ACTION, ICE_INVAL_ACT }; From patchwork Thu Apr 27 06:19:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126574 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1E9A42A08; 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a="375324289" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324289" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:37:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845696" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845696" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:55 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Eric Joyner , Grzegorz Nitka Subject: [PATCH 07/30] net/ice/base: add reading cap and ropo cap Date: Thu, 27 Apr 2023 06:19:38 +0000 Message-Id: <20230427062001.478032-8-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The driver can use this capability to see if temperature sensor reading or other HW sensor reading capabilities are supported before reading them using the Get Sensor Reading AQ command. Define and add parsing support for new device capability ICE_AQC_CAPS_NAC_TOPOLOGY. Signed-off-by: Eric Joyner Signed-off-by: Grzegorz Nitka Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 1 + drivers/net/ice/base/ice_common.c | 49 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_type.h | 13 +++++++ 3 files changed, 63 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 8731f35022..4c4fd27865 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -120,6 +120,7 @@ struct ice_aqc_list_caps_elem { #define ICE_AQC_CAPS_1588 0x0046 #define ICE_AQC_CAPS_MAX_MTU 0x0047 #define ICE_AQC_CAPS_IWARP 0x0051 +#define ICE_AQC_CAPS_SENSOR_READING 0x0067 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 5bd40ece78..a51a436df6 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2749,6 +2749,49 @@ ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, dev_p->num_flow_director_fltr); } +/** + * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap + * @hw: pointer to the HW struct + * @dev_p: pointer to device capabilities structure + * @cap: capability element to parse + * + * Parse ICE_AQC_CAPS_NAC_TOPOLOGY for device capabilities. + */ +static void +ice_parse_nac_topo_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, + struct ice_aqc_list_caps_elem *cap) +{ + dev_p->nac_topo.mode = LE32_TO_CPU(cap->number); + dev_p->nac_topo.id = LE32_TO_CPU(cap->phys_id) & ICE_NAC_TOPO_ID_M; + + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_primary = %d\n", + !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology is_dual = %d\n", + !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); + ice_debug(hw, ICE_DBG_INIT, "dev caps: nac topology id = %d\n", + dev_p->nac_topo.id); +} + +/** + * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap + * @hw: pointer to the HW struct + * @dev_p: pointer to device capabilities structure + * @cap: capability element to parse + * + * Parse ICE_AQC_CAPS_SENSOR_READING for device capability for reading + * enabled sensors. + */ +static void +ice_parse_sensor_reading_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, + struct ice_aqc_list_caps_elem *cap) +{ + dev_p->supported_sensors = LE32_TO_CPU(cap->number); + + ice_debug(hw, ICE_DBG_INIT, + "dev caps: supported sensors (bitmap) = 0x%x\n", + dev_p->supported_sensors); +} + /** * ice_parse_dev_caps - Parse device capabilities * @hw: pointer to the HW struct @@ -2794,6 +2837,12 @@ ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, case ICE_AQC_CAPS_FD: ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); break; + case ICE_AQC_CAPS_NAC_TOPOLOGY: + ice_parse_nac_topo_dev_caps(hw, dev_p, &cap_resp[i]); + break; + case ICE_AQC_CAPS_SENSOR_READING: + ice_parse_sensor_reading_cap(hw, dev_p, &cap_resp[i]); + break; default: /* Don't list common capabilities as unknown */ if (!found) diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index b2df99e472..17383ae23f 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -787,6 +787,15 @@ struct ice_ts_dev_info { u8 ts_ll_read : 1; }; +#define ICE_NAC_TOPO_PRIMARY_M BIT(0) +#define ICE_NAC_TOPO_DUAL_M BIT(1) +#define ICE_NAC_TOPO_ID_M MAKEMASK(0xf, 0) + +struct ice_nac_topology { + u32 mode; + u8 id; +}; + /* Function specific capabilities */ struct ice_hw_func_caps { struct ice_hw_common_caps common_cap; @@ -803,6 +812,10 @@ struct ice_hw_dev_caps { u32 num_flow_director_fltr; /* Number of FD filters available */ struct ice_ts_dev_info ts_dev_info; u32 num_funcs; + struct ice_nac_topology nac_topo; + /* bitmap of supported sensors */ + u32 supported_sensors; +#define ICE_SENSOR_SUPPORT_E810_INT_TEMP BIT(0) }; /* Information about MAC such as address, etc... */ From patchwork Thu Apr 27 06:19:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126575 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 34BB342A08; Thu, 27 Apr 2023 08:38:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CCC0742D9E; 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26 Apr 2023 23:37:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845704" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845704" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:57 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Martion Domagala Subject: [PATCH 08/30] net/ice/base: add function to read HW sensors Date: Thu, 27 Apr 2023 06:19:39 +0000 Message-Id: <20230427062001.478032-9-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adds new helper function to read from HW sensors via a new AQ command "Get Sensor Reading (0x0632)". Signed-off-by: Martion Domagala Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 29 +++++++++++++++++++++ drivers/net/ice/base/ice_common.c | 36 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_common.h | 6 +++-- 3 files changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 4c4fd27865..5a44ebbdc0 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1681,6 +1681,32 @@ struct ice_aqc_set_mac_lb { u8 reserved[15]; }; +/* Get sensor reading (direct 0x0632) */ +struct ice_aqc_get_sensor_reading { + u8 sensor; +#define ICE_AQC_INT_TEMP_SENSOR 0x0 + u8 format; +#define ICE_AQC_INT_TEMP_FORMAT 0x0 + u8 reserved[6]; + __le32 addr_high; + __le32 addr_low; +}; + +/* Get sensor reading response (direct 0x0632) */ +struct ice_aqc_get_sensor_reading_resp { + union { + u8 raw[8]; + /* Output data for sensor 0x00, format 0x00 */ + struct { + s8 temp; + u8 temp_warning_threshold; + u8 temp_critical_threshold; + u8 temp_fatal_threshold; + u8 reserved[4]; + } s0f0; + } data; +}; + struct ice_aqc_link_topo_params { u8 lport_num; u8 lport_num_valid; @@ -3032,6 +3058,8 @@ struct ice_aq_desc { struct ice_aqc_get_phy_caps get_phy; struct ice_aqc_set_phy_cfg set_phy; struct ice_aqc_restart_an restart_an; + struct ice_aqc_get_sensor_reading get_sensor_reading; + struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; struct ice_aqc_i2c read_write_i2c; struct ice_aqc_read_i2c_resp read_i2c_resp; struct ice_aqc_gpio read_write_gpio; @@ -3281,6 +3309,7 @@ enum ice_adminq_opc { ice_aqc_opc_get_link_status = 0x0607, ice_aqc_opc_set_event_mask = 0x0613, ice_aqc_opc_set_mac_lb = 0x0620, + ice_aqc_opc_get_sensor_reading = 0x0632, ice_aqc_opc_get_link_topo = 0x06E0, ice_aqc_opc_get_link_topo_pin = 0x06E1, ice_aqc_opc_read_i2c = 0x06E2, diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index a51a436df6..ed811e406d 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -5278,6 +5278,42 @@ ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, ICE_SCHED_NODE_OWNER_LAN); } +/** + * ice_aq_get_sensor_reading + * @hw: pointer to the HW struct + * @sensor: sensor type + * @format: requested response format + * @data: pointer to data to be read from the sensor + * @cd: pointer to command details structure or NULL + * + * Get sensor reading (0x0632) + */ +enum ice_status +ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, + struct ice_aqc_get_sensor_reading_resp *data, + struct ice_sq_cd *cd) +{ + struct ice_aqc_get_sensor_reading *cmd; + struct ice_aq_desc desc; + enum ice_status status; + + if (!data) + return ICE_ERR_PARAM; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sensor_reading); + cmd = &desc.params.get_sensor_reading; + cmd->sensor = sensor; + cmd->format = format; + + status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); + + if (!status) + ice_memcpy(data, &desc.params.get_sensor_reading_resp, + sizeof(*data), ICE_NONDMA_TO_NONDMA); + + return status; +} + /** * ice_is_main_vsi - checks whether the VSI is main VSI * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index f612ce7c52..ccefe85af7 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -29,7 +29,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw); void ice_deinit_hw(struct ice_hw *hw); enum ice_status ice_check_reset(struct ice_hw *hw); enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); - enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); @@ -61,7 +60,6 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, struct ice_aq_desc *desc, void *buf, u16 buf_size, struct ice_sq_cd *cd); void ice_clear_pxe_mode(struct ice_hw *hw); - enum ice_status ice_get_caps(struct ice_hw *hw); void ice_set_safe_mode_caps(struct ice_hw *hw); @@ -247,6 +245,10 @@ enum ice_status ice_sbq_rw_reg_lp(struct ice_hw *hw, void ice_sbq_lock(struct ice_hw *hw); void ice_sbq_unlock(struct ice_hw *hw); enum ice_status ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in); +enum ice_status +ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, + struct ice_aqc_get_sensor_reading_resp *data, + struct ice_sq_cd *cd); void ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat); From patchwork Thu Apr 27 06:19:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126576 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DDAE42A08; Thu, 27 Apr 2023 08:38:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC33242DA2; Thu, 27 Apr 2023 08:38:03 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id C274442D9B for ; Thu, 27 Apr 2023 08:38:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577481; 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26 Apr 2023 23:37:58 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Michal Wilczynski Subject: [PATCH 09/30] net/ice/base: add pre-allocate memory argument Date: Thu, 27 Apr 2023 06:19:40 +0000 Message-Id: <20230427062001.478032-10-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add an option to pre-allocate memory for ice_sched_node struct. Add new arguments to ice_sched_add() and ice_sched_add_elems() that allow for pre-allocation of memory for ice_sched_node struct Signed-off-by: Michal Wilczynski Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 4 +- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_dcb.c | 4 +- drivers/net/ice/base/ice_sched.c | 411 ++++++++++++++++++++++++-- drivers/net/ice/base/ice_sched.h | 71 ++++- drivers/net/ice/base/ice_type.h | 3 + 6 files changed, 466 insertions(+), 29 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 5a44ebbdc0..cd4a6ffddf 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1120,9 +1120,9 @@ struct ice_aqc_txsched_elem { u8 generic; #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 -#define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) +#define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 -#define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) +#define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index ed811e406d..984830ea37 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -5129,7 +5129,7 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, q_ctx->q_teid = LE32_TO_CPU(node.node_teid); /* add a leaf node into scheduler tree queue layer */ - status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); + status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); if (!status) status = ice_sched_replay_q_bw(pi, q_ctx); diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c index 2a308b02bf..ca418090bc 100644 --- a/drivers/net/ice/base/ice_dcb.c +++ b/drivers/net/ice/base/ice_dcb.c @@ -1370,7 +1370,7 @@ ice_add_dscp_tc_bw_tlv(struct ice_lldp_org_tlv *tlv, ICE_DSCP_SUBTYPE_TCBW); tlv->ouisubtype = HTONL(ouisubtype); - /* First Octet after subtype + /* First Octect after subtype * ---------------------------- * | RSV | CBS | RSV | Max TCs | * | 1b | 1b | 3b | 3b | @@ -1624,7 +1624,7 @@ ice_update_port_tc_tree_cfg(struct ice_port_info *pi, /* new TC */ status = ice_sched_query_elem(pi->hw, teid2, &elem); if (!status) - status = ice_sched_add_node(pi, 1, &elem); + status = ice_sched_add_node(pi, 1, &elem, NULL); if (status) break; /* update the TC number */ diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index e3a638dcdd..421a0085d6 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -143,12 +143,14 @@ ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, * @pi: port information structure * @layer: Scheduler layer of the node * @info: Scheduler element information from firmware + * @prealloc_node: preallocated ice_sched_node struct for SW DB * * This function inserts a scheduler node to the SW DB. */ enum ice_status ice_sched_add_node(struct ice_port_info *pi, u8 layer, - struct ice_aqc_txsched_elem_data *info) + struct ice_aqc_txsched_elem_data *info, + struct ice_sched_node *prealloc_node) { struct ice_aqc_txsched_elem_data elem; struct ice_sched_node *parent; @@ -176,7 +178,11 @@ ice_sched_add_node(struct ice_port_info *pi, u8 layer, status = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem); if (status) return status; - node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); + + if (prealloc_node) + node = prealloc_node; + else + node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); if (!node) return ICE_ERR_NO_MEMORY; if (hw->max_children[layer]) { @@ -901,13 +907,15 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes, * @num_nodes: number of nodes * @num_nodes_added: pointer to num nodes added * @first_node_teid: if new nodes are added then return the TEID of first node + * @prealloc_nodes: preallocated nodes struct for software DB * * This function add nodes to HW as well as to SW DB for a given layer */ -static enum ice_status +enum ice_status ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, struct ice_sched_node *parent, u8 layer, u16 num_nodes, - u16 *num_nodes_added, u32 *first_node_teid) + u16 *num_nodes_added, u32 *first_node_teid, + struct ice_sched_node **prealloc_nodes) { struct ice_sched_node *prev, *new_node; struct ice_aqc_add_elem *buf; @@ -953,7 +961,11 @@ ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, *num_nodes_added = num_nodes; /* add nodes to the SW DB */ for (i = 0; i < num_nodes; i++) { - status = ice_sched_add_node(pi, layer, &buf->generic[i]); + if (prealloc_nodes) + status = ice_sched_add_node(pi, layer, &buf->generic[i], prealloc_nodes[i]); + else + status = ice_sched_add_node(pi, layer, &buf->generic[i], NULL); + if (status != ICE_SUCCESS) { ice_debug(hw, ICE_DBG_SCHED, "add nodes in SW DB failed status =%d\n", status); @@ -1032,7 +1044,7 @@ ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi, } return ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, - num_nodes_added, first_node_teid); + num_nodes_added, first_node_teid, NULL); } /** @@ -1156,6 +1168,240 @@ static u8 ice_sched_get_agg_layer(struct ice_hw *hw) return hw->sw_entry_point_layer; } +/** + * ice_sched_set_l2_node_aq_elem - AQ element setup for L2 node creation + * @pi: port information structure + * @elem: admin queue command element + * + * Setup Admin Queue Command element to default values for L2 Tx node creation + */ +static enum ice_status +ice_sched_set_l2_node_aq_elem(struct ice_port_info *pi, + struct ice_aqc_txsched_elem_data *elem) +{ + if (!pi || !pi->root || !elem) + return ICE_ERR_PARAM; + + elem->parent_teid = pi->root->info.node_teid; + elem->data.elem_type = ICE_AQC_ELEM_TYPE_TC; + elem->data.valid_sections = + ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | + ICE_AQC_ELEM_VALID_EIR; + elem->data.generic = 0; + elem->data.cir_bw.bw_profile_idx = + CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); + elem->data.cir_bw.bw_alloc = + CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); + elem->data.eir_bw.bw_profile_idx = + CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); + elem->data.eir_bw.bw_alloc = + CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); + + return ICE_SUCCESS; +} + +/** + * ice_sched_add_dflt_l2_nodes - add default L2 TC nodes into Tx tree + * @pi: port information structure + * + * Function creates default L2 nodes configuration. FW provide TC0 node, + * here remaining TCs are added. + */ +enum ice_status ice_sched_add_dflt_l2_nodes(struct ice_port_info *pi) +{ + /* One node is already created by FW */ + const u16 num_nodes = ICE_MAX_CGD_PER_PORT - 1; + u16 i, buf_size, num_groups_added; + struct ice_aqc_add_elem *buf; + struct ice_sched_node *node; + enum ice_status status; + struct ice_hw *hw; + u32 teid; + + if (!pi || !pi->root) + return ICE_ERR_PARAM; + + hw = pi->hw; + + buf_size = ice_struct_size(buf, generic, num_nodes); + buf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size); + if (!buf) + return ICE_ERR_NO_MEMORY; + + ice_acquire_lock(&pi->sched_lock); + + buf->hdr.parent_teid = pi->root->info.node_teid; + buf->hdr.num_elems = CPU_TO_LE16(num_nodes); + + for (i = 0; i < num_nodes; i++) { + status = ice_sched_set_l2_node_aq_elem(pi, &buf->generic[i]); + if (status) + goto exit_add_dflt_l2_nodes; + } + + status = ice_aq_add_sched_elems(hw, 1, buf, buf_size, + &num_groups_added, NULL); + if (status != ICE_SUCCESS || num_groups_added != 1) { + ice_debug(hw, ICE_DBG_SCHED, "add node failed FW Error %d\n", + hw->adminq.sq_last_status); + status = ICE_ERR_CFG; + goto exit_add_dflt_l2_nodes; + } + + for (i = 0; i < num_nodes; i++) { + status = ice_sched_add_node(pi, 1, &buf->generic[i], NULL); + if (status != ICE_SUCCESS) { + ice_debug(hw, ICE_DBG_SCHED, "add nodes in SW DB failed status =%d\n", + status); + break; + } + + teid = LE32_TO_CPU(buf->generic[i].node_teid); + node = ice_sched_find_node_by_teid(pi->root, teid); + if (!node) { + ice_debug(hw, ICE_DBG_SCHED, "Node is missing for teid =%d\n", teid); + break; + } + node->sibling = NULL; + node->tc_num = i + 1; + } + +exit_add_dflt_l2_nodes: + ice_release_lock(&pi->sched_lock); + ice_free(hw, buf); + return status; +} + +/** + * ice_sched_clear_l2_nodes - remove all L2 TC nodes from port except for default TC0 + * @pi: port information structure + * + * Remove non-default L2 nodes configuration created by SW leaving only one TC0 L2 default node + */ +enum ice_status ice_sched_clear_l2_nodes(struct ice_port_info *pi) +{ + enum ice_status status = ICE_SUCCESS; + u32 teid; + u8 i; + + if (!pi || !pi->root) + return ICE_ERR_PARAM; + + ice_acquire_lock(&pi->sched_lock); + + /* iterate backwards and do not remove child at index 0 */ + for (i = pi->root->num_children - 1; i; i--) { + struct ice_sched_node *node = pi->root->children[i]; + + teid = LE32_TO_CPU(node->info.node_teid); + ice_free_sched_node(pi, node); + /* ice_free_sched_node does not remove L2 nodes from HW, removing explicitly */ + status = ice_sched_remove_elems(pi->hw, pi->root, 1, &teid); + if (status) + break; + } + + ice_release_lock(&pi->sched_lock); + return status; +} + +/** + * ice_sched_set_dflt_cgd_to_tc_map - setup default CGD to TC mapping + * @pi: port information structure + * + * Function creates default CGD to L2 nodes mapping + */ +enum ice_status ice_sched_set_dflt_cgd_to_tc_map(struct ice_port_info *pi) +{ + struct ice_aqc_cfg_l2_node_cgd_elem *buf; + struct ice_sched_node *root; + enum ice_status status; + u16 i, buf_size; + u8 cgd; + + if (!pi || !pi->root) + return ICE_ERR_PARAM; + + buf_size = sizeof(*buf) * ICE_MAX_CGD_PER_PORT; + buf = (struct ice_aqc_cfg_l2_node_cgd_elem *) + ice_malloc(pi->hw, buf_size); + if (!buf) + return ICE_ERR_NO_MEMORY; + + ice_acquire_lock(&pi->sched_lock); + root = pi->root; + + for (i = 0; i < root->num_children; i++) { + buf[i].node_teid = root->children[i]->info.node_teid; + cgd = i + pi->lport * ICE_MAX_CGD_PER_PORT; + buf[i].cgd = cgd; + root->children[i]->cgd = cgd; + } + + status = ice_aq_cfg_l2_node_cgd(pi->hw, root->num_children, buf, + buf_size, NULL); + + ice_release_lock(&pi->sched_lock); + ice_free(pi->hw, buf); + return status; +} + +/** + * ice_sched_copy_cgd - copy congestion domain mapping between ports + * @src: pointer to source port_info struct + * @dst: pointer to destination port_info struct + * @num_cgd: CGD count + * + * Copy first num_cgd congestion domain to TC node mappings from src port to dst port. + * Src port mapping does not change. + */ +enum ice_status +ice_sched_copy_cgd(struct ice_port_info *src, struct ice_port_info *dst, u8 num_cgd) +{ + struct ice_aqc_cfg_l2_node_cgd_elem *buf = NULL; + enum ice_status status; + u16 buf_size; + u8 cgd, i; + + if (!src || !dst || !num_cgd) + return ICE_ERR_PARAM; + + ice_acquire_lock(&src->sched_lock); + ice_acquire_lock(&dst->sched_lock); + + if (!src->root || src->root->num_children < num_cgd || + !dst->root || dst->root->num_children < num_cgd) { + status = ICE_ERR_PARAM; + goto err_copy_cgd; + } + + buf_size = sizeof(*buf) * num_cgd; + buf = (struct ice_aqc_cfg_l2_node_cgd_elem *)ice_malloc(src->hw, buf_size); + + if (!buf) { + status = ICE_ERR_NO_MEMORY; + goto err_copy_cgd; + } + + for (i = 0; i < num_cgd; i++) { + buf[i].node_teid = dst->root->children[i]->info.node_teid; + cgd = src->root->children[i]->cgd; + buf[i].cgd = cgd; + dst->root->children[i]->cgd = cgd; + } + + status = ice_aq_cfg_l2_node_cgd(src->hw, num_cgd, buf, buf_size, NULL); + +err_copy_cgd: + ice_release_lock(&dst->sched_lock); + ice_release_lock(&src->sched_lock); + + if (buf) + ice_free(src->hw, buf); + + return status; +} + /** * ice_rm_dflt_leaf_node - remove the default leaf node in the tree * @pi: port information structure @@ -1292,7 +1538,7 @@ enum ice_status ice_sched_init_port(struct ice_port_info *pi) ICE_AQC_ELEM_TYPE_ENTRY_POINT) hw->sw_entry_point_layer = j; - status = ice_sched_add_node(pi, j, &buf[i].generic[j]); + status = ice_sched_add_node(pi, j, &buf[i].generic[j], NULL); if (status) goto err_init_port; } @@ -1417,11 +1663,6 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw) clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; -#define PSM_CLK_SRC_367_MHZ 0x0 -#define PSM_CLK_SRC_416_MHZ 0x1 -#define PSM_CLK_SRC_446_MHZ 0x2 -#define PSM_CLK_SRC_390_MHZ 0x3 - switch (clk_src) { case PSM_CLK_SRC_367_MHZ: hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; @@ -1435,11 +1676,12 @@ void ice_sched_get_psm_clk_freq(struct ice_hw *hw) case PSM_CLK_SRC_390_MHZ: hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; break; - default: - ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", - clk_src); - /* fall back to a safe default */ - hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; + + /* default condition is not required as clk_src is restricted + * to a 2-bit value from GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M mask. + * The above switch statements cover the possible values of + * this variable. + */ } } @@ -2267,7 +2509,7 @@ ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, * This function removes the child from the old parent and adds it to a new * parent */ -static void +void ice_sched_update_parent(struct ice_sched_node *new_parent, struct ice_sched_node *node) { @@ -2301,7 +2543,7 @@ ice_sched_update_parent(struct ice_sched_node *new_parent, * * This function move the child nodes to a given parent. */ -static enum ice_status +enum ice_status ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, u16 num_items, u32 *list) { @@ -4372,7 +4614,7 @@ ice_sched_set_node_bw_dflt(struct ice_port_info *pi, * node's RL profile ID of type CIR, EIR, or SRL, and removes old profile * ID from local database. The caller needs to hold scheduler lock. */ -static enum ice_status +enum ice_status ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, enum ice_rl_type rl_type, u32 bw, u8 layer_num) { @@ -4408,6 +4650,58 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, ICE_AQC_RL_PROFILE_TYPE_M, old_id); } +/** + * ice_sched_set_node_priority - set node's priority + * @pi: port information structure + * @node: tree node + * @priority: number 0-7 representing priority among siblings + * + * This function sets priority of a node among it's siblings. + */ +enum ice_status +ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node, + u16 priority) +{ + struct ice_aqc_txsched_elem_data buf; + struct ice_aqc_txsched_elem *data; + + buf = node->info; + data = &buf.data; + + data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; + data->generic |= ICE_AQC_ELEM_GENERIC_PRIO_M & + (priority << ICE_AQC_ELEM_GENERIC_PRIO_S); + + return ice_sched_update_elem(pi->hw, node, &buf); +} + +/** + * ice_sched_set_node_weight - set node's weight + * @pi: port information structure + * @node: tree node + * @weight: number 1-200 representing weight for WFQ + * + * This function sets weight of the node for WFQ algorithm. + */ +enum ice_status +ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, u16 weight) +{ + struct ice_aqc_txsched_elem_data buf; + struct ice_aqc_txsched_elem *data; + + buf = node->info; + data = &buf.data; + + data->valid_sections = ICE_AQC_ELEM_VALID_CIR | ICE_AQC_ELEM_VALID_EIR | + ICE_AQC_ELEM_VALID_GENERIC; + data->cir_bw.bw_alloc = CPU_TO_LE16(weight); + data->eir_bw.bw_alloc = CPU_TO_LE16(weight); + data->generic |= ICE_AQC_ELEM_GENERIC_SP_M & + (0x0 << ICE_AQC_ELEM_GENERIC_SP_S); + + return ice_sched_update_elem(pi->hw, node, &buf); +} + /** * ice_sched_set_node_bw_lmt - set node's BW limit * @pi: port information structure @@ -4421,7 +4715,7 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, * NOTE: Caller provides the correct SRL node in case of shared profile * settings. */ -static enum ice_status +enum ice_status ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, enum ice_rl_type rl_type, u32 bw) { @@ -4444,6 +4738,81 @@ ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, return ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num); } +/** + * ice_sched_save_root_node_bw - save root node BW limit + * @pi: port information structure + * @rl_type: min or max + * @bw: bandwidth in Kbps + * + * This function saves the modified values of bandwidth settings for later + * replay purpose (restore) after tree recreation. + */ +static enum ice_status +ice_sched_save_root_node_bw(struct ice_port_info *pi, + enum ice_rl_type rl_type, u32 bw) +{ + switch (rl_type) { + case ICE_MIN_BW: + ice_set_clear_cir_bw(&pi->root_node_bw_t_info, bw); + break; + case ICE_MAX_BW: + ice_set_clear_eir_bw(&pi->root_node_bw_t_info, bw); + break; + case ICE_SHARED_BW: + ice_set_clear_shared_bw(&pi->root_node_bw_t_info, bw); + break; + default: + return ICE_ERR_PARAM; + } + return ICE_SUCCESS; +} + +/** + * ice_sched_set_root_node_bw_lmt - set root node's BW limit + * @pi: port information structure + * @rl_type: rate limit type min, max, or shared + * @bw: bandwidth in Kbps + * + * It updates root node's BW limit parameters like BW RL profile ID of type + * CIR, EIR, or SRL. + */ +static enum ice_status +ice_sched_set_root_node_bw_lmt(struct ice_port_info *pi, + enum ice_rl_type rl_type, u32 bw) +{ + enum ice_status status = ICE_ERR_PARAM; + + ice_acquire_lock(&pi->sched_lock); + if (!pi->root) + goto exit_set_root_node_bw; + + status = ice_sched_set_node_bw_lmt(pi, pi->root, rl_type, bw); + if (!status) + status = ice_sched_save_root_node_bw(pi, rl_type, bw); + +exit_set_root_node_bw: + ice_release_lock(&pi->sched_lock); + return status; +} + +/** + * ice_cfg_root_node_bw_lmt - configure the root BW + * @pi: port information structure + * @bw: bandwidth in Kbps - Kilo bits per sec + * @rl_type: rate limit type min, max, or shared + * + * This function configure the root node CIR, EIR or SRL BW limit + */ +enum ice_status +ice_cfg_root_node_bw_lmt(struct ice_port_info *pi, u32 bw, + enum ice_rl_type rl_type) +{ + if (!pi->root) + return ICE_ERR_PARAM; + + return ice_sched_set_root_node_bw_lmt(pi, rl_type, bw); +} + /** * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default * @pi: port information structure diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index a71619ebf0..d7a548e0c4 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -7,6 +7,8 @@ #include "ice_common.h" +#define SCHED_NODE_NAME_MAX_LEN 32 + #define ICE_SCHED_5_LAYERS 5 #define ICE_SCHED_9_LAYERS 9 @@ -38,6 +40,31 @@ #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 +/* bit definitions per recipe */ +#define ICE_RECIPE_BIT_INCL_IPG_AND_PREAMBLE BIT(4) +#define ICE_RECIPE_BIT_INCL_OFFSET BIT(3) +#define ICE_RECIPE_BIT_INCL_ESP_TRAILER BIT(2) +#define ICE_RECIPE_BIT_INCL_L2_PADDING BIT(1) +#define ICE_RECIPE_BIT_INCL_CRC BIT(0) + +/* protocol IDs from factory parsing program */ +#define ICE_PROT_ID_MAC_OUTER_1 0x01 +#define ICE_PROT_ID_MAC_OUTER_2 0x02 +#define ICE_PROT_ID_MAC_INNER_LAST 0x04 +#define ICE_PROT_ID_IPV4_OUTER_1 0x20 +#define ICE_PROT_ID_IPV4_INNER_LAST 0x21 +#define ICE_PROT_ID_IPV6_OUTER_1 0x28 +#define ICE_PROT_ID_IPV6_INNER_LAST 0x29 + +/* Packet adjustment profile ID */ +#define ICE_ADJ_PROFILE_ID 0 +#define ICE_DWORDS_PER_ADJ 8 + +#define PSM_CLK_SRC_367_MHZ 0x0 +#define PSM_CLK_SRC_416_MHZ 0x1 +#define PSM_CLK_SRC_446_MHZ 0x2 +#define PSM_CLK_SRC_390_MHZ 0x3 + struct rl_profile_params { u32 bw; /* in Kbps */ u16 rl_multiplier; @@ -96,7 +123,38 @@ enum ice_status ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, struct ice_aqc_txsched_elem_data *buf, u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd); + +enum ice_status +ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, + enum ice_rl_type rl_type, u32 bw); + +enum ice_status +ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, + enum ice_rl_type rl_type, u32 bw, u8 layer_num); + +enum ice_status +ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, + struct ice_sched_node *parent, u8 layer, u16 num_nodes, + u16 *num_nodes_added, u32 *first_node_teid, + struct ice_sched_node **prealloc_node); + +enum ice_status +ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, + u16 num_items, u32 *list); + +enum ice_status +ice_sched_set_node_priority(struct ice_port_info *pi, struct ice_sched_node *node, + u16 priority); +enum ice_status +ice_sched_set_node_weight(struct ice_port_info *pi, struct ice_sched_node *node, + u16 weight); + enum ice_status ice_sched_init_port(struct ice_port_info *pi); +enum ice_status ice_sched_add_dflt_l2_nodes(struct ice_port_info *pi); +enum ice_status ice_sched_clear_l2_nodes(struct ice_port_info *pi); +enum ice_status ice_sched_set_dflt_cgd_to_tc_map(struct ice_port_info *pi); +enum ice_status +ice_sched_copy_cgd(struct ice_port_info *src, struct ice_port_info *dst, u8 num_cgd); enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw); void ice_sched_get_psm_clk_freq(struct ice_hw *hw); @@ -112,7 +170,11 @@ ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); /* Add a scheduling node into SW DB for given info */ enum ice_status ice_sched_add_node(struct ice_port_info *pi, u8 layer, - struct ice_aqc_txsched_elem_data *info); + struct ice_aqc_txsched_elem_data *info, + struct ice_sched_node *prealloc_node); +void +ice_sched_update_parent(struct ice_sched_node *new_parent, + struct ice_sched_node *node); void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); struct ice_sched_node * @@ -221,6 +283,9 @@ enum ice_status ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, struct ice_sched_node *node, u8 priority); enum ice_status +ice_cfg_root_node_bw_lmt(struct ice_port_info *pi, u32 bw, + enum ice_rl_type rl_type); +enum ice_status ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, enum ice_rl_type rl_type, u8 bw_alloc); enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); @@ -229,7 +294,7 @@ void ice_sched_replay_agg(struct ice_hw *hw); enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi); enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi); -enum ice_status -ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); +enum ice_status ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); +void ice_cfg_pkt_len_adj_profiles(struct ice_hw *hw); #endif /* _ICE_SCHED_H_ */ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 17383ae23f..ec4892179a 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -992,9 +992,11 @@ struct ice_sched_node { u8 num_children; u8 tc_num; u8 owner; + u8 cgd; /* Valid only for Layer 2 */ #define ICE_SCHED_NODE_OWNER_LAN 0 #define ICE_SCHED_NODE_OWNER_AE 1 #define ICE_SCHED_NODE_OWNER_RDMA 2 +#define ICE_MAX_CGD_PER_PORT 4 }; /* Access Macros for Tx Sched Elements data */ @@ -1213,6 +1215,7 @@ struct ice_port_info { struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS]; struct ice_qos_cfg qos_cfg; u8 is_vf:1; + u8 is_custom_tx_enabled:1; }; struct ice_switch_info { From patchwork Thu Apr 27 06:19:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126577 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66E4642A08; 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a="375324309" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324309" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845718" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845718" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:00 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , LUkasz Plachno , Marcin Szycik Subject: [PATCH 10/30] net/ice/base: use coccinelle to instead macro Date: Thu, 27 Apr 2023 06:19:41 +0000 Message-Id: <20230427062001.478032-11-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org MSVC is not allowing array initialization with indexes, best way to avoid the issue when compiling for Windows is to use macro to remove index on Windows and use coccinelle to maintain compatibility with linux upstream. Signed-off-by: LUkasz Plachno Signed-off-by: Marcin Szycik Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 74 ++++++++++++++++++++++++++++ drivers/net/ice/base/ice_common.h | 8 +++ drivers/net/ice/base/ice_ddp.c | 3 ++ drivers/net/ice/base/ice_flow.h | 1 + drivers/net/ice/base/ice_lan_tx_rx.h | 1 - drivers/net/ice/base/ice_switch.c | 23 +-------- drivers/net/ice/base/ice_switch.h | 3 +- 7 files changed, 89 insertions(+), 24 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 984830ea37..cebf1504f1 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -11,6 +11,80 @@ #define ICE_PF_RESET_WAIT_COUNT 300 +static const char * const ice_link_mode_str_low[] = { + ice_arr_elem_idx(0, "100BASE_TX"), + ice_arr_elem_idx(1, "100M_SGMII"), + ice_arr_elem_idx(2, "1000BASE_T"), + ice_arr_elem_idx(3, "1000BASE_SX"), + ice_arr_elem_idx(4, "1000BASE_LX"), + ice_arr_elem_idx(5, "1000BASE_KX"), + ice_arr_elem_idx(6, "1G_SGMII"), + ice_arr_elem_idx(7, "2500BASE_T"), + ice_arr_elem_idx(8, "2500BASE_X"), + ice_arr_elem_idx(9, "2500BASE_KX"), + ice_arr_elem_idx(10, "5GBASE_T"), + ice_arr_elem_idx(11, "5GBASE_KR"), + ice_arr_elem_idx(12, "10GBASE_T"), + ice_arr_elem_idx(13, "10G_SFI_DA"), + ice_arr_elem_idx(14, "10GBASE_SR"), + ice_arr_elem_idx(15, "10GBASE_LR"), + ice_arr_elem_idx(16, "10GBASE_KR_CR1"), + ice_arr_elem_idx(17, "10G_SFI_AOC_ACC"), + ice_arr_elem_idx(18, "10G_SFI_C2C"), + ice_arr_elem_idx(19, "25GBASE_T"), + ice_arr_elem_idx(20, "25GBASE_CR"), + ice_arr_elem_idx(21, "25GBASE_CR_S"), + ice_arr_elem_idx(22, "25GBASE_CR1"), + ice_arr_elem_idx(23, "25GBASE_SR"), + ice_arr_elem_idx(24, "25GBASE_LR"), + ice_arr_elem_idx(25, "25GBASE_KR"), + ice_arr_elem_idx(26, "25GBASE_KR_S"), + ice_arr_elem_idx(27, "25GBASE_KR1"), + ice_arr_elem_idx(28, "25G_AUI_AOC_ACC"), + ice_arr_elem_idx(29, "25G_AUI_C2C"), + ice_arr_elem_idx(30, "40GBASE_CR4"), + ice_arr_elem_idx(31, "40GBASE_SR4"), + ice_arr_elem_idx(32, "40GBASE_LR4"), + ice_arr_elem_idx(33, "40GBASE_KR4"), + ice_arr_elem_idx(34, "40G_XLAUI_AOC_ACC"), + ice_arr_elem_idx(35, "40G_XLAUI"), + ice_arr_elem_idx(36, "50GBASE_CR2"), + ice_arr_elem_idx(37, "50GBASE_SR2"), + ice_arr_elem_idx(38, "50GBASE_LR2"), + ice_arr_elem_idx(39, "50GBASE_KR2"), + ice_arr_elem_idx(40, "50G_LAUI2_AOC_ACC"), + ice_arr_elem_idx(41, "50G_LAUI2"), + ice_arr_elem_idx(42, "50G_AUI2_AOC_ACC"), + ice_arr_elem_idx(43, "50G_AUI2"), + ice_arr_elem_idx(44, "50GBASE_CP"), + ice_arr_elem_idx(45, "50GBASE_SR"), + ice_arr_elem_idx(46, "50GBASE_FR"), + ice_arr_elem_idx(47, "50GBASE_LR"), + ice_arr_elem_idx(48, "50GBASE_KR_PAM4"), + ice_arr_elem_idx(49, "50G_AUI1_AOC_ACC"), + ice_arr_elem_idx(50, "50G_AUI1"), + ice_arr_elem_idx(51, "100GBASE_CR4"), + ice_arr_elem_idx(52, "100GBASE_SR4"), + ice_arr_elem_idx(53, "100GBASE_LR4"), + ice_arr_elem_idx(54, "100GBASE_KR4"), + ice_arr_elem_idx(55, "100G_CAUI4_AOC_ACC"), + ice_arr_elem_idx(56, "100G_CAUI4"), + ice_arr_elem_idx(57, "100G_AUI4_AOC_ACC"), + ice_arr_elem_idx(58, "100G_AUI4"), + ice_arr_elem_idx(59, "100GBASE_CR_PAM4"), + ice_arr_elem_idx(60, "100GBASE_KR_PAM4"), + ice_arr_elem_idx(61, "100GBASE_CP2"), + ice_arr_elem_idx(62, "100GBASE_SR2"), + ice_arr_elem_idx(63, "100GBASE_DR"), +}; + +static const char * const ice_link_mode_str_high[] = { + ice_arr_elem_idx(0, "100GBASE_KR2_PAM4"), + ice_arr_elem_idx(1, "100G_CAUI2_AOC_ACC"), + ice_arr_elem_idx(2, "100G_CAUI2"), + ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"), + ice_arr_elem_idx(4, "100G_AUI2"), +}; /** * dump_phy_type - helper function that prints PHY type strings * @hw: pointer to the HW structure diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index ccefe85af7..83ef438041 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -81,6 +81,14 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, */ #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) +/* Define a macro for initializing array using indexes. Due to limitation + * of MSVC compiler it is necessary to allow other projects to replace + * that macro and strip the index from initialization. + * Linux driver is using coccinelle to maintain source sync with upstream + * and is not requiring this macro. + */ +#define ice_arr_elem_idx(idx, val) [(idx)] = (val) + enum ice_status ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index); diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index 93ff2608d4..ae0a03c8ba 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -1579,6 +1579,9 @@ ice_get_sw_fv_list(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, struct ice_fv *fv; u32 offset; + if (!lkups->n_val_words) + return ICE_SUCCESS; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); if (!lkups->n_val_words || !hw->seg) diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 1415f5ba87..2e5a3b386e 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -7,6 +7,7 @@ #include "ice_flex_type.h" #include "ice_acl.h" +#include "ice_parser.h" #define ICE_IPV4_MAKE_PREFIX_MASK(prefix) ((u32)(~0) << (32 - (prefix))) #define ICE_FLOW_PROF_ID_INVAL 0xfffffffffffffffful diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index d816df0ff6..229db1041c 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -162,7 +162,6 @@ struct ice_fltr_desc { #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) -#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index dd4cc38114..b3d9847669 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7500,25 +7500,6 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm, return status; } -/** - * ice_get_fv - get field vectors/extraction sequences for spec. lookup types - * @hw: pointer to hardware structure - * @lkups: lookup elements or match criteria for the advanced recipe, one - * structure per protocol header - * @bm: bitmap of field vectors to consider - * @fv_list: pointer to a list that holds the returned field vectors - */ -static enum ice_status -ice_get_fv(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, - ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list) -{ - if (!lkups->n_val_words) - return ICE_SUCCESS; - - /* Find field vectors that include all specified protocol types */ - return ice_get_sw_fv_list(hw, lkups, bm, fv_list); -} - /** * ice_tun_type_match_word - determine if tun type needs a match mask * @tun_type: tunnel type @@ -7905,11 +7886,11 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, /* Get bitmap of field vectors (profiles) that are compatible with the * rule request; only these will be searched in the subsequent call to - * ice_get_fv. + * ice_get_sw_fv_list. */ ice_get_compat_fv_bitmap(hw, rinfo, fv_bitmap); - status = ice_get_fv(hw, lkup_exts, fv_bitmap, &rm->fv_list); + status = ice_get_sw_fv_list(hw, lkup_exts, fv_bitmap, &rm->fv_list); if (status) goto err_unroll; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index 49bd535c79..adb467eb66 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -498,8 +498,7 @@ ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries, bool res_shared, u16 *desc_id, struct ice_sq_cd *cd); enum ice_status ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list); -enum ice_status -ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list); +enum ice_status ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list); void ice_rem_all_sw_rules_info(struct ice_hw *hw); enum ice_status ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst); enum ice_status ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst); From patchwork Thu Apr 27 06:19:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126578 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9DD4D42A08; Thu, 27 Apr 2023 08:39:14 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E71FF42DB5; Thu, 27 Apr 2023 08:38:08 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 3797942D82 for ; Thu, 27 Apr 2023 08:38:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577485; x=1714113485; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7BZgG3Rw+N5cou1cIkOtIcZ2yHzCJIfYKPviovbR4ak=; b=iadWhKGZ1QEp8QiFMvaHgSPuhjmDH1/p4Yqb7k/+RyIrPqRcnBOKNMy3 LhVT3B1CdKkVXd7RpT4zfn34O1NMZH9I/zU//BCSzFsmVuqdSklcOM3Mx 6u54S+JRE5WYRUSc4PmWmJyLspQQloKPM/QZ0yI/i26iNkCK787YKhZtx RSDbuH0wy3DiXWKYhuDu//0T30g6TaZEa+oySw1yLbT4uxEGAW4qRqjlY PDoTu3pyYWvUQ+pSzGDCjHL4gm4bk9Uk3rkFSDZ0mYT4YWkCoknVJElz5 9DQghlK2aqPMb9N7kgUn6drFmrWbK84uI+kNqJQXg9pirOVOyeE8ShT7T A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324311" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324311" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845727" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845727" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:02 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jesse Brandeburg Subject: [PATCH 11/30] net/ice/base: add new fls function Date: Thu, 27 Apr 2023 06:19:42 +0000 Message-Id: <20230427062001.478032-12-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a new function called ice_fls() and merged some code clean. Signed-off-by: Jesse Brandeburg Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 40 ++++++++++++++++++++++-- drivers/net/ice/base/ice_common.h | 1 + drivers/net/ice/base/ice_protocol_type.h | 11 +++---- drivers/net/ice/base/ice_switch.c | 25 ++++++++------- drivers/net/ice/base/ice_type.h | 18 +++++++++++ 5 files changed, 75 insertions(+), 20 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index cebf1504f1..6967ff1a8f 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -3238,8 +3238,8 @@ bool ice_is_100m_speed_supported(struct ice_hw *hw) * Note: In the structure of [phy_type_low, phy_type_high], there should * be one bit set, as this function will convert one PHY type to its * speed. - * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned - * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned + * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned + * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned */ static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) @@ -6134,6 +6134,42 @@ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) ICE_FW_API_REPORT_DFLT_CFG_PATCH); } +/* each of the indexes into the following array match the speed of a return + * value from the list of AQ returned speeds like the range: + * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding + * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) The array is defined as 15 + * elements long because the link_speed returned by the firmware is a 16 bit + * value, but is indexed by [fls(speed) - 1] + */ +static const u32 ice_aq_to_link_speed[] = { + ICE_LINK_SPEED_10MBPS, /* BIT(0) */ + ICE_LINK_SPEED_100MBPS, + ICE_LINK_SPEED_1000MBPS, + ICE_LINK_SPEED_2500MBPS, + ICE_LINK_SPEED_5000MBPS, + ICE_LINK_SPEED_10000MBPS, + ICE_LINK_SPEED_20000MBPS, + ICE_LINK_SPEED_25000MBPS, + ICE_LINK_SPEED_40000MBPS, + ICE_LINK_SPEED_50000MBPS, + ICE_LINK_SPEED_100000MBPS, /* BIT(10) */ + ICE_LINK_SPEED_200000MBPS, +}; + +/** + * ice_get_link_speed - get integer speed from table + * @index: array index from fls(aq speed) - 1 + * + * Returns: u32 value containing integer speed + */ +u32 ice_get_link_speed(u16 index) +{ + if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) + return ICE_LINK_SPEED_UNKNOWN; + + return ice_aq_to_link_speed[index]; +} + /** * ice_fw_supports_fec_dis_auto * @hw: pointer to the hardware structure diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index 83ef438041..d8fb7a6163 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -217,6 +217,7 @@ enum ice_status ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, bool write, struct ice_sq_cd *cd); +u32 ice_get_link_speed(u16 index); enum ice_status ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index eeaf044059..1d9baea624 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -97,6 +97,10 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_IPV6_GTPU_EH_IPV6_UDP, ICE_SW_TUN_IPV6_GTPU_IPV6_TCP, ICE_SW_TUN_IPV6_GTPU_EH_IPV6_TCP, + ICE_SW_TUN_IPV4_GTPU_IPV4, + ICE_SW_TUN_IPV4_GTPU_IPV6, + ICE_SW_TUN_IPV6_GTPU_IPV4, + ICE_SW_TUN_IPV6_GTPU_IPV6, ICE_SW_TUN_PPPOE, ICE_SW_TUN_PPPOE_PAY, ICE_SW_TUN_PPPOE_IPV4, @@ -127,12 +131,6 @@ enum ice_sw_tunnel_type { ICE_SW_TUN_PPPOE_PAY_QINQ, ICE_SW_TUN_PPPOE_IPV4_QINQ, ICE_SW_TUN_PPPOE_IPV6_QINQ, - ICE_SW_TUN_IPV4_GTPU_IPV4, - ICE_SW_TUN_IPV4_GTPU_IPV6, - ICE_SW_TUN_IPV6_GTPU_IPV4, - ICE_SW_TUN_IPV6_GTPU_IPV6, - ICE_SW_TUN_GTP_IPV4, - ICE_SW_TUN_GTP_IPV6, ICE_ALL_TUNNELS /* All tunnel types including NVGRE */ }; @@ -224,6 +222,7 @@ enum ice_prot_id { #define ICE_TUN_FLAG_MDID_OFF(word) (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word))) #define ICE_TUN_FLAG_MASK 0xFF #define ICE_DIR_FLAG_MASK 0x10 +#define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */ #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index b3d9847669..1b8311fdc7 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -915,15 +915,6 @@ static const u8 dummy_ipv6_gtpu_ipv6_udp_packet[] = { 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = { - { ICE_MAC_OFOS, 0 }, - { ICE_IPV4_OFOS, 14 }, - { ICE_UDP_OF, 34 }, - { ICE_GTP, 42 }, - { ICE_IPV4_IL, 62 }, - { ICE_PROTOCOL_LAST, 0 }, -}; - static const u8 dummy_ipv4_gtpu_ipv4_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, @@ -954,8 +945,17 @@ static const u8 dummy_ipv4_gtpu_ipv4_packet[] = { 0x00, 0x00, }; -static const -struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = { +static const struct +ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv4_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_GTP, 42 }, + { ICE_IPV4_IL, 62 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const struct ice_dummy_pkt_offsets dummy_ipv4_gtpu_ipv6_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV4_OFOS, 14 }, { ICE_UDP_OF, 34 }, @@ -7532,7 +7532,8 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, case ICE_SW_TUN_GENEVE_VLAN: case ICE_SW_TUN_VXLAN_VLAN: - *mask = ICE_TUN_FLAG_MASK & ~ICE_TUN_FLAG_VLAN_MASK; + *mask = ICE_TUN_FLAG_MASK & ~(ICE_TUN_FLAG_VLAN_MASK | + ICE_TUN_FLAG_IN_VLAN_MASK); *off = ICE_TUN_FLAG_MDID_OFF(1); return true; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index ec4892179a..5779590a7e 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -43,6 +43,24 @@ static inline int ice_ilog2(u64 n) return -1; } +/** + * ice_fls - find the most significant bit set in a u64 + * @n: u64 value to scan for a bit + * + * Returns: 0 if no bits found, otherwise the index of the highest bit that was + * set, like ice_fls(0x20) == 6. This means this is returning a *1 based* + * count, and that the maximum largest value returned is 64! + */ +static inline unsigned int ice_fls(u64 n) +{ + int ret; + + ret = ice_ilog2(n); + + /* add one to turn to the ilog2 value into a 1 based index */ + return ret >= 0 ? ret + 1 : 0; +} + static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc) { return ice_is_bit_set(&bitmap, tc); From patchwork Thu Apr 27 06:19:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126579 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 732B342A08; Thu, 27 Apr 2023 08:39:20 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 267FE42DA5; Thu, 27 Apr 2023 08:38:10 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id C25B742D98 for ; Thu, 27 Apr 2023 08:38:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577488; x=1714113488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Dml7IPuwImFCYfQl9Ol3ZFdDKXyJSwna4GZz66SkY6U=; b=Bl6nxe4FZmFFsxUognEEkgRAYY7t8E7o/D2ul+fk5BXJhTuXu+/pTeZX v3Uu86euZLK/JXZyntM45hJSchP/Q7gQvnuVm+9OAtM4AJVXpe3MxLL6p MD36lRoHYAzAH3qwndSTKkhjMkAPDTmEsVK7RPnM91mSwwzm0qaSN43as x+TcCB19K6DozcVQjxLDq4VX67hZblKADJjvY9PV+VpXZ3dXvo3RT6W3S weIdwwdRmfNXPnxgjYLPfioyZro4wWmHF5D3r7uP4hXH9rG05WZuJiQXQ 5p/9Fy/jAUBTLqznmq95uUeSEPWPSlr4iqwszEdWJsjC20t87jSuuRT7E A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324315" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324315" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845740" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845740" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:04 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Paul Greenwalt Subject: [PATCH 12/30] net/ice/base: add E830 device ids Date: Thu, 27 Apr 2023 06:19:43 +0000 Message-Id: <20230427062001.478032-13-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added new E830 device id and related registers. Signed-off-by: Paul Greenwalt Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 8 +- drivers/net/ice/base/ice_ddp.c | 6 + drivers/net/ice/base/ice_ddp.h | 1 + drivers/net/ice/base/ice_devids.h | 8 + drivers/net/ice/base/ice_hw_autogen.h | 1640 +++++++++++++++++++++++++ drivers/net/ice/base/ice_lan_tx_rx.h | 2 +- drivers/net/ice/base/ice_nvm.c | 15 +- drivers/net/ice/base/ice_type.h | 1 + 8 files changed, 1673 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 6967ff1a8f..58da198d62 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -9,7 +9,7 @@ #include "ice_flow.h" #include "ice_switch.h" -#define ICE_PF_RESET_WAIT_COUNT 300 +#define ICE_PF_RESET_WAIT_COUNT 500 static const char * const ice_link_mode_str_low[] = { ice_arr_elem_idx(0, "100BASE_TX"), @@ -249,6 +249,12 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) case ICE_DEV_ID_E825X: hw->mac_type = ICE_MAC_GENERIC; break; + case ICE_DEV_ID_E830_BACKPLANE: + case ICE_DEV_ID_E830_QSFP56: + case ICE_DEV_ID_E830_SFP: + case ICE_DEV_ID_E830_SFP_DD: + hw->mac_type = ICE_MAC_E830; + break; default: hw->mac_type = ICE_MAC_UNKNOWN; break; diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index ae0a03c8ba..e3c1f413dd 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -439,6 +439,9 @@ static u32 ice_get_pkg_segment_id(enum ice_mac_type mac_type) u32 seg_id; switch (mac_type) { + case ICE_MAC_E830: + seg_id = SEGMENT_TYPE_ICE_E830; + break; case ICE_MAC_GENERIC: case ICE_MAC_GENERIC_3K: default: @@ -458,6 +461,9 @@ static u32 ice_get_pkg_sign_type(enum ice_mac_type mac_type) u32 sign_type; switch (mac_type) { + case ICE_MAC_E830: + sign_type = SEGMENT_SIGN_TYPE_RSA3K_SBB; + break; case ICE_MAC_GENERIC_3K: sign_type = SEGMENT_SIGN_TYPE_RSA3K; break; diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 4896e85b91..57b39c72ca 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -106,6 +106,7 @@ struct ice_generic_seg_hdr { #define SEGMENT_TYPE_METADATA 0x00000001 #define SEGMENT_TYPE_ICE_E810 0x00000010 #define SEGMENT_TYPE_SIGNING 0x00001001 +#define SEGMENT_TYPE_ICE_E830 0x00000017 #define SEGMENT_TYPE_ICE_RUN_TIME_CFG 0x00000020 __le32 seg_type; struct ice_pkg_ver seg_format_ver; diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index f80789ebc5..9ea915b967 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -15,6 +15,14 @@ #define ICE_DEV_ID_E823L_1GBE 0x124F /* Intel(R) Ethernet Connection E823-L for QSFP */ #define ICE_DEV_ID_E823L_QSFP 0x151D +/* Intel(R) Ethernet Controller E830-C for backplane */ +#define ICE_DEV_ID_E830_BACKPLANE 0x12D1 +/* Intel(R) Ethernet Controller E830-C for QSFP */ +#define ICE_DEV_ID_E830_QSFP56 0x12D2 +/* Intel(R) Ethernet Controller E830-C for SFP */ +#define ICE_DEV_ID_E830_SFP 0x12D3 +/* Intel(R) Ethernet Controller E830-C for SFP-DD */ +#define ICE_DEV_ID_E830_SFP_DD 0x12D4 /* Intel(R) Ethernet Controller E810-C for backplane */ #define ICE_DEV_ID_E810C_BACKPLANE 0x1591 /* Intel(R) Ethernet Controller E810-C for QSFP */ diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h index 4610cec6a7..522840a847 100644 --- a/drivers/net/ice/base/ice_hw_autogen.h +++ b/drivers/net/ice/base/ice_hw_autogen.h @@ -9458,5 +9458,1645 @@ #define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0) #define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20 #define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20) +#define E830_GL_QRX_CONTEXT_CTL 0x00296640 /* Reset Source: CORER */ +#define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_S 0 +#define E830_GL_QRX_CONTEXT_CTL_QUEUE_ID_M MAKEMASK(0xFFF, 0) +#define E830_GL_QRX_CONTEXT_CTL_CMD_S 16 +#define E830_GL_QRX_CONTEXT_CTL_CMD_M MAKEMASK(0x7, 16) +#define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_S 19 +#define E830_GL_QRX_CONTEXT_CTL_CMD_EXEC_M BIT(19) +#define E830_GL_QRX_CONTEXT_DATA(_i) (0x00296620 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_QRX_CONTEXT_DATA_MAX_INDEX 7 +#define E830_GL_QRX_CONTEXT_DATA_DATA_S 0 +#define E830_GL_QRX_CONTEXT_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_QRX_CONTEXT_STAT 0x00296644 /* Reset Source: CORER */ +#define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_S 0 +#define E830_GL_QRX_CONTEXT_STAT_CMD_IN_PROG_M BIT(0) +#define E830_GL_RCB_INTERNAL(_i) (0x00122600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GL_RCB_INTERNAL_MAX_INDEX 63 +#define E830_GL_RCB_INTERNAL_INTERNAL_S 0 +#define E830_GL_RCB_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_RLAN_INTERNAL(_i) (0x00296700 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GL_RLAN_INTERNAL_MAX_INDEX 63 +#define E830_GL_RLAN_INTERNAL_INTERNAL_S 0 +#define E830_GL_RLAN_INTERNAL_INTERNAL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS 0x002D30F8 /* Reset Source: CORER */ +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_S 0 +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_DBLQ_FDBL_M MAKEMASK(0xFF, 0) +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_S 8 +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 8) +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS 0x002D30FC /* Reset Source: CORER */ +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_S 0 +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_DBLQ_FDBL_M MAKEMASK(0x3F, 0) +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_S 6 +#define E830_GLPQMDBL_PQMDBL_OUT_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 6) +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS 0x002D30F0 /* Reset Source: CORER */ +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_DBLQ_S 0 +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_DBLQ_M MAKEMASK(0xFF, 0) +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_FDBL_S 8 +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_FDBL_M MAKEMASK(0xFF, 8) +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_TXT_S 16 +#define E830_GLPQMDBL_PQMMNG_IN_WRR_MAX_CREDITS_TXT_M MAKEMASK(0xFF, 16) +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS 0x002D30F4 /* Reset Source: CORER */ +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_DBLQ_S 0 +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_DBLQ_M MAKEMASK(0x3F, 0) +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_FDBL_S 6 +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_FDBL_M MAKEMASK(0x3F, 6) +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_TXT_S 12 +#define E830_GLPQMDBL_PQMMNG_IN_WRR_WEIGHTS_TXT_M MAKEMASK(0x3F, 12) +#define E830_GLQTX_TXTIME_DBELL_LSB(_DBQM) (0x002E0000 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_DBELL_LSB_MAX_INDEX 16383 +#define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLQTX_TXTIME_DBELL_MSB(_DBQM) (0x002E0004 + ((_DBQM) * 8)) /* _i=0...16383 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_DBELL_MSB_MAX_INDEX 16383 +#define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS 0x002D320C /* Reset Source: CORER */ +#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_S 0 +#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_DBL_M MAKEMASK(0xFF, 0) +#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_S 8 +#define E830_GLTXTIME_DBL_COMP_WRR_MAX_CREDITS_COMP_M MAKEMASK(0xFF, 8) +#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS 0x002D3210 /* Reset Source: CORER */ +#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_S 0 +#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_DBL_M MAKEMASK(0x3F, 0) +#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_S 6 +#define E830_GLTXTIME_DBL_COMP_WRR_WEIGHTS_COMP_M MAKEMASK(0x3F, 6) +#define E830_GLTXTIME_FETCH_PROFILE(_i, _j) (0x002D3500 + ((_i) * 4 + (_j) * 64)) /* _i=0...15, _j=0...15 */ /* Reset Source: CORER */ +#define E830_GLTXTIME_FETCH_PROFILE_MAX_INDEX 15 +#define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_S 0 +#define E830_GLTXTIME_FETCH_PROFILE_FETCH_TS_DESC_M MAKEMASK(0x1FF, 0) +#define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_S 9 +#define E830_GLTXTIME_FETCH_PROFILE_FETCH_FIFO_TRESH_M MAKEMASK(0x7F, 9) +#define E830_GLTXTIME_OUTST_REQ_CNTL 0x002D3214 /* Reset Source: CORER */ +#define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_S 0 +#define E830_GLTXTIME_OUTST_REQ_CNTL_THRESHOLD_M MAKEMASK(0x3FF, 0) +#define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_S 10 +#define E830_GLTXTIME_OUTST_REQ_CNTL_SNAPSHOT_M MAKEMASK(0x3FF, 10) +#define E830_GLTXTIME_QTX_CNTX_CTL 0x002D3204 /* Reset Source: CORER */ +#define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_S 0 +#define E830_GLTXTIME_QTX_CNTX_CTL_QUEUE_ID_M MAKEMASK(0x7FF, 0) +#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_S 16 +#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_M MAKEMASK(0x7, 16) +#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_S 19 +#define E830_GLTXTIME_QTX_CNTX_CTL_CMD_EXEC_M BIT(19) +#define E830_GLTXTIME_QTX_CNTX_DATA(_i) (0x002D3104 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */ +#define E830_GLTXTIME_QTX_CNTX_DATA_MAX_INDEX 6 +#define E830_GLTXTIME_QTX_CNTX_DATA_DATA_S 0 +#define E830_GLTXTIME_QTX_CNTX_DATA_DATA_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTXTIME_QTX_CNTX_STAT 0x002D3208 /* Reset Source: CORER */ +#define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_S 0 +#define E830_GLTXTIME_QTX_CNTX_STAT_CMD_IN_PROG_M BIT(0) +#define E830_GLTXTIME_TS_CFG 0x002D3100 /* Reset Source: CORER */ +#define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_S 0 +#define E830_GLTXTIME_TS_CFG_TXTIME_ENABLE_M BIT(0) +#define E830_GLTXTIME_TS_CFG_STORAGE_MODE_S 2 +#define E830_GLTXTIME_TS_CFG_STORAGE_MODE_M MAKEMASK(0x7, 2) +#define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_S 5 +#define E830_GLTXTIME_TS_CFG_PIPE_LATENCY_STATIC_M MAKEMASK(0x1FFF, 5) +#define E830_MBX_PF_DEC_ERR 0x00234100 /* Reset Source: CORER */ +#define E830_MBX_PF_DEC_ERR_DEC_ERR_S 0 +#define E830_MBX_PF_DEC_ERR_DEC_ERR_M BIT(0) +#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH 0x00234000 /* Reset Source: CORER */ +#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_S 0 +#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH_TRESH_M MAKEMASK(0x3FF, 0) +#define E830_MBX_VF_DEC_TRIG(_VF) (0x00233800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_MBX_VF_DEC_TRIG_MAX_INDEX 255 +#define E830_MBX_VF_DEC_TRIG_DEC_S 0 +#define E830_MBX_VF_DEC_TRIG_DEC_M MAKEMASK(0x3FF, 0) +#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT(_VF) (0x00233000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MAX_INDEX 255 +#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_S 0 +#define E830_MBX_VF_IN_FLIGHT_MSGS_AT_PF_CNT_MSGS_M MAKEMASK(0x3FF, 0) +#define E830_GLRCB_AG_ARBITER_CONFIG 0x00122500 /* Reset Source: CORER */ +#define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_S 0 +#define E830_GLRCB_AG_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0xFFFFF, 0) +#define E830_GLRCB_AG_DCB_ARBITER_CONFIG 0x00122518 /* Reset Source: CORER */ +#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_S 0 +#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_CREDIT_MAX_M MAKEMASK(0x7F, 0) +#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_S 7 +#define E830_GLRCB_AG_DCB_ARBITER_CONFIG_STRICT_WRR_M BIT(7) +#define E830_GLRCB_AG_DCB_NODE_CONFIG(_i) (0x00122510 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GLRCB_AG_DCB_NODE_CONFIG_MAX_INDEX 1 +#define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_S 0 +#define E830_GLRCB_AG_DCB_NODE_CONFIG_BWSHARE_M MAKEMASK(0xF, 0) +#define E830_GLRCB_AG_DCB_NODE_STATE(_i) (0x00122508 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GLRCB_AG_DCB_NODE_STATE_MAX_INDEX 1 +#define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_S 0 +#define E830_GLRCB_AG_DCB_NODE_STATE_CREDITS_M MAKEMASK(0xFF, 0) +#define E830_GLRCB_AG_NODE_CONFIG(_i) (0x001224E0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLRCB_AG_NODE_CONFIG_MAX_INDEX 7 +#define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_S 0 +#define E830_GLRCB_AG_NODE_CONFIG_BWSHARE_M MAKEMASK(0x7F, 0) +#define E830_GLRCB_AG_NODE_STATE(_i) (0x001224C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLRCB_AG_NODE_STATE_MAX_INDEX 7 +#define E830_GLRCB_AG_NODE_STATE_CREDITS_S 0 +#define E830_GLRCB_AG_NODE_STATE_CREDITS_M MAKEMASK(0xFFFFF, 0) +#define E830_PRT_AG_PORT_FC_MAP 0x00122520 /* Reset Source: CORER */ +#define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_S 0 +#define E830_PRT_AG_PORT_FC_MAP_AG_BITMAP_M MAKEMASK(0xFF, 0) +#define E830_GL_FW_LOGS_CTL 0x000827F8 /* Reset Source: POR */ +#define E830_GL_FW_LOGS_CTL_PAGE_SELECT_S 0 +#define E830_GL_FW_LOGS_CTL_PAGE_SELECT_M MAKEMASK(0x3FF, 0) +#define E830_GL_FW_LOGS_STS 0x000827FC /* Reset Source: POR */ +#define E830_GL_FW_LOGS_STS_MAX_PAGE_S 0 +#define E830_GL_FW_LOGS_STS_MAX_PAGE_M MAKEMASK(0x3FF, 0) +#define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_S 31 +#define E830_GL_FW_LOGS_STS_FW_LOGS_ENA_M BIT(31) +#define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_S 3 +#define E830_GLGEN_RTRIG_EMPR_WO_GLOBR_M BIT(3) +#define E830_GLPE_TSCD_NUM_PQS 0x0051E2FC /* Reset Source: CORER */ +#define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_S 0 +#define E830_GLPE_TSCD_NUM_PQS_NUM_PQS_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTPB_100G_RPB_FC_THRESH2 0x0009972C /* Reset Source: CORER */ +#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_S 0 +#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT4_FC_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_S 16 +#define E830_GLTPB_100G_RPB_FC_THRESH2_PORT5_FC_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_GLTPB_100G_RPB_FC_THRESH3 0x00099730 /* Reset Source: CORER */ +#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_S 0 +#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT6_FC_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_S 16 +#define E830_GLTPB_100G_RPB_FC_THRESH3_PORT7_FC_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PORT_TIMER_SEL(_i) (0x00088BE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_PORT_TIMER_SEL_MAX_INDEX 7 +#define E830_PORT_TIMER_SEL_TIMER_SEL_S 0 +#define E830_PORT_TIMER_SEL_TIMER_SEL_M BIT(0) +#define E830_GLINT_FW_DCF_CTL(_i) (0x0016CFD4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLINT_FW_DCF_CTL_MAX_INDEX 7 +#define E830_GLINT_FW_DCF_CTL_MSIX_INDX_S 0 +#define E830_GLINT_FW_DCF_CTL_MSIX_INDX_M MAKEMASK(0x7FF, 0) +#define E830_GLINT_FW_DCF_CTL_ITR_INDX_S 11 +#define E830_GLINT_FW_DCF_CTL_ITR_INDX_M MAKEMASK(0x3, 11) +#define E830_GLINT_FW_DCF_CTL_CAUSE_ENA_S 30 +#define E830_GLINT_FW_DCF_CTL_CAUSE_ENA_M BIT(30) +#define E830_GLINT_FW_DCF_CTL_INTEVENT_S 31 +#define E830_GLINT_FW_DCF_CTL_INTEVENT_M BIT(31) +#define E830_GL_MDET_RX_FIFO 0x00296840 /* Reset Source: CORER */ +#define E830_GL_MDET_RX_FIFO_FUNC_NUM_S 0 +#define E830_GL_MDET_RX_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) +#define E830_GL_MDET_RX_FIFO_PF_NUM_S 10 +#define E830_GL_MDET_RX_FIFO_PF_NUM_M MAKEMASK(0x7, 10) +#define E830_GL_MDET_RX_FIFO_FUNC_TYPE_S 13 +#define E830_GL_MDET_RX_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) +#define E830_GL_MDET_RX_FIFO_MAL_TYPE_S 15 +#define E830_GL_MDET_RX_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) +#define E830_GL_MDET_RX_FIFO_FIFO_FULL_S 20 +#define E830_GL_MDET_RX_FIFO_FIFO_FULL_M BIT(20) +#define E830_GL_MDET_RX_FIFO_VALID_S 21 +#define E830_GL_MDET_RX_FIFO_VALID_M BIT(21) +#define E830_GL_MDET_RX_PF_CNT(_i) (0x00296800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_RX_PF_CNT_MAX_INDEX 7 +#define E830_GL_MDET_RX_PF_CNT_CNT_S 0 +#define E830_GL_MDET_RX_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_RX_VF(_i) (0x00296820 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_RX_VF_MAX_INDEX 7 +#define E830_GL_MDET_RX_VF_VF_MAL_EVENT_S 0 +#define E830_GL_MDET_RX_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_TX_PQM_FIFO 0x002D4B00 /* Reset Source: CORER */ +#define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_S 0 +#define E830_GL_MDET_TX_PQM_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) +#define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_S 10 +#define E830_GL_MDET_TX_PQM_FIFO_PF_NUM_M MAKEMASK(0x7, 10) +#define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_S 13 +#define E830_GL_MDET_TX_PQM_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) +#define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_S 15 +#define E830_GL_MDET_TX_PQM_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) +#define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_S 20 +#define E830_GL_MDET_TX_PQM_FIFO_FIFO_FULL_M BIT(20) +#define E830_GL_MDET_TX_PQM_FIFO_VALID_S 21 +#define E830_GL_MDET_TX_PQM_FIFO_VALID_M BIT(21) +#define E830_GL_MDET_TX_PQM_PF_CNT(_i) (0x002D4AC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_TX_PQM_PF_CNT_MAX_INDEX 7 +#define E830_GL_MDET_TX_PQM_PF_CNT_CNT_S 0 +#define E830_GL_MDET_TX_PQM_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_TX_PQM_VF(_i) (0x002D4AE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_TX_PQM_VF_MAX_INDEX 7 +#define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_S 0 +#define E830_GL_MDET_TX_PQM_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_TX_TCLAN_FIFO 0x000FD000 /* Reset Source: CORER */ +#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_S 0 +#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) +#define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_S 10 +#define E830_GL_MDET_TX_TCLAN_FIFO_PF_NUM_M MAKEMASK(0x7, 10) +#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_S 13 +#define E830_GL_MDET_TX_TCLAN_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) +#define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_S 15 +#define E830_GL_MDET_TX_TCLAN_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) +#define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_S 20 +#define E830_GL_MDET_TX_TCLAN_FIFO_FIFO_FULL_M BIT(20) +#define E830_GL_MDET_TX_TCLAN_FIFO_VALID_S 21 +#define E830_GL_MDET_TX_TCLAN_FIFO_VALID_M BIT(21) +#define E830_GL_MDET_TX_TCLAN_PF_CNT(_i) (0x000FCFC0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_TX_TCLAN_PF_CNT_MAX_INDEX 7 +#define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_S 0 +#define E830_GL_MDET_TX_TCLAN_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_TX_TCLAN_VF(_i) (0x000FCFE0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_TX_TCLAN_VF_MAX_INDEX 7 +#define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_S 0 +#define E830_GL_MDET_TX_TCLAN_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_TX_TDPU_FIFO 0x00049D80 /* Reset Source: CORER */ +#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_S 0 +#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) +#define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_S 10 +#define E830_GL_MDET_TX_TDPU_FIFO_PF_NUM_M MAKEMASK(0x7, 10) +#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_S 13 +#define E830_GL_MDET_TX_TDPU_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) +#define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_S 15 +#define E830_GL_MDET_TX_TDPU_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) +#define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_S 20 +#define E830_GL_MDET_TX_TDPU_FIFO_FIFO_FULL_M BIT(20) +#define E830_GL_MDET_TX_TDPU_FIFO_VALID_S 21 +#define E830_GL_MDET_TX_TDPU_FIFO_VALID_M BIT(21) +#define E830_GL_MDET_TX_TDPU_PF_CNT(_i) (0x00049D40 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_TX_TDPU_PF_CNT_MAX_INDEX 7 +#define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_S 0 +#define E830_GL_MDET_TX_TDPU_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_TX_TDPU_VF(_i) (0x00049D60 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_TX_TDPU_VF_MAX_INDEX 7 +#define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_S 0 +#define E830_GL_MDET_TX_TDPU_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MNG_ECDSA_PUBKEY(_i) (0x00083300 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: EMPR */ +#define E830_GL_MNG_ECDSA_PUBKEY_MAX_INDEX 11 +#define E830_GL_MNG_ECDSA_PUBKEY_GL_MNG_ECDSA_PUBKEY_S 0 +#define E830_GL_MNG_ECDSA_PUBKEY_GL_MNG_ECDSA_PUBKEY_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_PPRS_RX_SIZE_CTRL_0(_i) (0x00084900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_INDEX 1 +#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_S 16 +#define E830_GL_PPRS_RX_SIZE_CTRL_0_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) +#define E830_GL_PPRS_RX_SIZE_CTRL_1(_i) (0x00085900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_INDEX 1 +#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_S 16 +#define E830_GL_PPRS_RX_SIZE_CTRL_1_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) +#define E830_GL_PPRS_RX_SIZE_CTRL_2(_i) (0x00086900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_INDEX 1 +#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_S 16 +#define E830_GL_PPRS_RX_SIZE_CTRL_2_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) +#define E830_GL_PPRS_RX_SIZE_CTRL_3(_i) (0x00087900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_INDEX 1 +#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_S 16 +#define E830_GL_PPRS_RX_SIZE_CTRL_3_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP 0x00200740 /* Reset Source: CORER */ +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00200744 /* Reset Source: CORER */ +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16) +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24 +#define E830_GL_RPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24) +#define E830_GL_RPRS_PROT_ID_MAP(_i) (0x00200800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_GL_RPRS_PROT_ID_MAP_MAX_INDEX 255 +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_S 0 +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0) +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_S 8 +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8) +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_S 16 +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16) +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_S 24 +#define E830_GL_RPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL(_i) (0x00201000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_MAX_INDEX 63 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28) +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30 +#define E830_GL_RPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30) +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL 0x00200748 /* Reset Source: CORER */ +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0 +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0) +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1 +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1) +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2 +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2) +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3 +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3) +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4 +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4) +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5 +#define E830_GL_RPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP 0x00203A04 /* Reset Source: CORER */ +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_S 0 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_0_M MAKEMASK(0xFF, 0) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_S 8 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV4_PROT_ID_1_M MAKEMASK(0xFF, 8) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_S 16 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_0_M MAKEMASK(0xFF, 16) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_S 24 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_IP_IPV6_PROT_ID_1_M MAKEMASK(0xFF, 24) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP 0x00203A08 /* Reset Source: CORER */ +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_S 0 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_0_M MAKEMASK(0xFF, 0) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_S 8 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_TCP_PROT_ID_1_M MAKEMASK(0xFF, 8) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_S 16 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_0_M MAKEMASK(0xFF, 16) +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_S 24 +#define E830_GL_TPRS_CSUM_PROT_ID_CFG_UDP_TCP_UDP_PROT_ID_1_M MAKEMASK(0xFF, 24) +#define E830_GL_TPRS_PROT_ID_MAP(_i) (0x00202200 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_GL_TPRS_PROT_ID_MAP_MAX_INDEX 255 +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_S 0 +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID0_M MAKEMASK(0xFF, 0) +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_S 8 +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID1_M MAKEMASK(0xFF, 8) +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_S 16 +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID2_M MAKEMASK(0xFF, 16) +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_S 24 +#define E830_GL_TPRS_PROT_ID_MAP_PROT_ID3_M MAKEMASK(0xFF, 24) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL(_i) (0x00202A00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_MAX_INDEX 63 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_S 0 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_0_M MAKEMASK(0x3, 0) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_S 2 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_1_M MAKEMASK(0x3, 2) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_S 4 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_2_M MAKEMASK(0x3, 4) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_S 6 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_3_M MAKEMASK(0x3, 6) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_S 8 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_4_M MAKEMASK(0x3, 8) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_S 10 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_5_M MAKEMASK(0x3, 10) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_S 12 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_6_M MAKEMASK(0x3, 12) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_S 14 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_7_M MAKEMASK(0x3, 14) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_S 16 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_8_M MAKEMASK(0x3, 16) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_S 18 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_9_M MAKEMASK(0x3, 18) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_S 20 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_10_M MAKEMASK(0x3, 20) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_S 22 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_11_M MAKEMASK(0x3, 22) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_S 24 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_12_M MAKEMASK(0x3, 24) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_S 26 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_13_M MAKEMASK(0x3, 26) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_S 28 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_14_M MAKEMASK(0x3, 28) +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_S 30 +#define E830_GL_TPRS_PROT_ID_MAP_PRFL_PTYPE_PRFL_15_M MAKEMASK(0x3, 30) +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL 0x00203A00 /* Reset Source: CORER */ +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_S 0 +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_0_EN_M BIT(0) +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_S 1 +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_UDP_LEN_1_EN_M BIT(1) +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_S 2 +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_0_M BIT(2) +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_S 3 +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_LEN_1_M BIT(3) +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_S 4 +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_0_M BIT(4) +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_S 5 +#define E830_GL_TPRS_VALIDATE_CHECKS_CTL_VALIDATE_L3_L4_COHERENT_1_M BIT(5) +#define E830_PRT_TDPU_TX_SIZE_CTRL 0x00049D20 /* Reset Source: CORER */ +#define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_S 16 +#define E830_PRT_TDPU_TX_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) +#define E830_PRT_TPB_RX_LB_SIZE_CTRL 0x00099740 /* Reset Source: CORER */ +#define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_S 16 +#define E830_PRT_TPB_RX_LB_SIZE_CTRL_MAX_HEADER_SIZE_M MAKEMASK(0x3FF, 16) +#define E830_GLNVM_AL_DONE_HLP_PAGE 0x02D004B0 /* Reset Source: POR */ +#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_CORER_S 0 +#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_CORER_M BIT(0) +#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_FULLR_S 1 +#define E830_GLNVM_AL_DONE_HLP_PAGE_HLP_FULLR_M BIT(1) +#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE(_DBQM) (0x04000008 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_MAX_INDEX 16383 +#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_DBELL_LSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE(_DBQM) (0x0400000C + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_MAX_INDEX 16383 +#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_DBELL_MSB_PAGE_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PF0INT_OICR_CPM_PAGE_PTM_COMP_S 8 +#define E830_PF0INT_OICR_CPM_PAGE_PTM_COMP_M BIT(8) +#define E830_PF0INT_OICR_CPM_PAGE_RSV4_S 9 +#define E830_PF0INT_OICR_CPM_PAGE_RSV4_M BIT(9) +#define E830_PF0INT_OICR_CPM_PAGE_RSV5_S 10 +#define E830_PF0INT_OICR_CPM_PAGE_RSV5_M BIT(10) +#define E830_PF0INT_OICR_HLP_PAGE_PTM_COMP_S 8 +#define E830_PF0INT_OICR_HLP_PAGE_PTM_COMP_M BIT(8) +#define E830_PF0INT_OICR_HLP_PAGE_RSV4_S 9 +#define E830_PF0INT_OICR_HLP_PAGE_RSV4_M BIT(9) +#define E830_PF0INT_OICR_HLP_PAGE_RSV5_S 10 +#define E830_PF0INT_OICR_HLP_PAGE_RSV5_M BIT(10) +#define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_S 8 +#define E830_PF0INT_OICR_PSM_PAGE_PTM_COMP_M BIT(8) +#define E830_PF0INT_OICR_PSM_PAGE_RSV4_S 9 +#define E830_PF0INT_OICR_PSM_PAGE_RSV4_M BIT(9) +#define E830_PF0INT_OICR_PSM_PAGE_RSV5_S 10 +#define E830_PF0INT_OICR_PSM_PAGE_RSV5_M BIT(10) +#define E830_GL_HIBA(_i) (0x00081000 + ((_i) * 4)) /* _i=0...1023 */ /* Reset Source: EMPR */ +#define E830_GL_HIBA_MAX_INDEX 1023 +#define E830_GL_HIBA_GL_HIBA_S 0 +#define E830_GL_HIBA_GL_HIBA_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_HICR 0x00082040 /* Reset Source: EMPR */ +#define E830_GL_HICR_C_S 1 +#define E830_GL_HICR_C_M BIT(1) +#define E830_GL_HICR_SV_S 2 +#define E830_GL_HICR_SV_M BIT(2) +#define E830_GL_HICR_EV_S 3 +#define E830_GL_HICR_EV_M BIT(3) +#define E830_GL_HICR_EN 0x00082044 /* Reset Source: EMPR */ +#define E830_GL_HICR_EN_EN_S 0 +#define E830_GL_HICR_EN_EN_M BIT(0) +#define E830_GL_HIDA(_i) (0x00082000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: EMPR */ +#define E830_GL_HIDA_MAX_INDEX 15 +#define E830_GL_HIDA_GL_HIDB_S 0 +#define E830_GL_HIDA_GL_HIDB_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_0_SPARE_M MAKEMASK(0xF, 18) +#define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_1_SPARE_M MAKEMASK(0xF, 18) +#define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_2_SPARE_M MAKEMASK(0xF, 18) +#define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_3_SPARE_M MAKEMASK(0xF, 18) +#define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_4_SPARE_M MAKEMASK(0xF, 18) +#define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_5_SPARE_M MAKEMASK(0xF, 18) +#define E830_GLFLXP_RXDID_FLX_WRD_6(_i) (0x0045CE00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GLFLXP_RXDID_FLX_WRD_6_MAX_INDEX 63 +#define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_S 0 +#define E830_GLFLXP_RXDID_FLX_WRD_6_PROT_MDID_M MAKEMASK(0xFF, 0) +#define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_S 8 +#define E830_GLFLXP_RXDID_FLX_WRD_6_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) +#define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_6_L2TAG_OVRD_EN_M BIT(18) +#define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_S 19 +#define E830_GLFLXP_RXDID_FLX_WRD_6_SPARE_M MAKEMASK(0x7, 19) +#define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_S 30 +#define E830_GLFLXP_RXDID_FLX_WRD_6_RXDID_OPCODE_M MAKEMASK(0x3, 30) +#define E830_GLFLXP_RXDID_FLX_WRD_7(_i) (0x0045CF00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GLFLXP_RXDID_FLX_WRD_7_MAX_INDEX 63 +#define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_S 0 +#define E830_GLFLXP_RXDID_FLX_WRD_7_PROT_MDID_M MAKEMASK(0xFF, 0) +#define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_S 8 +#define E830_GLFLXP_RXDID_FLX_WRD_7_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) +#define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_7_L2TAG_OVRD_EN_M BIT(18) +#define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_S 19 +#define E830_GLFLXP_RXDID_FLX_WRD_7_SPARE_M MAKEMASK(0x7, 19) +#define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_S 30 +#define E830_GLFLXP_RXDID_FLX_WRD_7_RXDID_OPCODE_M MAKEMASK(0x3, 30) +#define E830_GLFLXP_RXDID_FLX_WRD_8(_i) (0x0045D500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */ +#define E830_GLFLXP_RXDID_FLX_WRD_8_MAX_INDEX 63 +#define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_S 0 +#define E830_GLFLXP_RXDID_FLX_WRD_8_PROT_MDID_M MAKEMASK(0xFF, 0) +#define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_S 8 +#define E830_GLFLXP_RXDID_FLX_WRD_8_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8) +#define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_S 18 +#define E830_GLFLXP_RXDID_FLX_WRD_8_L2TAG_OVRD_EN_M BIT(18) +#define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_S 19 +#define E830_GLFLXP_RXDID_FLX_WRD_8_SPARE_M MAKEMASK(0x7, 19) +#define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_S 30 +#define E830_GLFLXP_RXDID_FLX_WRD_8_RXDID_OPCODE_M MAKEMASK(0x3, 30) +#define E830_GL_FW_LOGS(_i) (0x00082800 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: POR */ +#define E830_GL_FW_LOGS_MAX_INDEX 255 +#define E830_GL_FW_LOGS_GL_FW_LOGS_S 0 +#define E830_GL_FW_LOGS_GL_FW_LOGS_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_FWSTS_FWABS_S 10 +#define E830_GL_FWSTS_FWABS_M MAKEMASK(0x3, 10) +#define E830_GL_FWSTS_FW_FAILOVER_TRIG_S 12 +#define E830_GL_FWSTS_FW_FAILOVER_TRIG_M BIT(12) +#define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_S 19 +#define E830_GLGEN_RSTAT_EMPR_WO_GLOBR_CNT_M MAKEMASK(0x3, 19) +#define E830_GLPCI_PLATFORM_INFO 0x0009DDC4 /* Reset Source: POR */ +#define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_S 0 +#define E830_GLPCI_PLATFORM_INFO_PLATFORM_TYPE_M MAKEMASK(0xFF, 0) +#define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_S 21 +#define E830_GL_MDCK_TDAT_TCLAN_DESC_TYPE_ACL_DTYPE_NOT_ALLOWED_M BIT(21) +#define E830_GL_TPB_LOCAL_TOPO 0x000996F4 /* Reset Source: CORER */ +#define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_S 0 +#define E830_GL_TPB_LOCAL_TOPO_ALLOW_TOPO_OVERRIDE_M BIT(0) +#define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_S 1 +#define E830_GL_TPB_LOCAL_TOPO_TOPO_VAL_M MAKEMASK(0x3, 1) +#define E830_GL_TPB_PM_RESET 0x000996F0 /* Reset Source: CORER */ +#define E830_GL_TPB_PM_RESET_MAC_PM_RESET_S 0 +#define E830_GL_TPB_PM_RESET_MAC_PM_RESET_M BIT(0) +#define E830_GL_TPB_PM_RESET_RPB_PM_RESET_S 1 +#define E830_GL_TPB_PM_RESET_RPB_PM_RESET_M BIT(1) +#define E830_GLTPB_100G_MAC_FC_THRESH1 0x00099724 /* Reset Source: CORER */ +#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_S 0 +#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_S 16 +#define E830_GLTPB_100G_MAC_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_GLTPB_100G_RPB_FC_THRESH0 0x0009963C /* Reset Source: CORER */ +#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_S 0 +#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_S 16 +#define E830_GLTPB_100G_RPB_FC_THRESH0_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_GLTPB_100G_RPB_FC_THRESH1 0x00099728 /* Reset Source: CORER */ +#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_S 0 +#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT2_FC_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_S 16 +#define E830_GLTPB_100G_RPB_FC_THRESH1_PORT3_FC_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_S 12 +#define E830_GL_UFUSE_SOC_MAX_PORT_SPEED_M MAKEMASK(0xFFFF, 12) +#define E830_PF0INT_OICR_CPM_PTM_COMP_S 8 +#define E830_PF0INT_OICR_CPM_PTM_COMP_M BIT(8) +#define E830_PF0INT_OICR_CPM_RSV4_S 9 +#define E830_PF0INT_OICR_CPM_RSV4_M BIT(9) +#define E830_PF0INT_OICR_CPM_RSV5_S 10 +#define E830_PF0INT_OICR_CPM_RSV5_M BIT(10) +#define E830_PF0INT_OICR_HLP_PTM_COMP_S 8 +#define E830_PF0INT_OICR_HLP_PTM_COMP_M BIT(8) +#define E830_PF0INT_OICR_HLP_RSV4_S 9 +#define E830_PF0INT_OICR_HLP_RSV4_M BIT(9) +#define E830_PF0INT_OICR_HLP_RSV5_S 10 +#define E830_PF0INT_OICR_HLP_RSV5_M BIT(10) +#define E830_PF0INT_OICR_PSM_PTM_COMP_S 8 +#define E830_PF0INT_OICR_PSM_PTM_COMP_M BIT(8) +#define E830_PF0INT_OICR_PSM_RSV4_S 9 +#define E830_PF0INT_OICR_PSM_RSV4_M BIT(9) +#define E830_PF0INT_OICR_PSM_RSV5_S 10 +#define E830_PF0INT_OICR_PSM_RSV5_M BIT(10) +#define E830_PFINT_OICR_PTM_COMP_S 8 +#define E830_PFINT_OICR_PTM_COMP_M BIT(8) +#define E830_PFINT_OICR_RSV4_S 9 +#define E830_PFINT_OICR_RSV4_M BIT(9) +#define E830_PFINT_OICR_RSV5_S 10 +#define E830_PFINT_OICR_RSV5_M BIT(10) +#define E830_GLQF_FLAT_QTABLE(_i) (0x00488000 + ((_i) * 4)) /* _i=0...6143 */ /* Reset Source: CORER */ +#define E830_GLQF_FLAT_QTABLE_MAX_INDEX 6143 +#define E830_GLQF_FLAT_QTABLE_QINDEX_0_S 0 +#define E830_GLQF_FLAT_QTABLE_QINDEX_0_M MAKEMASK(0x7FF, 0) +#define E830_GLQF_FLAT_QTABLE_QINDEX_1_S 16 +#define E830_GLQF_FLAT_QTABLE_QINDEX_1_M MAKEMASK(0x7FF, 16) +#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA 0x001E3854 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_200G_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL01_QUANTA_THRESH 0x001E3864 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0 +#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16 +#define E830_PRTMAC_200G_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA 0x001E3858 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_200G_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL23_QUANTA_THRESH 0x001E3868 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0 +#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16 +#define E830_PRTMAC_200G_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA 0x001E385C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_200G_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL45_QUANTA_THRESH 0x001E386C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0 +#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16 +#define E830_PRTMAC_200G_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA 0x001E3860 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_200G_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_CL67_QUANTA_THRESH 0x001E3870 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0 +#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16 +#define E830_PRTMAC_200G_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_COMMAND_CONFIG 0x001E3808 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_S 0 +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ENA_M BIT(0) +#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_S 1 +#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_ENA_M BIT(1) +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED1_S 3 +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED1_M BIT(3) +#define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_S 4 +#define E830_PRTMAC_200G_COMMAND_CONFIG_PROMIS_EN_M BIT(4) +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED2_S 5 +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED2_M BIT(5) +#define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_S 6 +#define E830_PRTMAC_200G_COMMAND_CONFIG_CRC_FWD_M BIT(6) +#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_S 7 +#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_FWD_M BIT(7) +#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_S 8 +#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8) +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_S 9 +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9) +#define E830_PRTMAC_200G_COMMAND_CONFIG_LOOP_ENA_S 10 +#define E830_PRTMAC_200G_COMMAND_CONFIG_LOOP_ENA_M BIT(10) +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_S 11 +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_PAD_EN_M BIT(11) +#define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_S 12 +#define E830_PRTMAC_200G_COMMAND_CONFIG_SW_RESET_M BIT(12) +#define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_S 13 +#define E830_PRTMAC_200G_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13) +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED3_S 14 +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED3_M BIT(14) +#define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_S 15 +#define E830_PRTMAC_200G_COMMAND_CONFIG_PHY_TXENA_M BIT(15) +#define E830_PRTMAC_200G_COMMAND_CONFIG_FORCE_SEND__S 16 +#define E830_PRTMAC_200G_COMMAND_CONFIG_FORCE_SEND__M BIT(16) +#define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_S 17 +#define E830_PRTMAC_200G_COMMAND_CONFIG_NO_LGTH_CHECK_M BIT(17) +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED5_S 18 +#define E830_PRTMAC_200G_COMMAND_CONFIG_RESERVED5_M BIT(18) +#define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_S 19 +#define E830_PRTMAC_200G_COMMAND_CONFIG_PFC_MODE_M BIT(19) +#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20 +#define E830_PRTMAC_200G_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20) +#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_S 21 +#define E830_PRTMAC_200G_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21) +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_S 22 +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FLUSH_M BIT(22) +#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_S 25 +#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25) +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_S 26 +#define E830_PRTMAC_200G_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26) +#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_S 27 +#define E830_PRTMAC_200G_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27) +#define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_S 31 +#define E830_PRTMAC_200G_COMMAND_CONFIG_INV_LOOP_M BIT(31) +#define E830_PRTMAC_200G_CRC_INV_M 0x001E384C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_S 0 +#define E830_PRTMAC_200G_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_FRM_LENGTH 0x001E3814 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_S 0 +#define E830_PRTMAC_200G_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_S 16 +#define E830_PRTMAC_200G_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_HASHTABLE_LOAD 0x001E382C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_S 0 +#define E830_PRTMAC_200G_HASHTABLE_LOAD_HASH_TABLE_ADDR_M MAKEMASK(0x3F, 0) +#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED_2_S 6 +#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED_2_M MAKEMASK(0x3, 6) +#define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_S 8 +#define E830_PRTMAC_200G_HASHTABLE_LOAD_MCAST_EN_M BIT(8) +#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED1_S 9 +#define E830_PRTMAC_200G_HASHTABLE_LOAD_RESERVED1_M MAKEMASK(0x7FFFFF, 9) +#define E830_PRTMAC_200G_MAC_ADDR_0 0x001E380C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_S 0 +#define E830_PRTMAC_200G_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_MAC_ADDR_1 0x001E3810 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_S 0 +#define E830_PRTMAC_200G_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_MDIO_CFG_STATUS 0x001E3830 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_S 0 +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0) +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1 +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1) +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2 +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2) +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5 +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5) +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6 +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6) +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7 +#define E830_PRTMAC_200G_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7) +#define E830_PRTMAC_200G_MDIO_COMMAND 0x001E3834 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_S 0 +#define E830_PRTMAC_200G_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_MDIO_DATA 0x001E3838 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_S 0 +#define E830_PRTMAC_200G_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_MDIO_REGADDR 0x001E383C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_S 0 +#define E830_PRTMAC_200G_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_REVISION 0x001E3800 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_REVISION_CORE_REVISION_S 0 +#define E830_PRTMAC_200G_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0) +#define E830_PRTMAC_200G_REVISION_CORE_VERSION_S 8 +#define E830_PRTMAC_200G_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8) +#define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_S 16 +#define E830_PRTMAC_200G_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_RX_PAUSE_STATUS 0x001E3874 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0 +#define E830_PRTMAC_200G_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0) +#define E830_PRTMAC_200G_SCRATCH 0x001E3804 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_SCRATCH_SCRATCH_S 0 +#define E830_PRTMAC_200G_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_STATUS 0x001E3840 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_S 0 +#define E830_PRTMAC_200G_STATUS_RX_LOC_FAULT_M BIT(0) +#define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_S 1 +#define E830_PRTMAC_200G_STATUS_RX_REM_FAULT_M BIT(1) +#define E830_PRTMAC_200G_STATUS_PHY_LOS_S 2 +#define E830_PRTMAC_200G_STATUS_PHY_LOS_M BIT(2) +#define E830_PRTMAC_200G_STATUS_TS_AVAIL_S 3 +#define E830_PRTMAC_200G_STATUS_TS_AVAIL_M BIT(3) +#define E830_PRTMAC_200G_STATUS_RESERVED_5_S 4 +#define E830_PRTMAC_200G_STATUS_RESERVED_5_M BIT(4) +#define E830_PRTMAC_200G_STATUS_TX_EMPTY_S 5 +#define E830_PRTMAC_200G_STATUS_TX_EMPTY_M BIT(5) +#define E830_PRTMAC_200G_STATUS_RX_EMPTY_S 6 +#define E830_PRTMAC_200G_STATUS_RX_EMPTY_M BIT(6) +#define E830_PRTMAC_200G_STATUS_RESERVED1_S 7 +#define E830_PRTMAC_200G_STATUS_RESERVED1_M BIT(7) +#define E830_PRTMAC_200G_STATUS_TX_ISIDLE_S 8 +#define E830_PRTMAC_200G_STATUS_TX_ISIDLE_M BIT(8) +#define E830_PRTMAC_200G_STATUS_RESERVED2_S 9 +#define E830_PRTMAC_200G_STATUS_RESERVED2_M MAKEMASK(0x7FFFFF, 9) +#define E830_PRTMAC_200G_TS_TIMESTAMP 0x001E387C /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_S 0 +#define E830_PRTMAC_200G_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_200G_TX_FIFO_SECTIONS 0x001E3820 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0 +#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16 +#define E830_PRTMAC_200G_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_200G_TX_IPG_LENGTH 0x001E3844 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_S 0 +#define E830_PRTMAC_200G_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x7F, 0) +#define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_S 19 +#define E830_PRTMAC_200G_TX_IPG_LENGTH_IPG_COMP_12_0_M MAKEMASK(0x1FFF, 19) +#define E830_PRTMAC_200G_XIF_MODE 0x001E3880 /* Reset Source: GLOBR */ +#define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_S 0 +#define E830_PRTMAC_200G_XIF_MODE_RESERVED_1_M MAKEMASK(0x1F, 0) +#define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_S 5 +#define E830_PRTMAC_200G_XIF_MODE_ONE_STEP_ENA_M BIT(5) +#define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_S 17 +#define E830_PRTMAC_200G_XIF_MODE_PFC_PULSE_MODE_M BIT(17) +#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_S 18 +#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_MODE_M BIT(18) +#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_S 19 +#define E830_PRTMAC_200G_XIF_MODE_PFC_LP_16PRI_M BIT(19) +#define E830_PRTMAC_CF_GEN_STATUS 0x001E33C0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_S 0 +#define E830_PRTMAC_CF_GEN_STATUS_CF_GEN_SENT_M BIT(0) +#define E830_PRTMAC_CL01_PAUSE_QUANTA 0x001E32A0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL01_QUANTA_THRESH 0x001E3320 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_S 0 +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_S 16 +#define E830_PRTMAC_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL23_PAUSE_QUANTA 0x001E32C0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL23_QUANTA_THRESH 0x001E3340 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_S 0 +#define E830_PRTMAC_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_S 16 +#define E830_PRTMAC_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL45_PAUSE_QUANTA 0x001E32E0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL45_QUANTA_THRESH 0x001E3360 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_S 0 +#define E830_PRTMAC_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_S 16 +#define E830_PRTMAC_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL67_PAUSE_QUANTA 0x001E3300 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_S 0 +#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_S 16 +#define E830_PRTMAC_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_CL67_QUANTA_THRESH 0x001E3380 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_S 0 +#define E830_PRTMAC_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_S 16 +#define E830_PRTMAC_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_COMMAND_CONFIG 0x001E3040 /* Reset Source: GLOBR */ +#define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_S 0 +#define E830_PRTMAC_COMMAND_CONFIG_TX_ENA_M BIT(0) +#define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_S 1 +#define E830_PRTMAC_COMMAND_CONFIG_RX_ENA_M BIT(1) +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_S 3 +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED1_M BIT(3) +#define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_S 4 +#define E830_PRTMAC_COMMAND_CONFIG_PROMIS_EN_M BIT(4) +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_S 5 +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED2_M BIT(5) +#define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_S 6 +#define E830_PRTMAC_COMMAND_CONFIG_CRC_FWD_M BIT(6) +#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_S 7 +#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_FWD_M BIT(7) +#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_S 8 +#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_IGNORE_M BIT(8) +#define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_S 9 +#define E830_PRTMAC_COMMAND_CONFIG_TX_ADDR_INS_M BIT(9) +#define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_S 10 +#define E830_PRTMAC_COMMAND_CONFIG_LOOP_ENA_M BIT(10) +#define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_S 11 +#define E830_PRTMAC_COMMAND_CONFIG_TX_PAD_EN_M BIT(11) +#define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_S 12 +#define E830_PRTMAC_COMMAND_CONFIG_SW_RESET_M BIT(12) +#define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_S 13 +#define E830_PRTMAC_COMMAND_CONFIG_CNTL_FRM_ENA_M BIT(13) +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_S 14 +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED3_M BIT(14) +#define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_S 15 +#define E830_PRTMAC_COMMAND_CONFIG_PHY_TXENA_M BIT(15) +#define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__S 16 +#define E830_PRTMAC_COMMAND_CONFIG_FORCE_SEND__M BIT(16) +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_S 17 +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED4_M BIT(17) +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_S 18 +#define E830_PRTMAC_COMMAND_CONFIG_RESERVED5_M BIT(18) +#define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_S 19 +#define E830_PRTMAC_COMMAND_CONFIG_PFC_MODE_M BIT(19) +#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_S 20 +#define E830_PRTMAC_COMMAND_CONFIG_PAUSE_PFC_COMP_M BIT(20) +#define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_S 21 +#define E830_PRTMAC_COMMAND_CONFIG_RX_SFD_ANY_M BIT(21) +#define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_S 22 +#define E830_PRTMAC_COMMAND_CONFIG_TX_FLUSH_M BIT(22) +#define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_S 23 +#define E830_PRTMAC_COMMAND_CONFIG_TX_LOWP_ENA_M BIT(23) +#define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_S 24 +#define E830_PRTMAC_COMMAND_CONFIG_REG_LOWP_RXEMPTY_M BIT(24) +#define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_S 25 +#define E830_PRTMAC_COMMAND_CONFIG_FLT_TX_STOP_M BIT(25) +#define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_S 26 +#define E830_PRTMAC_COMMAND_CONFIG_TX_FIFO_RESET_M BIT(26) +#define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_S 27 +#define E830_PRTMAC_COMMAND_CONFIG_FLT_HDL_DIS_M BIT(27) +#define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_S 28 +#define E830_PRTMAC_COMMAND_CONFIG_TX_PAUSE_DIS_M BIT(28) +#define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_S 29 +#define E830_PRTMAC_COMMAND_CONFIG_RX_PAUSE_DIS_M BIT(29) +#define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_S 30 +#define E830_PRTMAC_COMMAND_CONFIG_SHORT_PREAM_M BIT(30) +#define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_S 31 +#define E830_PRTMAC_COMMAND_CONFIG_NO_PREAM_M BIT(31) +#define E830_PRTMAC_CRC_INV_M 0x001E3260 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_S 0 +#define E830_PRTMAC_CRC_INV_MASK_CRC_INV_MASK_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_CRC_MODE 0x001E3240 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CRC_MODE_RESERVED_1_S 0 +#define E830_PRTMAC_CRC_MODE_RESERVED_1_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_S 16 +#define E830_PRTMAC_CRC_MODE_DISABLE_RX_CRC_CHECKING_M BIT(16) +#define E830_PRTMAC_CRC_MODE_RESERVED1_S 17 +#define E830_PRTMAC_CRC_MODE_RESERVED1_M BIT(17) +#define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_S 18 +#define E830_PRTMAC_CRC_MODE_ONE_BYTE_CRC_M BIT(18) +#define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_S 19 +#define E830_PRTMAC_CRC_MODE_TWO_BYTES_CRC_M BIT(19) +#define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_S 20 +#define E830_PRTMAC_CRC_MODE_ZERO_BYTE_CRC_M BIT(20) +#define E830_PRTMAC_CRC_MODE_RESERVED2_S 21 +#define E830_PRTMAC_CRC_MODE_RESERVED2_M MAKEMASK(0x7FF, 21) +#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE 0x001E2180 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S 0 +#define E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0) +#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE 0x001E21A0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S 0 +#define E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0) +#define E830_PRTMAC_FRM_LENGTH 0x001E30A0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_S 0 +#define E830_PRTMAC_FRM_LENGTH_FRM_LENGTH_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_FRM_LENGTH_TX_MTU_S 16 +#define E830_PRTMAC_FRM_LENGTH_TX_MTU_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_MAC_ADDR_0 0x001E3060 /* Reset Source: GLOBR */ +#define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_S 0 +#define E830_PRTMAC_MAC_ADDR_0_MAC_ADDR_0_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_MAC_ADDR_1 0x001E3080 /* Reset Source: GLOBR */ +#define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_S 0 +#define E830_PRTMAC_MAC_ADDR_1_MAC_ADDR_1_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_MDIO_CFG_STATUS 0x001E3180 /* Reset Source: GLOBR */ +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_S 0 +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_BUSY_M BIT(0) +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_S 1 +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_RD_ERR_M BIT(1) +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_S 2 +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_HOLD_TIME_M MAKEMASK(0x7, 2) +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_S 5 +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_DIS_PREAMBLE_M BIT(5) +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_S 6 +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLS_45_EN_M BIT(6) +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_S 7 +#define E830_PRTMAC_MDIO_CFG_STATUS_MDIO_CLK_DIVISOR_M MAKEMASK(0x1FF, 7) +#define E830_PRTMAC_MDIO_COMMAND 0x001E31A0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_S 0 +#define E830_PRTMAC_MDIO_COMMAND_MDIO_COMMAND_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_MDIO_DATA 0x001E31C0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_MDIO_DATA_MDIO_DATA_S 0 +#define E830_PRTMAC_MDIO_DATA_MDIO_DATA_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_MDIO_REGADDR 0x001E31E0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_S 0 +#define E830_PRTMAC_MDIO_REGADDR_MDIO_REGADDR_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_REVISION 0x001E3000 /* Reset Source: GLOBR */ +#define E830_PRTMAC_REVISION_CORE_REVISION_S 0 +#define E830_PRTMAC_REVISION_CORE_REVISION_M MAKEMASK(0xFF, 0) +#define E830_PRTMAC_REVISION_CORE_VERSION_S 8 +#define E830_PRTMAC_REVISION_CORE_VERSION_M MAKEMASK(0xFF, 8) +#define E830_PRTMAC_REVISION_CUSTOMER_VERSION_S 16 +#define E830_PRTMAC_REVISION_CUSTOMER_VERSION_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_RX_PAUSE_STATUS 0x001E33A0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_S 0 +#define E830_PRTMAC_RX_PAUSE_STATUS_RX_PAUSE_STATUS_M MAKEMASK(0xFF, 0) +#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_S 12 +#define E830_PRTMAC_RX_PKT_DRP_CNT_RX_OFLOW_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 12) +#define E830_PRTMAC_SCRATCH 0x001E3020 /* Reset Source: GLOBR */ +#define E830_PRTMAC_SCRATCH_SCRATCH_S 0 +#define E830_PRTMAC_SCRATCH_SCRATCH_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_STATUS 0x001E3200 /* Reset Source: GLOBR */ +#define E830_PRTMAC_STATUS_RX_LOC_FAULT_S 0 +#define E830_PRTMAC_STATUS_RX_LOC_FAULT_M BIT(0) +#define E830_PRTMAC_STATUS_RX_REM_FAULT_S 1 +#define E830_PRTMAC_STATUS_RX_REM_FAULT_M BIT(1) +#define E830_PRTMAC_STATUS_PHY_LOS_S 2 +#define E830_PRTMAC_STATUS_PHY_LOS_M BIT(2) +#define E830_PRTMAC_STATUS_TS_AVAIL_S 3 +#define E830_PRTMAC_STATUS_TS_AVAIL_M BIT(3) +#define E830_PRTMAC_STATUS_RX_LOWP_S 4 +#define E830_PRTMAC_STATUS_RX_LOWP_M BIT(4) +#define E830_PRTMAC_STATUS_TX_EMPTY_S 5 +#define E830_PRTMAC_STATUS_TX_EMPTY_M BIT(5) +#define E830_PRTMAC_STATUS_RX_EMPTY_S 6 +#define E830_PRTMAC_STATUS_RX_EMPTY_M BIT(6) +#define E830_PRTMAC_STATUS_RX_LINT_FAULT_S 7 +#define E830_PRTMAC_STATUS_RX_LINT_FAULT_M BIT(7) +#define E830_PRTMAC_STATUS_TX_ISIDLE_S 8 +#define E830_PRTMAC_STATUS_TX_ISIDLE_M BIT(8) +#define E830_PRTMAC_STATUS_RESERVED_10_S 9 +#define E830_PRTMAC_STATUS_RESERVED_10_M MAKEMASK(0x7FFFFF, 9) +#define E830_PRTMAC_TS_RX_PCS_LATENCY 0x001E2220 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_S 0 +#define E830_PRTMAC_TS_RX_PCS_LATENCY_TS_RX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_TS_TIMESTAMP 0x001E33E0 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_S 0 +#define E830_PRTMAC_TS_TIMESTAMP_TS_TIMESTAMP_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_S 0 +#define E830_PRTMAC_TS_TX_MEM_VALID_H_TIMESTAMP_TX_VALID_ARR_H_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_S 0 +#define E830_PRTMAC_TS_TX_MEM_VALID_L_TIMESTAMP_TX_VALID_ARR_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PRTMAC_TS_TX_PCS_LATENCY 0x001E2200 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_S 0 +#define E830_PRTMAC_TS_TX_PCS_LATENCY_TS_TX_PCS_LATENCY_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_TX_FIFO_SECTIONS 0x001E3100 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_S 0 +#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_AVAIL_THRESHOLD_M MAKEMASK(0xFFFF, 0) +#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_S 16 +#define E830_PRTMAC_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_THRESHOLD_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_TX_IPG_LENGTH 0x001E3220 /* Reset Source: GLOBR */ +#define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_S 0 +#define E830_PRTMAC_TX_IPG_LENGTH_AVG_IPG_LEN_M MAKEMASK(0x3F, 0) +#define E830_PRTMAC_TX_IPG_LENGTH_RESERVED1_S 6 +#define E830_PRTMAC_TX_IPG_LENGTH_RESERVED1_M MAKEMASK(0x3, 6) +#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_S 8 +#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_23_16_M MAKEMASK(0xFF, 8) +#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_S 16 +#define E830_PRTMAC_TX_IPG_LENGTH_IPG_COMP_15_0_M MAKEMASK(0xFFFF, 16) +#define E830_PRTMAC_XIF_MODE 0x001E3400 /* Reset Source: GLOBR */ +#define E830_PRTMAC_XIF_MODE_XGMII_ENA_S 0 +#define E830_PRTMAC_XIF_MODE_XGMII_ENA_M BIT(0) +#define E830_PRTMAC_XIF_MODE_RESERVED_2_S 1 +#define E830_PRTMAC_XIF_MODE_RESERVED_2_M MAKEMASK(0x7, 1) +#define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_S 4 +#define E830_PRTMAC_XIF_MODE_PAUSETIMERX8_M BIT(4) +#define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_S 5 +#define E830_PRTMAC_XIF_MODE_ONE_STEP_ENA_M BIT(5) +#define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_S 6 +#define E830_PRTMAC_XIF_MODE_RX_PAUSE_BYPASS_M BIT(6) +#define E830_PRTMAC_XIF_MODE_RESERVED1_S 7 +#define E830_PRTMAC_XIF_MODE_RESERVED1_M BIT(7) +#define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_S 8 +#define E830_PRTMAC_XIF_MODE_TX_MAC_RS_ERR_M BIT(8) +#define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_S 9 +#define E830_PRTMAC_XIF_MODE_TS_DELTA_MODE_M BIT(9) +#define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_S 10 +#define E830_PRTMAC_XIF_MODE_TS_DELAY_MODE_M BIT(10) +#define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_S 11 +#define E830_PRTMAC_XIF_MODE_TS_BINARY_MODE_M BIT(11) +#define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_S 12 +#define E830_PRTMAC_XIF_MODE_TS_UPD64_MODE_M BIT(12) +#define E830_PRTMAC_XIF_MODE_RESERVED2_S 13 +#define E830_PRTMAC_XIF_MODE_RESERVED2_M MAKEMASK(0x7, 13) +#define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_S 16 +#define E830_PRTMAC_XIF_MODE_RX_CNT_MODE_M BIT(16) +#define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_S 17 +#define E830_PRTMAC_XIF_MODE_PFC_PULSE_MODE_M BIT(17) +#define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_S 18 +#define E830_PRTMAC_XIF_MODE_PFC_LP_MODE_M BIT(18) +#define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_S 19 +#define E830_PRTMAC_XIF_MODE_PFC_LP_16PRI_M BIT(19) +#define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_S 20 +#define E830_PRTMAC_XIF_MODE_TS_SFD_ENA_M BIT(20) +#define E830_PRTMAC_XIF_MODE_RESERVED3_S 21 +#define E830_PRTMAC_XIF_MODE_RESERVED3_M MAKEMASK(0x7FF, 21) +#define E830_PRTTSYN_TXTIME_H(_i) (0x001E5004 + ((_i) * 64)) /* _i=0...63 */ /* Reset Source: GLOBR */ +#define E830_PRTTSYN_TXTIME_H_MAX_INDEX 63 +#define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_S 0 +#define E830_PRTTSYN_TXTIME_H_TX_TIMESTAMP_HIGH_M MAKEMASK(0xFF, 0) +#define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 64)) /* _i=0...63 */ /* Reset Source: GLOBR */ +#define E830_PRTTSYN_TXTIME_L_MAX_INDEX 63 +#define E830_PRTTSYN_TXTIME_L_TX_VALID_S 0 +#define E830_PRTTSYN_TXTIME_L_TX_VALID_M BIT(0) +#define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_S 1 +#define E830_PRTTSYN_TXTIME_L_TX_TIMESTAMP_LOW_M MAKEMASK(0x7FFFFFFF, 1) +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_S 28 +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SW_ABOVE_HW_TAIL_M BIT(28) +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_S 29 +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_SAME_TAIL_M BIT(29) +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_S 30 +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_TAIL_GE_QLEN_M BIT(30) +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_S 31 +#define E830_GL_MDCK_EN_TX_PQM_TXT_MAL_UR_M BIT(31) +#define E830_GL_MDET_HIF_ERR_FIFO 0x00096844 /* Reset Source: CORER */ +#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_NUM_S 0 +#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_NUM_M MAKEMASK(0x3FF, 0) +#define E830_GL_MDET_HIF_ERR_FIFO_PF_NUM_S 10 +#define E830_GL_MDET_HIF_ERR_FIFO_PF_NUM_M MAKEMASK(0x7, 10) +#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_TYPE_S 13 +#define E830_GL_MDET_HIF_ERR_FIFO_FUNC_TYPE_M MAKEMASK(0x3, 13) +#define E830_GL_MDET_HIF_ERR_FIFO_MAL_TYPE_S 15 +#define E830_GL_MDET_HIF_ERR_FIFO_MAL_TYPE_M MAKEMASK(0x1F, 15) +#define E830_GL_MDET_HIF_ERR_FIFO_FIFO_FULL_S 20 +#define E830_GL_MDET_HIF_ERR_FIFO_FIFO_FULL_M BIT(20) +#define E830_GL_MDET_HIF_ERR_FIFO_VALID_S 21 +#define E830_GL_MDET_HIF_ERR_FIFO_VALID_M BIT(21) +#define E830_GL_MDET_HIF_ERR_PF_CNT(_i) (0x00096804 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_HIF_ERR_PF_CNT_MAX_INDEX 7 +#define E830_GL_MDET_HIF_ERR_PF_CNT_CNT_S 0 +#define E830_GL_MDET_HIF_ERR_PF_CNT_CNT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GL_MDET_HIF_ERR_VF(_i) (0x00096824 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GL_MDET_HIF_ERR_VF_MAX_INDEX 7 +#define E830_GL_MDET_HIF_ERR_VF_VF_MAL_EVENT_S 0 +#define E830_GL_MDET_HIF_ERR_VF_VF_MAL_EVENT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PF_MDET_HIF_ERR 0x00096880 /* Reset Source: CORER */ +#define E830_PF_MDET_HIF_ERR_VALID_S 0 +#define E830_PF_MDET_HIF_ERR_VALID_M BIT(0) +#define E830_VM_MDET_TX_TCLAN(_i) (0x000FC000 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ +#define E830_VM_MDET_TX_TCLAN_MAX_INDEX 767 +#define E830_VM_MDET_TX_TCLAN_VALID_S 0 +#define E830_VM_MDET_TX_TCLAN_VALID_M BIT(0) +#define E830_VP_MDET_HIF_ERR(_VF) (0x00096C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_VP_MDET_HIF_ERR_MAX_INDEX 255 +#define E830_VP_MDET_HIF_ERR_VALID_S 0 +#define E830_VP_MDET_HIF_ERR_VALID_M BIT(0) +#define E830_GLNVM_FLA_GLOBAL_LOCKED_S 7 +#define E830_GLNVM_FLA_GLOBAL_LOCKED_M BIT(7) +#define E830_DMA_AGENT_AT0 0x000BE268 /* Reset Source: PCIR */ +#define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_S 0 +#define E830_DMA_AGENT_AT0_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0) +#define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_S 2 +#define E830_DMA_AGENT_AT0_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2) +#define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_S 4 +#define E830_DMA_AGENT_AT0_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4) +#define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_S 6 +#define E830_DMA_AGENT_AT0_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6) +#define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_S 8 +#define E830_DMA_AGENT_AT0_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8) +#define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_S 10 +#define E830_DMA_AGENT_AT0_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10) +#define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_S 12 +#define E830_DMA_AGENT_AT0_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12) +#define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_S 14 +#define E830_DMA_AGENT_AT0_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14) +#define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_S 16 +#define E830_DMA_AGENT_AT0_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16) +#define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_S 18 +#define E830_DMA_AGENT_AT0_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18) +#define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_S 20 +#define E830_DMA_AGENT_AT0_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20) +#define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_S 22 +#define E830_DMA_AGENT_AT0_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22) +#define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_S 24 +#define E830_DMA_AGENT_AT0_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24) +#define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_S 26 +#define E830_DMA_AGENT_AT0_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26) +#define E830_DMA_AGENT_AT1 0x000BE26C /* Reset Source: PCIR */ +#define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_S 0 +#define E830_DMA_AGENT_AT1_RLAN_PASID_SELECTED_M MAKEMASK(0x3, 0) +#define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_S 2 +#define E830_DMA_AGENT_AT1_TCLAN_PASID_SELECTED_M MAKEMASK(0x3, 2) +#define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_S 4 +#define E830_DMA_AGENT_AT1_PQM_DBL_PASID_SELECTED_M MAKEMASK(0x3, 4) +#define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_S 6 +#define E830_DMA_AGENT_AT1_PQM_DESC_PASID_SELECTED_M MAKEMASK(0x3, 6) +#define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_S 8 +#define E830_DMA_AGENT_AT1_PQM_TS_DESC_PASID_SELECTED_M MAKEMASK(0x3, 8) +#define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_S 10 +#define E830_DMA_AGENT_AT1_RDPU_PASID_SELECTED_M MAKEMASK(0x3, 10) +#define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_S 12 +#define E830_DMA_AGENT_AT1_TDPU_PASID_SELECTED_M MAKEMASK(0x3, 12) +#define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_S 14 +#define E830_DMA_AGENT_AT1_MBX_PASID_SELECTED_M MAKEMASK(0x3, 14) +#define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_S 16 +#define E830_DMA_AGENT_AT1_MNG_PASID_SELECTED_M MAKEMASK(0x3, 16) +#define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_S 18 +#define E830_DMA_AGENT_AT1_TEP_PMAT_PASID_SELECTED_M MAKEMASK(0x3, 18) +#define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_S 20 +#define E830_DMA_AGENT_AT1_RX_PE_PASID_SELECTED_M MAKEMASK(0x3, 20) +#define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_S 22 +#define E830_DMA_AGENT_AT1_TX_PE_PASID_SELECTED_M MAKEMASK(0x3, 22) +#define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_S 24 +#define E830_DMA_AGENT_AT1_PEPMAT_PASID_SELECTED_M MAKEMASK(0x3, 24) +#define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_S 26 +#define E830_DMA_AGENT_AT1_FPMAT_PASID_SELECTED_M MAKEMASK(0x3, 26) +#define E830_GLPCI_CAPSUP_DOE_EN_S 1 +#define E830_GLPCI_CAPSUP_DOE_EN_M BIT(1) +#define E830_GLPCI_CAPSUP_GEN5_EXT_EN_S 12 +#define E830_GLPCI_CAPSUP_GEN5_EXT_EN_M BIT(12) +#define E830_GLPCI_CAPSUP_PTM_EN_S 13 +#define E830_GLPCI_CAPSUP_PTM_EN_M BIT(13) +#define E830_GLPCI_CAPSUP_SNPS_RAS_EN_S 14 +#define E830_GLPCI_CAPSUP_SNPS_RAS_EN_M BIT(14) +#define E830_GLPCI_CAPSUP_SIOV_EN_S 15 +#define E830_GLPCI_CAPSUP_SIOV_EN_M BIT(15) +#define E830_GLPCI_DOE_BUSY_STATUS 0x0009DF70 /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_S 0 +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_REQ_M BIT(0) +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_S 1 +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_EMPR_M BIT(1) +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_S 2 +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_PCIER_M BIT(2) +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_S 3 +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FLR_M BIT(3) +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_S 4 +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_CFG_ABORT_M BIT(4) +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_S 5 +#define E830_GLPCI_DOE_BUSY_STATUS_BUSY_FW_M BIT(5) +#define E830_GLPCI_DOE_CFG 0x0009DF54 /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_CFG_ENABLE_S 0 +#define E830_GLPCI_DOE_CFG_ENABLE_M BIT(0) +#define E830_GLPCI_DOE_CFG_ITR_SUPPORT_S 1 +#define E830_GLPCI_DOE_CFG_ITR_SUPPORT_M BIT(1) +#define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_S 2 +#define E830_GLPCI_DOE_CFG_POISON_CFGWR_PIOSF_EP_BIT_M BIT(2) +#define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_S 3 +#define E830_GLPCI_DOE_CFG_POISON_CFGWR_SBIOSF_AER_MSG_M BIT(3) +#define E830_GLPCI_DOE_CFG_MSIX_VECTOR_S 8 +#define E830_GLPCI_DOE_CFG_MSIX_VECTOR_M MAKEMASK(0x7FF, 8) +#define E830_GLPCI_DOE_CTRL 0x0009DF60 /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_S 0 +#define E830_GLPCI_DOE_CTRL_BUSY_FW_SET_M BIT(0) +#define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_S 1 +#define E830_GLPCI_DOE_CTRL_DOE_CFG_ERR_SET_M BIT(1) +#define E830_GLPCI_DOE_DBG 0x0009DF6C /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_DBG_CFG_BUSY_S 0 +#define E830_GLPCI_DOE_DBG_CFG_BUSY_M BIT(0) +#define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_S 1 +#define E830_GLPCI_DOE_DBG_CFG_DATA_OBJECT_READY_M BIT(1) +#define E830_GLPCI_DOE_DBG_CFG_ERROR_S 2 +#define E830_GLPCI_DOE_DBG_CFG_ERROR_M BIT(2) +#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_S 3 +#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_ENABLE_M BIT(3) +#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_S 4 +#define E830_GLPCI_DOE_DBG_CFG_INTERRUPT_STATUS_M BIT(4) +#define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_S 8 +#define E830_GLPCI_DOE_DBG_REQ_BUF_SW_WR_PTR_M MAKEMASK(0x1FF, 8) +#define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_S 20 +#define E830_GLPCI_DOE_DBG_RESP_BUF_SW_RD_PTR_M MAKEMASK(0x1FF, 20) +#define E830_GLPCI_DOE_ERR_EN 0x0009DF64 /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_S 0 +#define E830_GLPCI_DOE_ERR_EN_RD_REQ_BUF_ECC_ERR_EN_M BIT(0) +#define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_S 1 +#define E830_GLPCI_DOE_ERR_EN_RD_RESP_BUF_ECC_ERR_EN_M BIT(1) +#define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_S 2 +#define E830_GLPCI_DOE_ERR_EN_SW_WR_CFG_POISONED_EN_M BIT(2) +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_S 3 +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_EN_M BIT(3) +#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_S 4 +#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_REQ_EN_M BIT(4) +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_S 5 +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_EN_M BIT(5) +#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_S 6 +#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_FW_EN_M BIT(6) +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_S 7 +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_OVERFLOW_EN_M BIT(7) +#define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_S 8 +#define E830_GLPCI_DOE_ERR_EN_SW_GO_REQ_BUF_EMPTY_EN_M BIT(8) +#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_S 9 +#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_READY_LOW_EN_M BIT(9) +#define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_S 10 +#define E830_GLPCI_DOE_ERR_EN_SW_REQ_DURING_MNG_RST_EN_M BIT(10) +#define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_S 11 +#define E830_GLPCI_DOE_ERR_EN_FW_SET_ERROR_EN_M BIT(11) +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_S 12 +#define E830_GLPCI_DOE_ERR_EN_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(12) +#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_S 13 +#define E830_GLPCI_DOE_ERR_EN_SW_GO_ON_BUSY_DUE_ABORT_EN_M BIT(13) +#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_S 14 +#define E830_GLPCI_DOE_ERR_EN_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_EN_M BIT(14) +#define E830_GLPCI_DOE_ERR_STATUS 0x0009DF68 /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_S 0 +#define E830_GLPCI_DOE_ERR_STATUS_RD_REQ_BUF_ECC_ERR_M BIT(0) +#define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_S 1 +#define E830_GLPCI_DOE_ERR_STATUS_RD_RESP_BUF_ECC_ERR_M BIT(1) +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_S 2 +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_CFG_POISONED_M BIT(2) +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_S 3 +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_REQ_M BIT(3) +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_S 4 +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_REQ_M BIT(4) +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_S 5 +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_FW_M BIT(5) +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_S 6 +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_FW_M BIT(6) +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_S 7 +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_OVERFLOW_M BIT(7) +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_S 8 +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_REQ_BUF_EMPTY_M BIT(8) +#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_S 9 +#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_READY_LOW_M BIT(9) +#define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_S 10 +#define E830_GLPCI_DOE_ERR_STATUS_SW_REQ_DURING_MNG_RST_M BIT(10) +#define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_S 11 +#define E830_GLPCI_DOE_ERR_STATUS_FW_SET_ERROR_M BIT(11) +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_S 12 +#define E830_GLPCI_DOE_ERR_STATUS_SW_WR_REQ_BUF_ON_BUSY_DUE_ABORT_M BIT(12) +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_S 13 +#define E830_GLPCI_DOE_ERR_STATUS_SW_GO_ON_BUSY_DUE_ABORT_M BIT(13) +#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_S 14 +#define E830_GLPCI_DOE_ERR_STATUS_SW_RD_RESP_BUF_ON_BUSY_DUE_ABORT_M BIT(14) +#define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_S 24 +#define E830_GLPCI_DOE_ERR_STATUS_CFG_ERR_IDX_M MAKEMASK(0x1F, 24) +#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS 0x0009DF58 /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_S 0 +#define E830_GLPCI_DOE_REQ_MSG_NUM_DWS_GLPCI_DOE_REQ_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0) +#define E830_GLPCI_DOE_RESP 0x0009DF5C /* Reset Source: PCIR */ +#define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_S 0 +#define E830_GLPCI_DOE_RESP_MSG_NUM_DWS_M MAKEMASK(0x1FF, 0) +#define E830_GLPCI_DOE_RESP_READY_SET_S 16 +#define E830_GLPCI_DOE_RESP_READY_SET_M BIT(16) +#define E830_GLPCI_ERR_DBG 0x0009DF84 /* Reset Source: PCIR */ +#define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_S 0 +#define E830_GLPCI_ERR_DBG_ERR_MIFO_FULL_DROP_CTR_M MAKEMASK(0x3, 0) +#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_S 2 +#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_SM_M BIT(2) +#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_S 3 +#define E830_GLPCI_ERR_DBG_PCIE2SB_AER_MSG_FIFO_NUM_ENTRIES_M MAKEMASK(0x7, 3) +#define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_S 6 +#define E830_GLPCI_ERR_DBG_ERR_MIFO_NUM_ENTRIES_M MAKEMASK(0xF, 6) +#define E830_GLPCI_NPQ_CFG_HIGH_TO_S 20 +#define E830_GLPCI_NPQ_CFG_HIGH_TO_M BIT(20) +#define E830_GLPCI_NPQ_CFG_INC_150MS_TO_S 21 +#define E830_GLPCI_NPQ_CFG_INC_150MS_TO_M BIT(21) +#define E830_GLPCI_PUSH_PQM_CTRL 0x0009DF74 /* Reset Source: POR */ +#define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_S 0 +#define E830_GLPCI_PUSH_PQM_CTRL_PF_LEGACY_RANGE_EN_M BIT(0) +#define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_S 1 +#define E830_GLPCI_PUSH_PQM_CTRL_PF_TXTIME_RANGE_EN_M BIT(1) +#define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_S 2 +#define E830_GLPCI_PUSH_PQM_CTRL_PF_4K_RANGE_EN_M BIT(2) +#define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_S 3 +#define E830_GLPCI_PUSH_PQM_CTRL_VF_LEGACY_RANGE_EN_M BIT(3) +#define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_S 4 +#define E830_GLPCI_PUSH_PQM_CTRL_VF_TXTIME_RANGE_EN_M BIT(4) +#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_S 8 +#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_VAL_M MAKEMASK(0xF, 8) +#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_S 12 +#define E830_GLPCI_PUSH_PQM_CTRL_PUSH_PQM_IF_TO_DIS_M BIT(12) +#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_S 16 +#define E830_GLPCI_PUSH_PQM_CTRL_RD_COMP_LEN_2DWS_ONE_CHUNK_EN_M BIT(16) +#define E830_GLPCI_PUSH_PQM_DBG 0x0009DF7C /* Reset Source: PCIR */ +#define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_S 0 +#define E830_GLPCI_PUSH_PQM_DBG_EVENTS_CTR_M MAKEMASK(0xFF, 0) +#define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_S 8 +#define E830_GLPCI_PUSH_PQM_DBG_DROP_CTR_M MAKEMASK(0xFF, 8) +#define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_S 16 +#define E830_GLPCI_PUSH_PQM_DBG_ASYNC_FIFO_USED_SPACE_M MAKEMASK(0xF, 16) +#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_S 20 +#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_USED_SPACE_M MAKEMASK(0x1F, 20) +#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_S 25 +#define E830_GLPCI_PUSH_PQM_DBG_CDT_FIFO_PUSH_WHEN_FULL_ERR_M BIT(25) +#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS 0x0009DF78 /* Reset Source: PCIR */ +#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_S 0 +#define E830_GLPCI_PUSH_PQM_IF_TO_STATUS_GLPCI_PUSH_PQM_IF_TO_STATUS_M BIT(0) +#define E830_GLPCI_RDPU_CMD_DBG 0x000BE264 /* Reset Source: PCIR */ +#define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_S 0 +#define E830_GLPCI_RDPU_CMD_DBG_RDPU0_CMD_POP_CNT_M MAKEMASK(0xFF, 0) +#define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_S 8 +#define E830_GLPCI_RDPU_CMD_DBG_RDPU1_CMD_POP_CNT_M MAKEMASK(0xFF, 8) +#define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_S 16 +#define E830_GLPCI_RDPU_CMD_DBG_RDPU2_CMD_POP_CNT_M MAKEMASK(0xFF, 16) +#define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_S 24 +#define E830_GLPCI_RDPU_CMD_DBG_RDPU3_CMD_POP_CNT_M MAKEMASK(0xFF, 24) +#define E830_GLPCI_RDPU_CMD_FIFO_DBG0 0x000BE25C /* Reset Source: PCIR */ +#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_S 0 +#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU0_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0) +#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_S 16 +#define E830_GLPCI_RDPU_CMD_FIFO_DBG0_RDPU1_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16) +#define E830_GLPCI_RDPU_CMD_FIFO_DBG1 0x000BE260 /* Reset Source: PCIR */ +#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_S 0 +#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU2_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 0) +#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_S 16 +#define E830_GLPCI_RDPU_CMD_FIFO_DBG1_RDPU3_CMD_NUM_ENTRIES_M MAKEMASK(0x1FF, 16) +#define E830_GLPCI_RDPU_TAG 0x000BE258 /* Reset Source: PCIR */ +#define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_S 0 +#define E830_GLPCI_RDPU_TAG_OVERRIDE_DELAY_M MAKEMASK(0xFF, 0) +#define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_S 8 +#define E830_GLPCI_RDPU_TAG_EXPECTED_TAG_M MAKEMASK(0x3FF, 8) +#define E830_GLPCI_SB_AER_MSG_OUT 0x0009DF80 /* Reset Source: PCIR */ +#define E830_GLPCI_SB_AER_MSG_OUT_EN_S 0 +#define E830_GLPCI_SB_AER_MSG_OUT_EN_M BIT(0) +#define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_S 1 +#define E830_GLPCI_SB_AER_MSG_OUT_ANF_SET_EN_M BIT(1) +#define E830_PF_FUNC_RID_HOST_S 16 +#define E830_PF_FUNC_RID_HOST_M MAKEMASK(0x3, 16) +#define E830_GLPES_PFRXNPECNMARKEDPKTSHI(_i) (0x00553004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ +#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_MAX_INDEX 127 +#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_S 0 +#define E830_GLPES_PFRXNPECNMARKEDPKTSHI_RXNPECNMARKEDPKTSHI_M MAKEMASK(0xFFFFFF, 0) +#define E830_GLPES_PFRXNPECNMARKEDPKTSLO(_i) (0x00553000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */ +#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_MAX_INDEX 127 +#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S 0 +#define E830_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLPES_PFRXRPCNPHANDLED(_i) (0x00552C00 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ +#define E830_GLPES_PFRXRPCNPHANDLED_MAX_INDEX 127 +#define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_S 0 +#define E830_GLPES_PFRXRPCNPHANDLED_RXRPCNPHANDLED_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLPES_PFRXRPCNPIGNORED(_i) (0x00552800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ +#define E830_GLPES_PFRXRPCNPIGNORED_MAX_INDEX 127 +#define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_S 0 +#define E830_GLPES_PFRXRPCNPIGNORED_RXRPCNPIGNORED_M MAKEMASK(0xFFFFFF, 0) +#define E830_GLPES_PFTXNPCNPSENT(_i) (0x00553800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */ +#define E830_GLPES_PFTXNPCNPSENT_MAX_INDEX 127 +#define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_S 0 +#define E830_GLPES_PFTXNPCNPSENT_TXNPCNPSENT_M MAKEMASK(0xFFFFFF, 0) +#define E830_GLRPB_GBL_CFG 0x000AD260 /* Reset Source: CORER */ +#define E830_GLRPB_GBL_CFG_RESERVED_1_S 0 +#define E830_GLRPB_GBL_CFG_RESERVED_1_M MAKEMASK(0x3, 0) +#define E830_GLRPB_GBL_CFG_ALW_PE_RLS_S 2 +#define E830_GLRPB_GBL_CFG_ALW_PE_RLS_M BIT(2) +#define E830_GLRPB_GBL_CFG_LFSR_SHFT_S 3 +#define E830_GLRPB_GBL_CFG_LFSR_SHFT_M MAKEMASK(0x7, 3) +#define E830_GLQF_FLAT_HLUT(_i) (0x004C0000 + ((_i) * 4)) /* _i=0...8191 */ /* Reset Source: CORER */ +#define E830_GLQF_FLAT_HLUT_MAX_INDEX 8191 +#define E830_GLQF_FLAT_HLUT_LUT0_S 0 +#define E830_GLQF_FLAT_HLUT_LUT0_M MAKEMASK(0xFF, 0) +#define E830_GLQF_FLAT_HLUT_LUT1_S 8 +#define E830_GLQF_FLAT_HLUT_LUT1_M MAKEMASK(0xFF, 8) +#define E830_GLQF_FLAT_HLUT_LUT2_S 16 +#define E830_GLQF_FLAT_HLUT_LUT2_M MAKEMASK(0xFF, 16) +#define E830_GLQF_FLAT_HLUT_LUT3_S 24 +#define E830_GLQF_FLAT_HLUT_LUT3_M MAKEMASK(0xFF, 24) +#define E830_GLQF_QGRP_CNTX(_i) (0x00490000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ +#define E830_GLQF_QGRP_CNTX_MAX_INDEX 2047 +#define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_S 0 +#define E830_GLQF_QGRP_CNTX_QG_LUT_BASE_M MAKEMASK(0x7FFF, 0) +#define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_S 16 +#define E830_GLQF_QGRP_CNTX_QG_LUT_SIZE_M MAKEMASK(0xF, 16) +#define E830_GLQF_QGRP_CNTX_VSI_S 20 +#define E830_GLQF_QGRP_CNTX_VSI_M MAKEMASK(0x3FF, 20) +#define E830_GLQF_QGRP_PF_OWNER(_i) (0x00484000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ +#define E830_GLQF_QGRP_PF_OWNER_MAX_INDEX 2047 +#define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_S 0 +#define E830_GLQF_QGRP_PF_OWNER_OWNER_PF_M MAKEMASK(0x7, 0) +#define E830_GLQF_QGRP_VSI_MODE 0x0048E084 /* Reset Source: CORER */ +#define E830_GLQF_QGRP_VSI_MODE_QGRP_MODE_S 0 +#define E830_GLQF_QGRP_VSI_MODE_QGRP_MODE_M BIT(0) +#define E830_GLQF_QTABLE_MODE 0x0048E080 /* Reset Source: CORER */ +#define E830_GLQF_QTABLE_MODE_SCT_MODE_S 0 +#define E830_GLQF_QTABLE_MODE_SCT_MODE_M BIT(0) +#define E830_GLQF_QTABLE_MODE_SCT_MODE_SET_S 1 +#define E830_GLQF_QTABLE_MODE_SCT_MODE_SET_M BIT(1) +#define E830_PFQF_LUT_ALLOC 0x0048E000 /* Reset Source: CORER */ +#define E830_PFQF_LUT_ALLOC_LUT_BASE_S 0 +#define E830_PFQF_LUT_ALLOC_LUT_BASE_M MAKEMASK(0x7FFF, 0) +#define E830_PFQF_LUT_ALLOC_LUT_SIZE_S 16 +#define E830_PFQF_LUT_ALLOC_LUT_SIZE_M MAKEMASK(0xF, 16) +#define E830_PFQF_QTABLE_ALLOC 0x0048E040 /* Reset Source: CORER */ +#define E830_PFQF_QTABLE_ALLOC_BASE_S 0 +#define E830_PFQF_QTABLE_ALLOC_BASE_M MAKEMASK(0x3FFF, 0) +#define E830_PFQF_QTABLE_ALLOC_SIZE_S 16 +#define E830_PFQF_QTABLE_ALLOC_SIZE_M MAKEMASK(0x1FFF, 16) +#define E830_VSILAN_FLAT_Q(_VSI) (0x00487000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ +#define E830_VSILAN_FLAT_Q_MAX_INDEX 767 +#define E830_VSILAN_FLAT_Q_SCT_FLAT_BASE_S 0 +#define E830_VSILAN_FLAT_Q_SCT_FLAT_BASE_M MAKEMASK(0xFFF, 0) +#define E830_VSILAN_FLAT_Q_SCT_FLAT_SIZE_S 16 +#define E830_VSILAN_FLAT_Q_SCT_FLAT_SIZE_M MAKEMASK(0xFF, 16) +#define E830_VSIQF_DEF_QGRP(_VSI) (0x00486000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ +#define E830_VSIQF_DEF_QGRP_MAX_INDEX 767 +#define E830_VSIQF_DEF_QGRP_DEF_QGRP_S 0 +#define E830_VSIQF_DEF_QGRP_DEF_QGRP_M MAKEMASK(0x7FF, 0) +#define E830_GLPRT_BPRCH_BPRCH_S 0 +#define E830_GLPRT_BPRCH_BPRCH_M MAKEMASK(0xFF, 0) +#define E830_GLPRT_BPRCL_BPRCL_S 0 +#define E830_GLPRT_BPRCL_BPRCL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLPRT_BPTCH_BPTCH_S 0 +#define E830_GLPRT_BPTCH_BPTCH_M MAKEMASK(0xFF, 0) +#define E830_GLPRT_BPTCL_BPTCL_S 0 +#define E830_GLPRT_BPTCL_BPTCL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLPRT_UPTCL_UPTCL_S 0 +#define E830_GLPRT_UPTCL_UPTCL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLRPB_PEAK_DOC_LOG(_i) (0x000AD178 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ +#define E830_GLRPB_PEAK_DOC_LOG_MAX_INDEX 15 +#define E830_GLRPB_PEAK_DOC_LOG_PEAK_OC_S 0 +#define E830_GLRPB_PEAK_DOC_LOG_PEAK_OC_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLRPB_PEAK_SOC_LOG(_i) (0x000AD1B8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLRPB_PEAK_SOC_LOG_MAX_INDEX 7 +#define E830_GLRPB_PEAK_SOC_LOG_PEAK_OC_S 0 +#define E830_GLRPB_PEAK_SOC_LOG_PEAK_OC_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLPTM_ART_CTL 0x00088B50 /* Reset Source: POR */ +#define E830_GLPTM_ART_CTL_ACTIVE_S 0 +#define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0) +#define E830_GLPTM_ART_CTL_TIME_OUT_S 1 +#define E830_GLPTM_ART_CTL_TIME_OUT_M BIT(1) +#define E830_GLPTM_ART_CTL_PTM_READY_S 2 +#define E830_GLPTM_ART_CTL_PTM_READY_M BIT(2) +#define E830_GLPTM_ART_CTL_PTM_AUTO_S 3 +#define E830_GLPTM_ART_CTL_PTM_AUTO_M BIT(3) +#define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_S 4 +#define E830_GLPTM_ART_CTL_PTM_AUTO_LATCH_M BIT(4) +#define E830_GLPTM_ART_TIME_H 0x00088B54 /* Reset Source: POR */ +#define E830_GLPTM_ART_TIME_H_ART_TIME_H_S 0 +#define E830_GLPTM_ART_TIME_H_ART_TIME_H_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLPTM_ART_TIME_L 0x00088B58 /* Reset Source: POR */ +#define E830_GLPTM_ART_TIME_L_ART_TIME_L_S 0 +#define E830_GLPTM_ART_TIME_L_ART_TIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_PTMTIME_H(_i) (0x00088B48 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GLTSYN_PTMTIME_H_MAX_INDEX 1 +#define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_S 0 +#define E830_GLTSYN_PTMTIME_H_TSYNEVNT_H_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_PTMTIME_L(_i) (0x00088B40 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */ +#define E830_GLTSYN_PTMTIME_L_MAX_INDEX 1 +#define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_S 0 +#define E830_GLTSYN_PTMTIME_L_TSYNEVNT_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_H_0_AL 0x0008A004 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_H_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_H_1_AL 0x0008B004 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_H_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_L_0_AL 0x0008A000 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_L_0_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_L_1_AL 0x0008B000 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_L_1_AL_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_PFPTM_SEM 0x00088B00 /* Reset Source: PFR */ +#define E830_PFPTM_SEM_BUSY_S 0 +#define E830_PFPTM_SEM_BUSY_M BIT(0) +#define E830_PFPTM_SEM_PF_OWNER_S 4 +#define E830_PFPTM_SEM_PF_OWNER_M MAKEMASK(0x7, 4) +#define E830_VSI_PASID_1(_VSI) (0x00094000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ +#define E830_VSI_PASID_1_MAX_INDEX 767 +#define E830_VSI_PASID_1_PASID_S 0 +#define E830_VSI_PASID_1_PASID_M MAKEMASK(0xFFFFF, 0) +#define E830_VSI_PASID_1_EN_S 31 +#define E830_VSI_PASID_1_EN_M BIT(31) +#define E830_VSI_PASID_2(_VSI) (0x00095000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ +#define E830_VSI_PASID_2_MAX_INDEX 767 +#define E830_VSI_PASID_2_PASID_S 0 +#define E830_VSI_PASID_2_PASID_M MAKEMASK(0xFFFFF, 0) +#define E830_VSI_PASID_2_EN_S 31 +#define E830_VSI_PASID_2_EN_M BIT(31) +#define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_S 15 +#define E830_GLPE_CQM_FUNC_INVALIDATE_PMF_ID_M MAKEMASK(0x3F, 15) +#define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_S 29 +#define E830_GLPE_CQM_FUNC_INVALIDATE_INVALIDATE_TYPE_M MAKEMASK(0x3, 29) +#define E830_VFPE_MRTEIDXMASK_MAX_INDEX 255 +#define E830_GLSWR_PMCFG_RPB_REP_DHW(_i) (0x0020A7A0 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_DHW_MAX_INDEX 15 +#define E830_GLSWR_PMCFG_RPB_REP_DHW_DHW_TCN_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_DHW_DHW_TCN_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_DLW(_i) (0x0020A7E0 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_DLW_MAX_INDEX 15 +#define E830_GLSWR_PMCFG_RPB_REP_DLW_DLW_TCN_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_DLW_DLW_TCN_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_DPS(_i) (0x0020A760 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_DPS_MAX_INDEX 15 +#define E830_GLSWR_PMCFG_RPB_REP_DPS_DPS_TCN_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_DPS_DPS_TCN_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_SHW(_i) (0x0020A720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_SHW_MAX_INDEX 7 +#define E830_GLSWR_PMCFG_RPB_REP_SHW_SHW_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_SHW_SHW_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_SLW(_i) (0x0020A740 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_SLW_MAX_INDEX 7 +#define E830_GLSWR_PMCFG_RPB_REP_SLW_SLW_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_SLW_SLW_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_SPS(_i) (0x0020A700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_SPS_MAX_INDEX 7 +#define E830_GLSWR_PMCFG_RPB_REP_SPS_SPS_TCN_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_SPS_SPS_TCN_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG(_i) (0x0020A980 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_MAX_INDEX 31 +#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_D_POOL_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_D_POOL_M MAKEMASK(0xFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_S_POOL_S 16 +#define E830_GLSWR_PMCFG_RPB_REP_TC_CFG_S_POOL_M MAKEMASK(0xFFFF, 16) +#define E830_GLSWR_PMCFG_RPB_REP_TCHW(_i) (0x0020A880 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_TCHW_MAX_INDEX 31 +#define E830_GLSWR_PMCFG_RPB_REP_TCHW_TCHW_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_TCHW_TCHW_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLSWR_PMCFG_RPB_REP_TCLW(_i) (0x0020A900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ +#define E830_GLSWR_PMCFG_RPB_REP_TCLW_MAX_INDEX 31 +#define E830_GLSWR_PMCFG_RPB_REP_TCLW_TCLW_S 0 +#define E830_GLSWR_PMCFG_RPB_REP_TCLW_TCLW_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLQF_QGRP_CFG(_VSI) (0x00492000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */ +#define E830_GLQF_QGRP_CFG_MAX_INDEX 767 +#define E830_GLQF_QGRP_CFG_VSI_QGRP_ENABLE_S 0 +#define E830_GLQF_QGRP_CFG_VSI_QGRP_ENABLE_M BIT(0) +#define E830_GLQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_S 1 +#define E830_GLQF_QGRP_CFG_VSI_QGRP_GEN_INDEX_M MAKEMASK(0x7, 1) +#define E830_GLDCB_RTCTI_PD 0x00122740 /* Reset Source: CORER */ +#define E830_GLDCB_RTCTI_PD_PFCTIMEOUT_TC_S 0 +#define E830_GLDCB_RTCTI_PD_PFCTIMEOUT_TC_M MAKEMASK(0xFF, 0) +#define E830_GLDCB_RTCTQ_PD(_i) (0x00122700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLDCB_RTCTQ_PD_MAX_INDEX 7 +#define E830_GLDCB_RTCTQ_PD_RXQNUM_S 0 +#define E830_GLDCB_RTCTQ_PD_RXQNUM_M MAKEMASK(0x7FF, 0) +#define E830_GLDCB_RTCTQ_PD_IS_PF_Q_S 16 +#define E830_GLDCB_RTCTQ_PD_IS_PF_Q_M BIT(16) +#define E830_GLDCB_RTCTS_PD(_i) (0x00122720 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */ +#define E830_GLDCB_RTCTS_PD_MAX_INDEX 7 +#define E830_GLDCB_RTCTS_PD_PFCTIMER_S 0 +#define E830_GLDCB_RTCTS_PD_PFCTIMER_M MAKEMASK(0x3FFF, 0) +#define E830_GLRPB_PEAK_TC_OC_LOG(_i) (0x000AD1D8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ +#define E830_GLRPB_PEAK_TC_OC_LOG_MAX_INDEX 31 +#define E830_GLRPB_PEAK_TC_OC_LOG_PEAK_OC_S 0 +#define E830_GLRPB_PEAK_TC_OC_LOG_PEAK_OC_M MAKEMASK(0x3FFFFF, 0) +#define E830_GLRPB_TC_TOTAL_PC(_i) (0x000ACFE0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */ +#define E830_GLRPB_TC_TOTAL_PC_MAX_INDEX 31 +#define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_S 0 +#define E830_GLRPB_TC_TOTAL_PC_BYTE_CNT_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_VFINT_ITRN_64(_i, _j) (0x00002C00 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...2 */ /* Reset Source: CORER */ +#define E830_VFINT_ITRN_64_MAX_INDEX 63 +#define E830_VFINT_ITRN_64_INTERVAL_S 0 +#define E830_VFINT_ITRN_64_INTERVAL_M MAKEMASK(0xFFF, 0) +#define E830_GLQTX_TXTIME_DBELL_LSB1(_DBQM) (0x0000D000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_DBELL_LSB1_MAX_INDEX 255 +#define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_DBELL_LSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLQTX_TXTIME_DBELL_MSB1(_DBQM) (0x0000D004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_DBELL_MSB1_MAX_INDEX 255 +#define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_DBELL_MSB1_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB(_DBQM) (0x00040000 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_MAX_INDEX 255 +#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_LARGE_DBELL_LSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB(_DBQM) (0x00040004 + ((_DBQM) * 8)) /* _i=0...255 */ /* Reset Source: CORER */ +#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_MAX_INDEX 255 +#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_S 0 +#define E830_GLQTX_TXTIME_LARGE_DBELL_MSB_QTX_TXTIME_DBELL_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_H_0_AL1 0x00003004 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_H_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_H_1_AL1 0x0000300C /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_H_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_L_0_AL1 0x00003000 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_L_0_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_GLTSYN_TIME_L_1_AL1 0x00003008 /* Reset Source: CORER */ +#define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_S 0 +#define E830_GLTSYN_TIME_L_1_AL1_TSYNTIME_L_M MAKEMASK(0xFFFFFFFF, 0) +#define E830_VSI_VSI2F_LEM(_VSI) (0x006100A0 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */ +#define E830_VSI_VSI2F_LEM_MAX_INDEX 767 +#define E830_VSI_VSI2F_LEM_VFVMNUMBER_S 0 +#define E830_VSI_VSI2F_LEM_VFVMNUMBER_M MAKEMASK(0x3FF, 0) +#define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_S 10 +#define E830_VSI_VSI2F_LEM_FUNCTIONTYPE_M MAKEMASK(0x3, 10) +#define E830_VSI_VSI2F_LEM_PFNUMBER_S 12 +#define E830_VSI_VSI2F_LEM_PFNUMBER_M MAKEMASK(0x7, 12) +#define E830_VSI_VSI2F_LEM_BUFFERNUMBER_S 16 +#define E830_VSI_VSI2F_LEM_BUFFERNUMBER_M MAKEMASK(0x7, 16) +#define E830_VSI_VSI2F_LEM_VSI_NUMBER_S 20 +#define E830_VSI_VSI2F_LEM_VSI_NUMBER_M MAKEMASK(0x3FF, 20) +#define E830_VSI_VSI2F_LEM_VSI_ENABLE_S 31 +#define E830_VSI_VSI2F_LEM_VSI_ENABLE_M BIT(31) #endif /* !_ICE_HW_AUTOGEN_H_ */ diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index 229db1041c..d8ac841e46 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -2469,5 +2469,5 @@ static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) #define ICE_LINK_SPEED_40000MBPS 40000 #define ICE_LINK_SPEED_50000MBPS 50000 #define ICE_LINK_SPEED_100000MBPS 100000 - +#define ICE_LINK_SPEED_200000MBPS 200000 #endif /* _ICE_LAN_TX_RX_H_ */ diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index cb45cb8134..6ab359af33 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -1330,14 +1330,17 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd, return status; /* Reject requests to write to read-only registers */ - switch (cmd->offset) { - case GL_HICR_EN: - case GLGEN_RSTAT: - return ICE_ERR_OUT_OF_RANGE; - default: - break; + if (hw->mac_type == ICE_MAC_E830) { + if (cmd->offset == E830_GL_HICR_EN) + return ICE_ERR_OUT_OF_RANGE; + } else { + if (cmd->offset == GL_HICR_EN) + return ICE_ERR_OUT_OF_RANGE; } + if (cmd->offset == GLGEN_RSTAT) + return ICE_ERR_OUT_OF_RANGE; + ice_debug(hw, ICE_DBG_NVM, "NVM access: writing register %08x with value %08x\n", cmd->offset, data->regval); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 5779590a7e..576998549e 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -222,6 +222,7 @@ enum ice_set_fc_aq_failures { enum ice_mac_type { ICE_MAC_UNKNOWN = 0, ICE_MAC_E810, + ICE_MAC_E830, ICE_MAC_GENERIC, ICE_MAC_GENERIC_3K, }; From patchwork Thu Apr 27 06:19:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126580 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 02F6C42A08; Thu, 27 Apr 2023 08:39:29 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C8F3642DA4; Thu, 27 Apr 2023 08:38:12 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 7680B42D98 for ; Thu, 27 Apr 2023 08:38:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577489; x=1714113489; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xIYxF+vEvuia9tIbokR3uhZYxRXBrKoe5ugLWwPwXgo=; b=AcaVI+rpqOV1ZzqVR/BE/3fjSpAH7P/j0mrGVdh7fvhgLNxVNCvNc7fH NRyFAevEMXOdb6z2vDzyfNsJtJrBccPEjXite1OkddTxkP01qoqRIGxJv Sq6KBprljL7lkCc1QQ4tQz4mj7cuJtrWo0IWYlTY76jgy5KWYaZNnbBQb oNsszkZbCu0l6CUfFy8E1zUX/nUEB/4kcs3Yln+gx9bYUqwei7LxVC+Nm oZuBarXTsL7gae9qpvKe1cJNO5Y75hbHoktj6Kdh8hW/Cuu/+vgKbIR21 lvjwWXQBTB+kNG1D69uiTFX9p3zyUN+bjyvEG7tCM60Kdw7l6HQhp6Bzq w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324320" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324320" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845785" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845785" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:06 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Yahui Cao Subject: [PATCH 13/30] net/ice/base: add function to get rxq context Date: Thu, 27 Apr 2023 06:19:44 +0000 Message-Id: <20230427062001.478032-14-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch exports rxq context which is consumed by linux linve migration driver to save device state. Signed-off-by: Yahui Cao Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 75 +++++++++++++++++++++++++++---- drivers/net/ice/base/ice_common.h | 7 ++- 2 files changed, 71 insertions(+), 11 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 58da198d62..ed822afc30 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1397,6 +1397,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) return ICE_SUCCESS; } +/** + * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW + * @hw: pointer to the hardware structure + * @ice_rxq_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Copies rxq context from HW register space to dense structure + */ +static enum ice_status +ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) +{ + u8 i; + + if (!ice_rxq_ctx) + return ICE_ERR_BAD_PTR; + + if (rxq_index > QRX_CTRL_MAX_INDEX) + return ICE_ERR_PARAM; + + /* Copy each dword separately from HW */ + for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { + u32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32))); + + *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); + + ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); + } + + return ICE_SUCCESS; +} + /* LAN Rx Queue Context */ static const struct ice_ctx_ele ice_rlan_ctx_info[] = { /* Field Width LSB */ @@ -1448,6 +1479,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); } +/** + * ice_read_rxq_ctx - Read rxq context from HW + * @hw: pointer to the hardware structure + * @rlan_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Read rxq context from HW register space and then converts it from dense + * structure to sparse + */ +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index) +{ + u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; + enum ice_status status; + + if (!rlan_ctx) + return ICE_ERR_BAD_PTR; + + status = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index); + if (status) + return status; + + return ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info); +} + /** * ice_clear_rxq_ctx * @hw: pointer to the hardware structure @@ -4883,7 +4940,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, * @ce_info: a description of the struct to be filled */ static void -ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u8 dest_byte, mask; u8 *src, *target; @@ -4901,7 +4958,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); - dest_byte &= ~(mask); + dest_byte &= mask; dest_byte >>= shift_width; @@ -4919,7 +4976,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u16 dest_word, mask; u8 *src, *target; @@ -4941,7 +4998,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) /* the data in the memory is stored as little endian so mask it * correctly */ - src_word &= ~(CPU_TO_LE16(mask)); + src_word &= CPU_TO_LE16(mask); /* get the data back into host order before shifting */ dest_word = LE16_TO_CPU(src_word); @@ -4962,7 +5019,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u32 dest_dword, mask; __le32 src_dword; @@ -4992,7 +5049,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) /* the data in the memory is stored as little endian so mask it * correctly */ - src_dword &= ~(CPU_TO_LE32(mask)); + src_dword &= CPU_TO_LE32(mask); /* get the data back into host order before shifting */ dest_dword = LE32_TO_CPU(src_dword); @@ -5013,7 +5070,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u64 dest_qword, mask; __le64 src_qword; @@ -5043,7 +5100,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) /* the data in the memory is stored as little endian so mask it * correctly */ - src_qword &= ~(CPU_TO_LE64(mask)); + src_qword &= CPU_TO_LE64(mask); /* get the data back into host order before shifting */ dest_qword = LE64_TO_CPU(src_qword); @@ -5064,7 +5121,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the structure to be read from */ enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { int f; diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index d8fb7a6163..3e03f2e903 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -92,6 +92,9 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, enum ice_status ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index); +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index); enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); enum ice_status ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); @@ -135,6 +138,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[]; enum ice_status ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); +enum ice_status +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); enum ice_status ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, @@ -229,8 +234,6 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw, u32 start_address, u8 *buf, u8 buf_size, struct ice_sq_cd *cd); -enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); enum ice_status ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, u16 *q_handle, u16 *q_ids, u32 *q_teids, From patchwork Thu Apr 27 06:19:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126581 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 93C2F42A08; Thu, 27 Apr 2023 08:39:34 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 223B542DBC; Thu, 27 Apr 2023 08:38:15 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id B406042F84 for ; Thu, 27 Apr 2023 08:38:11 +0200 (CEST) DKIM-Signature: v=1; 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d="scan'208";a="805845794" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:08 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang Subject: [PATCH 14/30] net/ice/base: removed no need 56G releated code Date: Thu, 27 Apr 2023 06:19:45 +0000 Message-Id: <20230427062001.478032-15-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org As 56G related code is no need, delete unnecessary code. Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 1396 ----------------------------- drivers/net/ice/base/ice_ptp_hw.h | 38 - 2 files changed, 1434 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 548ef5e820..61145262ac 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -448,1375 +448,6 @@ static void ice_ptp_clean_cmd(struct ice_hw *hw) ice_flush(hw); } -/* 56G PHY access functions */ -static const u32 eth56g_port_base[ICE_NUM_PHY_PORTS] = { - ICE_PHY0_BASE, - ICE_PHY1_BASE, - ICE_PHY2_BASE, - ICE_PHY3_BASE, - ICE_PHY4_BASE, -}; - -/** - * ice_write_phy_eth56g_raw_lp - Write a PHY port register with lock parameter - * @hw: pointer to the HW struct - * @reg_addr: PHY register address - * @val: Value to write - * @lock_sbq: true to lock the sideband queue - */ -static enum ice_status -ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 val, - bool lock_sbq) -{ - struct ice_sbq_msg_input phy_msg; - enum ice_status status; - - phy_msg.opcode = ice_sbq_msg_wr; - - phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr); - phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr); - - phy_msg.data = val; - phy_msg.dest_dev = phy_56g; - - status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq); - - if (status) - ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", - status); - - return status; -} - -/** - * ice_read_phy_eth56g_raw_lp - Read a PHY port register with lock parameter - * @hw: pointer to the HW struct - * @reg_addr: PHY port register address - * @val: Pointer to the value to read (out param) - * @lock_sbq: true to lock the sideband queue - */ -static enum ice_status -ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val, - bool lock_sbq) -{ - struct ice_sbq_msg_input phy_msg; - enum ice_status status; - - phy_msg.opcode = ice_sbq_msg_rd; - - phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr); - phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr); - - phy_msg.dest_dev = phy_56g; - - status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq); - - if (status) - ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", - status); - else - *val = phy_msg.data; - - return status; -} - -/** - * ice_phy_port_reg_address_eth56g - Calculate a PHY port register address - * @port: Port number to be written - * @offset: Offset from PHY port register base - * @address: The result address - */ -static enum ice_status -ice_phy_port_reg_address_eth56g(u8 port, u16 offset, u32 *address) -{ - u8 phy, lane; - - if (port >= ICE_NUM_EXTERNAL_PORTS) - return ICE_ERR_OUT_OF_RANGE; - - phy = port / ICE_PORTS_PER_QUAD; - lane = port % ICE_PORTS_PER_QUAD; - - *address = offset + eth56g_port_base[phy] + - PHY_PTP_LANE_ADDR_STEP * lane; - - return ICE_SUCCESS; -} - -/** - * ice_phy_port_mem_address_eth56g - Calculate a PHY port memory address - * @port: Port number to be written - * @offset: Offset from PHY port register base - * @address: The result address - */ -static enum ice_status -ice_phy_port_mem_address_eth56g(u8 port, u16 offset, u32 *address) -{ - u8 phy, lane; - - if (port >= ICE_NUM_EXTERNAL_PORTS) - return ICE_ERR_OUT_OF_RANGE; - - phy = port / ICE_PORTS_PER_QUAD; - lane = port % ICE_PORTS_PER_QUAD; - - *address = offset + eth56g_port_base[phy] + - PHY_PTP_MEM_START + PHY_PTP_MEM_LANE_STEP * lane; - - return ICE_SUCCESS; -} - -/** - * ice_write_phy_reg_eth56g_lp - Write a PHY port register with lock parameter - * @hw: pointer to the HW struct - * @port: Port number to be written - * @offset: Offset from PHY port register base - * @val: Value to write - * @lock_sbq: true to lock the sideband queue - */ -static enum ice_status -ice_write_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val, - bool lock_sbq) -{ - enum ice_status status; - u32 reg_addr; - - status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr); - if (status) - return status; - - return ice_write_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq); -} - -/** - * ice_write_phy_reg_eth56g - Write a PHY port register with sbq locked - * @hw: pointer to the HW struct - * @port: Port number to be written - * @offset: Offset from PHY port register base - * @val: Value to write - */ -enum ice_status -ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val) -{ - return ice_write_phy_reg_eth56g_lp(hw, port, offset, val, true); -} - -/** - * ice_read_phy_reg_eth56g_lp - Read a PHY port register with - * lock parameter - * @hw: pointer to the HW struct - * @port: Port number to be read - * @offset: Offset from PHY port register base - * @val: Pointer to the value to read (out param) - * @lock_sbq: true to lock the sideband queue - */ -static enum ice_status -ice_read_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val, - bool lock_sbq) -{ - enum ice_status status; - u32 reg_addr; - - status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr); - if (status) - return status; - - return ice_read_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq); -} - -/** - * ice_read_phy_reg_eth56g - Read a PHY port register with sbq locked - * @hw: pointer to the HW struct - * @port: Port number to be read - * @offset: Offset from PHY port register base - * @val: Pointer to the value to read (out param) - */ -enum ice_status -ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val) -{ - return ice_read_phy_reg_eth56g_lp(hw, port, offset, val, true); -} - -/** - * ice_phy_port_mem_read_eth56g_lp - Read a PHY port memory location - * with lock parameter - * @hw: pointer to the HW struct - * @port: Port number to be read - * @offset: Offset from PHY port register base - * @val: Pointer to the value to read (out param) - * @lock_sbq: true to lock the sideband queue - */ -static enum ice_status -ice_phy_port_mem_read_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, - u32 *val, bool lock_sbq) -{ - enum ice_status status; - u32 mem_addr; - - status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr); - if (status) - return status; - - return ice_read_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq); -} - -/** - * ice_phy_port_mem_read_eth56g - Read a PHY port memory location with - * sbq locked - * @hw: pointer to the HW struct - * @port: Port number to be read - * @offset: Offset from PHY port register base - * @val: Pointer to the value to read (out param) - */ -static enum ice_status -ice_phy_port_mem_read_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val) -{ - return ice_phy_port_mem_read_eth56g_lp(hw, port, offset, val, true); -} - -/** - * ice_phy_port_mem_write_eth56g_lp - Write a PHY port memory location with - * lock parameter - * @hw: pointer to the HW struct - * @port: Port number to be read - * @offset: Offset from PHY port register base - * @val: Pointer to the value to read (out param) - * @lock_sbq: true to lock the sideband queue - */ -static enum ice_status -ice_phy_port_mem_write_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, - u32 val, bool lock_sbq) -{ - enum ice_status status; - u32 mem_addr; - - status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr); - if (status) - return status; - - return ice_write_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq); -} - -/** - * ice_phy_port_mem_write_eth56g - Write a PHY port memory location with - * sbq locked - * @hw: pointer to the HW struct - * @port: Port number to be read - * @offset: Offset from PHY port register base - * @val: Pointer to the value to read (out param) - */ -static enum ice_status -ice_phy_port_mem_write_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val) -{ - return ice_phy_port_mem_write_eth56g_lp(hw, port, offset, val, true); -} - -/** - * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register - * @low_addr: the low address to check - * - * Checks if the provided low address is one of the known 64bit PHY values - * represented as two 32bit registers. - */ -static bool ice_is_64b_phy_reg_eth56g(u16 low_addr) -{ - switch (low_addr) { - case PHY_REG_TX_TIMER_INC_PRE_L: - case PHY_REG_RX_TIMER_INC_PRE_L: - case PHY_REG_TX_CAPTURE_L: - case PHY_REG_RX_CAPTURE_L: - case PHY_REG_TOTAL_TX_OFFSET_L: - case PHY_REG_TOTAL_RX_OFFSET_L: - return true; - default: - return false; - } -} - -/** - * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register - * @low_addr: the low address to check - * - * Checks if the provided low address is one of the known 40bit PHY values - * split into two registers with the lower 8 bits in the low register and the - * upper 32 bits in the high register. - */ -static bool ice_is_40b_phy_reg_eth56g(u16 low_addr) -{ - switch (low_addr) { - case PHY_REG_TIMETUS_L: - return true; - default: - return false; - } -} - -/** - * ice_read_40b_phy_reg_eth56g - Read a 40bit value from PHY registers - * @hw: pointer to the HW struct - * @port: PHY port to read from - * @low_addr: offset of the lower register to read from - * @val: on return, the contents of the 40bit value from the PHY registers - * - * Reads the two registers associated with a 40bit value and returns it in the - * val pointer. - * This function checks that the caller has specified a known 40 bit register - * offset - */ -static enum ice_status -ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) -{ - u16 high_addr = low_addr + sizeof(u32); - enum ice_status status; - u32 lo, hi; - - if (!ice_is_40b_phy_reg_eth56g(low_addr)) - return ICE_ERR_PARAM; - - status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d", - (int)low_addr, status); - return status; - } - - status = ice_read_phy_reg_eth56g(hw, port, low_addr + sizeof(u32), &hi); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %08x\n, status %d", - high_addr, status); - return status; - } - - *val = ((u64)hi << P_REG_40B_HIGH_S) | (lo & P_REG_40B_LOW_M); - - return ICE_SUCCESS; -} - -/** - * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers - * @hw: pointer to the HW struct - * @port: PHY port to read from - * @low_addr: offset of the lower register to read from - * @val: on return, the contents of the 64bit value from the PHY registers - * - * Reads the two registers associated with a 64bit value and returns it in the - * val pointer. - * This function checks that the caller has specified a known 64 bit register - * offset - */ -static enum ice_status -ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) -{ - u16 high_addr = low_addr + sizeof(u32); - enum ice_status status; - u32 lo, hi; - - if (!ice_is_64b_phy_reg_eth56g(low_addr)) - return ICE_ERR_PARAM; - - status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d", - low_addr, status); - return status; - } - - status = ice_read_phy_reg_eth56g(hw, port, high_addr, &hi); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, status %d", - high_addr, status); - return status; - } - - *val = ((u64)hi << 32) | lo; - - return ICE_SUCCESS; -} - -/** - * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY - * @hw: pointer to the HW struct - * @port: port to write to - * @low_addr: offset of the low register - * @val: 40b value to write - * - * Write the provided 40b value to the two associated registers by splitting - * it up into two chunks, the lower 8 bits and the upper 32 bits. - * This function checks that the caller has specified a known 40 bit register - * offset - */ -static enum ice_status -ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) -{ - u16 high_addr = low_addr + sizeof(u32); - enum ice_status status; - u32 lo, hi; - - if (!ice_is_40b_phy_reg_eth56g(low_addr)) - return ICE_ERR_PARAM; - - lo = (u32)(val & P_REG_40B_LOW_M); - hi = (u32)(val >> P_REG_40B_HIGH_S); - - status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d", - low_addr, status); - return status; - } - - status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d", - high_addr, status); - return status; - } - - return ICE_SUCCESS; -} - -/** - * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers - * @hw: pointer to the HW struct - * @port: PHY port to read from - * @low_addr: offset of the lower register to read from - * @val: the contents of the 64bit value to write to PHY - * - * Write the 64bit value to the two associated 32bit PHY registers. - * This function checks that the caller has specified a known 64 bit register - * offset - */ -static enum ice_status -ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) -{ - u16 high_addr = low_addr + sizeof(u32); - enum ice_status status; - u32 lo, hi; - - if (!ice_is_64b_phy_reg_eth56g(low_addr)) - return ICE_ERR_PARAM; - - lo = ICE_LO_DWORD(val); - hi = ICE_HI_DWORD(val); - - status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d", - low_addr, status); - return status; - } - - status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d", - high_addr, status); - return status; - } - - return ICE_SUCCESS; -} - -/** - * ice_read_phy_tstamp_eth56g - Read a PHY timestamp out of the port memory - * @hw: pointer to the HW struct - * @port: the port to read from - * @idx: the timestamp index to read - * @tstamp: on return, the 40bit timestamp value - * - * Read a 40bit timestamp value out of the two associated entries in the - * port memory block of the internal PHYs of the 56G devices. - */ -static enum ice_status -ice_read_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp) -{ - enum ice_status status; - u16 lo_addr, hi_addr; - u32 lo, hi; - - lo_addr = (u16)PHY_TSTAMP_L(idx); - hi_addr = (u16)PHY_TSTAMP_U(idx); - - status = ice_phy_port_mem_read_eth56g(hw, port, lo_addr, &lo); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n", - status); - return status; - } - - status = ice_phy_port_mem_read_eth56g(hw, port, hi_addr, &hi); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n", - status); - return status; - } - - /* For 56G based internal PHYs, the timestamp is reported with the - * lower 8 bits in the low register, and the upper 32 bits in the high - * register. - */ - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); - - return ICE_SUCCESS; -} - -/** - * ice_clear_phy_tstamp_eth56g - Clear a timestamp from the quad block - * @hw: pointer to the HW struct - * @port: the quad to read from - * @idx: the timestamp index to reset - * - * Clear a timestamp, resetting its valid bit, in the PHY port memory of - * internal PHYs of the 56G devices. - */ -static enum ice_status -ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) -{ - enum ice_status status; - u16 lo_addr; - - lo_addr = (u16)PHY_TSTAMP_L(idx); - - status = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n", - status); - return status; - } - - return ICE_SUCCESS; -} - -/** - * ice_ptp_prep_port_phy_time_eth56g - Prepare one PHY port with initial time - * @hw: pointer to the HW struct - * @port: port number - * @phy_time: time to initialize the PHY port clocks to - * - * Write a new initial time value into registers of a specific PHY port. - */ -static enum ice_status -ice_ptp_prep_port_phy_time_eth56g(struct ice_hw *hw, u8 port, u64 phy_time) -{ - enum ice_status status; - - /* Tx case */ - status = ice_write_64b_phy_reg_eth56g(hw, port, - PHY_REG_TX_TIMER_INC_PRE_L, - phy_time); - if (status) - return status; - - /* Rx case */ - return ice_write_64b_phy_reg_eth56g(hw, port, - PHY_REG_RX_TIMER_INC_PRE_L, - phy_time); -} - -/** - * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time - * @hw: pointer to the HW struct - * @time: Time to initialize the PHY port clocks to - * - * Program the PHY port registers with a new initial time value. The port - * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync - * command. The time value is the upper 32 bits of the PHY timer, usually in - * units of nominal nanoseconds. - */ -static enum ice_status -ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) -{ - enum ice_status status; - u64 phy_time; - u8 port; - - /* The time represents the upper 32 bits of the PHY timer, so we need - * to shift to account for this when programming. - */ - phy_time = (u64)time << 32; - - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { - if (!(hw->ena_lports & BIT(port))) - continue; - status = ice_ptp_prep_port_phy_time_eth56g(hw, port, - phy_time); - - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n", - port, status); - return status; - } - } - - return ICE_SUCCESS; -} - -/** - * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust - * @hw: pointer to HW struct - * @port: Port number to be programmed - * @time: time in cycles to adjust the port Tx and Rx clocks - * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the - * sq_lock has already been locked at a higher level - * - * Program the port for an atomic adjustment by writing the Tx and Rx timer - * registers. The atomic adjustment won't be completed until the driver issues - * an ICE_PTP_ADJ_TIME command. - * - * Note that time is not in units of nanoseconds. It is in clock time - * including the lower sub-nanosecond portion of the port timer. - * - * Negative adjustments are supported using 2s complement arithmetic. - */ -enum ice_status -ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time, - bool lock_sbq) -{ - enum ice_status status; - u32 l_time, u_time; - - l_time = ICE_LO_DWORD(time); - u_time = ICE_HI_DWORD(time); - - /* Tx case */ - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_TX_TIMER_INC_PRE_L, - l_time, lock_sbq); - if (status) - goto exit_err; - - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_TX_TIMER_INC_PRE_U, - u_time, lock_sbq); - if (status) - goto exit_err; - - /* Rx case */ - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_RX_TIMER_INC_PRE_L, - l_time, lock_sbq); - if (status) - goto exit_err; - - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_RX_TIMER_INC_PRE_U, - u_time, lock_sbq); - if (status) - goto exit_err; - - return ICE_SUCCESS; - -exit_err: - ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n", - port, status); - return status; -} - -/** - * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment - * @hw: pointer to HW struct - * @adj: adjustment in nanoseconds - * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the - * sq_lock has already been locked at a higher level - * - * Prepare the PHY ports for an atomic time adjustment by programming the PHY - * Tx and Rx port registers. The actual adjustment is completed by issuing an - * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. - */ -static enum ice_status -ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq) -{ - enum ice_status status = ICE_SUCCESS; - s64 cycles; - u8 port; - - /* The port clock supports adjustment of the sub-nanosecond portion of - * the clock. We shift the provided adjustment in nanoseconds to - * calculate the appropriate adjustment to program into the PHY ports. - */ - cycles = (s64)adj << 32; - - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { - if (!(hw->ena_lports & BIT(port))) - continue; - - status = ice_ptp_prep_port_adj_eth56g(hw, port, cycles, - lock_sbq); - if (status) - break; - } - - return status; -} - -/** - * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment - * @hw: pointer to HW struct - * @incval: new increment value to prepare - * - * Prepare each of the PHY ports for a new increment value by programming the - * port's TIMETUS registers. The new increment value will be updated after - * issuing an ICE_PTP_INIT_INCVAL command. - */ -static enum ice_status -ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) -{ - enum ice_status status; - u8 port; - - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { - if (!(hw->ena_lports & BIT(port))) - continue; - status = ice_write_40b_phy_reg_eth56g(hw, port, - PHY_REG_TIMETUS_L, - incval); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n", - port, status); - return status; - } - } - - return ICE_SUCCESS; -} - -/** - * ice_ptp_read_phy_incval_eth56g - Read a PHY port's current incval - * @hw: pointer to the HW struct - * @port: the port to read - * @incval: on return, the time_clk_cyc incval for this port - * - * Read the time_clk_cyc increment value for a given PHY port. - */ -enum ice_status -ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval) -{ - enum ice_status status; - - status = ice_read_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, - incval); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n", - status); - return status; - } - - ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n", - (unsigned long long)*incval); - - return ICE_SUCCESS; -} - -/** - * ice_ptp_prep_phy_adj_target_eth56g - Prepare PHY for adjust at target time - * @hw: pointer to HW struct - * @target_time: target time to program - * - * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the - * ICE_PTP_ADJ_TIME_AT_TIME command. This should be used in conjunction with - * ice_ptp_prep_phy_adj_eth56g to program an atomic adjustment that is - * delayed until a specified target time. - * - * Note that a target time adjustment is not currently supported on E810 - * devices. - */ -static enum ice_status -ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time) -{ - enum ice_status status; - u8 port; - - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { - if (!(hw->ena_lports & BIT(port))) - continue; - - /* Tx case */ - /* No sub-nanoseconds data */ - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_TX_TIMER_CNT_ADJ_L, - 0, true); - if (status) - goto exit_err; - - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_TX_TIMER_CNT_ADJ_U, - target_time, true); - if (status) - goto exit_err; - - /* Rx case */ - /* No sub-nanoseconds data */ - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_RX_TIMER_CNT_ADJ_L, - 0, true); - if (status) - goto exit_err; - - status = ice_write_phy_reg_eth56g_lp(hw, port, - PHY_REG_RX_TIMER_CNT_ADJ_U, - target_time, true); - if (status) - goto exit_err; - } - - return ICE_SUCCESS; - -exit_err: - ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n", - port, status); - - return status; -} - -/** - * ice_ptp_read_port_capture_eth56g - Read a port's local time capture - * @hw: pointer to HW struct - * @port: Port number to read - * @tx_ts: on return, the Tx port time capture - * @rx_ts: on return, the Rx port time capture - * - * Read the port's Tx and Rx local time capture values. - */ -enum ice_status -ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts, - u64 *rx_ts) -{ - enum ice_status status; - - /* Tx case */ - status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, - tx_ts); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n", - status); - return status; - } - - ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", - (unsigned long long)*tx_ts); - - /* Rx case */ - status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, - rx_ts); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n", - status); - return status; - } - - ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", - (unsigned long long)*rx_ts); - - return ICE_SUCCESS; -} - -/** - * ice_ptp_one_port_cmd_eth56g - Prepare a single PHY port for a timer command - * @hw: pointer to HW struct - * @port: Port to which cmd has to be sent - * @cmd: Command to be sent to the port - * @lock_sbq: true if the sideband queue lock must be acquired - * - * Prepare the requested port for an upcoming timer sync command. - */ -enum ice_status -ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port, - enum ice_ptp_tmr_cmd cmd, bool lock_sbq) -{ - enum ice_status status; - u32 cmd_val, val; - u8 tmr_idx; - - tmr_idx = ice_get_ptp_src_clock_index(hw); - cmd_val = tmr_idx << SEL_PHY_SRC; - switch (cmd) { - case ICE_PTP_INIT_TIME: - cmd_val |= PHY_CMD_INIT_TIME; - break; - case ICE_PTP_INIT_INCVAL: - cmd_val |= PHY_CMD_INIT_INCVAL; - break; - case ICE_PTP_ADJ_TIME: - cmd_val |= PHY_CMD_ADJ_TIME; - break; - case ICE_PTP_ADJ_TIME_AT_TIME: - cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME; - break; - case ICE_PTP_READ_TIME: - cmd_val |= PHY_CMD_READ_TIME; - break; - default: - ice_warn(hw, "Unknown timer command %u\n", cmd); - return ICE_ERR_PARAM; - } - - /* Tx case */ - /* Read, modify, write */ - status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, &val, - lock_sbq); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n", - status); - return status; - } - - /* Modify necessary bits only and perform write */ - val &= ~TS_CMD_MASK; - val |= cmd_val; - - status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, val, - lock_sbq); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n", - status); - return status; - } - - /* Rx case */ - /* Read, modify, write */ - status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, &val, - lock_sbq); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n", - status); - return status; - } - - /* Modify necessary bits only and perform write */ - val &= ~TS_CMD_MASK; - val |= cmd_val; - - status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, val, - lock_sbq); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n", - status); - return status; - } - - return ICE_SUCCESS; -} - -/** - * ice_ptp_port_cmd_eth56g - Prepare all ports for a timer command - * @hw: pointer to the HW struct - * @cmd: timer command to prepare - * @lock_sbq: true if the sideband queue lock must be acquired - * - * Prepare all ports connected to this device for an upcoming timer sync - * command. - */ -static enum ice_status -ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, - bool lock_sbq) -{ - enum ice_status status; - u8 port; - - for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { - if (!(hw->ena_lports & BIT(port))) - continue; - - status = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq); - if (status) - return status; - } - - return ICE_SUCCESS; -} - -/** - * ice_calc_fixed_tx_offset_eth56g - Calculated Fixed Tx offset for a port - * @hw: pointer to the HW struct - * @link_spd: the Link speed to calculate for - * - * Calculate the fixed offset due to known static latency data. - */ -static u64 -ice_calc_fixed_tx_offset_eth56g(struct ice_hw *hw, - enum ice_ptp_link_spd link_spd) -{ - u64 fixed_offset = 0; - return fixed_offset; -} - -/** - * ice_phy_cfg_tx_offset_eth56g - Configure total Tx timestamp offset - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * Program the PHY_REG_TOTAL_TX_OFFSET register with the total number of TUs to - * adjust Tx timestamps by. - * - * To avoid overflow, when calculating the offset based on the known static - * latency values, we use measurements in 1/100th of a nanosecond, and divide - * the TUs per second up front. This avoids overflow while allowing - * calculation of the adjustment using integer arithmetic. - */ -enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port) -{ - enum ice_ptp_link_spd link_spd = ICE_PTP_LNK_SPD_10G; - enum ice_status status; - u64 total_offset; - - total_offset = ice_calc_fixed_tx_offset_eth56g(hw, link_spd); - - /* Now that the total offset has been calculated, program it to the - * PHY and indicate that the Tx offset is ready. After this, - * timestamps will be enabled. - */ - status = ice_write_64b_phy_reg_eth56g(hw, port, - PHY_REG_TOTAL_TX_OFFSET_L, - total_offset); - if (status) - return status; - - return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); -} - -/** - * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port - * @hw: pointer to HW struct - * @link_spd: The Link speed to calculate for - * - * Determine the fixed Rx latency for a given link speed. - */ -static u64 -ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw, - enum ice_ptp_link_spd link_spd) -{ - u64 fixed_offset = 0; - return fixed_offset; -} - -/** - * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * Program the PHY_REG_TOTAL_RX_OFFSET register with the number of Time Units to - * adjust Rx timestamps by. This combines calculations from the Vernier offset - * measurements taken in hardware with some data about known fixed delay as - * well as adjusting for multi-lane alignment delay. - * - * This function must be called only after the offset registers are valid, - * i.e. after the Vernier calibration wait has passed, to ensure that the PHY - * has measured the offset. - * - * To avoid overflow, when calculating the offset based on the known static - * latency values, we use measurements in 1/100th of a nanosecond, and divide - * the TUs per second up front. This avoids overflow while allowing - * calculation of the adjustment using integer arithmetic. - */ -enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) -{ - enum ice_status status; - u64 total_offset; - - total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0); - - /* Now that the total offset has been calculated, program it to the - * PHY and indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - */ - status = ice_write_64b_phy_reg_eth56g(hw, port, - PHY_REG_TOTAL_RX_OFFSET_L, - total_offset); - if (status) - return status; - - return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); -} - -/** - * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time - * @hw: pointer to the HW struct - * @port: the PHY port to read - * @phy_time: on return, the 64bit PHY timer value - * @phc_time: on return, the lower 64bits of PHC time - * - * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY - * and PHC timer values. - */ -static enum ice_status -ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time, - u64 *phc_time) -{ - enum ice_status status; - u64 tx_time, rx_time; - u32 zo, lo; - u8 tmr_idx; - - tmr_idx = ice_get_ptp_src_clock_index(hw); - - /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ - ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); - - /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ - status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true); - if (status) - return status; - - /* Issue the sync to start the ICE_PTP_READ_TIME capture */ - ice_ptp_exec_tmr_cmd(hw); - ice_ptp_clean_cmd(hw); - - /* Read the captured PHC time from the shadow time registers */ - zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); - lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); - *phc_time = (u64)lo << 32 | zo; - - /* Read the captured PHY time from the PHY shadow registers */ - status = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); - if (status) - return status; - - /* If the PHY Tx and Rx timers don't match, log a warning message. - * Note that this should not happen in normal circumstances since the - * driver always programs them together. - */ - if (tx_time != rx_time) - ice_warn(hw, "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", - port, (unsigned long long)tx_time, - (unsigned long long)rx_time); - - *phy_time = tx_time; - - return ICE_SUCCESS; -} - -/** - * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer - * @hw: pointer to the HW struct - * @port: the PHY port to synchronize - * - * Perform an adjustment to ensure that the PHY and PHC timers are in sync. - * This is done by issuing a ICE_PTP_READ_TIME command which triggers a - * simultaneous read of the PHY timer and PHC timer. Then we use the - * difference to calculate an appropriate 2s complement addition to add - * to the PHY timer in order to ensure it reads the same value as the - * primary PHC timer. - */ -static enum ice_status ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) -{ - u64 phc_time, phy_time, difference; - enum ice_status status; - - if (!ice_ptp_lock(hw)) { - ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); - return ICE_ERR_NOT_READY; - } - - status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, - &phc_time); - if (status) - goto err_unlock; - - /* Calculate the amount required to add to the port time in order for - * it to match the PHC time. - * - * Note that the port adjustment is done using 2s complement - * arithmetic. This is convenient since it means that we can simply - * calculate the difference between the PHC time and the port time, - * and it will be interpreted correctly. - */ - - ice_ptp_src_cmd(hw, ICE_PTP_NOP); - difference = phc_time - phy_time; - - status = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference, true); - if (status) - goto err_unlock; - - status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true); - if (status) - goto err_unlock; - - /* Issue the sync to activate the time adjustment */ - ice_ptp_exec_tmr_cmd(hw); - ice_ptp_clean_cmd(hw); - - /* Re-capture the timer values to flush the command registers and - * verify that the time was properly adjusted. - */ - - status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, - &phc_time); - if (status) - goto err_unlock; - - ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", - port, (unsigned long long)phy_time, - (unsigned long long)phc_time); - -err_unlock: - ice_ptp_unlock(hw); - return status; -} - -/** - * ice_stop_phy_timer_eth56g - Stop the PHY clock timer - * @hw: pointer to the HW struct - * @port: the PHY port to stop - * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS - * - * Stop the clock of a PHY port. This must be done as part of the flow to - * re-calibrate Tx and Rx timestamping offsets whenever the clock time is - * initialized or when link speed changes. - */ -enum ice_status -ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) -{ - enum ice_status status; - - status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); - if (status) - return status; - - status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); - if (status) - return status; - - ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); - - return ICE_SUCCESS; -} - -/** - * ice_start_phy_timer_eth56g - Start the PHY clock timer - * @hw: pointer to the HW struct - * @port: the PHY port to start - * @bypass: unused, for compatibility - * - * Start the clock of a PHY port. This must be done as part of the flow to - * re-calibrate Tx and Rx timestamping offsets whenever the clock time is - * initialized or when link speed changes. - * - */ -enum ice_status -ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass) -{ - enum ice_status status; - u32 lo, hi; - u64 incval; - u8 tmr_idx; - - tmr_idx = ice_get_ptp_src_clock_index(hw); - - status = ice_stop_phy_timer_eth56g(hw, port, false); - if (status) - return status; - - ice_ptp_src_cmd(hw, ICE_PTP_NOP); - - lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); - hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); - incval = (u64)hi << 32 | lo; - - status = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, - incval); - if (status) - return status; - - status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL, - true); - if (status) - return status; - - ice_ptp_exec_tmr_cmd(hw); - - status = ice_sync_phy_timer_eth56g(hw, port); - if (status) - return status; - - /* Program the Tx offset */ - status = ice_phy_cfg_tx_offset_eth56g(hw, port); - if (status) - return status; - - /* Program the Rx offset */ - status = ice_phy_cfg_rx_offset_eth56g(hw, port); - if (status) - return status; - - ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); - - return ICE_SUCCESS; -} - -/** - * ice_ptp_init_phc_eth56g - Perform E822 specific PHC initialization - * @hw: pointer to HW struct - * - * Perform PHC initialization steps specific to E822 devices. - */ -static enum ice_status ice_ptp_init_phc_eth56g(struct ice_hw *hw) -{ - enum ice_status status = ICE_SUCCESS; - u32 regval; - - /* Enable reading switch and PHY registers over the sideband queue */ -#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) -#define PF_SB_REM_DEV_CTL_PHY0 BIT(2) - regval = rd32(hw, PF_SB_REM_DEV_CTL); - regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | - PF_SB_REM_DEV_CTL_PHY0); - wr32(hw, PF_SB_REM_DEV_CTL, regval); - - /* Initialize the Clock Generation Unit */ - status = ice_init_cgu_e822(hw); - - return status; -} - -/** - * ice_ptp_read_tx_hwtstamp_status_eth56g - Get the current TX timestamp - * status mask. Returns the mask of ports where TX timestamps are available - * @hw: pointer to the HW struct - * @ts_status: the timestamp mask pointer - */ -enum ice_status -ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) -{ - enum ice_status status; - - status = ice_read_phy_eth56g_raw_lp(hw, PHY_PTP_INT_STATUS, ts_status, - true); - if (status) - return status; - - ice_debug(hw, ICE_DBG_PTP, "PHY interrupt status: %x\n", *ts_status); - - return ICE_SUCCESS; -} - -/** - * ice_ptp_init_phy_cfg - Get the current TX timestamp status - * mask. Returns the mask of ports where TX timestamps are available - * @hw: pointer to the HW struct - */ -enum ice_status -ice_ptp_init_phy_cfg(struct ice_hw *hw) -{ - enum ice_status status; - u32 phy_rev; - - status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev, - true); - if (status) - return status; - - if (phy_rev == PHY_REVISION_ETH56G) { - hw->phy_cfg = ICE_PHY_ETH56G; - return ICE_SUCCESS; - } - - if (ice_is_e810(hw)) - hw->phy_cfg = ICE_PHY_E810; - else - hw->phy_cfg = ICE_PHY_E822; - - return ICE_SUCCESS; -} /* ---------------------------------------------------------------------------- * E822 family functions @@ -4891,9 +3522,6 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) /* Next, prepare the ports */ switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_port_cmd_eth56g(hw, cmd, lock_sbq); - break; case ICE_PHY_E810: status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq); break; @@ -4946,9 +3574,6 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_prep_phy_time_eth56g(hw, time & 0xFFFFFFFF); - break; case ICE_PHY_E810: status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); break; @@ -4991,9 +3616,6 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval) wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_prep_phy_incval_eth56g(hw, incval); - break; case ICE_PHY_E810: status = ice_ptp_prep_phy_incval_e810(hw, incval); break; @@ -5062,9 +3684,6 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq) wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq); - break; case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq); break; @@ -5123,9 +3742,6 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) /* Prepare PHY port adjustments */ switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_prep_phy_adj_eth56g(hw, adj, true); - break; case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_e810(hw, adj, true); break; @@ -5141,9 +3757,6 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) /* Set target time for each PHY port */ switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_prep_phy_adj_target_eth56g(hw, time_lo); - break; case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo); break; @@ -5177,9 +3790,6 @@ ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) enum ice_status status; switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp); - break; case ICE_PHY_E810: status = ice_read_phy_tstamp_e810(hw, block, idx, tstamp); break; @@ -5209,9 +3819,6 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) enum ice_status status; switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_clear_phy_tstamp_eth56g(hw, block, idx); - break; case ICE_PHY_E810: status = ice_clear_phy_tstamp_e810(hw, block, idx); break; @@ -5243,9 +3850,6 @@ enum ice_status ice_ptp_init_phc(struct ice_hw *hw) (void)rd32(hw, GLTSYN_STAT(src_idx)); switch (hw->phy_cfg) { - case ICE_PHY_ETH56G: - status = ice_ptp_init_phc_eth56g(hw); - break; case ICE_PHY_E810: status = ice_ptp_init_phc_e810(hw); break; diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 3667c9882d..d2581e63f9 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -235,38 +235,7 @@ bool ice_is_pca9575_present(struct ice_hw *hw); void ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event); -/* ETH56G family functions */ -enum ice_status -ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val); -enum ice_status -ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val); -enum ice_status -ice_read_phy_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val); -enum ice_status -ice_write_phy_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val); - -enum ice_status -ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time, - bool lock_sbq); - -enum ice_status -ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval); -enum ice_status -ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, - u64 *tx_ts, u64 *rx_ts); -enum ice_status -ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port, - enum ice_ptp_tmr_cmd cmd, bool lock_sbq); -enum ice_status -ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status); -enum ice_status -ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset); -enum ice_status -ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass); -enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port); -enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port); -enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw); #define PFTSYN_SEM_BYTES 4 @@ -528,12 +497,6 @@ enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw); #define ICE_E810T_SMA_MIN_BIT 3 #define ICE_E810T_SMA_MAX_BIT 7 #define ICE_E810T_P1_OFFSET 8 -/* 56G PHY quad register base addresses */ -#define ICE_PHY0_BASE 0x092000 -#define ICE_PHY1_BASE 0x126000 -#define ICE_PHY2_BASE 0x1BA000 -#define ICE_PHY3_BASE 0x24E000 -#define ICE_PHY4_BASE 0x2E2000 /* Timestamp memory */ #define PHY_PTP_LANE_ADDR_STEP 0x98 @@ -602,6 +565,5 @@ enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw); #define PHY_TSTAMP_U(x) (((x) * 8) + 4) #define PHY_REG_REVISION 0x85000 -#define PHY_REVISION_ETH56G 0x10200 #endif /* _ICE_PTP_HW_H_ */ From patchwork Thu Apr 27 06:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126582 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 13A7E42A08; Thu, 27 Apr 2023 08:39:41 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E99F42DC8; Thu, 27 Apr 2023 08:38:16 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id D513742DC2 for ; Thu, 27 Apr 2023 08:38:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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26 Apr 2023 23:38:10 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Sergey Temerkhanov Subject: [PATCH 15/30] net/ice/base: allow skip main timer Date: Thu, 27 Apr 2023 06:19:46 +0000 Message-Id: <20230427062001.478032-16-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Allow initialization functions to skip main timer programming. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 32 ++++++++++++++++++++----------- drivers/net/ice/base/ice_ptp_hw.h | 9 ++++++--- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 61145262ac..43b7e313f4 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3550,6 +3550,7 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) * ice_ptp_init_time - Initialize device time to provided value * @hw: pointer to HW struct * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) + * @wr_main_tmr: program the main timer * * Initialize the device to the specified time provided. This requires a three * step process: @@ -3559,7 +3560,8 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) * 3) issue an init_time timer command to synchronously switch both the source * and port timers to the new init time value at the next clock cycle. */ -enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) +enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time, + bool wr_main_tmr) { enum ice_status status; u8 tmr_idx; @@ -3567,9 +3569,11 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; /* Source timers */ - wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); - wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + if (wr_main_tmr) { + wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time)); + wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); + } /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ @@ -3594,8 +3598,9 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) * ice_ptp_write_incval - Program PHC with new increment value * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * - * Program the PHC with a new increment value. This requires a three-step + * Program the timers with a new increment value. This requires a three-step * process: * * 1) Write the increment value to the source timer shadow registers @@ -3604,16 +3609,19 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time) * the source and port timers to the new increment value at the next clock * cycle. */ -enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval) +enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { enum ice_status status; u8 tmr_idx; tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; - /* Shadow Adjust */ - wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); - wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + if (wr_main_tmr) { + /* Shadow Adjust */ + wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval)); + wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); + } switch (hw->phy_cfg) { case ICE_PHY_E810: @@ -3636,17 +3644,19 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval) * ice_ptp_write_incval_locked - Program new incval while holding semaphore * @hw: pointer to HW struct * @incval: Source timer increment value per clock cycle + * @wr_main_tmr: Program the main timer * * Program a new PHC incval while holding the PTP semaphore. */ -enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) +enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr) { enum ice_status status; if (!ice_ptp_lock(hw)) return ICE_ERR_NOT_READY; - status = ice_ptp_write_incval(hw, incval); + status = ice_ptp_write_incval(hw, incval, wr_main_tmr); ice_ptp_unlock(hw); diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index d2581e63f9..48a30f1f4e 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -131,9 +131,12 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd); -enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time); -enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval); -enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); +enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time, + bool wr_main_tmr); +enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); +enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, + bool wr_main_tmr); enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); enum ice_status ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 9a88cf9796..6700893bc5 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -5832,7 +5832,7 @@ ice_timesync_enable(struct rte_eth_dev *dev) return -1; } - ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810); + ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, 1); if (ret) { PMD_DRV_LOG(ERR, "Failed to write PHC increment time value"); From patchwork Thu Apr 27 06:19:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126583 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 38B5C42A08; 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a="375324346" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324346" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845817" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845817" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:11 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Paul Greenwalt , Sergey Temerkhanov Subject: [PATCH 16/30] net/ice/base: add E830 PTP init Date: Thu, 27 Apr 2023 06:19:47 +0000 Message-Id: <20230427062001.478032-17-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The E830, E822 and E810 PTP initialization flows are similar. So related fix are also added. Signed-off-by: Paul Greenwalt Signed-off-by: Sergey Temerkhanov Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 295 +++++++++++++++++++----------- drivers/net/ice/base/ice_ptp_hw.h | 94 +++++++++- drivers/net/ice/base/ice_type.h | 18 +- drivers/net/ice/ice_ethdev.c | 6 +- 4 files changed, 298 insertions(+), 115 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 43b7e313f4..a638bb114c 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -448,6 +448,17 @@ static void ice_ptp_clean_cmd(struct ice_hw *hw) ice_flush(hw); } +/** + * ice_ptp_zero_syn_dlay - Set synchronization delay to zero + * @hw: pointer to HW struct + * + * Zero E810 and E830 specific PTP hardware clock synchronization delay. + */ +static void ice_ptp_zero_syn_dlay(struct ice_hw *hw) +{ + wr32(hw, GLTSYN_SYNC_DLAY, 0); + ice_flush(hw); +} /* ---------------------------------------------------------------------------- * E822 family functions @@ -1037,6 +1048,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) return ICE_SUCCESS; } +/** + * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block + * @hw: pointer to the HW struct + * @quad: the quad to read from + * + * Clear all timestamps from the PHY quad block that is shared between the + * internal PHYs on the E822 devices. + */ +void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad) +{ + ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); + ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); +} + +/** + * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks + * @hw: pointer to the HW struct + */ +static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw) +{ + u8 quad; + + for (quad = 0; quad < ICE_MAX_QUAD; quad++) { + ice_ptp_reset_ts_memory_quad_e822(hw, quad); + } +} + /** * ice_ptp_set_vernier_wl - Set the window length for vernier calibration * @hw: pointer to the HW struct @@ -2652,89 +2690,43 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) } /** - * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations + * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * After hardware finishes vernier calculations for the Tx and Rx offset, this - * function can be used to exit bypass mode by updating the total Tx and Rx - * offsets, and then disabling bypass. This will enable hardware to include - * the more precise offset calibrations, increasing precision of the generated - * timestamps. + * @quad: the timestamp quad to read from + * @tstamp_ready: contents of the Tx memory status register * - * This cannot be done until hardware has measured the offsets, which requires - * waiting until at least one packet has been sent and received by the device. + * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in + * the PHY are ready. A set bit means the corresponding timestamp is valid and + * ready to be captured from the PHY timestamp block. */ -enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port) +static enum ice_status +ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) { enum ice_status status; - u32 val; + u32 hi, lo; - status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val); + status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U, + &hi); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, status %d\n", - port, status); + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, status %d\n", + quad, status); return status; } - if (!(val & P_REG_TX_OV_STATUS_OV_M)) { - ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port %u\n", - port); - return ICE_ERR_NOT_READY; - } - - status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val); + status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L, + &lo); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, status %d\n", - port, status); + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, status %d\n", + quad, status); return status; } - if (!(val & P_REG_TX_OV_STATUS_OV_M)) { - ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port %u\n", - port); - return ICE_ERR_NOT_READY; - } - - status = ice_phy_cfg_tx_offset_e822(hw, port); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset for port %u, status %d\n", - port, status); - return status; - } - - status = ice_phy_cfg_rx_offset_e822(hw, port); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset for port %u, status %d\n", - port, status); - return status; - } - - /* Exit bypass mode now that the offset has been updated */ - status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port %u, status %d\n", - port, status); - return status; - } - - if (!(val & P_REG_PS_BYPASS_MODE_M)) - ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n", - port); - - val &= ~P_REG_PS_BYPASS_MODE_M; - status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port %u, status %d\n", - port, status); - return status; - } - - ice_info(hw, "Exiting bypass mode on PHY port %u\n", port); + *tstamp_ready = (u64)hi << 32 | (u64)lo; return ICE_SUCCESS; } + /* E810 functions * * The following functions operate on the E810 series devices which use @@ -3218,6 +3210,22 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, return ICE_SUCCESS; } +/** + * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register + * @hw: pointer to the HW struct + * @port: the PHY port to read + * @tstamp_ready: contents of the Tx memory status register + * + * E810 devices do not use a Tx memory status register. Instead simply + * indicate that all timestamps are currently ready. + */ +static enum ice_status +ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) +{ + *tstamp_ready = 0xFFFFFFFFFFFFFFFF; + return ICE_SUCCESS; +} + /* E810T SMA functions * * The following functions operate specifically on E810T hardware and are used @@ -3445,6 +3453,23 @@ bool ice_is_pca9575_present(struct ice_hw *hw) return false; } +/* E830 functions + * + * The following functions operate on the E830 series devices. + * + */ + +/** + * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization + * @hw: pointer to HW struct + * + * Perform E830-specific PTP hardware clock initialization steps. + */ +static enum ice_status ice_ptp_init_phc_e830(struct ice_hw *hw) +{ + ice_ptp_zero_syn_dlay(hw); + return ICE_SUCCESS; +} /* Device agnostic functions * * The following functions implement shared behavior common to both E822/E823 @@ -3501,6 +3526,29 @@ void ice_ptp_unlock(struct ice_hw *hw) wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); } +#define ICE_DEVID_MASK 0xFFF8 + +/** + * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type + * @hw: pointer to the HW structure + * + * Determine the PHY model for the device, and initialize hw->phy_model + * for use by other functions. + */ +enum ice_status ice_ptp_init_phy_model(struct ice_hw *hw) +{ + + if (ice_is_e810(hw)) + hw->phy_model = ICE_PHY_E810; + else if (ice_is_e830(hw)) + hw->phy_model = ICE_PHY_E830; + else + hw->phy_model = ICE_PHY_E822; + hw->phy_ports = ICE_NUM_EXTERNAL_PORTS; + + return ICE_SUCCESS; +} + /** * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command * @hw: pointer to HW struct @@ -3521,16 +3569,20 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) ice_ptp_src_cmd(hw, cmd); /* Next, prepare the ports */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq); break; case ICE_PHY_E822: status = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq); break; + case ICE_PHY_E830: + status = ICE_SUCCESS; + break; default: status = ICE_ERR_NOT_SUPPORTED; } + if (status) { ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, status %d\n", cmd, status); @@ -3577,13 +3629,16 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time, /* PHY Clks */ /* Fill Rx and Tx ports and send msg to PHY */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); break; case ICE_PHY_E822: status = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF); break; + case ICE_PHY_E830: + status = ICE_SUCCESS; + break; default: status = ICE_ERR_NOT_SUPPORTED; } @@ -3623,13 +3678,16 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval, wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval)); } - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: status = ice_ptp_prep_phy_incval_e810(hw, incval); break; case ICE_PHY_E822: status = ice_ptp_prep_phy_incval_e822(hw, incval); break; + case ICE_PHY_E830: + status = ICE_SUCCESS; + break; default: status = ICE_ERR_NOT_SUPPORTED; } @@ -3693,7 +3751,7 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq) wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq); break; @@ -3751,7 +3809,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) wr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi); /* Prepare PHY port adjustments */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_e810(hw, adj, true); break; @@ -3766,7 +3824,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return status; /* Set target time for each PHY port */ - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo); break; @@ -3797,49 +3855,58 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) enum ice_status ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) { - enum ice_status status; - - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: - status = ice_read_phy_tstamp_e810(hw, block, idx, tstamp); - break; + return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); case ICE_PHY_E822: - status = ice_read_phy_tstamp_e822(hw, block, idx, tstamp); - break; + return ice_read_phy_tstamp_e822(hw, block, idx, tstamp); default: - status = ICE_ERR_NOT_SUPPORTED; + return ICE_ERR_NOT_SUPPORTED; } - - return status; } /** - * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block + * ice_clear_phy_tstamp - Drop a timestamp from the timestamp block * @hw: pointer to the HW struct * @block: the block to read from * @idx: the timestamp index to reset * - * Clear a timestamp, resetting its valid bit, from the timestamp block. For - * E822 devices, the block is the quad to clear from. For E810 devices, the - * block is the logical port to clear from. + * Drop a timestamp from the timestamp block by reading it. This will reset + * the memory status bit allowing the timestamp index to be reused. For E822 + * devices, the block is the quad to clear from. For E810 devices, the block + * is the logical port to clear from. + * + * This function should only be called on a timestamp index whose valid bit + * is set according to ice_get_phy_tx_tstamp_ready. */ enum ice_status ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) { - enum ice_status status; - - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: - status = ice_clear_phy_tstamp_e810(hw, block, idx); - break; + return ice_clear_phy_tstamp_e810(hw, block, idx); case ICE_PHY_E822: - status = ice_clear_phy_tstamp_e822(hw, block, idx); - break; + return ice_clear_phy_tstamp_e822(hw, block, idx); default: - status = ICE_ERR_NOT_SUPPORTED; + return ICE_ERR_NOT_SUPPORTED; } +} - return status; +/** + * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks + * @hw: pointer to the HW struct + */ +void ice_ptp_reset_ts_memory(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_E822: + ice_ptp_reset_ts_memory_e822(hw); + break; + case ICE_PHY_E810: + case ICE_PHY_E830: + default: + return; + } } /** @@ -3850,7 +3917,6 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) */ enum ice_status ice_ptp_init_phc(struct ice_hw *hw) { - enum ice_status status; u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; /* Enable source clocks */ @@ -3859,16 +3925,41 @@ enum ice_status ice_ptp_init_phc(struct ice_hw *hw) /* Clear event status indications for auxiliary pins */ (void)rd32(hw, GLTSYN_STAT(src_idx)); - switch (hw->phy_cfg) { + switch (hw->phy_model) { case ICE_PHY_E810: - status = ice_ptp_init_phc_e810(hw); - break; + return ice_ptp_init_phc_e810(hw); case ICE_PHY_E822: - status = ice_ptp_init_phc_e822(hw); - break; + return ice_ptp_init_phc_e822(hw); + case ICE_PHY_E830: + return ice_ptp_init_phc_e830(hw); default: - status = ICE_ERR_NOT_SUPPORTED; + return ICE_ERR_NOT_SUPPORTED; } +} - return status; +/** + * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication + * @hw: pointer to the HW struct + * @block: the timestamp block to check + * @tstamp_ready: storage for the PHY Tx memory status information + * + * Check the PHY for Tx timestamp memory status. This reports a 64 bit value + * which indicates which timestamps in the block may be captured. A set bit + * means the timestamp can be read. An unset bit means the timestamp is not + * ready and software should avoid reading the register. + */ +enum ice_status +ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) +{ + switch (hw->phy_model) { + case ICE_PHY_E810: + return ice_get_phy_tx_tstamp_ready_e810(hw, block, + tstamp_ready); + case ICE_PHY_E822: + return ice_get_phy_tx_tstamp_ready_e822(hw, block, + tstamp_ready); + break; + default: + return ICE_ERR_NOT_SUPPORTED; + } } diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 48a30f1f4e..e25018a68f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -41,6 +41,14 @@ enum ice_ptp_fec_mode { ICE_PTP_FEC_MODE_RS_FEC }; +/* Main timer mode */ +enum ice_src_tmr_mode { + ICE_SRC_TMR_MODE_NANOSECONDS, + ICE_SRC_TMR_MODE_LOCKED, + + NUM_ICE_SRC_TMR_MODE +}; + /** * struct ice_time_ref_info_e822 * @pll_freq: Frequency of PLL that drives timer ticks in Hz @@ -123,7 +131,10 @@ extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD]; /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for * the E810 devices. Based off of a PLL with an 812.5 MHz frequency. */ -#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL + +#define ICE_E810_PLL_FREQ 812500000 +#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL +#define E810_OUT_PROP_DELAY_NS 1 /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); @@ -144,9 +155,13 @@ enum ice_status ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); enum ice_status ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx); +void ice_ptp_reset_ts_memory(struct ice_hw *hw); enum ice_status ice_ptp_init_phc(struct ice_hw *hw); - +enum ice_status +ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready); /* E822 family functions */ +#define LOCKED_INCVAL_E822 0x100000000ULL + enum ice_status ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val); enum ice_status @@ -166,6 +181,7 @@ ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, enum ice_status ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); +void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad); enum ice_status ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, enum ice_clk_src clk_src); @@ -236,9 +252,83 @@ enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data); enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data); bool ice_is_pca9575_present(struct ice_hw *hw); +/* + * ice_is_e830 + * @hw: pointer to the hardware structure + * + * returns true if the device is E830 based, false if not. + */ +static inline bool ice_is_e830(struct ice_hw *hw) +{ + return hw->mac_type == ICE_MAC_E830; +} + void ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event); +enum ice_status ice_ptp_init_phy_model(struct ice_hw *hw); + +/** + * ice_ptp_get_pll_freq - Get PLL frequency + * @hw: Board private structure + */ +static inline u64 +ice_ptp_get_pll_freq(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_E810: + return ICE_E810_PLL_FREQ; + case ICE_PHY_E822: + return ice_e822_pll_freq(ice_e822_time_ref(hw)); + default: + return 0; + } +} + +static inline u64 +ice_prop_delay(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_E810: + return E810_OUT_PROP_DELAY_NS; + case ICE_PHY_E822: + return ice_e822_pps_delay(ice_e822_time_ref(hw)); + default: + return 0; + } +} + +static inline enum ice_time_ref_freq +ice_time_ref(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_E810: + case ICE_PHY_E822: + return ice_e822_time_ref(hw); + default: + return ICE_TIME_REF_FREQ_INVALID; + } +} + +static inline u64 +ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode) +{ + switch (hw->phy_model) { + + case ICE_PHY_E810: + return ICE_PTP_NOMINAL_INCVAL_E810; + case ICE_PHY_E822: + if (src_tmr_mode == ICE_SRC_TMR_MODE_NANOSECONDS && + ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ) + return ice_e822_nominal_incval(ice_e822_time_ref(hw)); + else + return LOCKED_INCVAL_E822; + + break; + default: + return 0; + } +} #define PFTSYN_SEM_BYTES 4 diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 576998549e..d072b0bfe2 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -760,7 +760,9 @@ enum ice_time_ref_freq { ICE_TIME_REF_FREQ_156_250 = 4, ICE_TIME_REF_FREQ_245_760 = 5, - NUM_ICE_TIME_REF_FREQ + NUM_ICE_TIME_REF_FREQ, + + ICE_TIME_REF_FREQ_INVALID = -1, }; /* Clock source specification */ @@ -1246,11 +1248,12 @@ struct ice_switch_info { ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); }; -/* PHY configuration */ -enum ice_phy_cfg { - ICE_PHY_E810 = 1, +/* PHY model */ +enum ice_phy_model { + ICE_PHY_UNSUP = -1, + ICE_PHY_E810 = 1, ICE_PHY_E822, - ICE_PHY_ETH56G, + ICE_PHY_E830, }; /* Port hardware description */ @@ -1277,7 +1280,8 @@ struct ice_hw { u8 revision_id; u8 pf_id; /* device profile info */ - enum ice_phy_cfg phy_cfg; + enum ice_phy_model phy_model; + u8 phy_ports; u8 logical_pf_id; u16 max_burst_size; /* driver sets this value */ @@ -1311,7 +1315,6 @@ struct ice_hw { void *buf, u16 buf_size); void *aq_send_cmd_param; u8 dcf_enabled; /* Device Config Function */ - u8 api_branch; /* API branch version */ u8 api_maj_ver; /* API major version */ u8 api_min_ver; /* API minor version */ @@ -1665,7 +1668,6 @@ struct ice_aq_get_set_rss_lut_params { /* AQ API version for report default configuration */ #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 - #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 /* FW version for FEC disable in Auto FEC mode */ diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 6700893bc5..a5bf8317a7 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2414,11 +2414,11 @@ ice_dev_init(struct rte_eth_dev *dev) ice_tm_conf_init(dev); if (ice_is_e810(hw)) - hw->phy_cfg = ICE_PHY_E810; + hw->phy_model = ICE_PHY_E810; else - hw->phy_cfg = ICE_PHY_E822; + hw->phy_model = ICE_PHY_E822; - if (hw->phy_cfg == ICE_PHY_E822) { + if (hw->phy_model == ICE_PHY_E822) { ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); From patchwork Thu Apr 27 06:19:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126584 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DAFAB42A08; Thu, 27 Apr 2023 08:39:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DF7042FA4; Thu, 27 Apr 2023 08:38:19 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 5D05B42F8A for ; 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a="805845828" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845828" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:13 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Grzegorz Nitka Subject: [PATCH 17/30] net/ice/base: add C825X device support Date: Thu, 27 Apr 2023 06:19:48 +0000 Message-Id: <20230427062001.478032-18-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Use ICE_MAC_GENERIC_3K type for C825X devices and fix E825X name to C825X. Signed-off-by: Grzegorz Nitka Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 13 +++++++++---- drivers/net/ice/base/ice_ddp.c | 8 +++++++- drivers/net/ice/base/ice_ddp.h | 1 + drivers/net/ice/base/ice_devids.h | 11 ++++------- drivers/net/ice/base/ice_type.h | 1 + drivers/net/ice/ice_ethdev.c | 3 +-- 6 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index ed822afc30..e4b25321db 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -241,13 +241,17 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) case ICE_DEV_ID_E823C_QSFP: case ICE_DEV_ID_E823C_SFP: case ICE_DEV_ID_E823C_SGMII: + hw->mac_type = ICE_MAC_GENERIC; + break; case ICE_DEV_ID_E824S: + hw->mac_type = ICE_MAC_GENERIC_3K; + break; case ICE_DEV_ID_E825C_BACKPLANE: case ICE_DEV_ID_E825C_QSFP: case ICE_DEV_ID_E825C_SFP: - case ICE_DEV_ID_E825C_1GBE: - case ICE_DEV_ID_E825X: - hw->mac_type = ICE_MAC_GENERIC; + case ICE_DEV_ID_C825X: + case ICE_DEV_ID_E825C_SGMII: + hw->mac_type = ICE_MAC_GENERIC_3K_E825; break; case ICE_DEV_ID_E830_BACKPLANE: case ICE_DEV_ID_E830_QSFP56: @@ -273,7 +277,8 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw) bool ice_is_generic_mac(struct ice_hw *hw) { return (hw->mac_type == ICE_MAC_GENERIC || - hw->mac_type == ICE_MAC_GENERIC_3K); + hw->mac_type == ICE_MAC_GENERIC_3K || + hw->mac_type == ICE_MAC_GENERIC_3K_E825); } /** diff --git a/drivers/net/ice/base/ice_ddp.c b/drivers/net/ice/base/ice_ddp.c index e3c1f413dd..e43aab981d 100644 --- a/drivers/net/ice/base/ice_ddp.c +++ b/drivers/net/ice/base/ice_ddp.c @@ -444,6 +444,7 @@ static u32 ice_get_pkg_segment_id(enum ice_mac_type mac_type) break; case ICE_MAC_GENERIC: case ICE_MAC_GENERIC_3K: + case ICE_MAC_GENERIC_3K_E825: default: seg_id = SEGMENT_TYPE_ICE_E810; break; @@ -467,6 +468,9 @@ static u32 ice_get_pkg_sign_type(enum ice_mac_type mac_type) case ICE_MAC_GENERIC_3K: sign_type = SEGMENT_SIGN_TYPE_RSA3K; break; + case ICE_MAC_GENERIC_3K_E825: + sign_type = SEGMENT_SIGN_TYPE_RSA3K_E825; + break; case ICE_MAC_GENERIC: default: sign_type = SEGMENT_SIGN_TYPE_RSA2K; @@ -1632,8 +1636,10 @@ ice_get_sw_fv_list(struct ice_hw *hw, struct ice_prot_lkup_ext *lkups, } } } while (fv); - if (LIST_EMPTY(fv_list)) + if (LIST_EMPTY(fv_list)) { + ice_warn(hw, "Required profiles not found in currently loaded DDP package"); return ICE_ERR_CFG; + } return ICE_SUCCESS; err: diff --git a/drivers/net/ice/base/ice_ddp.h b/drivers/net/ice/base/ice_ddp.h index 57b39c72ca..6c87f11972 100644 --- a/drivers/net/ice/base/ice_ddp.h +++ b/drivers/net/ice/base/ice_ddp.h @@ -99,6 +99,7 @@ struct ice_pkg_hdr { #define SEGMENT_SIGN_TYPE_RSA2K 0x00000001 #define SEGMENT_SIGN_TYPE_RSA3K 0x00000002 #define SEGMENT_SIGN_TYPE_RSA3K_SBB 0x00000003 /* Secure Boot Block */ +#define SEGMENT_SIGN_TYPE_RSA3K_E825 0x00000005 /* generic segment */ struct ice_generic_seg_hdr { diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 9ea915b967..0e0a20542b 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -76,13 +76,10 @@ /* Intel(R) Ethernet Connection E825-C for backplane */ #define ICE_DEV_ID_E825C_BACKPLANE 0x579C /* Intel(R) Ethernet Connection E825-C for QSFP */ -#define ICE_DEV_ID_E825C_QSFP 0x579D +#define ICE_DEV_ID_E825C_QSFP 0x579D /* Intel(R) Ethernet Connection E825-C for SFP */ -#define ICE_DEV_ID_E825C_SFP 0x579E +#define ICE_DEV_ID_E825C_SFP 0x579E /* Intel(R) Ethernet Connection E825-C 1GbE */ -#define ICE_DEV_ID_E825C_1GBE 0x579F -/* Intel(R) Ethernet Connection E825-X */ -#define ICE_DEV_ID_E825X 0x0DCD - - +#define ICE_DEV_ID_E825C_SGMII 0x579F +#define ICE_DEV_ID_C825X 0x0DCD #endif /* _ICE_DEVIDS_H_ */ diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index d072b0bfe2..9651720470 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -225,6 +225,7 @@ enum ice_mac_type { ICE_MAC_E830, ICE_MAC_GENERIC, ICE_MAC_GENERIC_3K, + ICE_MAC_GENERIC_3K_E825, }; /* Media Types */ diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index a5bf8317a7..2a4073c4d1 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -196,8 +196,7 @@ static const struct rte_pci_id pci_id_ice_map[] = { { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_BACKPLANE) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_QSFP) }, { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_SFP) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825C_1GBE) }, - { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E825X) }, + { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_C825X) }, { .vendor_id = 0, /* sentinel */ }, }; From patchwork Thu Apr 27 06:19:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126585 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A8B6842A08; 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a="375324352" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324352" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845833" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845833" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:15 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang Subject: [PATCH 18/30] net/ice/base: add VLAN TPID in switchdev Date: Thu, 27 Apr 2023 06:19:49 +0000 Message-Id: <20230427062001.478032-19-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_protocol_type.h | 6 +++- drivers/net/ice/base/ice_switch.c | 42 ++++++++++++++++++------ drivers/net/ice/base/ice_switch.h | 1 + 3 files changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 1d9baea624..7f5f5069b6 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -215,7 +215,7 @@ enum ice_prot_id { */ #define ICE_UDP_OF_HW 52 /* UDP Tunnels */ #define ICE_GRE_OF_HW 64 /* NVGRE */ -#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel type */ +#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel and VLAN type */ #define ICE_MDID_SIZE 2 #define ICE_TUN_FLAG_MDID 20 @@ -226,6 +226,10 @@ enum ice_prot_id { #define ICE_TUN_FLAG_VLAN_MASK 0x01 #define ICE_TUN_FLAG_FV_IND 2 +#define ICE_VLAN_FLAG_MDID 20 +#define ICE_VLAN_FLAG_MDID_OFF (ICE_MDID_SIZE * ICE_VLAN_FLAG_MDID) +#define ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK 0xD000 + #define ICE_PROTOCOL_MAX_ENTRIES 16 /* Mapping of software defined protocol ID to hardware defined protocol ID */ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 1b8311fdc7..7b3c367e94 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7502,13 +7502,14 @@ ice_create_recipe_group(struct ice_hw *hw, struct ice_sw_recipe *rm, /** * ice_tun_type_match_word - determine if tun type needs a match mask - * @tun_type: tunnel type + * @rinfo: other information regarding the rule e.g. priority and action info * @off: offset of packet flag * @mask: mask to be used for the tunnel */ -static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, u16 *mask) +static bool +ice_tun_type_match_word(struct ice_adv_rule_info *rinfo, u16 *off, u16 *mask) { - switch (tun_type) { + switch (rinfo->tun_type) { case ICE_SW_TUN_VXLAN_GPE: case ICE_SW_TUN_GENEVE: case ICE_SW_TUN_VXLAN: @@ -7526,9 +7527,14 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, return true; case ICE_SW_TUN_AND_NON_TUN: - *mask = ICE_DIR_FLAG_MASK; - *off = ICE_TUN_FLAG_MDID_OFF(0); - return true; + if (rinfo->add_dir_lkup) { + *mask = ICE_DIR_FLAG_MASK; + *off = ICE_TUN_FLAG_MDID_OFF(0); + return true; + } + *mask = 0; + *off = 0; + return false; case ICE_SW_TUN_GENEVE_VLAN: case ICE_SW_TUN_VXLAN_VLAN: @@ -7548,10 +7554,11 @@ static bool ice_tun_type_match_word(enum ice_sw_tunnel_type tun_type, u16 *off, * ice_add_special_words - Add words that are not protocols, such as metadata * @rinfo: other information regarding the rule e.g. priority and action info * @lkup_exts: lookup word structure + * @dvm_ena: is double VLAN mode enabled */ static enum ice_status ice_add_special_words(struct ice_adv_rule_info *rinfo, - struct ice_prot_lkup_ext *lkup_exts) + struct ice_prot_lkup_ext *lkup_exts, bool dvm_ena) { u16 mask; u16 off; @@ -7560,7 +7567,7 @@ ice_add_special_words(struct ice_adv_rule_info *rinfo, * tunnel bit in the packet metadata flags. If this is a tun_and_non_tun * packet, then add recipe index to match the direction bit in the flag. */ - if (ice_tun_type_match_word(rinfo->tun_type, &off, &mask)) { + if (ice_tun_type_match_word(rinfo, &off, &mask)) { if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) { u8 word = lkup_exts->n_val_words++; @@ -7572,6 +7579,19 @@ ice_add_special_words(struct ice_adv_rule_info *rinfo, } } + if (rinfo->vlan_type != 0 && dvm_ena) { + if (lkup_exts->n_val_words < ICE_MAX_CHAIN_WORDS) { + u8 word = lkup_exts->n_val_words++; + + lkup_exts->fv_words[word].prot_id = ICE_META_DATA_ID_HW; + lkup_exts->fv_words[word].off = ICE_VLAN_FLAG_MDID_OFF; + lkup_exts->field_mask[word] = + ICE_PKT_FLAGS_0_TO_15_VLAN_FLAGS_MASK; + } else { + return ICE_ERR_MAX_LIMIT; + } + } + return ICE_SUCCESS; } @@ -7898,7 +7918,7 @@ ice_add_adv_recipe(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, /* Create any special protocol/offset pairs, such as looking at tunnel * bits by extracting metadata */ - status = ice_add_special_words(rinfo, lkup_exts); + status = ice_add_special_words(rinfo, lkup_exts, ice_is_dvm_ena(hw)); if (status) goto err_free_lkup_exts; @@ -8745,6 +8765,7 @@ ice_find_adv_rule_entry(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, } if (rinfo->sw_act.flag == list_itr->rule_info.sw_act.flag && rinfo->tun_type == list_itr->rule_info.tun_type && + rinfo->vlan_type == list_itr->rule_info.vlan_type && lkups_matched) return list_itr; } @@ -9240,6 +9261,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, } else { adv_fltr->lkups = NULL; } + if (!adv_fltr->lkups && !prof_rule) { status = ICE_ERR_NO_MEMORY; goto err_ice_add_adv_rule; @@ -9410,7 +9432,7 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, /* Create any special protocol/offset pairs, such as looking at tunnel * bits by extracting metadata */ - status = ice_add_special_words(rinfo, &lkup_exts); + status = ice_add_special_words(rinfo, &lkup_exts, ice_is_dvm_ena(hw)); if (status) return status; diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index adb467eb66..366b9bb425 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -300,6 +300,7 @@ struct ice_adv_rule_info { struct ice_sw_act_ctrl sw_act; u32 priority; u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */ + u8 add_dir_lkup; u16 fltr_rule_id; u16 lg_id; u16 vlan_type; From patchwork Thu Apr 27 06:19:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126586 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E16F542A08; Thu, 27 Apr 2023 08:40:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 12DA642FC2; Thu, 27 Apr 2023 08:38:22 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 8516142FA8 for ; Thu, 27 Apr 2023 08:38:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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26 Apr 2023 23:38:16 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Jacob Keller Subject: [PATCH 19/30] net/ice/base: reduce time to read Option ROM CIVD Date: Thu, 27 Apr 2023 06:19:50 +0000 Message-Id: <20230427062001.478032-20-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Re-write ice_get_orom_civd_data to allocate memory to store the Option ROM data. Copy the entire OptionROM contents at once using ice_read_flash_module. Finally, use this memory copy to scan for the '$CIV' section. This change significantly reduces the time to read the Option ROM CIVD section from ~10 seconds down to ~1 second. This has a significant impact on the total time to complete a driver rebuild or probe. Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_nvm.c | 54 +++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 14 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index 6ab359af33..ba855533ec 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -190,12 +190,14 @@ ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data) enum ice_status ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access) { + u32 timeout = ICE_NVM_TIMEOUT; + ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); if (hw->flash.blank_nvm_mode) return ICE_SUCCESS; - return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT); + return ice_acquire_res(hw, ICE_NVM_RES_ID, access, timeout); } /** @@ -724,43 +726,67 @@ static enum ice_status ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_civd_info *civd) { - struct ice_orom_civd_info tmp; + u8 *orom_data; + enum ice_status status; u32 offset; /* The CIVD section is located in the Option ROM aligned to 512 bytes. * The first 4 bytes must contain the ASCII characters "$CIV". * A simple modulo 256 sum of all of the bytes of the structure must * equal 0. + * + * The exact location is unknown and varies between images but is + * usually somewhere in the middle of the bank. We need to scan the + * Option ROM bank to locate it. + * + * It's significantly faster to read the entire Option ROM up front + * using the maximum page size, than to read each possible location + * with a separate firmware command. */ + orom_data = (u8 *)ice_calloc(hw, hw->flash.banks.orom_size, sizeof(u8)); + if (!orom_data) + return ICE_ERR_NO_MEMORY; + + status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, 0, + orom_data, hw->flash.banks.orom_size); + if (status) { + ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM data\n"); + return status; + } + + /* Scan the memory buffer to locate the CIVD data section */ for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) { - enum ice_status status; + struct ice_orom_civd_info *tmp; u8 sum = 0, i; - status = ice_read_flash_module(hw, bank, ICE_SR_1ST_OROM_BANK_PTR, - offset, (u8 *)&tmp, sizeof(tmp)); - if (status) { - ice_debug(hw, ICE_DBG_NVM, "Unable to read Option ROM CIVD data\n"); - return status; - } + tmp = (struct ice_orom_civd_info *)&orom_data[offset]; /* Skip forward until we find a matching signature */ - if (memcmp("$CIV", tmp.signature, sizeof(tmp.signature)) != 0) + if (memcmp("$CIV", tmp->signature, sizeof(tmp->signature)) != 0) continue; + ice_debug(hw, ICE_DBG_NVM, "Found CIVD section at offset %u\n", + offset); + /* Verify that the simple checksum is zero */ - for (i = 0; i < sizeof(tmp); i++) - sum += ((u8 *)&tmp)[i]; + for (i = 0; i < sizeof(*tmp); i++) + sum += ((u8 *)tmp)[i]; if (sum) { ice_debug(hw, ICE_DBG_NVM, "Found CIVD data with invalid checksum of %u\n", sum); - return ICE_ERR_NVM; + goto err_invalid_checksum; } - *civd = tmp; + *civd = *tmp; + ice_free(hw, orom_data); return ICE_SUCCESS; } + ice_debug(hw, ICE_DBG_NVM, "Unable to locate CIVD data within the Option ROM\n"); + +err_invalid_checksum: + ice_free(hw, orom_data); return ICE_ERR_NVM; } From patchwork Thu Apr 27 06:19:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126587 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E035342A08; Thu, 27 Apr 2023 08:40:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5639342FBC; Thu, 27 Apr 2023 08:38:24 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 8C17242FBC for ; Thu, 27 Apr 2023 08:38:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577501; x=1714113501; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bZHKGgHhejGps5506e2lcpC14P7HXkck+O23Nu6oxHg=; b=CXUUxtDfbi8z/98pBPYpz/1Kg6KdluUoIQz/dUsG20dzG0EOgh1p+Lk5 tMV830ssxg9A92kCu1V1LuphxINf1H6rE7CSfJfucM6qac2v4GS7UQDoq JLULjTMP/YPPw+LdgD6ZqvF7VMi+9JL4uRiEWllk2n8NxrJldYpkuThL0 fKklyUwbtISsnXrhvEghYx1kvf3G9lRSZIO4Q9S35xtR6xq0BtYxVMnPA wAJ+ylkWqMZiFo4/AzoD2/ufPzCcgzU+t1MY2xI8mAocGhDrREqFc2dmi MWz17Ccnxyf6kwblYXR5vmepfUcUSQlYWmcMzbExu9GdI9+kvvxvTJCcN w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324367" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324367" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845847" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845847" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:18 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Wojciech Drewek Subject: [PATCH 20/30] net/ice/base: add L2TPv3 support for adv rules Date: Thu, 27 Apr 2023 06:19:51 +0000 Message-Id: <20230427062001.478032-21-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch unwraps L2TPv3 dummy packet, date structures and defines from DPDK_SUPPORT. Signed-off-by: Wojciech Drewek Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_nvm.h | 1 - drivers/net/ice/base/ice_protocol_type.h | 5 +- drivers/net/ice/base/ice_switch.c | 740 +++++++++++++++-------- 3 files changed, 495 insertions(+), 251 deletions(-) diff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h index c3e61a301f..824526e8f8 100644 --- a/drivers/net/ice/base/ice_nvm.h +++ b/drivers/net/ice/base/ice_nvm.h @@ -34,7 +34,6 @@ struct ice_orom_civd_info { u8 combo_name_len; /* Length of the unicode combo image version string, max of 32 */ __le16 combo_name[32]; /* Unicode string representing the Combo Image version */ }; - #pragma pack() #define ICE_NVM_ACCESS_MAJOR_VER 0 diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index 7f5f5069b6..1ef23c5a50 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -31,6 +31,7 @@ enum ice_protocol_type { ICE_MAC_OFOS = 0, ICE_MAC_IL, ICE_ETYPE_OL, + ICE_ETYPE_IL, ICE_VLAN_OFOS, ICE_IPV4_OFOS, ICE_IPV4_IL, @@ -195,6 +196,7 @@ enum ice_prot_id { #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 +#define ICE_ETYPE_IL_HW 10 #define ICE_VLAN_OF_HW 16 #define ICE_VLAN_OL_HW 17 #define ICE_IPV4_OFOS_HW 32 @@ -219,7 +221,8 @@ enum ice_prot_id { #define ICE_MDID_SIZE 2 #define ICE_TUN_FLAG_MDID 20 -#define ICE_TUN_FLAG_MDID_OFF(word) (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word))) +#define ICE_TUN_FLAG_MDID_OFF(word) \ + (ICE_MDID_SIZE * (ICE_TUN_FLAG_MDID + (word))) #define ICE_TUN_FLAG_MASK 0xFF #define ICE_DIR_FLAG_MASK 0x10 #define ICE_TUN_FLAG_IN_VLAN_MASK 0x80 /* VLAN inside tunneled header */ diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 7b3c367e94..c78ec448ae 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -139,6 +139,7 @@ static const struct ice_dummy_pkt_offsets dummy_udp_tun_tcp_packet_offsets[] = { { ICE_GENEVE, 42 }, { ICE_VXLAN_GPE, 42 }, { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, { ICE_IPV4_IL, 64 }, { ICE_TCP_IL, 84 }, { ICE_PROTOCOL_LAST, 0 }, @@ -229,6 +230,224 @@ static const u8 dummy_udp_tun_udp_packet[] = { 0x00, 0x08, 0x00, 0x00, }; +static const struct ice_dummy_pkt_offsets +dummy_gre_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_NVGRE, 34 }, + { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, + { ICE_IPV6_IL, 56 }, + { ICE_TCP_IL, 96 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x66, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x2F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 54 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 56 */ + 0x00, 0x08, 0x06, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 96 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x02, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const struct ice_dummy_pkt_offsets +dummy_gre_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_NVGRE, 34 }, + { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, + { ICE_IPV6_IL, 56 }, + { ICE_UDP_ILOS, 96 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_gre_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x5a, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x2F, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x80, 0x00, 0x65, 0x58, /* ICE_NVGRE 34 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 54 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 56 */ + 0x00, 0x08, 0x11, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 96 */ + 0x00, 0x08, 0x00, 0x00, +}; + +static const struct ice_dummy_pkt_offsets +dummy_udp_tun_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_VXLAN, 42 }, + { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, + { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, + { ICE_IPV6_IL, 64 }, + { ICE_TCP_IL, 104 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_udp_tun_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x6e, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x40, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */ + 0x00, 0x5a, 0x00, 0x00, + + 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 62 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */ + 0x00, 0x08, 0x06, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 104 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x02, 0x20, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static const struct ice_dummy_pkt_offsets +dummy_udp_tun_ipv6_udp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_UDP_OF, 34 }, + { ICE_VXLAN, 42 }, + { ICE_GENEVE, 42 }, + { ICE_VXLAN_GPE, 42 }, + { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, + { ICE_IPV6_IL, 64 }, + { ICE_UDP_ILOS, 104 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_udp_tun_ipv6_udp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ + + 0x45, 0x00, 0x00, 0x62, /* ICE_IPV4_OFOS 14 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x12, 0xb5, /* ICE_UDP_OF 34 */ + 0x00, 0x4e, 0x00, 0x00, + + 0x00, 0x00, 0x65, 0x58, /* ICE_VXLAN 42 */ + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x86, 0xdd, /* ICE_ETYPE_IL 62 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 64 */ + 0x00, 0x08, 0x11, 0x40, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 104 */ + 0x00, 0x08, 0x00, 0x00, +}; + /* offset info for MAC + IPv4 + UDP dummy packet */ static const struct ice_dummy_pkt_offsets dummy_udp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, @@ -1000,8 +1219,7 @@ static const u8 dummy_ipv4_gtpu_ipv6_packet[] = { 0x00, 0x00, }; -static const -struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv4_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV6_OFOS, 14 }, { ICE_UDP_OF, 54 }, @@ -1046,8 +1264,7 @@ static const u8 dummy_ipv6_gtpu_ipv4_packet[] = { 0x00, 0x00, }; -static const -struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv6_gtpu_ipv6_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV6_OFOS, 14 }, { ICE_UDP_OF, 54 }, @@ -1434,83 +1651,6 @@ static const u8 dummy_pppoe_ipv4_packet[] = { 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const -struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_tcp_packet_offsets[] = { - { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_OFOS, 12 }, - { ICE_ETYPE_OL, 16 }, - { ICE_PPPOE, 18 }, - { ICE_IPV4_OFOS, 26 }, - { ICE_TCP_IL, 46 }, - { ICE_PROTOCOL_LAST, 0 }, -}; - -static const u8 dummy_pppoe_ipv4_tcp_packet[] = { - 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ - - 0x88, 0x64, /* ICE_ETYPE_OL 16 */ - - 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ - 0x00, 0x16, - - 0x00, 0x21, /* PPP Link Layer 24 */ - - 0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 26 */ - 0x00, 0x01, 0x00, 0x00, - 0x00, 0x06, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 46 */ - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ -}; - -static const -struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_udp_packet_offsets[] = { - { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_OFOS, 12 }, - { ICE_ETYPE_OL, 16 }, - { ICE_PPPOE, 18 }, - { ICE_IPV4_OFOS, 26 }, - { ICE_UDP_ILOS, 46 }, - { ICE_PROTOCOL_LAST, 0 }, -}; - -static const u8 dummy_pppoe_ipv4_udp_packet[] = { - 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ - - 0x88, 0x64, /* ICE_ETYPE_OL 16 */ - - 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ - 0x00, 0x16, - - 0x00, 0x21, /* PPP Link Layer 24 */ - - 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 26 */ - 0x00, 0x01, 0x00, 0x00, - 0x00, 0x11, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 46 */ - 0x00, 0x08, 0x00, 0x00, - - 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ -}; - static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_VLAN_OFOS, 12 }, @@ -1548,78 +1688,45 @@ static const u8 dummy_pppoe_ipv6_packet[] = { 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const -struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_tcp_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv4_esp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_OFOS, 12 }, - { ICE_ETYPE_OL, 16 }, - { ICE_PPPOE, 18 }, - { ICE_IPV6_OFOS, 26 }, - { ICE_TCP_IL, 66 }, + { ICE_IPV4_OFOS, 14 }, + { ICE_ESP, 34 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_pppoe_ipv6_tcp_packet[] = { +static const u8 dummy_ipv4_esp_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, - 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ - - 0x88, 0x64, /* ICE_ETYPE_OL 16 */ - - 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ - 0x00, 0x2a, - - 0x00, 0x57, /* PPP Link Layer 24 */ - - 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */ - 0x00, 0x14, 0x06, 0x00, /* Next header is TCP */ - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_IL 14 */ + 0x00, 0x00, 0x40, 0x00, + 0x40, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 66 */ - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* ICE_ESP 34 */ 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const -struct ice_dummy_pkt_offsets dummy_pppoe_packet_ipv6_udp_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv6_esp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_OFOS, 12 }, - { ICE_ETYPE_OL, 16 }, - { ICE_PPPOE, 18 }, - { ICE_IPV6_OFOS, 26 }, - { ICE_UDP_ILOS, 66 }, + { ICE_IPV6_OFOS, 14 }, + { ICE_ESP, 54 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_pppoe_ipv6_udp_packet[] = { +static const u8 dummy_ipv6_esp_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x86, 0xDD, - 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ - - 0x88, 0x64, /* ICE_ETYPE_OL 16 */ - - 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ - 0x00, 0x2a, - - 0x00, 0x57, /* PPP Link Layer 24 */ - - 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */ - 0x00, 0x08, 0x11, 0x00, /* Next header UDP*/ + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */ + 0x00, 0x08, 0x32, 0x00, /* Next header ESP */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1629,51 +1736,51 @@ static const u8 dummy_pppoe_ipv6_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 66 */ - 0x00, 0x08, 0x00, 0x00, - + 0x00, 0x00, 0x00, 0x00, /* ICE_ESP 54 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv4_esp_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv4_ah_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV4_OFOS, 14 }, - { ICE_ESP, 34 }, + { ICE_AH, 34 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_ipv4_esp_pkt[] = { +static const u8 dummy_ipv4_ah_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, - 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_IL 14 */ + 0x45, 0x00, 0x00, 0x20, /* ICE_IPV4_IL 14 */ 0x00, 0x00, 0x40, 0x00, - 0x40, 0x32, 0x00, 0x00, + 0x40, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* ICE_ESP 34 */ + 0x00, 0x00, 0x00, 0x00, /* ICE_AH 34 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv6_esp_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv6_ah_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV6_OFOS, 14 }, - { ICE_ESP, 54 }, + { ICE_AH, 54 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_ipv6_esp_pkt[] = { +static const u8 dummy_ipv6_ah_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */ - 0x00, 0x08, 0x32, 0x00, /* Next header ESP */ + 0x00, 0x0c, 0x33, 0x00, /* Next header AH */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1683,51 +1790,56 @@ static const u8 dummy_ipv6_esp_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* ICE_ESP 54 */ + 0x00, 0x00, 0x00, 0x00, /* ICE_AH 54 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv4_ah_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv4_nat_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV4_OFOS, 14 }, - { ICE_AH, 34 }, + { ICE_UDP_ILOS, 34 }, + { ICE_NAT_T, 42 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_ipv4_ah_pkt[] = { +static const u8 dummy_ipv4_nat_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, - 0x45, 0x00, 0x00, 0x20, /* ICE_IPV4_IL 14 */ + 0x45, 0x00, 0x00, 0x24, /* ICE_IPV4_IL 14 */ 0x00, 0x00, 0x40, 0x00, - 0x40, 0x33, 0x00, 0x00, + 0x40, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* ICE_AH 34 */ + 0x00, 0x00, 0x11, 0x94, /* ICE_NAT_T 34 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv6_ah_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_ipv6_nat_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, { ICE_IPV6_OFOS, 14 }, - { ICE_AH, 54 }, + { ICE_UDP_ILOS, 54 }, + { ICE_NAT_T, 62 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_ipv6_ah_pkt[] = { +static const u8 dummy_ipv6_nat_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0xDD, 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */ - 0x00, 0x0c, 0x33, 0x00, /* Next header AH */ + 0x00, 0x10, 0x11, 0x00, /* Next header NAT_T */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1737,57 +1849,85 @@ static const u8 dummy_ipv6_ah_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, /* ICE_AH 54 */ + 0x00, 0x00, 0x11, 0x94, /* ICE_NAT_T 54 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ + }; -static const struct ice_dummy_pkt_offsets dummy_ipv4_nat_packet_offsets[] = { +static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_IPV4_OFOS, 14 }, - { ICE_UDP_ILOS, 34 }, - { ICE_NAT_T, 42 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_PPPOE, 22 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const +struct ice_dummy_pkt_offsets dummy_qinq_pppoe_ipv4_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_PPPOE, 22 }, + { ICE_IPV4_OFOS, 30 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_ipv4_nat_pkt[] = { +static const u8 dummy_qinq_pppoe_ipv4_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, - 0x45, 0x00, 0x00, 0x24, /* ICE_IPV4_IL 14 */ - 0x00, 0x00, 0x40, 0x00, - 0x40, 0x11, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ + 0x88, 0x64, /* ICE_ETYPE_OL 20 */ - 0x00, 0x00, 0x11, 0x94, /* ICE_NAT_T 34 */ - 0x00, 0x00, 0x00, 0x00, + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */ + 0x00, 0x16, + + 0x00, 0x21, /* PPP Link Layer 28 */ + 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 byte alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_ipv6_nat_packet_offsets[] = { +static const +struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_ipv6_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_IPV6_OFOS, 14 }, - { ICE_UDP_ILOS, 54 }, - { ICE_NAT_T, 62 }, + { ICE_VLAN_EX, 12 }, + { ICE_VLAN_IN, 16 }, + { ICE_ETYPE_OL, 20 }, + { ICE_PPPOE, 22 }, + { ICE_IPV6_OFOS, 30 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_ipv6_nat_pkt[] = { +static const u8 dummy_qinq_pppoe_ipv6_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x86, 0xDD, - 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */ - 0x00, 0x10, 0x11, 0x00, /* Next header NAT_T */ - 0x00, 0x00, 0x00, 0x00, + 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ + 0x88, 0x64, /* ICE_ETYPE_OL 20 */ + + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */ + 0x00, 0x2a, + + 0x00, 0x57, /* PPP Link Layer 28*/ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 30 */ + 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1795,18 +1935,14 @@ static const u8 dummy_ipv6_nat_pkt[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - - 0x00, 0x00, 0x11, 0x94, /* ICE_NAT_T 54 */ 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ - }; static const struct ice_dummy_pkt_offsets dummy_ipv4_l2tpv3_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, { ICE_IPV4_OFOS, 14 }, { ICE_L2TPV3, 34 }, { ICE_PROTOCOL_LAST, 0 }, @@ -1816,7 +1952,8 @@ static const u8 dummy_ipv4_l2tpv3_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_OL 12 */ 0x45, 0x00, 0x00, 0x20, /* ICE_IPV4_IL 14 */ 0x00, 0x00, 0x40, 0x00, @@ -1832,6 +1969,7 @@ static const u8 dummy_ipv4_l2tpv3_pkt[] = { static const struct ice_dummy_pkt_offsets dummy_ipv6_l2tpv3_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, { ICE_IPV6_OFOS, 14 }, { ICE_L2TPV3, 54 }, { ICE_PROTOCOL_LAST, 0 }, @@ -1841,7 +1979,8 @@ static const u8 dummy_ipv6_l2tpv3_pkt[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x86, 0xDD, + + 0x86, 0xDD, /* ICE_ETYPE_OL 12 */ 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_IL 14 */ 0x00, 0x0c, 0x73, 0x40, @@ -1860,76 +1999,155 @@ static const u8 dummy_ipv6_l2tpv3_pkt[] = { 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; -static const struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_offsets[] = { +static const +struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_tcp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_EX, 12 }, - { ICE_VLAN_IN, 16 }, - { ICE_ETYPE_OL, 20 }, - { ICE_PPPOE, 22 }, + { ICE_VLAN_OFOS, 12 }, + { ICE_ETYPE_OL, 16 }, + { ICE_PPPOE, 18 }, + { ICE_IPV4_OFOS, 26 }, + { ICE_TCP_IL, 46 }, { ICE_PROTOCOL_LAST, 0 }, }; +static const u8 dummy_pppoe_ipv4_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ + + 0x88, 0x64, /* ICE_ETYPE_OL 16 */ + + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ + 0x00, 0x16, + + 0x00, 0x21, /* PPP Link Layer 24 */ + + 0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_OFOS 26 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x06, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 46 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ +}; + static const -struct ice_dummy_pkt_offsets dummy_qinq_pppoe_ipv4_packet_offsets[] = { +struct ice_dummy_pkt_offsets dummy_pppoe_ipv4_udp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_EX, 12 }, - { ICE_VLAN_IN, 16 }, - { ICE_ETYPE_OL, 20 }, - { ICE_PPPOE, 22 }, - { ICE_IPV4_OFOS, 30 }, + { ICE_VLAN_OFOS, 12 }, + { ICE_ETYPE_OL, 16 }, + { ICE_PPPOE, 18 }, + { ICE_IPV4_OFOS, 26 }, + { ICE_UDP_ILOS, 46 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_qinq_pppoe_ipv4_pkt[] = { +static const u8 dummy_pppoe_ipv4_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ - 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ - 0x88, 0x64, /* ICE_ETYPE_OL 20 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ - 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */ + 0x88, 0x64, /* ICE_ETYPE_OL 16 */ + + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ 0x00, 0x16, - 0x00, 0x21, /* PPP Link Layer 28 */ + 0x00, 0x21, /* PPP Link Layer 24 */ - 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 30 */ + 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_OFOS 26 */ + 0x00, 0x01, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 46 */ + 0x00, 0x08, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ +}; + +static const +struct ice_dummy_pkt_offsets dummy_pppoe_ipv6_tcp_packet_offsets[] = { + { ICE_MAC_OFOS, 0 }, + { ICE_VLAN_OFOS, 12 }, + { ICE_ETYPE_OL, 16 }, + { ICE_PPPOE, 18 }, + { ICE_IPV6_OFOS, 26 }, + { ICE_TCP_IL, 66 }, + { ICE_PROTOCOL_LAST, 0 }, +}; + +static const u8 dummy_pppoe_ipv6_tcp_packet[] = { + 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, /* 2 bytes for 4 byte alignment */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ + + 0x88, 0x64, /* ICE_ETYPE_OL 16 */ + + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ + 0x00, 0x2a, + + 0x00, 0x57, /* PPP Link Layer 24 */ + + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */ + 0x00, 0x14, 0x06, 0x00, /* Next header is TCP */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, 0x00, 0x00, /* ICE_TCP_IL 66 */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + + 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; static const -struct ice_dummy_pkt_offsets dummy_qinq_pppoe_packet_ipv6_offsets[] = { +struct ice_dummy_pkt_offsets dummy_pppoe_ipv6_udp_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, - { ICE_VLAN_EX, 12 }, - { ICE_VLAN_IN, 16 }, - { ICE_ETYPE_OL, 20 }, - { ICE_PPPOE, 22 }, - { ICE_IPV6_OFOS, 30 }, + { ICE_VLAN_OFOS, 12 }, + { ICE_ETYPE_OL, 16 }, + { ICE_PPPOE, 18 }, + { ICE_IPV6_OFOS, 26 }, + { ICE_UDP_ILOS, 66 }, { ICE_PROTOCOL_LAST, 0 }, }; -static const u8 dummy_qinq_pppoe_ipv6_packet[] = { +static const u8 dummy_pppoe_ipv6_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */ - 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */ - 0x88, 0x64, /* ICE_ETYPE_OL 20 */ + 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_OFOS 12 */ - 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 22 */ + 0x88, 0x64, /* ICE_ETYPE_OL 16 */ + + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ 0x00, 0x2a, - 0x00, 0x57, /* PPP Link Layer 28*/ + 0x00, 0x57, /* PPP Link Layer 24 */ - 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 30 */ - 0x00, 0x00, 0x3b, 0x00, + 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 26 */ + 0x00, 0x08, 0x11, 0x00, /* Next header UDP*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1939,6 +2157,9 @@ static const u8 dummy_qinq_pppoe_ipv6_packet[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, /* ICE_UDP_ILOS 66 */ + 0x00, 0x08, 0x00, 0x00, + 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; @@ -8060,6 +8281,7 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, const struct ice_dummy_pkt_offsets **offsets) { bool tcp = false, udp = false, outer_ipv6 = false, vlan = false; + bool inner_ipv6 = false, pppoe = false; bool cvlan = false; bool gre = false, mpls = false; u16 i; @@ -8389,42 +8611,14 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, if (tun_type == ICE_SW_TUN_PPPOE_IPV6_TCP) { *pkt = dummy_pppoe_ipv6_tcp_packet; *pkt_len = sizeof(dummy_pppoe_ipv6_tcp_packet); - *offsets = dummy_pppoe_packet_ipv6_tcp_offsets; + *offsets = dummy_pppoe_ipv6_tcp_packet_offsets; return; } if (tun_type == ICE_SW_TUN_PPPOE_IPV6_UDP) { *pkt = dummy_pppoe_ipv6_udp_packet; *pkt_len = sizeof(dummy_pppoe_ipv6_udp_packet); - *offsets = dummy_pppoe_packet_ipv6_udp_offsets; - return; - } - - if (tun_type == ICE_SW_IPV4_TCP) { - *pkt = dummy_tcp_packet; - *pkt_len = sizeof(dummy_tcp_packet); - *offsets = dummy_tcp_packet_offsets; - return; - } - - if (tun_type == ICE_SW_IPV4_UDP) { - *pkt = dummy_udp_packet; - *pkt_len = sizeof(dummy_udp_packet); - *offsets = dummy_udp_packet_offsets; - return; - } - - if (tun_type == ICE_SW_IPV6_TCP) { - *pkt = dummy_tcp_ipv6_packet; - *pkt_len = sizeof(dummy_tcp_ipv6_packet); - *offsets = dummy_tcp_ipv6_packet_offsets; - return; - } - - if (tun_type == ICE_SW_IPV6_UDP) { - *pkt = dummy_udp_ipv6_packet; - *pkt_len = sizeof(dummy_udp_ipv6_packet); - *offsets = dummy_udp_ipv6_packet_offsets; + *offsets = dummy_pppoe_ipv6_udp_packet_offsets; return; } @@ -8436,6 +8630,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } if (tun_type == ICE_SW_TUN_NVGRE || gre) { + if (tcp && inner_ipv6) { + *pkt = dummy_gre_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_gre_ipv6_tcp_packet); + *offsets = dummy_gre_ipv6_tcp_packet_offsets; + return; + } + if (tcp) { *pkt = dummy_gre_tcp_packet; *pkt_len = sizeof(dummy_gre_tcp_packet); @@ -8443,6 +8644,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (inner_ipv6) { + *pkt = dummy_gre_ipv6_udp_packet; + *pkt_len = sizeof(dummy_gre_ipv6_udp_packet); + *offsets = dummy_gre_ipv6_udp_packet_offsets; + return; + } + *pkt = dummy_gre_udp_packet; *pkt_len = sizeof(dummy_gre_udp_packet); *offsets = dummy_gre_udp_packet_offsets; @@ -8453,6 +8661,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, tun_type == ICE_SW_TUN_VXLAN_GPE || tun_type == ICE_SW_TUN_UDP || tun_type == ICE_SW_TUN_GENEVE_VLAN || tun_type == ICE_SW_TUN_VXLAN_VLAN) { + if (tcp && inner_ipv6) { + *pkt = dummy_udp_tun_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_udp_tun_ipv6_tcp_packet); + *offsets = dummy_udp_tun_ipv6_tcp_packet_offsets; + return; + } + if (tcp) { *pkt = dummy_udp_tun_tcp_packet; *pkt_len = sizeof(dummy_udp_tun_tcp_packet); @@ -8460,6 +8675,13 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, return; } + if (inner_ipv6) { + *pkt = dummy_udp_tun_ipv6_udp_packet; + *pkt_len = sizeof(dummy_udp_tun_ipv6_udp_packet); + *offsets = dummy_udp_tun_ipv6_udp_packet_offsets; + return; + } + *pkt = dummy_udp_tun_udp_packet; *pkt_len = sizeof(dummy_udp_tun_udp_packet); *offsets = dummy_udp_tun_udp_packet_offsets; @@ -8472,6 +8694,11 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt_len = sizeof(dummy_vlan_udp_packet); *offsets = dummy_vlan_udp_packet_offsets; return; + } else if (pppoe) { + *pkt = dummy_pppoe_ipv4_udp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv4_udp_packet); + *offsets = dummy_pppoe_ipv4_udp_packet_offsets; + return; } *pkt = dummy_udp_packet; *pkt_len = sizeof(dummy_udp_packet); @@ -8483,6 +8710,11 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt_len = sizeof(dummy_vlan_udp_ipv6_packet); *offsets = dummy_vlan_udp_ipv6_packet_offsets; return; + } else if (pppoe) { + *pkt = dummy_pppoe_ipv6_udp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv6_udp_packet); + *offsets = dummy_pppoe_ipv6_udp_packet_offsets; + return; } *pkt = dummy_udp_ipv6_packet; *pkt_len = sizeof(dummy_udp_ipv6_packet); @@ -8494,6 +8726,11 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt_len = sizeof(dummy_vlan_tcp_ipv6_packet); *offsets = dummy_vlan_tcp_ipv6_packet_offsets; return; + } else if (pppoe) { + *pkt = dummy_pppoe_ipv6_tcp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv6_tcp_packet); + *offsets = dummy_pppoe_ipv6_tcp_packet_offsets; + return; } *pkt = dummy_tcp_ipv6_packet; *pkt_len = sizeof(dummy_tcp_ipv6_packet); @@ -8505,7 +8742,12 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, *pkt = dummy_vlan_tcp_packet; *pkt_len = sizeof(dummy_vlan_tcp_packet); *offsets = dummy_vlan_tcp_packet_offsets; - } else if (mpls) { + } else if (pppoe) { + *pkt = dummy_pppoe_ipv4_tcp_packet; + *pkt_len = sizeof(dummy_pppoe_ipv4_tcp_packet); + *offsets = dummy_pppoe_ipv4_tcp_packet_offsets; + return; + } else if (mpls) { *pkt = dummy_mpls_packet; *pkt_len = sizeof(dummy_mpls_packet); *offsets = dummy_mpls_packet_offsets; From patchwork Thu Apr 27 06:19:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126588 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3232942A08; 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a="375324374" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324374" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845855" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845855" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:20 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Karol Kolacinski Subject: [PATCH 21/30] net/ice/base: add PHY OFFSET READY register clear Date: Thu, 27 Apr 2023 06:19:52 +0000 Message-Id: <20230427062001.478032-22-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a possibility to mark all transmitted/received timestamps as invalid by clearing PHY OFFSET_READY registers. Signed-off-by: Karol Kolacinski Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 4 + drivers/net/ice/base/ice_ptp_hw.c | 126 ++++++++------------------ drivers/net/ice/base/ice_ptp_hw.h | 1 + 3 files changed, 43 insertions(+), 88 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index cd4a6ffddf..c51054ecc1 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2897,6 +2897,10 @@ enum ice_aqc_driver_params { ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0, /* OS clock index for PTP timer Domain 1 */ ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1, + /* Request ID to recalibrate PHC logic */ + ICE_AQC_DRIVER_PARAM_PHC_RECALC, + /* Indicates that PTP clock controller failed */ + ICE_AQC_DRIVER_PARAM_PTP_CC_FAILED, /* Add new parameters above */ ICE_AQC_DRIVER_PARAM_MAX = 16, diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index a638bb114c..f27131efcc 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2027,47 +2027,6 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) return ICE_SUCCESS; } -/** - * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode - * @hw: pointer to the HW struct - * @port: the PHY port to configure - * - * Calculate and program the fixed Tx offset, and indicate that the offset is - * ready. This can be used when operating in bypass mode. - */ -static enum ice_status -ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) -{ - enum ice_ptp_link_spd link_spd; - enum ice_ptp_fec_mode fec_mode; - enum ice_status status; - u64 total_offset; - - status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); - if (status) - return status; - - total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); - - /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L - * register, then indicate that the Tx offset is ready. After this, - * timestamps will be enabled. - * - * Note that this skips including the more precise offsets generated - * by the Vernier calibration. - */ - status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, - total_offset); - if (status) - return status; - - status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); - if (status) - return status; - - return ICE_SUCCESS; -} - /** * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx * @hw: pointer to the HW struct @@ -2348,43 +2307,33 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) return ICE_SUCCESS; } + /** - * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode + * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers * @hw: pointer to the HW struct - * @port: the PHY port to configure * - * Calculate and program the fixed Rx offset, and indicate that the offset is - * ready. This can be used when operating in bypass mode. + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. */ -static enum ice_status -ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) +static enum ice_status ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) { - enum ice_ptp_link_spd link_spd; - enum ice_ptp_fec_mode fec_mode; - enum ice_status status; - u64 total_offset; - - status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); - if (status) - return status; + u8 port; - total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); + for (port = 0; port < hw->phy_ports; port++) { + enum ice_status status; - /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L - * register, then indicate that the Rx offset is ready. After this, - * timestamps will be enabled. - * - * Note that this skips including the more precise offsets generated - * by Vernier calibration. - */ - status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, - total_offset); - if (status) - return status; + status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); + if (status) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return status; + } - status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); - if (status) - return status; + status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); + if (status) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return status; + } + } return ICE_SUCCESS; } @@ -2666,24 +2615,6 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) if (status) return status; - if (bypass) { - val |= P_REG_PS_BYPASS_MODE_M; - /* Enter BYPASS mode, enabling timestamps immediately. */ - status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (status) - return status; - - /* Program the fixed Tx offset */ - status = ice_phy_cfg_fixed_tx_offset_e822(hw, port); - if (status) - return status; - - /* Program the fixed Rx offset */ - status = ice_phy_cfg_fixed_rx_offset_e822(hw, port); - if (status) - return status; - } - ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); return ICE_SUCCESS; @@ -3841,6 +3772,25 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true); } +/** + * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw) +{ + switch (hw->phy_model) { + case ICE_PHY_E810: + return ICE_SUCCESS; + case ICE_PHY_E822: + return ice_ptp_clear_phy_offset_ready_e822(hw); + default: + return ICE_ERR_NOT_SUPPORTED; + } +} + /** * ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index e25018a68f..f4d64ea02b 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -151,6 +151,7 @@ enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval, enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); enum ice_status ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); +enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw); enum ice_status ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); enum ice_status From patchwork Thu Apr 27 06:19:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126589 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D005542A08; 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a="375324381" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324381" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845863" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845863" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:22 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Karol Kolacinski Subject: [PATCH 22/30] net/ice/base: return CGU PLL config function params Date: Thu, 27 Apr 2023 06:19:53 +0000 Message-Id: <20230427062001.478032-23-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Change params in ice_cfg_cgu_pll_e822 to pointers to return real values of frequency and clock source. Remove static from frequency and clock source conversion functions. Signed-off-by: Karol Kolacinski Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 39 ++++++++++++++++++------------- drivers/net/ice/base/ice_ptp_hw.h | 4 ++-- 2 files changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index f27131efcc..cc6c1f3152 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -218,8 +218,8 @@ static const char *ice_clk_src_str(u8 clk_src) * time reference, enabling the PLL which drives the PTP hardware clock. */ enum ice_status -ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, - enum ice_clk_src clk_src) +ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, + enum ice_clk_src *clk_src) { union tspll_ro_bwm_lf bwm_lf; union nac_cgu_dword19 dw19; @@ -228,18 +228,18 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, union nac_cgu_dword9 dw9; enum ice_status status; - if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { - ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq); + if (*clk_freq >= NUM_ICE_TIME_REF_FREQ) { + ice_warn(hw, "Invalid TIME_REF frequency %u\n", *clk_freq); return ICE_ERR_PARAM; } - if (clk_src >= NUM_ICE_CLK_SRC) { - ice_warn(hw, "Invalid clock source %u\n", clk_src); + if (*clk_src >= NUM_ICE_CLK_SRC) { + ice_warn(hw, "Invalid clock source %u\n", *clk_src); return ICE_ERR_PARAM; } - if (clk_src == ICE_CLK_SRC_TCX0 && - clk_freq != ICE_TIME_REF_FREQ_25_000) { + if (*clk_src == ICE_CLK_SRC_TCX0 && + *clk_freq != ICE_TIME_REF_FREQ_25_000) { ice_warn(hw, "TCX0 only supports 25 MHz frequency\n"); return ICE_ERR_PARAM; } @@ -273,7 +273,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, } /* Set the frequency */ - dw9.field.time_ref_freq_sel = clk_freq; + dw9.field.time_ref_freq_sel = *clk_freq; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val); if (status) return status; @@ -283,7 +283,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, if (status) return status; - dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; + dw19.field.tspll_fbdiv_intgr = e822_cgu_params[*clk_freq].feedback_div; dw19.field.tspll_ndivratio = 1; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val); @@ -295,7 +295,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, if (status) return status; - dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; + dw22.field.time1588clk_div = e822_cgu_params[*clk_freq].post_pll_div; dw22.field.time1588clk_sel_div2 = 0; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val); @@ -307,9 +307,9 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, if (status) return status; - dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; - dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; - dw24.field.time_ref_sel = clk_src; + dw24.field.ref1588_ck_div = e822_cgu_params[*clk_freq].refclk_pre_div; + dw24.field.tspll_fbdiv_frac = e822_cgu_params[*clk_freq].frac_n_div; + dw24.field.time_ref_sel = *clk_src; status = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); if (status) @@ -341,6 +341,9 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, ice_clk_freq_str(dw9.field.time_ref_freq_sel), bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); + *clk_freq = (enum ice_time_ref_freq)dw9.field.time_ref_freq_sel; + *clk_src = (enum ice_clk_src)dw24.field.time_ref_sel; + return ICE_SUCCESS; } @@ -354,6 +357,8 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw) { struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; union tspll_cntr_bist_settings cntr_bist; + enum ice_time_ref_freq time_ref_freq; + enum ice_clk_src clk_src; enum ice_status status; status = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS, @@ -373,8 +378,9 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw) /* Configure the CGU PLL using the parameters from the function * capabilities. */ - status = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref, - (enum ice_clk_src)ts_info->clk_src); + time_ref_freq = (enum ice_time_ref_freq)ts_info->time_ref; + clk_src = (enum ice_clk_src)ts_info->clk_src; + status = ice_cfg_cgu_pll_e822(hw, &time_ref_freq, &clk_src); if (status) return status; @@ -2024,6 +2030,7 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) if (status) return status; + return ICE_SUCCESS; } diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index f4d64ea02b..4d5d728e26 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -184,8 +184,8 @@ ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd, bool lock_sbq); void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad); enum ice_status -ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, - enum ice_clk_src clk_src); +ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq, + enum ice_clk_src *clk_src); /** * ice_e822_time_ref - Get the current TIME_REF from capabilities From patchwork Thu Apr 27 06:19:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126590 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85AA542A08; Thu, 27 Apr 2023 08:40:28 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2DCCC42FD8; Thu, 27 Apr 2023 08:38:28 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 878C742FDE for ; Thu, 27 Apr 2023 08:38:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577506; x=1714113506; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vZ9ro9fQXZYR2KiMMVikLsShm4W8AQDL0FQ/tzd0psU=; b=HZayea0csAvFhtCRupgYT2WsNdLVmQXTgQbXdz+WIE88Yp1wPcxnoCwA OqtngIhjrktqw335TmXGFn1pke1HTVD/aMYhTb8cxPs6pQb5eXe4wR+z8 XtC/4mRC5Rb0UXxzYoSOtxghRXuHBMskHWbZfVqjAptclF2L8hJLJTEUS wlFbcGipGS0SWG/UfpLZFYD71MMBzH0NcYoxQ52am0MEP0EvONcnwfgmn XVkPeyvy7HGJMQqE6nBmnHHCBsVt9dKv4+eF1wW5iRTDC6WvhiRGeil+U ODKQcsgJMh3G1EbDcjBw+8d4TQg/Wt/x7oGjfvSHdgxw0zUaAGEYO0MLC g==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324388" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324388" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845867" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845867" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:23 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Milena Olech Subject: [PATCH 23/30] net/ice/base: change method to get pca9575 handle Date: Thu, 27 Apr 2023 06:19:54 +0000 Message-Id: <20230427062001.478032-24-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org More universal method for getting pca9575 handle is introduced. The first step is to look for CLK_MUX handle. Having that it is possible to find CLK_MUX GPIO pin. Provided data let check what is driving the pin - the expectation is that pca9575 node part number is returned. Signed-off-by: Milena Olech Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 12 ++- drivers/net/ice/base/ice_ptp_hw.c | 125 ++++++++++++++++++++++---- 2 files changed, 120 insertions(+), 17 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index c51054ecc1..29b123d900 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1723,6 +1723,8 @@ struct ice_aqc_link_topo_params { #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 +#define ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX 10 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS 11 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ @@ -1760,8 +1762,13 @@ struct ice_aqc_link_topo_addr { struct ice_aqc_get_link_topo { struct ice_aqc_link_topo_addr addr; u8 node_part_num; -#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 -#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_SI5383_5384 0x25 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_E822_PHY 0x30 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_C827 0x31 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 u8 rsvd[9]; }; @@ -1789,6 +1796,7 @@ struct ice_aqc_get_link_topo_pin { #define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12 #define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13 #define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14 +#define ICE_AQC_LINK_TOPO_IO_FUNC_CLK_IN 20 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \ (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index cc6c1f3152..29840b2b91 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1962,14 +1962,19 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) * adjust Tx timestamps by. This is calculated by combining some known static * latency along with the Vernier offset computations done by hardware. * - * This function must be called only after the offset registers are valid, - * i.e. after the Vernier calibration wait has passed, to ensure that the PHY - * has measured the offset. + * This function will not return successfully until the Tx offset calculations + * have been completed, which requires waiting until at least one packet has + * been transmitted by the device. It is safe to call this function + * periodically until calibration succeeds, as it will only program the offset + * once. * * To avoid overflow, when calculating the offset based on the known static * latency values, we use measurements in 1/100th of a nanosecond, and divide * the TUs per second up front. This avoids overflow while allowing * calculation of the adjustment using integer arithmetic. + * + * Returns zero on success, ICE_ERR_NOT_READY if the hardware vernier offset + * calibration has not completed, or another error code on failure. */ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) { @@ -1977,6 +1982,28 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) enum ice_ptp_fec_mode fec_mode; enum ice_status status; u64 total_offset, val; + u32 reg; + + /* Nothing to do if we've already programmed the offset */ + status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OR, ®); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, status %d\n", + port, status); + return status; + } + + if (reg) + return ICE_SUCCESS; + + status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, ®); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, status %d\n", + port, status); + return status; + } + + if (!(reg & P_REG_TX_OV_STATUS_OV_M)) + return ICE_ERR_NOT_READY; status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); if (status) @@ -2030,6 +2057,7 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) if (status) return status; + ice_info(hw, "Port=%d Tx vernier offset calibration complete\n", port); return ICE_SUCCESS; } @@ -2236,6 +2264,11 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) * measurements taken in hardware with some data about known fixed delay as * well as adjusting for multi-lane alignment delay. * + * This function will not return successfully until the Rx offset calculations + * have been completed, which requires waiting until at least one packet has + * been received by the device. It is safe to call this function periodically + * until calibration succeeds, as it will only program the offset once. + * * This function must be called only after the offset registers are valid, * i.e. after the Vernier calibration wait has passed, to ensure that the PHY * has measured the offset. @@ -2244,6 +2277,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) * latency values, we use measurements in 1/100th of a nanosecond, and divide * the TUs per second up front. This avoids overflow while allowing * calculation of the adjustment using integer arithmetic. + * + * Returns zero on success, ICE_ERR_NOT_READY if the hardware vernier offset + * calibration has not completed, or another error code on failure. */ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) { @@ -2251,6 +2287,28 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) enum ice_ptp_fec_mode fec_mode; u64 total_offset, pmd, val; enum ice_status status; + u32 reg; + + /* Nothing to do if we've already programmed the offset */ + status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OR, ®); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, status %d\n", + port, status); + return status; + } + + if (reg) + return ICE_SUCCESS; + + status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, ®); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, status %d\n", + port, status); + return status; + } + + if (!(reg & P_REG_RX_OV_STATUS_OV_M)) + return ICE_ERR_NOT_READY; status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); if (status) @@ -2311,10 +2369,11 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) if (status) return status; + ice_info(hw, "Port=%d Rx vernier offset calibration complete\n", port); + return ICE_SUCCESS; } - /** * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers * @hw: pointer to the HW struct @@ -2424,7 +2483,8 @@ static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port) return ICE_ERR_NOT_READY; } - status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); + status = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, + &phc_time); if (status) goto err_unlock; @@ -3175,17 +3235,18 @@ ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) * @hw: pointer to the hw struct * @pca9575_handle: GPIO controller's handle * - * Find and return the GPIO controller's handle in the netlist. - * When found - the value will be cached in the hw structure and following calls - * will return cached value + * Find and return the GPIO controller's handle by checking what drives clock + * mux pin. When found - the value will be cached in the hw structure and + * following calls will return cached value. */ static enum ice_status ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) { + u8 node_part_number, idx, node_type_ctx_clk_mux, node_part_num_clk_mux; + struct ice_aqc_get_link_topo_pin cmd_pin; + u16 node_handle, clock_mux_handle; struct ice_aqc_get_link_topo cmd; - u8 node_part_number, idx; enum ice_status status; - u16 node_handle; if (!hw || !pca9575_handle) return ICE_ERR_PARAM; @@ -3197,11 +3258,46 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) } memset(&cmd, 0, sizeof(cmd)); + memset(&cmd_pin, 0, sizeof(cmd_pin)); + + node_type_ctx_clk_mux = (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + node_type_ctx_clk_mux |= (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + node_part_num_clk_mux = ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX; - /* Set node type to GPIO controller */ + /* Look for CLOCK MUX handle in the netlist */ + status = ice_find_netlist_node(hw, node_type_ctx_clk_mux, + node_part_num_clk_mux, + &clock_mux_handle); + if (status) + return ICE_ERR_NOT_SUPPORTED; + + /* Take CLOCK MUX GPIO pin */ + cmd_pin.input_io_params = (ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_GPIO << + ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S); + cmd_pin.input_io_params |= (ICE_AQC_LINK_TOPO_IO_FUNC_CLK_IN << + ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S); + cmd_pin.addr.handle = CPU_TO_LE16(clock_mux_handle); + cmd_pin.addr.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_TYPE_CLK_MUX << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd_pin.addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + + status = ice_aq_get_netlist_node_pin(hw, &cmd_pin, &node_handle); + if (status) + return ICE_ERR_NOT_SUPPORTED; + + /* Check what is driving the pin */ cmd.addr.topo_params.node_type_ctx = - (ICE_AQC_LINK_TOPO_NODE_TYPE_M & - ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); + (ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL << + ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd.addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + cmd.addr.handle = CPU_TO_LE16(node_handle); #define SW_PCA9575_SFP_TOPO_IDX 2 #define SW_PCA9575_QSFP_TOPO_IDX 1 @@ -3215,13 +3311,12 @@ ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) return ICE_ERR_NOT_SUPPORTED; cmd.addr.topo_params.index = idx; - status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, &node_handle); if (status) return ICE_ERR_NOT_SUPPORTED; - /* Verify if we found the right IO expander type */ + /* Verify if PCA9575 drives the pin */ if (node_part_number != ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575) return ICE_ERR_NOT_SUPPORTED; From patchwork Thu Apr 27 06:19:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126591 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 96A2242A08; Thu, 27 Apr 2023 08:40:35 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA73242FC8; Thu, 27 Apr 2023 08:38:30 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 74D5E42FEE for ; Thu, 27 Apr 2023 08:38:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577508; x=1714113508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RTWZG6CbobzfAdjJq9ogTnAwsK38yYIWdCErbBqrIYI=; b=UuRGhZ4CKVBjOf38mVpWseTfaLKeab1zxSqqfqVJO8jRchAKfuFXKSEf cPRnliVsAwAz0nylR1SAPGIjVIX6ZD6dySCw4ug6dmLwoihUTsZyzTNEJ dFLxd8lvYOTXwiJ5UYEepWAYvjrvojv+lxbQjE9GRlfZhs8uobGbTxkvl 8pd/eYJiIoGNXZqYE06k52H4GDGIcKdHbiTJtujPvNV2p1gb76Ri1Ngs+ ZqFLTH8GgeVHRtTO6P4yMmjA4CDo1YeuGnIfhRuk3zts2rVK/ZPqOvD60 wEt8dho8iiVJB48R6ePTqEIVKiDBHtS4ktrUDCHSIutOz6Vk82wdq14E0 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324391" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324391" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845872" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845872" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:25 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Karol Kolacinski , Jacob Keller Subject: [PATCH 24/30] net/ice/base: cleanup timestamp registers correct Date: Thu, 27 Apr 2023 06:19:55 +0000 Message-Id: <20230427062001.478032-25-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org E822 PHY TS registers should not be written and the only way to cleanup them is to reset QUAD memory. To ensure that the status bit for the timestamp index is cleared, ensure that ice_clear_phy_tstamp implementations first read the timestamp out. Implementations which can write the register continue to do so. Add a note to indicate this function should only be called on timestamps which have their valid bit set. Signed-off-by: Karol Kolacinski Signed-off-by: Jacob Keller Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 54 ++++++++++++++++++------------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 29840b2b91..e559d4907f 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1020,34 +1020,31 @@ ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) } /** - * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block + * ice_clear_phy_tstamp_e822 - Drop a timestamp from the quad block * @hw: pointer to the HW struct * @quad: the quad to read from * @idx: the timestamp index to reset * - * Clear a timestamp, resetting its valid bit, from the PHY quad block that is - * shared between the internal PHYs on the E822 devices. + * Read the timetamp out of the quad to clear its timestamp status bit from + * the PHY quad block that is shared between the internal PHYs of the E822 + * devices. + * + * Note that software cannot directly write the quad memory bank registers, + * and must use ice_ptp_reset_ts_memory_quad_e822 for that purpose. + * + * This function should only be called on an idx whose bit is set according to + * ice_get_phy_tx_tstamp_ready. */ static enum ice_status ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) { enum ice_status status; - u16 lo_addr, hi_addr; - - lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); - hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); - - status = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); - if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n", - status); - return status; - } + u64 unused_tstamp; - status = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); + status = ice_read_phy_tstamp_e822(hw, quad, idx, &unused_tstamp); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n", - status); + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, status %d\n", + quad, idx, status); return status; } @@ -2926,29 +2923,40 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) * @lport: the lport to read from * @idx: the timestamp index to reset * - * Clear a timestamp, resetting its valid bit, from the timestamp block of the - * external PHY on the E810 device. + * Read the timestamp and then forcibly overwrite its value to clear the valid + * bit from the timestamp block of the external PHY on the E810 device. + * + * This function should only be called on an idx whose bit is set according to + * ice_get_phy_tx_tstamp_ready. */ static enum ice_status ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) { enum ice_status status; u32 lo_addr, hi_addr; + u64 unused_tstamp; + + status = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); + if (status) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, status %d\n", + lport, idx, status); + return status; + } lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); status = ice_write_phy_reg_e810(hw, lo_addr, 0); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n", - status); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, status %d\n", + lport, idx, status); return status; } status = ice_write_phy_reg_e810(hw, hi_addr, 0); if (status) { - ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, status %d\n", - status); + ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, status %d\n", + lport, idx, status); return status; } From patchwork Thu Apr 27 06:19:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126592 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A014242A08; Thu, 27 Apr 2023 08:40:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DCDD242FFE; Thu, 27 Apr 2023 08:38:31 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 3BCDA42D5A for ; Thu, 27 Apr 2023 08:38:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577510; x=1714113510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MogW/kSypzmg5eaVecXc2DuRzVgto8D54Exq9h0wf8A=; b=aGFXWyA8PtbhyhrIFRaQyx6uPla5EOEJGqP52jDEIJTPGx0XH5wd2Riz x5pwKiYiM5i7eeXoLvMUErSkZsFDHHK7TYnrgtwVofpO08cpKQ2nAhxxF Cu3e35H2kG4ljZIfRoE6vm228CKjwS7a06nrQwe/HeTldqYWbWOU+hdip zvQqCEJXAU0AZSQEPucMvqFFc5YOTAkS+lIW9XilovOYlpX92IjsIN8du iBqQPmm7Zmk9Crm+PsAqJrtyZ749+Lry7oKCd9omHdN3p3XHNCMj4tFkM cy9vgU5D0xbu+Fy+2+yQvVA6CanVf7HIT9LyiZKepYOKck0dbeQAE0k2K w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324398" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324398" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845877" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845877" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:27 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Marcin Szycik , Lukasz Plachno Subject: [PATCH 25/30] net/ice/base: add PPPoE hardware offload Date: Thu, 27 Apr 2023 06:19:56 +0000 Message-Id: <20230427062001.478032-26-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for creating PPPoE filters in switchdev mode. Add support for parsing PPPoE and PPP-specific tc options: pppoe_sid and ppp_proto. Signed-off-by: Marcin Szycik Signed-off-by: Lukasz Plachno Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 82 ++++++++++++++++++++++++------- 1 file changed, 65 insertions(+), 17 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index c78ec448ae..37c192fb87 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7390,6 +7390,17 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles, return (u16)ice_bitmap_hweight(free_idx, ICE_MAX_FV_WORDS); } +static void ice_set_recipe_index(unsigned long idx, u8 *bitmap) +{ + u32 byte = idx / BITS_PER_BYTE; + u32 bit = idx % BITS_PER_BYTE; + + if (byte >= 8) + return; + + bitmap[byte] |= 1 << bit; +} + /** * ice_add_sw_recipe - function to call AQ calls to create switch recipe * @hw: pointer to hardware structure @@ -7517,10 +7528,10 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm, } /* fill recipe dependencies */ - ice_zero_bitmap((ice_bitmap_t *)buf[recps].recipe_bitmap, - ICE_MAX_NUM_RECIPES); - ice_set_bit(buf[recps].recipe_indx, - (ice_bitmap_t *)buf[recps].recipe_bitmap); + ice_memset(buf[recps].recipe_bitmap, 0, + sizeof(buf[recps].recipe_bitmap), ICE_NONDMA_MEM); + ice_set_recipe_index(buf[recps].recipe_indx, + buf[recps].recipe_bitmap); buf[recps].content.act_ctrl_fwd_priority = rm->priority; recps++; } @@ -8305,18 +8316,26 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, lkups[i].m_u.ethertype.ethtype_id == CPU_TO_BE16(0xFFFF)) outer_ipv6 = true; + else if (lkups[i].type == ICE_ETYPE_IL && + lkups[i].h_u.ethertype.ethtype_id == + CPU_TO_BE16(ICE_IPV6_ETHER_ID) && + lkups[i].m_u.ethertype.ethtype_id == + CPU_TO_BE16(0xFFFF)) + inner_ipv6 = true; + else if (lkups[i].type == ICE_PPPOE) { + pppoe = true; + if (lkups[i].h_u.pppoe_hdr.ppp_prot_id == + CPU_TO_BE16(ICE_PPP_IPV6_PROTO_ID) && + lkups[i].m_u.pppoe_hdr.ppp_prot_id == + CPU_TO_BE16(0xFFFF)) + outer_ipv6 = true; + } else if (lkups[i].type == ICE_IPV4_OFOS && lkups[i].h_u.ipv4_hdr.protocol == ICE_IPV4_NVGRE_PROTO_ID && lkups[i].m_u.ipv4_hdr.protocol == 0xFF) gre = true; - else if (lkups[i].type == ICE_PPPOE && - lkups[i].h_u.pppoe_hdr.ppp_prot_id == - CPU_TO_BE16(ICE_PPP_IPV6_PROTO_ID) && - lkups[i].m_u.pppoe_hdr.ppp_prot_id == - 0xFFFF) - outer_ipv6 = true; else if (lkups[i].type == ICE_IPV4_IL && lkups[i].h_u.ipv4_hdr.protocol == ICE_TCP_PROTO_ID && @@ -8373,6 +8392,34 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, } } + if (tun_type == ICE_SW_IPV4_TCP) { + *pkt = dummy_tcp_packet; + *pkt_len = sizeof(dummy_tcp_packet); + *offsets = dummy_tcp_packet_offsets; + return; + } + + if (tun_type == ICE_SW_IPV4_UDP) { + *pkt = dummy_udp_packet; + *pkt_len = sizeof(dummy_udp_packet); + *offsets = dummy_udp_packet_offsets; + return; + } + + if (tun_type == ICE_SW_IPV6_TCP) { + *pkt = dummy_tcp_ipv6_packet; + *pkt_len = sizeof(dummy_tcp_ipv6_packet); + *offsets = dummy_tcp_ipv6_packet_offsets; + return; + } + + if (tun_type == ICE_SW_IPV6_UDP) { + *pkt = dummy_udp_ipv6_packet; + *pkt_len = sizeof(dummy_udp_ipv6_packet); + *offsets = dummy_udp_ipv6_packet_offsets; + return; + } + if (tun_type == ICE_SW_TUN_PPPOE_IPV6_QINQ) { *pkt = dummy_qinq_pppoe_ipv6_packet; *pkt_len = sizeof(dummy_qinq_pppoe_ipv6_packet); @@ -8811,6 +8858,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, len = sizeof(struct ice_ether_hdr); break; case ICE_ETYPE_OL: + case ICE_ETYPE_IL: len = sizeof(struct ice_ethtype_hdr); break; case ICE_VLAN_OFOS: @@ -8843,9 +8891,6 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, len = sizeof(struct ice_udp_tnl_hdr); break; - case ICE_PPPOE: - len = sizeof(struct ice_pppoe_hdr); - break; case ICE_ESP: len = sizeof(struct ice_esp_hdr); break; @@ -8855,13 +8900,16 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt, case ICE_AH: len = sizeof(struct ice_ah_hdr); break; - case ICE_L2TPV3: - len = sizeof(struct ice_l2tpv3_sess_hdr); - break; - case ICE_GTP: case ICE_GTP_NO_PAY: + case ICE_GTP: len = sizeof(struct ice_udp_gtp_hdr); break; + case ICE_PPPOE: + len = sizeof(struct ice_pppoe_hdr); + break; + case ICE_L2TPV3: + len = sizeof(struct ice_l2tpv3_sess_hdr); + break; default: return ICE_ERR_PARAM; } From patchwork Thu Apr 27 06:19:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126593 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 688FB42A08; Thu, 27 Apr 2023 08:40:45 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 02B1542D8E; Thu, 27 Apr 2023 08:38:35 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id D407942FCA for ; Thu, 27 Apr 2023 08:38:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; 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26 Apr 2023 23:38:29 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Milena Olech Subject: [PATCH 26/30] net/ice/base: remove bypass mode Date: Thu, 27 Apr 2023 06:19:57 +0000 Message-Id: <20230427062001.478032-27-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previous implementation switches between bypass and Vernier mode dynamically. However bypass mode should be removed due to low precision. Signed-off-by: Milena Olech Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_ptp_hw.c | 46 ++++++++++++++++++++++++++----- drivers/net/ice/base/ice_ptp_hw.h | 5 ++-- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 43 insertions(+), 10 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index e559d4907f..f67e0b0c34 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -2584,20 +2584,15 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) * ice_start_phy_timer_e822 - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start - * @bypass: if true, start the PHY in bypass mode * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * - * Bypass mode enables timestamps immediately without waiting for Vernier - * calibration to complete. Hardware will still continue taking Vernier - * measurements on Tx or Rx of packets, but they will not be applied to - * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware - * has completed offset calculation. + * Hardware will take Vernier measurements on Tx or Rx of packets. */ enum ice_status -ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) +ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) { enum ice_status status; u32 lo, hi, val; @@ -2721,6 +2716,43 @@ ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) return ICE_SUCCESS; } +/** + * ice_phy_cfg_intr_e822 - Configure TX timestamp interrupt + * @hw: pointer to the HW struct + * @quad: the timestamp quad + * @ena: enable or disable interrupt + * @threshold: interrupt threshold + * + * Configure TX timestamp interrupt for the specified quad + */ + +enum ice_status +ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) +{ + enum ice_status err; + u32 val; + + err = ice_read_quad_reg_e822(hw, quad, + Q_REG_TX_MEM_GBL_CFG, + &val); + if (err) + return err; + + if (ena) { + val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; + val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) & + Q_REG_TX_MEM_GBL_CFG_INTR_THR_M); + } else { + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; + } + + err = ice_write_quad_reg_e822(hw, quad, + Q_REG_TX_MEM_GBL_CFG, + val); + + return err; +} /* E810 functions * diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 4d5d728e26..0a7c6d052c 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -237,10 +237,11 @@ void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port); enum ice_status ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); enum ice_status -ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass); +ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port); enum ice_status ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port); -enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port); +enum ice_status +ice_phy_cfg_intr_e822(struct ice_hw *hw, u8 quad, bool ena, u8 threshold); /* E810 family functions */ bool ice_is_gps_present_e810t(struct ice_hw *hw); diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 2a4073c4d1..8b41753b83 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2418,7 +2418,7 @@ ice_dev_init(struct rte_eth_dev *dev) hw->phy_model = ICE_PHY_E822; if (hw->phy_model == ICE_PHY_E822) { - ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); + ret = ice_start_phy_timer_e822(hw, hw->pf_id); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); } From patchwork Thu Apr 27 06:19:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126594 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1A4CE42A08; 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a="375324408" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324408" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845884" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845884" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:30 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Martyna Szapar-Mudlaw Subject: [PATCH 27/30] net/ice/base: support inner etype in switchdev Date: Thu, 27 Apr 2023 06:19:58 +0000 Message-Id: <20230427062001.478032-28-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable support for adding TC rules that filter on the inner EtherType field of tunneled packet headers. Signed-off-by: Martyna Szapar-Mudlaw Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 32 ++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 37c192fb87..5061af5d79 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -49,6 +49,7 @@ static const struct ice_dummy_pkt_offsets dummy_gre_tcp_packet_offsets[] = { { ICE_IPV4_OFOS, 14 }, { ICE_NVGRE, 34 }, { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, { ICE_IPV4_IL, 56 }, { ICE_TCP_IL, 76 }, { ICE_PROTOCOL_LAST, 0 }, @@ -73,7 +74,8 @@ static const u8 dummy_gre_tcp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 54 */ 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, @@ -94,6 +96,7 @@ static const struct ice_dummy_pkt_offsets dummy_gre_udp_packet_offsets[] = { { ICE_IPV4_OFOS, 14 }, { ICE_NVGRE, 34 }, { ICE_MAC_IL, 42 }, + { ICE_ETYPE_IL, 54 }, { ICE_IPV4_IL, 56 }, { ICE_UDP_ILOS, 76 }, { ICE_PROTOCOL_LAST, 0 }, @@ -118,7 +121,8 @@ static const u8 dummy_gre_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 42 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 54 */ 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, @@ -167,7 +171,8 @@ static const u8 dummy_udp_tun_tcp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 62*/ 0x45, 0x00, 0x00, 0x28, /* ICE_IPV4_IL 64 */ 0x00, 0x01, 0x00, 0x00, @@ -191,6 +196,7 @@ static const struct ice_dummy_pkt_offsets dummy_udp_tun_udp_packet_offsets[] = { { ICE_GENEVE, 42 }, { ICE_VXLAN_GPE, 42 }, { ICE_MAC_IL, 50 }, + { ICE_ETYPE_IL, 62 }, { ICE_IPV4_IL, 64 }, { ICE_UDP_ILOS, 84 }, { ICE_PROTOCOL_LAST, 0 }, @@ -218,7 +224,8 @@ static const u8 dummy_udp_tun_udp_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_IL 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, + + 0x08, 0x00, /* ICE_ETYPE_IL 62 */ 0x45, 0x00, 0x00, 0x1c, /* ICE_IPV4_IL 64 */ 0x00, 0x01, 0x00, 0x00, @@ -2216,6 +2223,7 @@ static struct ice_prof_type_entry ice_prof_type_tbl[ICE_GTPU_PROFILE] = { /** * ice_get_tun_type_for_recipe - get tunnel type for the recipe * @rid: recipe ID that we are populating + * @vlan: flag of vlan protocol */ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan) { @@ -2224,7 +2232,8 @@ static enum ice_sw_tunnel_type ice_get_tun_type_for_recipe(u8 rid, bool vlan) u8 pppoe_profile[7] = {34, 35, 36, 37, 38, 39, 40}; u8 non_tun_profile[6] = {4, 5, 6, 7, 8, 9}; enum ice_sw_tunnel_type tun_type; - u16 i, j, k, profile_num = 0; + u16 i, j, profile_num = 0; + u16 k; bool non_tun_valid = false; bool pppoe_valid = false; bool vxlan_valid = false; @@ -3355,6 +3364,8 @@ ice_aq_add_update_mir_rule(struct ice_hw *hw, u16 rule_type, u16 dest_vsi, else /* remove VSI from mirror rule */ mr_list[i] = CPU_TO_LE16(id); } + + desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); } cmd = &desc.params.add_update_rule; @@ -6984,6 +6995,7 @@ static const struct ice_prot_ext_tbl_entry ice_prot_ext[ICE_PROTOCOL_LAST] = { { ICE_MAC_OFOS, { 0, 2, 4, 6, 8, 10, 12 } }, { ICE_MAC_IL, { 0, 2, 4, 6, 8, 10, 12 } }, { ICE_ETYPE_OL, { 0 } }, + { ICE_ETYPE_IL, { 0 } }, { ICE_VLAN_OFOS, { 2, 0 } }, { ICE_IPV4_OFOS, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } }, { ICE_IPV4_IL, { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18 } }, @@ -7021,6 +7033,7 @@ static struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = { { ICE_MAC_OFOS, ICE_MAC_OFOS_HW }, { ICE_MAC_IL, ICE_MAC_IL_HW }, { ICE_ETYPE_OL, ICE_ETYPE_OL_HW }, + { ICE_ETYPE_IL, ICE_ETYPE_IL_HW }, { ICE_VLAN_OFOS, ICE_VLAN_OL_HW }, { ICE_IPV4_OFOS, ICE_IPV4_OFOS_HW }, { ICE_IPV4_IL, ICE_IPV4_IL_HW }, @@ -7051,6 +7064,8 @@ static struct ice_protocol_entry ice_prot_id_tbl[ICE_PROTOCOL_LAST] = { * ice_find_recp - find a recipe * @hw: pointer to the hardware structure * @lkup_exts: extension sequence to match + * @tun_type: tunnel type of switch filter + * @priority: priority of switch filter * * Returns index of matching recipe, or ICE_MAX_NUM_RECIPES if not found. */ @@ -8961,13 +8976,11 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type, if (!ice_get_open_tunnel_port(hw, TNL_VXLAN, &open_port)) return ICE_ERR_CFG; break; - case ICE_SW_TUN_GENEVE: case ICE_SW_TUN_GENEVE_VLAN: if (!ice_get_open_tunnel_port(hw, TNL_GENEVE, &open_port)) return ICE_ERR_CFG; break; - default: /* Nothing needs to be done for this tunnel type */ return ICE_SUCCESS; @@ -9579,7 +9592,6 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, err_ice_add_adv_rule: if (status && rinfo->sw_act.fltr_act == ICE_SET_MARK) ice_free_sw_marker_lg(hw, lg_act_id, rinfo->sw_act.markid); - if (status && adv_fltr) { ice_free(hw, adv_fltr->lkups); ice_free(hw, adv_fltr); @@ -9861,8 +9873,7 @@ enum ice_status ice_rem_adv_rule_for_vsi(struct ice_hw *hw, u16 vsi_handle) if (!map_info) continue; - if (!ice_is_bit_set(map_info->vsi_map, - vsi_handle)) + if (!ice_is_bit_set(map_info->vsi_map, vsi_handle)) continue; } else if (rinfo.sw_act.vsi_handle != vsi_handle) { continue; @@ -9871,7 +9882,6 @@ enum ice_status ice_rem_adv_rule_for_vsi(struct ice_hw *hw, u16 vsi_handle) rinfo.sw_act.vsi_handle = vsi_handle; status = ice_rem_adv_rule(hw, list_itr->lkups, list_itr->lkups_cnt, &rinfo); - if (status) return status; } From patchwork Thu Apr 27 06:19:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126595 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1290642A08; Thu, 27 Apr 2023 08:40:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 383D04300E; Thu, 27 Apr 2023 08:38:37 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 129CB42FF2 for ; Thu, 27 Apr 2023 08:38:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577515; x=1714113515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FAs8M5VxU+bGxECfHE3AswCJ/rmCPxXPTOdphycIZvE=; b=D4jKz2wt0IX6Va+AEOpXc1j4lpLxOJtY/c00sCK+ZtnaFYZTQQVTYm6D d2RdkPP02HtTVbfZ21jogY7OtbRbg4HKSEXfDods/lf6wj0bP+8Teq6O9 zf6HoeoPnqnEP1Psjr9n6g2pR/Y5KsKLJsTGt0/T+daXN+Qz5uX4m1d32 1IfXJQM+QSiBetfmMbjNeH56OfN+nUp0s0aNyUqPMJoIvtj2RoedonW8I JJdqndE6Mtn4HU9ZA5B9mgA4UaC3gNqT778/hzPK4ufqyB/ObRxajNlfg sOIc0tTupk2GSdOqd5Ym3YMDzeNIHDXYi1B4U/m3vyBxs7XEJNZr6A43E Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324410" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324410" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845887" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845887" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:32 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Lukasz Plachno Subject: [PATCH 28/30] net/ice/base: use const array to store link modes Date: Thu, 27 Apr 2023 06:19:59 +0000 Message-Id: <20230427062001.478032-29-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Change suggested during review on E1000 mailing list. Implementation moves 1,5k of .text to .rodata Signed-off-by: Lukasz Plachno Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 135 +++++++----------------------- 1 file changed, 30 insertions(+), 105 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index e4b25321db..f899e4644c 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -85,118 +85,36 @@ static const char * const ice_link_mode_str_high[] = { ice_arr_elem_idx(3, "100G_AUI2_AOC_ACC"), ice_arr_elem_idx(4, "100G_AUI2"), }; -/** - * dump_phy_type - helper function that prints PHY type strings - * @hw: pointer to the HW structure - * @phy: 64 bit PHY type to decipher - * @i: bit index within phy - * @phy_string: string corresponding to bit i in phy - * @prefix: prefix string to differentiate multiple dumps - */ -static void -dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string, - const char *prefix) -{ - if (phy & BIT_ULL(i)) - ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i, - phy_string); -} /** - * ice_dump_phy_type_low - helper function to dump phy_type_low + * ice_dump_phy_type - helper function to dump phy_type * @hw: pointer to the HW structure * @low: 64 bit value for phy_type_low + * @high: 64 bit value for phy_type_high * @prefix: prefix string to differentiate multiple dumps */ static void -ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix) +ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) { + u32 i; + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, (unsigned long long)low); - dump_phy_type(hw, low, 0, "100BASE_TX", prefix); - dump_phy_type(hw, low, 1, "100M_SGMII", prefix); - dump_phy_type(hw, low, 2, "1000BASE_T", prefix); - dump_phy_type(hw, low, 3, "1000BASE_SX", prefix); - dump_phy_type(hw, low, 4, "1000BASE_LX", prefix); - dump_phy_type(hw, low, 5, "1000BASE_KX", prefix); - dump_phy_type(hw, low, 6, "1G_SGMII", prefix); - dump_phy_type(hw, low, 7, "2500BASE_T", prefix); - dump_phy_type(hw, low, 8, "2500BASE_X", prefix); - dump_phy_type(hw, low, 9, "2500BASE_KX", prefix); - dump_phy_type(hw, low, 10, "5GBASE_T", prefix); - dump_phy_type(hw, low, 11, "5GBASE_KR", prefix); - dump_phy_type(hw, low, 12, "10GBASE_T", prefix); - dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix); - dump_phy_type(hw, low, 14, "10GBASE_SR", prefix); - dump_phy_type(hw, low, 15, "10GBASE_LR", prefix); - dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix); - dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix); - dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix); - dump_phy_type(hw, low, 19, "25GBASE_T", prefix); - dump_phy_type(hw, low, 20, "25GBASE_CR", prefix); - dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix); - dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix); - dump_phy_type(hw, low, 23, "25GBASE_SR", prefix); - dump_phy_type(hw, low, 24, "25GBASE_LR", prefix); - dump_phy_type(hw, low, 25, "25GBASE_KR", prefix); - dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix); - dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix); - dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix); - dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix); - dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix); - dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix); - dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix); - dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix); - dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix); - dump_phy_type(hw, low, 35, "40G_XLAUI", prefix); - dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix); - dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix); - dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix); - dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix); - dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix); - dump_phy_type(hw, low, 41, "50G_LAUI2", prefix); - dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix); - dump_phy_type(hw, low, 43, "50G_AUI2", prefix); - dump_phy_type(hw, low, 44, "50GBASE_CP", prefix); - dump_phy_type(hw, low, 45, "50GBASE_SR", prefix); - dump_phy_type(hw, low, 46, "50GBASE_FR", prefix); - dump_phy_type(hw, low, 47, "50GBASE_LR", prefix); - dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix); - dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix); - dump_phy_type(hw, low, 50, "50G_AUI1", prefix); - dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix); - dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix); - dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix); - dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix); - dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix); - dump_phy_type(hw, low, 56, "100G_CAUI4", prefix); - dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix); - dump_phy_type(hw, low, 58, "100G_AUI4", prefix); - dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix); - dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix); - dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix); - dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix); - dump_phy_type(hw, low, 63, "100GBASE_DR", prefix); -} - -/** - * ice_dump_phy_type_high - helper function to dump phy_type_high - * @hw: pointer to the HW structure - * @high: 64 bit value for phy_type_high - * @prefix: prefix string to differentiate multiple dumps - */ -static void -ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix) -{ + for (i = 0; i < ARRAY_SIZE(ice_link_mode_str_low); i++) { + if (low & BIT_ULL(i)) + ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", + prefix, i, ice_link_mode_str_low[i]); + } + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, (unsigned long long)high); - dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix); - dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix); - dump_phy_type(hw, high, 2, "100G_CAUI2", prefix); - dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix); - dump_phy_type(hw, high, 4, "100G_AUI2", prefix); + for (i = 0; i < ARRAY_SIZE(ice_link_mode_str_high); i++) { + if (high & BIT_ULL(i)) + ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", + prefix, i, ice_link_mode_str_high[i]); + } } /** @@ -551,23 +469,30 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); cmd->param0 |= CPU_TO_LE16(report_mode); + status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); - if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) + switch (report_mode) { + case ICE_AQC_REPORT_TOPO_CAP_MEDIA: prefix = "phy_caps_media"; - else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA) + break; + case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: prefix = "phy_caps_no_media"; - else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG) + break; + case ICE_AQC_REPORT_ACTIVE_CFG: prefix = "phy_caps_active"; - else if (report_mode == ICE_AQC_REPORT_DFLT_CFG) + break; + case ICE_AQC_REPORT_DFLT_CFG: prefix = "phy_caps_default"; - else + break; + default: prefix = "phy_caps_invalid"; + } - ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix); - ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix); + ice_dump_phy_type(hw, LE64_TO_CPU(pcaps->phy_type_low), + LE64_TO_CPU(pcaps->phy_type_high), prefix); ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", prefix, report_mode); From patchwork Thu Apr 27 06:20:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126596 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DBE8642A08; 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a="375324415" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324415" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845890" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845890" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:34 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Milena Olech Subject: [PATCH 29/30] net/ice/base: introduce a new ID for E810 NIC Date: Thu, 27 Apr 2023 06:20:00 +0000 Message-Id: <20230427062001.478032-30-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Signed-off-by: Milena Olech Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_adminq_cmd.h | 4 ++-- drivers/net/ice/base/ice_common.c | 1 + drivers/net/ice/base/ice_devids.h | 5 +++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 29b123d900..06452481bb 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2051,8 +2051,8 @@ struct ice_aqc_lldp_get_mib { #define ICE_AQ_LLDP_DCBX_S 6 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S) #define ICE_AQ_LLDP_DCBX_NA 0 -#define ICE_AQ_LLDP_DCBX_IEEE 1 -#define ICE_AQ_LLDP_DCBX_CEE 2 +#define ICE_AQ_LLDP_DCBX_CEE 1 +#define ICE_AQ_LLDP_DCBX_IEEE 2 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) * and in the LLDP MIB Change Event (0x0A01). They are valid for the * Get LLDP MIB (0x0A00) response only. diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index f899e4644c..7d2a254c47 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -226,6 +226,7 @@ bool ice_is_e810t(struct ice_hw *hw) case ICE_SUBDEV_ID_E810T3: case ICE_SUBDEV_ID_E810T4: case ICE_SUBDEV_ID_E810T5: + case ICE_SUBDEV_ID_E810T7: return true; } break; diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h index 0e0a20542b..81d993bfea 100644 --- a/drivers/net/ice/base/ice_devids.h +++ b/drivers/net/ice/base/ice_devids.h @@ -6,6 +6,8 @@ #define _ICE_DEVIDS_H_ /* Device IDs */ +#define ICE_DEV_ID_E822_SI_DFLT 0x1888 +/* Intel(R) Ethernet Connection E823-L for backplane */ #define ICE_DEV_ID_E823L_BACKPLANE 0x124C /* Intel(R) Ethernet Connection E823-L for SFP */ #define ICE_DEV_ID_E823L_SFP 0x124D @@ -35,6 +37,7 @@ #define ICE_SUBDEV_ID_E810T4 0x02EA #define ICE_SUBDEV_ID_E810T5 0x0010 #define ICE_SUBDEV_ID_E810T6 0x0012 +#define ICE_SUBDEV_ID_E810T7 0x0011 /* Intel(R) Ethernet Controller E810-XXV for backplane */ #define ICE_DEV_ID_E810_XXV_BACKPLANE 0x1599 /* Intel(R) Ethernet Controller E810-XXV for QSFP */ @@ -42,8 +45,6 @@ /* Intel(R) Ethernet Controller E810-XXV for SFP */ #define ICE_DEV_ID_E810_XXV_SFP 0x159B /* Intel(R) Ethernet Connection E823-C for backplane */ -#define ICE_DEV_ID_E822_SI_DFLT 0x1888 -/* Intel(R) Ethernet Connection E823-L for backplane */ #define ICE_DEV_ID_E823C_BACKPLANE 0x188A /* Intel(R) Ethernet Connection E823-C for QSFP */ #define ICE_DEV_ID_E823C_QSFP 0x188B From patchwork Thu Apr 27 06:20:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 126597 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B975442A08; Thu, 27 Apr 2023 08:41:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 095C34301A; Thu, 27 Apr 2023 08:38:41 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 3904E42DB8; Thu, 27 Apr 2023 08:38:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682577518; x=1714113518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=maqANsBilWmahHiq04uLYfoc3tmCUU3mkjNx/8z8ICs=; b=AiCkM0lYK6LdgXn/5KyHO8TKp48OhYTs9IosinpcUpqHMp6KC++v4a4y uY9xu8qQxD+Djj5TUvYhG4Lk4WklOHL9TcXeCGMg9amiIEgQHMNNiq2bu NUzQGswovYqWv1gjVIs/6P5xOqMO6yAi332B2CV5wPaGOBnHN4htfHzog U20xKWclCTXpd2t1HUchXGxvQcmMxreeF7ZKUpyAJDrEoTOkFZtllakRS VWtEco/kK9qiCENqtpZd1mDLFXonEapDbOdfVLO0X0bHsnNq+f+ulvIOm b3rtle239wd3YVsGAufY+UWx7yvgBeP+v8KKA/sw49aUI4e7dPxxL4CF4 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="375324418" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="375324418" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 23:38:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10692"; a="805845900" X-IronPort-AV: E=Sophos;i="5.99,230,1677571200"; d="scan'208";a="805845900" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:35 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , stable@dpdk.org, Paul Greenwalt Subject: [PATCH 30/30] net/ice/base: fix Generic Checksum acronym Date: Thu, 27 Apr 2023 06:20:01 +0000 Message-Id: <20230427062001.478032-31-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230427062001.478032-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fixes: c31095a0b20f ("net/ice/base: add GCO defines and GCO flex descriptor") Cc: stable@dpdk.org Signed-off-by: Paul Greenwalt Signed-off-by: Qiming Yang Signed-off-by: Paul Greenwalt Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 7d2a254c47..c324500b54 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1488,7 +1488,7 @@ const struct ice_ctx_ele ice_tlan_ctx_info[] = { ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), - ICE_CTX_STORE(ice_tlan_ctx, gsc_ena, 1, 172), + ICE_CTX_STORE(ice_tlan_ctx, gcs_ena, 1, 172), { 0 } }; diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h index d8ac841e46..d84f2f6db5 100644 --- a/drivers/net/ice/base/ice_lan_tx_rx.h +++ b/drivers/net/ice/base/ice_lan_tx_rx.h @@ -747,7 +747,7 @@ enum ice_rxdid { ICE_RXDID_FLEX_NIC = 2, ICE_RXDID_FLEX_NIC_2 = 6, ICE_RXDID_HW = 7, - ICE_RXDID_GSC = 9, + ICE_RXDID_GCS = 9, ICE_RXDID_COMMS_GENERIC = 16, ICE_RXDID_COMMS_AUX_VLAN = 17, ICE_RXDID_COMMS_AUX_IPV4 = 18, @@ -1069,14 +1069,14 @@ enum ice_tx_desc_len_fields { struct ice_tx_ctx_desc { __le32 tunneling_params; __le16 l2tag2; - __le16 gsc; + __le16 gcs; __le64 qw1; }; -#define ICE_TX_GSC_DESC_START 0 /* 7 BITS */ -#define ICE_TX_GSC_DESC_OFFSET 7 /* 4 BITS */ -#define ICE_TX_GSC_DESC_TYPE 11 /* 2 BITS */ -#define ICE_TX_GSC_DESC_ENA 13 /* 1 BIT */ +#define ICE_TX_GCS_DESC_START 0 /* 7 BITS */ +#define ICE_TX_GCS_DESC_OFFSET 7 /* 4 BITS */ +#define ICE_TX_GCS_DESC_TYPE 11 /* 2 BITS */ +#define ICE_TX_GCS_DESC_ENA 13 /* 1 BIT */ #define ICE_TXD_CTX_QW1_DTYPE_S 0 #define ICE_TXD_CTX_QW1_DTYPE_M (0xFUL << ICE_TXD_CTX_QW1_DTYPE_S) @@ -1188,8 +1188,9 @@ struct ice_tlan_ctx { u8 drop_ena; u8 cache_prof_idx; u8 pkt_shaper_prof_idx; - u8 gsc_ena; + u8 gcs_ena; u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ + u16 tail; }; /* LAN Tx Completion Queue data */