From patchwork Thu Jun 8 10:19:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiyang He X-Patchwork-Id: 128361 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0438E42C57; Thu, 8 Jun 2023 04:50:13 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 840C5410D3; Thu, 8 Jun 2023 04:50:13 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 7CF0040042; Thu, 8 Jun 2023 04:50:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686192611; x=1717728611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IrvruXq8gjbHikH71eZdJrN4lQpubHCdIhMKqF8oIco=; b=eii6MalfRB1F6H+c4B+WP5EbMGABMPavkoV1paskDAcrfIbhz6Wkoxld GWTD9BbWJwSmJDAJ+xE3f533Nr07RYKPeWgJ1ZRmoL1RKvYMusoWmm4gX YwVF1pZK1mRSZzugRqEWzDhjuuFffEEfuJjyi/UZWE4IqOmFC5UBvRRMb xXU/SOzdtw/WqAZb+xr8pQSEFbDyM3ltaFOgz0kIoZJsniou5IDwT9m+d 6wNbjWrad2p+eGxsDO63fSWIAXWzF0sRAPo6dtSUNK3q6EUpNyCAjqICo 3fOj4vemQbMLDnOXpAlpjIkZagVzDe4orkHx01whkQxK6Viq3sD16aW4f Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="341837613" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="341837613" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:50:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="703906515" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="703906515" Received: from unknown (HELO root..) ([10.239.252.115]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:50:07 -0700 From: Shiyang He To: dev@dpdk.org Cc: yidingx.zhou@intel.com, Shiyang He , stable@dpdk.org, Qiming Yang , Qi Zhang , Beilei Xing Subject: [PATCH v2] net/ice:fix tunnel packet TX descriptor error Date: Thu, 8 Jun 2023 10:19:04 +0000 Message-Id: <20230608101904.65340-1-shiyangx.he@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230530153603.105257-1-shiyangx.he@intel.com> References: <20230530153603.105257-1-shiyangx.he@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The TX descriptor of tunnel packet filled incorrectly due to the MACLEN is not set. This patch fixes this issue by setting MACLEN to correctly fill the TX descriptor. Fixes: bd70c451532c ("net/ice: support Tx checksum offload for tunnel") Cc: stable@dpdk.org Signed-off-by: Shiyang He Acked-by: Qi Zhang Tested-by: Ke Xu --- drivers/net/ice/ice_rxtx.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 0ea0045836..3af552f3e1 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2738,10 +2738,7 @@ ice_txd_enable_checksum(uint64_t ol_flags, union ice_tx_offload tx_offload) { /* Set MACLEN */ - if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) - *td_offset |= (tx_offload.outer_l2_len >> 1) - << ICE_TX_DESC_LEN_MACLEN_S; - else + if (!(ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)) *td_offset |= (tx_offload.l2_len >> 1) << ICE_TX_DESC_LEN_MACLEN_S; @@ -3002,9 +2999,12 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) /* Fill in tunneling parameters if necessary */ cd_tunneling_params = 0; - if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) + if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) { + td_offset |= (tx_offload.outer_l2_len >> 1) + << ICE_TX_DESC_LEN_MACLEN_S; ice_parse_tunneling_params(ol_flags, tx_offload, &cd_tunneling_params); + } /* Enable checksum offloading */ if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)