From patchwork Wed Jul 12 07:42:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 129491 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4CD1542E52; Wed, 12 Jul 2023 10:00:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4AF0A42B8C; Wed, 12 Jul 2023 10:00:07 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 761D3406BA for ; Wed, 12 Jul 2023 10:00:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689148805; x=1720684805; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L5AYY0GXRCHpLLgTqykbcgtlYufOGr1dc8rsFnyINgg=; b=KpWckMOyEAaBOlN/1ABdCxO0RzPwxjcV0ieUGI4+QiogreSfO0tEu5Pb o44v9AoDw+IlVaXm++U1mVoXrHhUP9+jgne6IRNkthg9jRj1vC1NNPTSL uPccANvjVgcvA1PXbJRkmuzITQH9vQI+3DIVyXTnt7JdlOwza3CKMj6+h 8hrqNzx5cMJU2JeqbO3u7ltW/GoMNK0RkD4jDOtoFoIBfljS+lRAMP8wg sIzb9CrGPmRHr8Djubb8DNGpkL3RuSkmBfZQdYJxV22LDrkWknCds52ql HfjTH9+jjz1esEBUSeo65jrty+TlNR8JP0+C3iZzMNoBmGEbAorEuH+x9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="354736655" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="354736655" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 01:00:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="845564066" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="845564066" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by orsmga004.jf.intel.com with ESMTP; 12 Jul 2023 00:59:52 -0700 From: Qiming Yang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, Qiming Yang , Jie Hai Subject: [PATCH 1/3] net/ixgbevf: fix Rx and Tx queue status get Date: Wed, 12 Jul 2023 07:42:13 +0000 Message-Id: <20230712074215.3249336-2-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230712074215.3249336-1-qiming.yang@intel.com> References: <20230712074215.3249336-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Ixgbevf driver don't enable queue start/stop functions, queue status is not updated when the HW queue enabled or disabled. It caused application can't get correct queue status. This patch fixes the issue by updating the queue states when the queue is disabled or enabled. Fixes: 429c6d86b371 ("ixgbe: prepare for vector pmd") Fixes: f0c50e5f56fa ("ixgbe: move PMD specific fields out of base driver") Signed-off-by: Qiming Yang Signed-off-by: Jie Hai --- drivers/net/ixgbe/ixgbe_rxtx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 61f17cd90b..954ef241a0 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -3378,6 +3378,7 @@ ixgbe_dev_clear_queues(struct rte_eth_dev *dev) if (txq != NULL) { txq->ops->release_mbufs(txq); txq->ops->reset(txq); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } @@ -3387,6 +3388,7 @@ ixgbe_dev_clear_queues(struct rte_eth_dev *dev) if (rxq != NULL) { ixgbe_rx_queue_release_mbufs(rxq); ixgbe_reset_rx_queue(adapter, rxq); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } /* If loopback mode was enabled, reconfigure the link accordingly */ @@ -5896,6 +5898,8 @@ ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev) } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE)); if (!poll_ms) PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i); + else + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } for (i = 0; i < dev->data->nb_rx_queues; i++) { @@ -5913,6 +5917,8 @@ ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev) } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE)); if (!poll_ms) PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i); + else + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; rte_wmb(); IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1); From patchwork Wed Jul 12 07:42:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 129492 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EF27C42E52; Wed, 12 Jul 2023 10:00:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C6C242BB1; Wed, 12 Jul 2023 10:00:09 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 19E31406BA for ; Wed, 12 Jul 2023 10:00:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689148806; x=1720684806; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6C1iwd/eZQ1DUY1gaePavfJxZ8s8XWAHqvvBKCsBh80=; b=UdooDWqqdMwjJ448Grimv4E3Mor7NgAr9CIUoTyM+uF0tZaLmOIArynO 7/I35uyDJlK44Q3JebfMbkFEunb6FHDVCAk0ZGg7GXEn6LAWWBbOQ2xCF +xA0h6nTifXmP7stb04ALcSgh2KqL/K2KuV57LL0UtoEOF/bZsbwA8irI 5QNkr6qAHDGynfVzFHPLgXhNAiG9nNRboFraO/s7BlL4mSNEBTI5ZVpeO yEQ6DCyw1xZVGhj4O7MpvK87wskuviOVz7RbwKovkRLBJGVfkf2qkvMkb p8CSHyP9Z+3nB7e2P3swWG4NnJFItKiNgp7DvASF/t6C6ESO7B+Y/0jJY g==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="354736660" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="354736660" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 01:00:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="845564072" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="845564072" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by orsmga004.jf.intel.com with ESMTP; 12 Jul 2023 00:59:54 -0700 From: Qiming Yang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, Qiming Yang , Mingjin Ye Subject: [PATCH 2/3] net/igc: fix Rx and Tx queue status get Date: Wed, 12 Jul 2023 07:42:14 +0000 Message-Id: <20230712074215.3249336-3-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230712074215.3249336-1-qiming.yang@intel.com> References: <20230712074215.3249336-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Igc driver don't enable queue start/stop functions, queue status is not updated when the HW queue enabled or disabled. It caused application can't get correct queue status. This patch fixes the issue by updating the queue states when the queue is disabled or enabled. Fixes: a5aeb2b9e225 ("net/igc: support Rx and Tx") Signed-off-by: Qiming Yang Signed-off-by: Mingjin Ye --- drivers/net/igc/igc_txrx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c index c11b6f7f25..5c60e3e997 100644 --- a/drivers/net/igc/igc_txrx.c +++ b/drivers/net/igc/igc_txrx.c @@ -1215,6 +1215,7 @@ igc_rx_init(struct rte_eth_dev *dev) dvmolr |= IGC_DVMOLR_STRCRC; IGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } return 0; @@ -1888,6 +1889,7 @@ igc_dev_clear_queues(struct rte_eth_dev *dev) if (txq != NULL) { igc_tx_queue_release_mbufs(txq); igc_reset_tx_queue(txq); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } @@ -1896,6 +1898,7 @@ igc_dev_clear_queues(struct rte_eth_dev *dev) if (rxq != NULL) { igc_rx_queue_release_mbufs(rxq); igc_reset_rx_queue(rxq); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } } @@ -2143,6 +2146,7 @@ igc_tx_init(struct rte_eth_dev *dev) IGC_TXDCTL_WTHRESH_MSK; txdctl |= IGC_TXDCTL_QUEUE_ENABLE; IGC_WRITE_REG(hw, IGC_TXDCTL(txq->reg_idx), txdctl); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } if (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) { From patchwork Wed Jul 12 07:42:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiming Yang X-Patchwork-Id: 129493 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BA1E242E52; Wed, 12 Jul 2023 10:00:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7293442C54; Wed, 12 Jul 2023 10:00:10 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 4561A427F5 for ; Wed, 12 Jul 2023 10:00:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689148807; x=1720684807; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2OB3z+lqKYgO4Yyf/dzrb1q0gTAcC0ZbVTJ7Nk+8N4g=; b=YxPzcvxIC3EbECZ7BU1YYrCJk7mTKcgCCmB9sWtixc8TFuhO0rcglB+j U3O0NML0uk2hyYNdibWNno/ZWodGS9beOZ6CGin1F/l1CWoMJDVncuRXa vOHMxZUJaNX8TVnh83pD4QiUj+peP2uO+hDtPEm/JkJko6OpbRZUhS/Gq yq4xKrMnIU8y+BU4JKK39dqETdbNV5ppuTr9Xrlzoqw18At1N7+10x2dF EIS14g2smZOIrA7aPjNwZhjsvrOQw+WLR9W1MGQ5FkfmOU0TLS1lWKKoj cOfZ9xNaWVS92J+V0Hw8jubN1heoCdFLcsyhwqOv0H9Yve8vW68bOMuRu A==; X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="354736666" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="354736666" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 01:00:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10768"; a="845564079" X-IronPort-AV: E=Sophos;i="6.01,199,1684825200"; d="scan'208";a="845564079" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by orsmga004.jf.intel.com with ESMTP; 12 Jul 2023 00:59:56 -0700 From: Qiming Yang To: dev@dpdk.org Cc: beilei.xing@intel.com, qi.z.zhang@intel.com, Qiming Yang , Mingjin Ye Subject: [PATCH 3/3] net/e1000: fix Rx and Tx queue status Date: Wed, 12 Jul 2023 07:42:15 +0000 Message-Id: <20230712074215.3249336-4-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230712074215.3249336-1-qiming.yang@intel.com> References: <20230712074215.3249336-1-qiming.yang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Igb driver don't enable queue start/stop functions, queue status is not updated when the HW queue enabled or disabled. It caused application can't get correct queue status. This patch fixes the issue by updating the queue states when the queue is disabled or enabled. Fixes: be2d648a2dd3 ("igb: add PF support") Signed-off-by: Qiming Yang Signed-off-by: Mingjin Ye --- drivers/net/e1000/igb_rxtx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index 25ad9eb4e5..61c6394310 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -1854,6 +1854,7 @@ igb_dev_clear_queues(struct rte_eth_dev *dev) if (txq != NULL) { igb_tx_queue_release_mbufs(txq); igb_reset_tx_queue(txq, dev); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } @@ -1862,6 +1863,7 @@ igb_dev_clear_queues(struct rte_eth_dev *dev) if (rxq != NULL) { igb_rx_queue_release_mbufs(rxq); igb_reset_rx_queue(rxq); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; } } } @@ -2442,6 +2444,7 @@ eth_igb_rx_init(struct rte_eth_dev *dev) rxdctl |= ((rxq->hthresh & 0x1F) << 8); rxdctl |= ((rxq->wthresh & 0x1F) << 16); E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl); + dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { @@ -2606,6 +2609,7 @@ eth_igb_tx_init(struct rte_eth_dev *dev) txdctl |= ((txq->wthresh & 0x1F) << 16); txdctl |= E1000_TXDCTL_QUEUE_ENABLE; E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl); + dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; } /* Program the Transmit Control Register. */