From patchwork Mon Jul 24 08:41:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 129695 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 182E642EFE; Mon, 24 Jul 2023 10:42:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C45B240ED7; Mon, 24 Jul 2023 10:42:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1A82C40ED5 for ; Mon, 24 Jul 2023 10:42:05 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36O8NEZm015971 for ; Mon, 24 Jul 2023 01:42:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=l91WrCr84IUULBRj3Dbnt0eGjcs2nDjm7dbwRb8uuAE=; b=KuSln+J/eV/qa1TVd1j3k8ZMXWMUytak6rQfU/ubMQniGdl3gqwSBDdhg+hnT9icRS4q xJQw02t0DrSv8ZYND0GzwcEdwmccth0hA40Fr6+Q3Wt8z98YA1VeuWACrSWaILC2i7Jl FqG9sWU3qJmOfU0Kz5s5MfgHMXwxiL/k6IVb7gPSyagFe5DByPsX/gtY/h7M0Zkp2zrP FpVblFrhUy65YQF4O9v28X2ZqKdU4lO4UTrNac2bB15LXiEOLMOavdp5af0OnmrR4FV8 EMKtw/rgsQkb/PoB9GhJUW2bMHg3G5VZ1uNiSaJ2xxSn/+vIIFkZ7Xw1O+ZZUYrmrbI0 Kg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3s1nra81kr-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 24 Jul 2023 01:42:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 24 Jul 2023 01:42:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 24 Jul 2023 01:42:03 -0700 Received: from MININT-80QBFE8.corp.innovium.com (unknown [10.193.66.84]) by maili.marvell.com (Postfix) with ESMTP id 86CCA3F7044; Mon, 24 Jul 2023 01:42:01 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH] event/cnxk: add asm to support CASP for clang Date: Mon, 24 Jul 2023 14:11:56 +0530 Message-ID: <20230724084156.2891-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: WBzKIOtENZgJsrfMp3r-xyQRVfVO9SAh X-Proofpoint-GUID: WBzKIOtENZgJsrfMp3r-xyQRVfVO9SAh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-24_06,2023-07-20_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Clang fails to use register pairs for CASP instruction, use inline asm to fix register pairs. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_worker.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index b4ee023723..e71ab3c523 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -239,19 +239,32 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev, } gw; gw.get_work = ws->gw_wdata; -#if defined(RTE_ARCH_ARM64) && !defined(__clang__) +#if defined(RTE_ARCH_ARM64) +#if !defined(__clang__) asm volatile( PLT_CPU_FEATURE_PREAMBLE "caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n" : [wdata] "+r"(gw.get_work) : [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0) : "memory"); +#else + register uint64_t x0 __asm("x0") = (uint64_t)gw.u64[0]; + register uint64_t x1 __asm("x1") = (uint64_t)gw.u64[1]; + asm volatile(".arch armv8-a+lse\n" + "caspal %[x0], %[x1], %[x0], %[x1], [%[dst]]\n" + : [x0] "+r"(x0), [x1] "+r"(x1) + : [dst] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0) + : "memory"); + gw.u64[0] = x0; + gw.u64[1] = x1; +#endif #else plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0); do { roc_load_pair(gw.u64[0], gw.u64[1], ws->base + SSOW_LF_GWS_WQE0); } while (gw.u64[0] & BIT_ULL(63)); + rte_atomic_thread_fence(__ATOMIC_SEQ_CST); #endif ws->gw_rdata = gw.u64[0]; if (gw.u64[1])