From patchwork Fri Aug 11 08:57:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130115 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F7E243032; Fri, 11 Aug 2023 10:58:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 40DC0410E3; Fri, 11 Aug 2023 10:58:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8BF7F410E3 for ; Fri, 11 Aug 2023 10:58:13 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjx5G001610 for ; Fri, 11 Aug 2023 01:58:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pftw1U7JORUEQ3yIcXpg3sxn5xyZMTrRwABznshNmaE=; b=U8TuV+Kfm5QIeysikdh+Hi0YpTGrrBG44p6NHRfnGs/W3R8PWwHH0/oeXUWakWAZAbj6 OxfMJ/VzmvvmcuItPWFHVzJwlq6+QPjch0V7BWcbRjvEI2hJt+N6MD5b2ZeeZyO2H6oo /TD9BTQXk2qrdAgRF493SKNcNB9vrNehocqEl48IH04bx8JaQ5KKUeDiW6x0z3il+SMw 8VKqYqX3cIaMIufM0VM+SC6gqLfECq2MggDGLhpN1kZW88DS3lhybwrmci91p3jrqrWV q+r61YeGaUjkdgMtXCaMIZ/a05cL90NE2SWbEhnKDZeQ3AWB4/ZsmVZdGMzNyGTEwQsn 7w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r57-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:12 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:10 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7022B3F706D; Fri, 11 Aug 2023 01:58:08 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 01/31] common/cnxk: add aura ref count mechanism Date: Fri, 11 Aug 2023 14:27:35 +0530 Message-ID: <20230811085805.441256-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: lp2PfJpHwDA8JMxZmh5N5O_5bidfKDRM X-Proofpoint-GUID: lp2PfJpHwDA8JMxZmh5N5O_5bidfKDRM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Each RQ can be associated with lpb_aura and spb_aura. lpb_aura or spb_aura is shared across multiple RQs then cleanup via one RQ will reset the aura context. To prevent, adding ref count mechanism. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix_fc.c | 6 ++++++ drivers/common/cnxk/roc_npa_priv.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index d8ca5f9996..1f5ef960da 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -537,6 +537,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); } else { + lf->aura_attr[aura_id].ref_count++; plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64, roc_nix->port_id, tc, pool_id); } @@ -552,6 +553,8 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui if (ena) { if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true)) plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); + else + lf->aura_attr[aura_id].ref_count++; } else { bool found = !!force; @@ -561,6 +564,9 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui found = true; if (!found) return; + else if ((lf->aura_attr[aura_id].ref_count > 0) && + --lf->aura_attr[aura_id].ref_count) + return; if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false)) plt_err("Disabling backpressue failed on aura 0x%" PRIx64, pool_id); diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index d2118cc4fb..704d93d5dc 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -49,6 +49,7 @@ struct npa_aura_lim { struct npa_aura_attr { int buf_type[ROC_NPA_BUF_TYPE_END]; + uint16_t ref_count; }; struct dev; From patchwork Fri Aug 11 08:57:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130116 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D690F43032; 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Fri, 11 Aug 2023 01:58:15 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:13 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 611743F706A; Fri, 11 Aug 2023 01:58:11 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 02/31] common/cnxk: optimize time while configuring fc on VF Date: Fri, 11 Aug 2023 14:27:36 +0530 Message-ID: <20230811085805.441256-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: vQRtR5gweMJ0OOscrqC0rPXSgyfCs6Z5 X-Proofpoint-GUID: vQRtR5gweMJ0OOscrqC0rPXSgyfCs6Z5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla PFC configuration function is taking 8 ms due to mailbox communication to check whether sso is connected to RQ and whether back pressure is enabled on each aura. To optimize this time we are updating aura attributes in nixlf and sso_ena parameter in RQ during write configuration and the same updated value is accessed while configuring flow control, reducing time to 6 ms. Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/roc_nix_fc.c | 47 ++++++++---------------------- drivers/common/cnxk/roc_npa.c | 16 +++++++++- drivers/common/cnxk/roc_npa_priv.h | 6 ++++ 3 files changed, 33 insertions(+), 36 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 1f5ef960da..d58b35268e 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -285,15 +285,11 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) struct roc_nix_fc_cfg tmp; uint64_t pool_drop_pct; struct roc_nix_rq *rq; - int sso_ena = 0, rc; + int rc; rq = nix->rqs[fc_cfg->rq_cfg.rq]; - /* Check whether RQ is connected to SSO or not */ - sso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq); - if (sso_ena < 0) - return -EINVAL; - if (sso_ena) { + if (rq->sso_ena) { pool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct; /* Use default value for zero pct */ if (fc_cfg->rq_cfg.enable && !pool_drop_pct) @@ -486,12 +482,10 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui uint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id); struct nix *nix = roc_nix_to_nix_priv(roc_nix); struct npa_lf *lf = idev_npa_obj_get(); - struct npa_aq_enq_req *req; - struct npa_aq_enq_rsp *rsp; + struct npa_aura_attr *aura_attr; uint8_t bp_thresh, bp_intf; - struct mbox *mbox; uint16_t bpid; - int rc, i; + int i; if (roc_nix_is_sdp(roc_nix)) return; @@ -499,30 +493,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui if (!lf) return; - mbox = lf->mbox; - req = mbox_alloc_msg_npa_aq_enq(mbox_get(mbox)); - if (req == NULL) { - mbox_put(mbox); - return; - } - - req->aura_id = aura_id; - req->ctype = NPA_AQ_CTYPE_AURA; - req->op = NPA_AQ_INSTOP_READ; - - rc = mbox_process_msg(mbox, (void *)&rsp); - mbox_put(mbox); - if (rc) { - plt_nix_dbg("Failed to read context of aura 0x%" PRIx64, pool_id); - return; - } + aura_attr = &lf->aura_attr[aura_id]; bp_intf = 1 << nix->is_nix1; - bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift); + bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift); - bpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid; + bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid; /* BP is already enabled. */ - if (rsp->aura.bp_ena && ena) { + if (aura_attr->bp_ena && ena) { /* Disable BP if BPIDs don't match and couldn't add new BPID. */ if (bpid != nix->bpid[tc]) { uint16_t bpid_new = NIX_BPID_INVALID; @@ -537,7 +515,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); } else { - lf->aura_attr[aura_id].ref_count++; + aura_attr->ref_count++; plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64, roc_nix->port_id, tc, pool_id); } @@ -547,14 +525,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui } /* BP was previously enabled but now disabled skip. */ - if (rsp->aura.bp && ena) + if (aura_attr->bp && ena) return; if (ena) { if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true)) plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); else - lf->aura_attr[aura_id].ref_count++; + aura_attr->ref_count++; } else { bool found = !!force; @@ -564,8 +542,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui found = true; if (!found) return; - else if ((lf->aura_attr[aura_id].ref_count > 0) && - --lf->aura_attr[aura_id].ref_count) + else if ((aura_attr->ref_count > 0) && --(aura_attr->ref_count)) return; if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false)) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 3b9a70028b..d5c3a53b9b 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -535,6 +535,8 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size, if (rc) goto stack_mem_free; + lf->aura_attr[aura_id].shift = aura->shift; + lf->aura_attr[aura_id].limit = aura->limit; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); /* Update aura count */ roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count); @@ -657,6 +659,8 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id, if (rc) return rc; + lf->aura_attr[aura_id].shift = aura->shift; + lf->aura_attr[aura_id].limit = aura->limit; *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base); return 0; @@ -735,6 +739,9 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit) aura_req->aura.limit = aura_limit; aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit); rc = mbox_process(mbox); + if (rc) + goto exit; + lf->aura_attr[aura_req->aura_id].limit = aura_req->aura.limit; exit: mbox_put(mbox); return rc; @@ -931,7 +938,14 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf, req->aura.bp_ena = bp_intf; req->aura_mask.bp_ena = ~(req->aura_mask.bp_ena); - mbox_process(mbox); + rc = mbox_process(mbox); + if (rc) + goto fail; + + lf->aura_attr[aura_id].nix0_bpid = req->aura.nix0_bpid; + lf->aura_attr[aura_id].nix1_bpid = req->aura.nix1_bpid; + lf->aura_attr[aura_id].bp_ena = req->aura.bp_ena; + lf->aura_attr[aura_id].bp = req->aura.bp; fail: mbox_put(mbox); return rc; diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h index 704d93d5dc..060df9ab04 100644 --- a/drivers/common/cnxk/roc_npa_priv.h +++ b/drivers/common/cnxk/roc_npa_priv.h @@ -50,6 +50,12 @@ struct npa_aura_lim { struct npa_aura_attr { int buf_type[ROC_NPA_BUF_TYPE_END]; uint16_t ref_count; + uint64_t nix0_bpid; + uint64_t nix1_bpid; + uint64_t shift; + uint64_t limit; + uint8_t bp_ena; + uint8_t bp; }; struct dev; From patchwork Fri Aug 11 08:57:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130117 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 86AF043032; Fri, 11 Aug 2023 10:58:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 754D143261; Fri, 11 Aug 2023 10:58:22 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E4DB240F16 for ; Fri, 11 Aug 2023 10:58:20 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WUt011282 for ; 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Fri, 11 Aug 2023 01:58:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:18 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 8B1643F706C; Fri, 11 Aug 2023 01:58:14 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 03/31] common/cnxk: use only user sqb slack when provided Date: Fri, 11 Aug 2023 14:27:37 +0530 Message-ID: <20230811085805.441256-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: CwB7soMdEOIdEhY66KFXRZRi4ECGVBR_ X-Proofpoint-GUID: CwB7soMdEOIdEhY66KFXRZRi4ECGVBR_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao This patch preferred user provided argument while configuring slack. If no platform argument given then by default MAX(24, 30% of SQ size) was configured as slack. Currently even if user provided SQB slack, we take max of internally calculated value and user given one Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 08e8bf7ea2..5e689d08be 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -7,6 +7,9 @@ #include "roc_api.h" #include "roc_priv.h" +/* Default SQB slack per SQ */ +#define ROC_NIX_SQB_SLACK_DFLT 24 + static inline uint32_t nix_qsize_to_val(enum nix_q_size qsize) { @@ -1012,7 +1015,10 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb); sq->nb_sqb_bufs_adj = nb_sqb_bufs; - nb_sqb_bufs += PLT_MAX(thr, roc_nix->sqb_slack); + if (roc_nix->sqb_slack) + nb_sqb_bufs += roc_nix->sqb_slack; + else + nb_sqb_bufs += PLT_MAX((int)thr, (int)ROC_NIX_SQB_SLACK_DFLT); /* Explicitly set nat_align alone as by default pool is with both * nat_align and buf_offset = 1 which we don't want for SQB. */ From patchwork Fri Aug 11 08:57:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130118 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8AECB43032; Fri, 11 Aug 2023 10:58:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 817AA43266; Fri, 11 Aug 2023 10:58:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6A4D740F16 for ; Fri, 11 Aug 2023 10:58:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjlLm001536 for ; Fri, 11 Aug 2023 01:58:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mbao0JEJAn2WMgMgLFxmyByE8ETbY4eQO+ERdUaNnMY=; b=KycYRiiE4cZw/irlOxbxcI67HeF5gxb1dGfcq47sUYes9DaQpOVW86w7K6zUJ499ttAp ID/+3e0y8gVXNPKqbf91ii7jDASPJW9IY1t7SSCPJwepgms/A1tq9YnQY+hVknTMlijZ jwlzfR5PUo8lJzxZgeeUOo1c+tG0EloerkS7cvmiMgL8PXyNDu15Gkqzz+O5MeARvccx jk2cc68uRgA5ez8PWxph3GwZQD1zGvz4IgB3cc1vKYpneWcK7fIFEKLCqpyyFPsc0cJf I5gOW5GmpWTi+Hp41BwlBeU6FSWzWTRY42Ino/3ogj4aNcNYsIr82rH6k5nDh+ZN0m2o TQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r5w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:21 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:19 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:19 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9848B3F7081; Fri, 11 Aug 2023 01:58:17 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 04/31] common/cnxk: add workaround for CPT ctx fetch issue Date: Fri, 11 Aug 2023 14:27:38 +0530 Message-ID: <20230811085805.441256-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: hcobNQOL1bhEBHSc67xOl8kwErKH-LdO X-Proofpoint-GUID: hcobNQOL1bhEBHSc67xOl8kwErKH-LdO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add workaround for CPT context fetch issue in CN10KB by setting CTX_ILEN to that of CTX_SIZE and enabling FLR_FLUSH in CPT_LF_CTX_CTL. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_cpt.c | 23 ++++++++++++++++++++--- drivers/common/cnxk/roc_cpt.h | 2 ++ drivers/common/cnxk/roc_cpt_priv.h | 4 ++-- drivers/common/cnxk/roc_errata.h | 7 +++++++ drivers/common/cnxk/roc_ie_ot.h | 3 +++ drivers/common/cnxk/roc_mbox.h | 4 ++++ drivers/common/cnxk/roc_nix_inl.c | 14 +++++++++++++- drivers/common/cnxk/roc_nix_inl_dev.c | 10 +++++++++- 8 files changed, 60 insertions(+), 7 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index d235ff51ca..981e85a204 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -331,6 +331,8 @@ roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_inline_ipse req->param2 = cfg->param2; req->opcode = cfg->opcode; req->bpid = cfg->bpid; + req->ctx_ilen_valid = cfg->ctx_ilen_valid; + req->ctx_ilen = cfg->ctx_ilen; rc = mbox_process(mbox); exit: @@ -460,8 +462,8 @@ cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf) } int -cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, - bool inl_dev_sso) +cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, bool inl_dev_sso, + bool ctx_ilen_valid, uint8_t ctx_ilen) { struct cpt_lf_alloc_req_msg *req; struct mbox *mbox = mbox_get(dev->mbox); @@ -485,6 +487,8 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr, req->sso_pf_func = idev_sso_pffunc_get(); req->eng_grpmsk = eng_grpmsk; req->blkaddr = blkaddr; + req->ctx_ilen_valid = ctx_ilen_valid; + req->ctx_ilen = ctx_ilen; rc = mbox_process(mbox); exit: @@ -587,6 +591,8 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt); uint8_t blkaddr[ROC_CPT_MAX_BLKS]; struct msix_offset_rsp *rsp; + bool ctx_ilen_valid = false; + uint16_t ctx_ilen = 0; uint8_t eng_grpmsk; int blknum = 0; int rc, i; @@ -618,7 +624,13 @@ roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf) (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) | (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]); - rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false); + if (roc_errata_cpt_has_ctx_fetch_issue()) { + ctx_ilen_valid = true; + /* Inbound SA size is max context size */ + ctx_ilen = (PLT_ALIGN(ROC_OT_IPSEC_SA_SZ_MAX, ROC_ALIGN) / 128) - 1; + } + + rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr[blknum], false, ctx_ilen_valid, ctx_ilen); if (rc) goto lfs_detach; @@ -1108,6 +1120,11 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf) lf_inprog.s.eena = 1; plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); + if (roc_errata_cpt_has_ctx_fetch_issue()) { + /* Enable flush on FLR */ + plt_write64(1, lf->rbase + CPT_LF_CTX_CTL); + } + cpt_lf_dump(lf); } diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index 910bd37a0c..787bccb27d 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -161,6 +161,8 @@ struct roc_cpt_inline_ipsec_inb_cfg { uint16_t bpid; uint32_t credit_th; uint8_t egrp; + uint8_t ctx_ilen_valid : 1; + uint8_t ctx_ilen : 7; }; int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h index 61dec9a168..4ed87c857b 100644 --- a/drivers/common/cnxk/roc_cpt_priv.h +++ b/drivers/common/cnxk/roc_cpt_priv.h @@ -21,8 +21,8 @@ roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt) int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf); int cpt_lfs_detach(struct dev *dev); -int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk, - bool inl_dev_sso); +int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk, bool inl_dev_sso, + bool ctx_ilen_valid, uint8_t ctx_ilen); int cpt_lfs_free(struct dev *dev); int cpt_lf_init(struct roc_cpt_lf *lf); void cpt_lf_fini(struct roc_cpt_lf *lf); diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index 22d2406e94..6f84e06603 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -82,6 +82,13 @@ roc_errata_cpt_hang_on_x2p_bp(void) return roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1(); } +/* Errata IPBUCPT-38756 */ +static inline bool +roc_errata_cpt_has_ctx_fetch_issue(void) +{ + return roc_model_is_cn10kb(); +} + /* IPBUNIXRX-40400 */ static inline bool roc_errata_nix_no_meta_aura(void) diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h index b7fcdf9ba7..af2691e0eb 100644 --- a/drivers/common/cnxk/roc_ie_ot.h +++ b/drivers/common/cnxk/roc_ie_ot.h @@ -570,6 +570,9 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) == PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) == 31 * sizeof(uint64_t)); +#define ROC_OT_IPSEC_SA_SZ_MAX \ + (PLT_MAX(sizeof(struct roc_ot_ipsec_inb_sa), sizeof(struct roc_ot_ipsec_outb_sa))) + void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline); void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa); diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 2f85b2f755..f038d3e02b 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -2002,6 +2002,8 @@ struct cpt_lf_alloc_req_msg { uint16_t __io sso_pf_func; uint16_t __io eng_grpmsk; uint8_t __io blkaddr; + uint8_t __io ctx_ilen_valid : 1; + uint8_t __io ctx_ilen : 7; }; #define CPT_INLINE_INBOUND 0 @@ -2083,6 +2085,8 @@ struct cpt_rx_inline_lf_cfg_msg { uint32_t __io credit_th; uint16_t __io bpid; uint32_t __io reserved; + uint8_t __io ctx_ilen_valid : 1; + uint8_t __io ctx_ilen : 7; }; struct cpt_caps_rsp_msg { diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 16f858f561..5cb1f11f53 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -851,6 +851,11 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) nix->cpt_nixbpid = bpids[0]; cfg.bpid = nix->cpt_nixbpid; } + + if (roc_errata_cpt_has_ctx_fetch_issue()) { + cfg.ctx_ilen_valid = true; + cfg.ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1; + } } /* Do onetime Inbound Inline config in CPTPF */ @@ -931,7 +936,9 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) struct dev *dev = &nix->dev; struct msix_offset_rsp *rsp; struct nix_inl_dev *inl_dev; + bool ctx_ilen_valid = false; size_t sa_sz, ring_sz; + uint8_t ctx_ilen = 0; uint16_t sso_pffunc; uint8_t eng_grpmask; uint64_t blkaddr, i; @@ -967,12 +974,17 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix) return rc; } + if (!roc_model_is_cn9k() && roc_errata_cpt_has_ctx_fetch_issue()) { + ctx_ilen = (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ / 128) - 1; + ctx_ilen_valid = true; + } + /* Alloc CPT LF */ eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE | 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE | 1ULL << ROC_CPT_DFLT_ENG_GRP_AE); rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr, - !roc_nix->ipsec_out_sso_pffunc); + !roc_nix->ipsec_out_sso_pffunc, ctx_ilen_valid, ctx_ilen); if (rc) { plt_err("Failed to alloc CPT LF resources, rc=%d", rc); goto lf_detach; diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index d76158e30d..2863d5da51 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -176,7 +176,9 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso) { struct roc_cpt_lf *lf = &inl_dev->cpt_lf; struct dev *dev = &inl_dev->dev; + bool ctx_ilen_valid = false; uint8_t eng_grpmask; + uint8_t ctx_ilen = 0; int rc; if (!inl_dev->attach_cptlf) @@ -186,7 +188,13 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso) eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE | 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE | 1ULL << ROC_CPT_DFLT_ENG_GRP_AE); - rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso); + if (roc_errata_cpt_has_ctx_fetch_issue()) { + ctx_ilen = (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ / 128) - 1; + ctx_ilen_valid = true; + } + + rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, inl_dev_sso, ctx_ilen_valid, + ctx_ilen); if (rc) { plt_err("Failed to alloc CPT LF resources, rc=%d", rc); return rc; From patchwork Fri Aug 11 08:57:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130119 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D318843032; Fri, 11 Aug 2023 10:58:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D57564326D; Fri, 11 Aug 2023 10:58:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7989743271 for ; Fri, 11 Aug 2023 10:58:25 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2LhS011196 for ; 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Fri, 11 Aug 2023 01:58:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:22 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 877F63F706A; Fri, 11 Aug 2023 01:58:20 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 05/31] common/cnxk: support rate limit on PFC TM tree Date: Fri, 11 Aug 2023 14:27:39 +0530 Message-ID: <20230811085805.441256-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: abXP39VS7Av572sl-KKTR-Y0W6LVEyTt X-Proofpoint-GUID: abXP39VS7Av572sl-KKTR-Y0W6LVEyTt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao New SQ rate limit API to support SQ rate limit on PFC tree. In PFC tree each SQ had its one to one mapped TL3, this patch configures shaper rate on TL3. Also configures the TL2 with link rate. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix.h | 9 ++- drivers/common/cnxk/roc_nix_tm_ops.c | 98 ++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 106 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 9c2ba9a685..1d84f4de9d 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -707,8 +707,13 @@ int __roc_api roc_nix_tm_node_stats_get(struct roc_nix *roc_nix, /* * TM ratelimit tree API. */ -int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, - uint64_t rate); +int __roc_api roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate); + +/* + * TM PFC tree ratelimit API. + */ +int __roc_api roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate); + /* * TM hierarchy enable/disable API. */ diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 4e88ad1beb..e1cef7a670 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -1032,6 +1032,104 @@ roc_nix_tm_init(struct roc_nix *roc_nix) return rc; } +int +roc_nix_tm_pfc_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_tm_shaper_profile profile; + struct mbox *mbox = (&nix->dev)->mbox; + struct nix_tm_node *node, *parent; + struct roc_nix_link_info link_info; + + volatile uint64_t *reg, *regval; + struct nix_txschq_config *req; + uint64_t tl2_rate = 0; + uint16_t flags; + uint8_t k = 0; + int rc; + + if ((nix->tm_tree != ROC_NIX_TM_PFC) || !(nix->tm_flags & NIX_TM_HIERARCHY_ENA)) + return NIX_ERR_TM_INVALID_TREE; + + node = nix_tm_node_search(nix, qid, nix->tm_tree); + + /* check if we found a valid leaf node */ + if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent || + node->parent->hw_id == NIX_TM_HW_ID_INVALID) { + return NIX_ERR_TM_INVALID_NODE; + } + + /* Get the link Speed */ + if (roc_nix_mac_link_info_get(roc_nix, &link_info)) + return -EINVAL; + + if (link_info.status) + tl2_rate = link_info.speed * (uint64_t)1E6; + + /* Configure TL3 of leaf node with requested rate */ + parent = node->parent; /* SMQ/MDQ */ + parent = parent->parent; /* TL4 */ + parent = parent->parent; /* TL3 */ + flags = parent->flags; + + req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox)); + req->lvl = parent->hw_lvl; + reg = req->reg; + regval = req->regval; + + if (rate == 0) { + k += nix_tm_sw_xoff_prep(parent, true, ®[k], ®val[k]); + flags &= ~NIX_TM_NODE_ENABLED; + goto exit; + } + + if (!(flags & NIX_TM_NODE_ENABLED)) { + k += nix_tm_sw_xoff_prep(parent, false, ®[k], ®val[k]); + flags |= NIX_TM_NODE_ENABLED; + } + + /* Use only PIR for rate limit */ + memset(&profile, 0, sizeof(profile)); + profile.peak.rate = rate; + /* Minimum burst of ~4us Bytes of Tx */ + profile.peak.size = + PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix), (4ul * rate) / ((uint64_t)1E6 * 8)); + if (!nix->tm_rate_min || nix->tm_rate_min > rate) + nix->tm_rate_min = rate; + + k += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]); +exit: + req->num_regs = k; + rc = mbox_process(mbox); + mbox_put(mbox); + if (rc) + return rc; + + parent->flags = flags; + + /* If link is up then configure TL2 with link speed */ + if (tl2_rate && (flags & NIX_TM_NODE_ENABLED)) { + k = 0; + parent = parent->parent; + req = mbox_alloc_msg_nix_txschq_cfg(mbox_get(mbox)); + req->lvl = parent->hw_lvl; + reg = req->reg; + regval = req->regval; + + /* Use only PIR for rate limit */ + memset(&profile, 0, sizeof(profile)); + profile.peak.rate = tl2_rate; + /* Minimum burst of ~4us Bytes of Tx */ + profile.peak.size = PLT_MAX((uint64_t)roc_nix_max_pkt_len(roc_nix), + (4ul * tl2_rate) / ((uint64_t)1E6 * 8)); + k += nix_tm_shaper_reg_prep(parent, &profile, ®[k], ®val[k]); + req->num_regs = k; + rc = mbox_process(mbox); + mbox_put(mbox); + } + return rc; +} + int roc_nix_tm_rlimit_sq(struct roc_nix *roc_nix, uint16_t qid, uint64_t rate) { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8c71497df8..1436c90e12 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -379,6 +379,7 @@ INTERNAL { roc_nix_tm_node_suspend_resume; roc_nix_tm_prealloc_res; roc_nix_tm_pfc_prepare_tree; + roc_nix_tm_pfc_rlimit_sq; roc_nix_tm_prepare_rate_limited_tree; roc_nix_tm_rlimit_sq; roc_nix_tm_root_has_sp; From patchwork Fri Aug 11 08:57:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130120 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4995743032; Fri, 11 Aug 2023 10:58:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 088794326C; Fri, 11 Aug 2023 10:58:30 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6B39A43264 for ; Fri, 11 Aug 2023 10:58:28 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjx5O001610 for ; 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Fri, 11 Aug 2023 01:58:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:25 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 790183F706B; Fri, 11 Aug 2023 01:58:23 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rahul Bhansali Subject: [PATCH 06/31] common/cnxk: fixes CGX promisc toggling Date: Fri, 11 Aug 2023 14:27:40 +0530 Message-ID: <20230811085805.441256-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 6ZvSjBKVN55ZmGyW3spREuHB1xD0w9aC X-Proofpoint-GUID: 6ZvSjBKVN55ZmGyW3spREuHB1xD0w9aC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali This will allow CGX promisc toggling even when exact match feature is enabled. Also, In case of exact feature, CGX promisc enable/disable mbox response returns failure code -1101 in case if no change in the state. This failure code can be ignored and proceed further. Fixes: a90649722b51 ("common/cnxk: skip CGX promisc mode with NPC exact match") Signed-off-by: Rahul Bhansali --- drivers/common/cnxk/roc_dev.c | 13 ++++++++++++- drivers/common/cnxk/roc_mbox.h | 15 +++++++++++++++ drivers/common/cnxk/roc_nix_mac.c | 8 -------- 3 files changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index 4b0ba218ed..128b9751e4 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -451,7 +451,6 @@ process_msgs(struct dev *dev, struct mbox *mbox) * while PFC already configured on other VFs. This is * not an error but a warning which can be ignored. */ -#define LMAC_AF_ERR_PERM_DENIED -1103 if (msg->rc) { if (msg->rc == LMAC_AF_ERR_PERM_DENIED) { plt_mbox_dbg( @@ -464,6 +463,18 @@ process_msgs(struct dev *dev, struct mbox *mbox) } } break; + case MBOX_MSG_CGX_PROMISC_DISABLE: + case MBOX_MSG_CGX_PROMISC_ENABLE: + if (msg->rc) { + if (msg->rc == LMAC_AF_ERR_INVALID_PARAM) { + plt_mbox_dbg("Already in same promisc state"); + msg->rc = 0; + } else { + plt_err("Message (%s) response has err=%d", + mbox_id2name(msg->id), msg->rc); + } + } + break; default: if (msg->rc) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index f038d3e02b..2fd01cd710 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -540,6 +540,21 @@ struct lmtst_tbl_setup_req { }; /* CGX mbox message formats */ +/* CGX mailbox error codes + * Range 1101 - 1200. + */ +enum cgx_af_status { + LMAC_AF_ERR_INVALID_PARAM = -1101, + LMAC_AF_ERR_PF_NOT_MAPPED = -1102, + LMAC_AF_ERR_PERM_DENIED = -1103, + LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104, + LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105, + LMAC_AF_ERR_CMD_TIMEOUT = -1106, + LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107, + LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108, + LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109, + LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110, +}; struct cgx_stats_rsp { struct mbox_msghdr hdr; diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index 754d75ac73..ac30fb52d1 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -201,14 +201,6 @@ roc_nix_mac_promisc_mode_enable(struct roc_nix *roc_nix, int enable) goto exit; } - /* Skip CGX promisc toggling if NPC exact match is enabled as - * CGX filtering is disabled permanently. - */ - if (nix->exact_match_ena) { - rc = 0; - goto exit; - } - if (enable) mbox_alloc_msg_cgx_promisc_enable(mbox); else From patchwork Fri Aug 11 08:57:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130121 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53C4943032; Fri, 11 Aug 2023 10:58:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 103BB4326B; Fri, 11 Aug 2023 10:58:34 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B6EB843264 for ; Fri, 11 Aug 2023 10:58:31 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjlII001539 for ; Fri, 11 Aug 2023 01:58:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0BAAJRz+raby09RtKWnl0VAEVe7N6Xmt+TdWOZRvX64=; b=CPTuRw88/yqsvavXJc7c/8ClKwSoQW3YPuW2gCwXqlcsV9gygalTrkRoTOIyex2wDnFU R2z4/Ki1qNP+1SRf/pJN+sf1C1HeQ25xrqaKL0CzOkchrEhDaHNA8HELqxIEMPe0Tl6e M4K2FOy6ozYAzbAKoryEOtAz34YyiwXw4RIn4GoyVu2D+Ed4vhG5AryCt39kxjZVoZL5 HbSTpKXUS4CcfD1XgQHbo3OKDLUY0do9nUFbPB+GCZhsYyPr5fvIlWiozz2iOm5Ga09X HqnZWKriHAQyOOcuoBy3WV3Ap6DhU/0ZFwBUiBEyylnparyDa4yf9jaGlUbWAk47PuB+ pA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r6m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:29 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A86853F706A; Fri, 11 Aug 2023 01:58:26 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH 07/31] common/cnxk: fix xstats for different packet sizes Date: Fri, 11 Aug 2023 14:27:41 +0530 Message-ID: <20230811085805.441256-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: VmKHmoqNOZSK5oF1nohLFq99i7qvsohe X-Proofpoint-GUID: VmKHmoqNOZSK5oF1nohLFq99i7qvsohe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla xstats for transmitted packets with different sizes are not updated as sizeof mbox response structure are different in dpdk and kernel.This patch fixes the same. Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions") Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/roc_mbox.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 2fd01cd710..169bbcb664 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -558,7 +558,7 @@ enum cgx_af_status { struct cgx_stats_rsp { struct mbox_msghdr hdr; -#define CGX_RX_STATS_COUNT 13 +#define CGX_RX_STATS_COUNT 9 #define CGX_TX_STATS_COUNT 18 uint64_t __io rx_stats[CGX_RX_STATS_COUNT]; uint64_t __io tx_stats[CGX_TX_STATS_COUNT]; From patchwork Fri Aug 11 08:57:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130122 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2AD5E43032; Fri, 11 Aug 2023 10:58:58 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2234C43269; Fri, 11 Aug 2023 10:58:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8602343275 for ; Fri, 11 Aug 2023 10:58:34 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjx5Q001610 for ; Fri, 11 Aug 2023 01:58:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2HkxTBem3DVl6hATeJbITshVI9QigA/OT+5OgID5AOQ=; b=e6+ExVaScheQsnRsMKDe7gk5ve8NzowjLJC1zut3ppnPI9Kw6knv6VNzXKLYmOMblhPw 6+bRQQXSYBlfwQkZXoLTljCobIVRHFEvSKV9PjCd/HZurqroP1aa2Ik/krpxrSrLTNl6 59EOVfyenXiJ9XzCraz12BWJp065aCuGeBOX+JaBrOa157X1FCzEjvmrDn1LYoIQ7QZQ xl9+PYLUp0GJNpnPG+qp6mDCBY7n53vHXwhJGS3BmhsToJ5EyXFXn0BMqTwjEju8dPBj cf8PAIZEO4PRF/tuuMJt5YcO6jFUYKIZQenh3uRJYQ9u0Ez8DC+9KPcOTEKXr0PBU4PC 5Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r6t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:33 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:32 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D97E73F706B; Fri, 11 Aug 2023 01:58:29 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 08/31] common/cnxk: disable BP on SDP link while closing SQ Date: Fri, 11 Aug 2023 14:27:42 +0530 Message-ID: <20230811085805.441256-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: feWx17d2rl7LmgtZQsR0UvrlgJJncTX4 X-Proofpoint-GUID: feWx17d2rl7LmgtZQsR0UvrlgJJncTX4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Host SDP port closes the SDP link on NIX causes crash when BP enabled on SDP link. This patch disables BP on SDP link when SQ flush fails due to link disabled at host. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_tm.c | 73 ++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index c104611355..ce1e44ac4f 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -610,8 +610,6 @@ roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq) return 0; exit: - roc_nix_tm_dump(sq->roc_nix, NULL); - roc_nix_queues_ctx_dump(sq->roc_nix, NULL); return -EFAULT; } @@ -748,6 +746,70 @@ roc_nix_tm_sq_free_pending_sqe(struct nix *nix, int q) return 0; } +static inline int +nix_tm_sdp_sq_drop_pkts(struct roc_nix *roc_nix, struct roc_nix_sq *sq) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = mbox_get((&nix->dev)->mbox); + struct nix_txschq_config *req = NULL, *rsp; + enum roc_nix_tm_tree tree = nix->tm_tree; + int rc = 0, qid = sq->qid; + struct nix_tm_node *node; + uint64_t regval; + + /* Find the node for this SQ */ + node = nix_tm_node_search(nix, qid, tree); + while (node) { + if (node->hw_lvl != NIX_TXSCH_LVL_TL4) { + node = node->parent; + continue; + } + break; + } + if (!node) { + plt_err("Invalid node/state for sq %u", qid); + return -EFAULT; + } + + /* Get present link config */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->read = 1; + req->lvl = NIX_TXSCH_LVL_TL4; + req->reg[0] = NIX_AF_TL4X_SDP_LINK_CFG(node->hw_id); + req->num_regs = 1; + rc = mbox_process_msg(mbox, (void **)&rsp); + if (rc || rsp->num_regs != 1) + goto err; + regval = rsp->regval[0]; + /* Disable BP_ENA in SDP link config */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = NIX_TXSCH_LVL_TL4; + req->reg[0] = NIX_AF_TL4X_SDP_LINK_CFG(node->hw_id); + req->regval[0] = 0x0ull; + req->regval_mask[0] = ~(BIT_ULL(13)); + req->num_regs = 1; + rc = mbox_process(mbox); + if (rc) + goto err; + mbox_put(mbox); + /* Flush SQ to drop all packets */ + rc = roc_nix_tm_sq_flush_spin(sq); + if (rc) + plt_nix_dbg("SQ flush failed with link reset config rc %d", rc); + mbox = mbox_get((&nix->dev)->mbox); + /* Restore link config */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->reg[0] = NIX_AF_TL4X_SDP_LINK_CFG(node->hw_id); + req->lvl = NIX_TXSCH_LVL_TL4; + req->regval[0] = regval; + req->regval_mask[0] = ~(BIT_ULL(13) | BIT_ULL(12) | GENMASK_ULL(7, 0)); + req->num_regs = 1; + rc = mbox_process(mbox); +err: + mbox_put(mbox); + return rc; +} + /* Flush and disable tx queue and its parent SMQ */ int nix_tm_sq_flush_pre(struct roc_nix_sq *sq) @@ -834,8 +896,13 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq) /* Wait for sq entries to be flushed */ rc = roc_nix_tm_sq_flush_spin(sq); if (rc) { - rc = roc_nix_tm_sq_free_pending_sqe(nix, sq->qid); + if (nix->sdp_link) + rc = nix_tm_sdp_sq_drop_pkts(roc_nix, sq); + else + rc = roc_nix_tm_sq_free_pending_sqe(nix, sq->qid); if (rc) { + roc_nix_tm_dump(sq->roc_nix, NULL); + roc_nix_queues_ctx_dump(sq->roc_nix, NULL); plt_err("Failed to drain sq %u, rc=%d\n", sq->qid, rc); return rc; } From patchwork Fri Aug 11 08:57:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130123 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A3EB843032; Fri, 11 Aug 2023 10:59:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 443184327B; Fri, 11 Aug 2023 10:58:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 013B840E03 for ; Fri, 11 Aug 2023 10:58:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMj86q014471 for ; Fri, 11 Aug 2023 01:58:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; 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Fri, 11 Aug 2023 01:58:35 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C45523F706D; Fri, 11 Aug 2023 01:58:32 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 09/31] common/cnxk: fix leak in error path Date: Fri, 11 Aug 2023 14:27:43 +0530 Message-ID: <20230811085805.441256-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: NPxWJefJOc6Ozjne4G_Pj7IzYxrvxBLh X-Proofpoint-GUID: NPxWJefJOc6Ozjne4G_Pj7IzYxrvxBLh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal Fixed resource leak when pthread create fails in dev_init(). Fixes: 1c7a4d37e73d ("common/cnxk: fix mailbox timeout due to deadlock") Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_dev.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c index 128b9751e4..18d7981825 100644 --- a/drivers/common/cnxk/roc_dev.c +++ b/drivers/common/cnxk/roc_dev.c @@ -1472,7 +1472,7 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev) pf_vf_mbox_thread_main, dev); if (rc != 0) { plt_err("Failed to create thread for VF mbox handling\n"); - goto iounmap; + goto thread_fail; } } @@ -1500,9 +1500,10 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev) dev->sync.start_thread = false; pthread_cond_signal(&dev->sync.pfvf_msg_cond); pthread_join(dev->sync.pfvf_msg_thread, NULL); - pthread_mutex_destroy(&dev->sync.mutex); - pthread_cond_destroy(&dev->sync.pfvf_msg_cond); } +thread_fail: + pthread_mutex_destroy(&dev->sync.mutex); + pthread_cond_destroy(&dev->sync.pfvf_msg_cond); iounmap: dev_vf_mbase_put(pci_dev, vf_mbase); mbox_unregister: From patchwork Fri Aug 11 08:57:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130124 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F202843032; Fri, 11 Aug 2023 10:59:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 40A9043257; Fri, 11 Aug 2023 10:58:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 15CA34327D for ; Fri, 11 Aug 2023 10:58:40 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMkPcv002990 for ; Fri, 11 Aug 2023 01:58:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=MZzo9FvZSfJzKAYrd6S86bUWu1cK99t/v4lCuXWkoAU=; b=g/6NBgEOD5dALq6jPLtf9XYHb6h98T3XiUgp8k/fehaKRlCBB+fkZ5XPb3IfYx0mFDag u8G8/vHIuYgFrlYQDEr0ZffYE7NTWeYK3PDyMgNkU+sQm06Khl6GEXabdLu/myj31iwW 7Dpp2dPW7DHqSK48Mp32KPmwA6xoBuQcivfrgwQkKnvTG8rkmKzV/Et4uRp6yWX6jFE3 PHqLPDCLJCj7wkrhUZ9IX2mlJT77of8E214zUmCnquNYKSkrCnObVncgd1XkC+zhb1xP AZMg6shM4KZYVoXZwpFnBJpartu3Bllqoh3U+8A+WtH3g1FoyOBWRs5DAveDrETKvZ5g LA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r7k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:38 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0966F3F706A; Fri, 11 Aug 2023 01:58:35 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 10/31] common/cnxk: fix different size bit operations Date: Fri, 11 Aug 2023 14:27:44 +0530 Message-ID: <20230811085805.441256-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: _jvUktsMx_XjZnKux4xoNlZtI-Eid4Eh X-Proofpoint-GUID: _jvUktsMx_XjZnKux4xoNlZtI-Eid4Eh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal WORD_SIZE is made as unsigned long long so that bit operations are done on same size of variables. Fixes: 1ec23c7523b4 ("common/cnxk: support anti-replay check in SW for cn9k") Signed-off-by: Akhil Goyal --- drivers/common/cnxk/cnxk_security_ar.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/cnxk/cnxk_security_ar.h b/drivers/common/cnxk/cnxk_security_ar.h index deb38db0d0..d0151a752c 100644 --- a/drivers/common/cnxk/cnxk_security_ar.h +++ b/drivers/common/cnxk/cnxk_security_ar.h @@ -17,7 +17,7 @@ BITS_PER_LONG_LONG) #define WORD_SHIFT 6 -#define WORD_SIZE (1 << WORD_SHIFT) +#define WORD_SIZE (1ULL << WORD_SHIFT) #define WORD_MASK (WORD_SIZE - 1) #define IPSEC_ANTI_REPLAY_FAILED (-1) From patchwork Fri Aug 11 08:57:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130125 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7F2843032; Fri, 11 Aug 2023 10:59:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9FC0343264; Fri, 11 Aug 2023 10:58:45 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7000F4325B for ; Fri, 11 Aug 2023 10:58:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WUx011282 for ; Fri, 11 Aug 2023 01:58:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=pqXvvDC+iMQazmEz6MuhwBCFT66XejZO6PtUNrpq4M0=; b=IFmG8TtvFIAAvMF3J5we8ScUb8j7+eqO9I/p5N9kh94JYYD734mRJR/CF16dIDmWw9Z7 GBXZnJcWgm8LG4WpDUYT1QYechiFP448W3Njhc5efzaokIPI5IrV7mSKrbKNcfzmw2av SN5KVYCUnq1V7yz8IsSGAe5CwoOwabwYdYLs1TPSimF2SkkCDmFcfWHDETmVQgiof9D3 UzHGMlwRW/s1X5FOwc6uxFRdecGcnWZcgHcjB0HgKCyTmhi6BIjz5xyKxw7xvu9YplS4 pz02OdsPKTO6lE2Plgf0fnj8dUU7z/vGwtdAUfMuF3jNGCKrM4aChS2zLoxmy5Uv+rNe hA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1g94-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:41 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 422FB3F706B; Fri, 11 Aug 2023 01:58:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 11/31] common/cnxk: fix different size bit operations Date: Fri, 11 Aug 2023 14:27:45 +0530 Message-ID: <20230811085805.441256-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5ehsOj5gRgm73uh2M4YcOMktA8Gz4isX X-Proofpoint-GUID: 5ehsOj5gRgm73uh2M4YcOMktA8Gz4isX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal Bitwise or is being done on relchan which is 32 bit, but the result is 64 bit, hence typecast to uint64_t. Fixes: 8f867a87b9c5 ("common/cnxk: enable SDP channel backpressure to TL4") Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable") Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_nix_tm_utils.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 3840d6d457..ce26ddff50 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -588,7 +588,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq); regval[k] = BIT_ULL(12); regval[k] |= BIT_ULL(13); - regval[k] |= relchan; + regval[k] |= (uint64_t)relchan; k++; } break; @@ -606,7 +606,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, if (!nix->sdp_link && nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) { reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); - regval[k] = BIT_ULL(12) | relchan; + regval[k] = BIT_ULL(12) | (uint64_t)relchan; k++; } @@ -625,7 +625,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, if (!nix->sdp_link && nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) { reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); - regval[k] = BIT_ULL(12) | relchan; + regval[k] = BIT_ULL(12) | (uint64_t)relchan; k++; } From patchwork Fri Aug 11 08:57:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130126 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4953843032; Fri, 11 Aug 2023 10:59:24 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BEADE4327D; Fri, 11 Aug 2023 10:58:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 8583C4327D for ; Fri, 11 Aug 2023 10:58:47 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMj86v014471 for ; Fri, 11 Aug 2023 01:58:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=bP8bmSUkKTCb806p3hJVR4+dQUbmgAF3OBavbArNFCo=; b=RiVcirto9ZQnsif9LDYfFseIgeLaoC1KliBXxoO0teXa7xobGufRBntes3j2u/WIn490 DQjEbGhGPSLPYludHvJLRWnb8rwjisdb5edoWUP5RpLfiYRs1Vu8TO9HiVEQHIZ3qIHb I9pFojCyTTQQVIFh4RDVU7hWTjGxVpvN4Ohaz52uZXJlcDedGVssjyMti+c6AxC/sQx2 yeXMaX5Ivshp+ESWL5op620uK237vlIb+AXsPNTBjBX4ZR9634spejB8QVqQ9touaVTj v23odUsgd3/16Es+hE0AITrPZe1HnCiHOi1xTAAwVDh9nCzWVQJll+KlS0Yp7AoP9+4n Dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1g99-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:58:46 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:44 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:44 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 708A53F706A; Fri, 11 Aug 2023 01:58:42 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 12/31] common/cnxk: remove unnecessory ROC API calls Date: Fri, 11 Aug 2023 14:27:46 +0530 Message-ID: <20230811085805.441256-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: dB5K_D72nl_vAVXeWVx62xi2-GTtBW1Q X-Proofpoint-GUID: dB5K_D72nl_vAVXeWVx62xi2-GTtBW1Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal Removed the calls to roc_nix_num_rx[tx]_xstats which does a model check again for cn9k/cn10k. The model check is already done before the call in the same leg, hence not needed to call these APIs. Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_nix_stats.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c index 1e93191a07..7a9619b39d 100644 --- a/drivers/common/cnxk/roc_nix_stats.c +++ b/drivers/common/cnxk/roc_nix_stats.c @@ -400,14 +400,14 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats, if (rc) goto exit; - for (i = 0; i < roc_nix_num_rx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_CGX; i++) { xstats[count].value = cgx_resp->rx_stats[nix_rx_xstats_cgx[i].offset]; xstats[count].id = count; count++; } - for (i = 0; i < roc_nix_num_tx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_CGX; i++) { xstats[count].value = cgx_resp->tx_stats[nix_tx_xstats_cgx[i].offset]; xstats[count].id = count; @@ -426,14 +426,14 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats, if (rc) goto exit; - for (i = 0; i < roc_nix_num_rx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_RPM; i++) { xstats[count].value = rpm_resp->rx_stats[nix_rx_xstats_rpm[i].offset]; xstats[count].id = count; count++; } - for (i = 0; i < roc_nix_num_tx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_RPM; i++) { xstats[count].value = rpm_resp->tx_stats[nix_tx_xstats_rpm[i].offset]; xstats[count].id = count; @@ -504,26 +504,26 @@ roc_nix_xstats_names_get(struct roc_nix *roc_nix, return count; if (roc_model_is_cn9k()) { - for (i = 0; i < roc_nix_num_rx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_CGX; i++) { NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats_cgx, i); count++; } - for (i = 0; i < roc_nix_num_tx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_CGX; i++) { NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats_cgx, i); count++; } } else { - for (i = 0; i < roc_nix_num_rx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_RPM; i++) { NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats_rpm, i); count++; } - for (i = 0; i < roc_nix_num_tx_xstats(); i++) { + for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_RPM; i++) { NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats_rpm, i); count++; From patchwork Fri Aug 11 08:57:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130127 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3088F43032; Fri, 11 Aug 2023 10:59:30 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E90164328A; Fri, 11 Aug 2023 10:58:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D1F9D4325C for ; Fri, 11 Aug 2023 10:58:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2MC1011226 for ; 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Fri, 11 Aug 2023 01:58:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:48 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A75CB3F706B; Fri, 11 Aug 2023 01:58:45 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Srujana Challa Subject: [PATCH 13/31] common/cnxk: sync MAC addr set mailbox structure Date: Fri, 11 Aug 2023 14:27:47 +0530 Message-ID: <20230811085805.441256-13-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: FATWfWEEwCMwFpyZvq4W3C1kAyVOVIdE X-Proofpoint-GUID: FATWfWEEwCMwFpyZvq4W3C1kAyVOVIdE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Sync MAC address set mailbox format with kernel. And send match table index to the kernel to add the mac address. This fixes the issues on cn10kb, where traffic was not received when promisc is disabled and two ports are used. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_mbox.h | 1 + drivers/common/cnxk/roc_nix.c | 1 + drivers/common/cnxk/roc_nix_mac.c | 8 ++++++-- drivers/common/cnxk/roc_nix_priv.h | 1 + 4 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 169bbcb664..04fc56465e 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -584,6 +584,7 @@ struct cgx_fec_stats_rsp { struct cgx_mac_addr_set_or_get { struct mbox_msghdr hdr; uint8_t __io mac_addr[PLT_ETHER_ADDR_LEN]; + uint32_t index; }; /* Structure for requesting the operation to diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 152ef7269e..498328d6ed 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -475,6 +475,7 @@ roc_nix_dev_init(struct roc_nix *roc_nix) nix->pci_dev = pci_dev; nix->reta_sz = reta_sz; nix->mtu = ROC_NIX_DEFAULT_HW_FRS; + nix->dmac_flt_idx = -1; /* Register error and ras interrupts */ rc = nix_register_irqs(nix); diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index ac30fb52d1..e2e87be525 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -81,9 +81,9 @@ int roc_nix_mac_addr_set(struct roc_nix *roc_nix, const uint8_t addr[]) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct cgx_mac_addr_set_or_get *req, *rsp; struct dev *dev = &nix->dev; struct mbox *mbox = mbox_get(dev->mbox); - struct cgx_mac_addr_set_or_get *req; int rc; if (roc_nix_is_vf_or_sdp(roc_nix)) { @@ -97,9 +97,13 @@ roc_nix_mac_addr_set(struct roc_nix *roc_nix, const uint8_t addr[]) } req = mbox_alloc_msg_cgx_mac_addr_set(mbox); + req->index = nix->dmac_flt_idx; mbox_memcpy(req->mac_addr, addr, PLT_ETHER_ADDR_LEN); - rc = mbox_process(mbox); + rc = mbox_process_msg(mbox, (void *)&rsp); + if (rc) + goto exit; + nix->dmac_flt_idx = rsp->index; exit: mbox_put(mbox); return rc; diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index ea4211dfed..f82e411b70 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -153,6 +153,7 @@ struct nix { uint8_t sdp_links; uint8_t tx_link; uint16_t sqb_size; + uint32_t dmac_flt_idx; /* Without FCS, with L2 overhead */ uint16_t mtu; uint16_t chan_cnt; From patchwork Fri Aug 11 08:57:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130128 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A75043032; Fri, 11 Aug 2023 10:59:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A0BE4325D; Fri, 11 Aug 2023 10:58:56 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 0AFED43260 for ; Fri, 11 Aug 2023 10:58:53 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN18uL008578 for ; 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Fri, 11 Aug 2023 01:58:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:51 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id DDB423F706A; Fri, 11 Aug 2023 01:58:48 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rahul Bhansali Subject: [PATCH 14/31] common/cnxk: add API to get Rx chan count from NIX Date: Fri, 11 Aug 2023 14:27:48 +0530 Message-ID: <20230811085805.441256-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ng-Ci6nsVZPov9Y9EFeG8-N2FQCwTxQ6 X-Proofpoint-GUID: ng-Ci6nsVZPov9Y9EFeG8-N2FQCwTxQ6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali For SDP, provide an API to get Rx chan count from NIX as all channels are always active. Signed-off-by: Rahul Bhansali --- drivers/common/cnxk/roc_nix.c | 8 ++++++++ drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/version.map | 1 + 3 files changed, 10 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 498328d6ed..f64933a1d9 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -21,6 +21,14 @@ roc_nix_get_base_chan(struct roc_nix *roc_nix) return nix->rx_chan_base; } +uint8_t +roc_nix_get_rx_chan_cnt(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + + return nix->rx_chan_cnt; +} + uint16_t roc_nix_get_vwqe_interval(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 1d84f4de9d..377b9604ea 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -527,6 +527,7 @@ bool __roc_api roc_nix_is_sdp(struct roc_nix *roc_nix); bool __roc_api roc_nix_is_pf(struct roc_nix *roc_nix); bool __roc_api roc_nix_is_vf_or_sdp(struct roc_nix *roc_nix); int __roc_api roc_nix_get_base_chan(struct roc_nix *roc_nix); +uint8_t __roc_api roc_nix_get_rx_chan_cnt(struct roc_nix *roc_nix); int __roc_api roc_nix_get_pf(struct roc_nix *roc_nix); int __roc_api roc_nix_get_vf(struct roc_nix *roc_nix); uint16_t __roc_api roc_nix_get_pf_func(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 1436c90e12..f2df099ad4 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -214,6 +214,7 @@ INTERNAL { roc_nix_get_base_chan; roc_nix_get_pf; roc_nix_get_pf_func; + roc_nix_get_rx_chan_cnt; roc_nix_get_vf; roc_nix_get_vwqe_interval; roc_nix_inl_cb_register; From patchwork Fri Aug 11 08:57:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130129 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D13D743032; 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Fri, 11 Aug 2023 01:58:55 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:58:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:58:54 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 1A53E3F706B; Fri, 11 Aug 2023 01:58:51 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 15/31] common/cnxk: fix BP threshold calculation Date: Fri, 11 Aug 2023 14:27:49 +0530 Message-ID: <20230811085805.441256-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5yUG4ojwWWu2G0dDygj5oiBapaOtv4q2 X-Proofpoint-GUID: 5yUG4ojwWWu2G0dDygj5oiBapaOtv4q2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Current macro to calculate BP threshold were evaluating incorrect threshold because aura_limit is first shifted by shift then percentage is calculated. While first percentage should be calculated and the resultant should be shifted by shift. So formula is updated accordingly. Fixes: cb4bfd6e7bdf ("event/cnxk: support Rx adapter") Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix_fc.c | 2 +- drivers/common/cnxk/roc_nix_priv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index d58b35268e..0f9b5cbbc0 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -496,7 +496,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui aura_attr = &lf->aura_attr[aura_id]; bp_intf = 1 << nix->is_nix1; - bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift); + bp_thresh = NIX_RQ_AURA_BP_THRESH(drop_percent, aura_attr->limit, aura_attr->shift); bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid; /* BP is already enabled. */ diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index f82e411b70..a582b9df33 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -20,7 +20,7 @@ /* Apply LBP at 75% of actual BP */ #define NIX_CQ_LPB_THRESH_FRAC (75 * 16 / 100) #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) -#define NIX_RQ_AURA_THRESH(percent, val) (((val) * (percent)) / 100) +#define NIX_RQ_AURA_BP_THRESH(percent, limit, shift) ((((limit) * (percent)) / 100) >> (shift)) /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */ #define CQ_CQE_THRESH_DEFAULT 0x1ULL From patchwork Fri Aug 11 08:57:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130130 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C23AD43032; Fri, 11 Aug 2023 10:59:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 529A943288; Fri, 11 Aug 2023 10:59:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E3C1F43287 for ; Fri, 11 Aug 2023 10:58:59 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMj870014471 for ; Fri, 11 Aug 2023 01:58:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; 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Fri, 11 Aug 2023 01:58:57 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0394F3F706A; Fri, 11 Aug 2023 01:58:54 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 16/31] common/cnxk: allow same TC on multiple RQs Date: Fri, 11 Aug 2023 14:27:50 +0530 Message-ID: <20230811085805.441256-16-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: bip1VuPZIF4dnAE-OXcGBc0Cf3kW0PTf X-Proofpoint-GUID: bip1VuPZIF4dnAE-OXcGBc0Cf3kW0PTf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori To achieve actual PFC behavior, user needs to configure different TC on different aura so that PFC can be generated for specific TC but same TC can also configured on multiple RQs which has same configured aura. In this patch, aura with same BP configuration is allowed on multiple RQs. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix_fc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 0f9b5cbbc0..2a58567751 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -501,7 +501,6 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid; /* BP is already enabled. */ if (aura_attr->bp_ena && ena) { - /* Disable BP if BPIDs don't match and couldn't add new BPID. */ if (bpid != nix->bpid[tc]) { uint16_t bpid_new = NIX_BPID_INVALID; @@ -519,15 +518,13 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64, roc_nix->port_id, tc, pool_id); } + } else { + aura_attr->ref_count++; } return; } - /* BP was previously enabled but now disabled skip. */ - if (aura_attr->bp && ena) - return; - if (ena) { if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true)) plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id); From patchwork Fri Aug 11 08:57:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130131 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3162C43032; Fri, 11 Aug 2023 10:59:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CEF604324E; Fri, 11 Aug 2023 10:59:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A02DF43293 for ; Fri, 11 Aug 2023 10:59:02 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMk3fg002130 for ; Fri, 11 Aug 2023 01:59:01 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=AryHH6F24PP4iQQsNyXVHNeb0Rr0/6HNr/XXhSKb41M=; b=VFs+5XP455OdM5pWQAKL3hvDy3KAy7T72xYMIB1eHFZ35X9NS5ZZ7GxVbkrfeDJfPFNs GzwQyByKyeNqFWxdKI/wWRPA6G/NcKwCcioLKeHh3WXl3MnZMzIjPMaZAylcH3SaBT2u +MmppwUiquvm3j27nLn/K8IdhKwPGtNdiqa5dkeBNmYDo7uzDi5aGXo2CcMVedzfG1rH vcCE4j+9lm5058d6xenrvF0Y3geQSUfIu2qeOFOGUzjD+pkrJF6L8NK3c7rKpJ5272iG Snj0lrb9mVLBnxLG3ij39nfe3WBqYyAWK8lVnFO110RfbP50EQKJ4sXCLZhWUJEGJta2 zw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9r9e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:00 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E16AD3F706B; Fri, 11 Aug 2023 01:58:57 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 17/31] common/cnxk: expose different params for bp config Date: Fri, 11 Aug 2023 14:27:51 +0530 Message-ID: <20230811085805.441256-17-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: CkpUZa0i8-jbgdD4bP89YUwuyhzYVZ2D X-Proofpoint-GUID: CkpUZa0i8-jbgdD4bP89YUwuyhzYVZ2D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Currently same bp percentage is applied on SPB and LPB pool but both pools can be configured with different bp level. Added one more parameter so that separate threshold parameters can be passed for SPB and LPB pools. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix.h | 3 ++- drivers/common/cnxk/roc_nix_fc.c | 14 +++++++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 377b9604ea..bb55fbe971 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -196,10 +196,11 @@ struct roc_nix_fc_cfg { uint32_t rq; uint16_t tc; uint16_t cq_drop; - bool enable; uint64_t pool; uint64_t spb_pool; uint64_t pool_drop_pct; + uint64_t spb_pool_drop_pct; + bool enable; } rq_cfg; struct { diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 2a58567751..12bfb9816b 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -282,8 +282,8 @@ static int nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); + uint64_t pool_drop_pct, spb_pool_drop_pct; struct roc_nix_fc_cfg tmp; - uint64_t pool_drop_pct; struct roc_nix_rq *rq; int rc; @@ -295,14 +295,18 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg) if (fc_cfg->rq_cfg.enable && !pool_drop_pct) pool_drop_pct = ROC_NIX_AURA_THRESH; - roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, - fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, - fc_cfg->rq_cfg.tc, pool_drop_pct); + roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.pool, fc_cfg->rq_cfg.enable, + roc_nix->force_rx_aura_bp, fc_cfg->rq_cfg.tc, pool_drop_pct); if (rq->spb_ena) { + spb_pool_drop_pct = fc_cfg->rq_cfg.spb_pool_drop_pct; + /* Use default value for zero pct */ + if (!spb_pool_drop_pct) + spb_pool_drop_pct = ROC_NIX_AURA_THRESH; + roc_nix_fc_npa_bp_cfg(roc_nix, fc_cfg->rq_cfg.spb_pool, fc_cfg->rq_cfg.enable, roc_nix->force_rx_aura_bp, - fc_cfg->rq_cfg.tc, pool_drop_pct); + fc_cfg->rq_cfg.tc, spb_pool_drop_pct); } if (roc_nix->local_meta_aura_ena && roc_nix->meta_aura_handle) From patchwork Fri Aug 11 08:57:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130132 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C92543032; Fri, 11 Aug 2023 11:00:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00C9843293; Fri, 11 Aug 2023 10:59:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 19CE043293 for ; Fri, 11 Aug 2023 10:59:06 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2clb011369 for ; Fri, 11 Aug 2023 01:59:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=0KnPYzwId2TWsriSwu3JhAFQHExGq7Fn72COmjYhevU=; b=V3uYphoxkPUnqgwOcrkSQJDPUYC56Ht0f2N2u/Av1QZZHnL/XQqv1WuQjvb+GnjW7pKr njbrDDq0BPNdtV6jK1vQC42isbXDeUTYchgk4gY6h3uVc4gDBbg1pO38/nSGqZzv1Vrb isto3m9AZcNkUuoNw2ET1VEdsWrcXwiweolIcRhxskZyENHlS1j8R7FSxE9Bxi66LfrY VnJQjaK1z6g/DWT/ohnZPUZh1oTwLA+r7o+L+J/qymdmzRrR61hAqXwojdsPyMCNRklf 0iZoRt3SrRxaLHltnwop5W85MIPilrov8fyYaX6ZB0tLmsdo6nQ0UEdsjxH0UABQoJiW nw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1gar-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:05 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:03 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D218F3F706A; Fri, 11 Aug 2023 01:59:00 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Kommula Shiva Shankar Subject: [PATCH 18/31] common/cnxk: enable CQ stashing Date: Fri, 11 Aug 2023 14:27:52 +0530 Message-ID: <20230811085805.441256-18-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 9gjCBmmE-m-MdkU_dE2RbonPRp_eEc6x X-Proofpoint-GUID: 9gjCBmmE-m-MdkU_dE2RbonPRp_eEc6x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kommula Shiva Shankar This patch enables CQ stashing for better CQE processing performance Signed-off-by: Kommula Shiva Shankar --- drivers/common/cnxk/roc_features.h | 6 ++++++ drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 7 +++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h index 815f800e7a..a461ca46c5 100644 --- a/drivers/common/cnxk/roc_features.h +++ b/drivers/common/cnxk/roc_features.h @@ -46,6 +46,12 @@ roc_feature_nix_has_reass(void) return roc_model_is_cn10ka(); } +static inline bool +roc_feature_nix_has_cqe_stash(void) +{ + return roc_model_is_cn10ka_b0(); +} + static inline bool roc_feature_nix_has_rxchan_multi_bpid(void) { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index bb55fbe971..5892de6b24 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -368,6 +368,7 @@ struct roc_nix_cq { /* Input parameters */ uint16_t qid; uint32_t nb_desc; + uint8_t stash_thresh; /* End of Input parameters */ uint16_t drop_thresh; struct roc_nix *roc_nix; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 5e689d08be..f96d5c3a96 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -908,6 +908,13 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) } cq_ctx->bp = cq->drop_thresh; + if (roc_feature_nix_has_cqe_stash()) { + if (cq_ctx->caching) { + cq_ctx->stashing = 1; + cq_ctx->stash_thresh = cq->stash_thresh; + } + } + rc = mbox_process(mbox); mbox_put(mbox); if (rc) From patchwork Fri Aug 11 08:57:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130133 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E415E43032; Fri, 11 Aug 2023 11:00:05 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 403F343261; Fri, 11 Aug 2023 10:59:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B05A442D3F for ; Fri, 11 Aug 2023 10:59:10 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjl8H001550 for ; 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Fri, 11 Aug 2023 01:59:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:06 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0BFDB3F706B; Fri, 11 Aug 2023 01:59:03 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Pavan Nikhilesh Subject: [PATCH 19/31] common/cnxk: fix incorrect aura ID Date: Fri, 11 Aug 2023 14:27:53 +0530 Message-ID: <20230811085805.441256-19-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: izaLVkHd-hQC3RBp_1mndJqEzN9otEfw X-Proofpoint-GUID: izaLVkHd-hQC3RBp_1mndJqEzN9otEfw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh The function `sso_hwgrp_alloc_xaq` expects aura ID, fix incorrectly passing aura handle to it. Fixes: 7e9a94909eea ("common/cnxk: realloc inline device XAQ AURA") Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_nix_inl_dev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 2863d5da51..de3498a4f7 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -678,7 +678,8 @@ roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle) } /* Setup xaq for hwgrps */ - rc = sso_hwgrp_alloc_xaq(&inl_dev->dev, inl_dev->xaq.aura_handle, 1); + rc = sso_hwgrp_alloc_xaq(&inl_dev->dev, + roc_npa_aura_handle_to_aura(inl_dev->xaq.aura_handle), 1); if (rc) { plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc); return rc; From patchwork Fri Aug 11 08:57:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130134 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8E76843032; Fri, 11 Aug 2023 11:00:11 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5195643296; Fri, 11 Aug 2023 10:59:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4C67943273 for ; Fri, 11 Aug 2023 10:59:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjx5e001610 for ; Fri, 11 Aug 2023 01:59:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=OLgRfEdjQ6y7bRjd5iHVG4Wte1g7joYmyT9Y3UoQ3oM=; b=ct2DkV1qGibDD6wCWXMXQu9ud/lW9Q21LuSvZ72t63tRANBNA95ih8mdH1ERr+KS26xU 8niJ5xvsq6jAK1XzYMRO8Zg/QO1dW7JN/VsMumLkDNxtqjZYcEANI5tIZr6Bhlx52zOS +gm/Sd27g3DqjaKjzwfSRiB4NkHctmhox7JAe637mejC5P0A1Soj4szY6pYao7eBd8sD y9rh98swpKwXuUTus5Rl3NOtUxEg38P67oSqw8+iidgXMDh8/Gieu7L+HI9b3YkBCvNg rGZtzXOosxRA5Mw8tQ5Ih3mvrn13K/IjzZB7pK+ANfROE/cjtg6affnNoyMF+Ni9v0MC ZA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9rab-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:09 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4752F3F706A; Fri, 11 Aug 2023 01:59:07 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Subject: [PATCH 20/31] net/cnxk: fix CQ allocation Date: Fri, 11 Aug 2023 14:27:54 +0530 Message-ID: <20230811085805.441256-20-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: KeyMc6zpXdIAgPanxAXr-n4C9tjEis0i X-Proofpoint-GUID: KeyMc6zpXdIAgPanxAXr-n4C9tjEis0i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Allocate number of CQs sufficient to handle completions of both RQs and SQs. Fixes: dd9446991212 ("net/cnxk: add transmit completion handler") Cc: rkudurumalla@marvell.com Signed-off-by: Satha Rao --- drivers/net/cnxk/cnxk_ethdev.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 4b98faa729..46450088eb 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1197,8 +1197,8 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE]; struct roc_nix_fc_cfg fc_cfg = {0}; struct roc_nix *nix = &dev->nix; + uint16_t nb_rxq, nb_txq, nb_cq; struct rte_ether_addr *ea; - uint16_t nb_rxq, nb_txq; uint64_t rx_cfg; void *qs; int rc; @@ -1309,6 +1309,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) nb_rxq = data->nb_rx_queues; nb_txq = data->nb_tx_queues; + nb_cq = nb_rxq; + if (nix->tx_compl_ena) + nb_cq += nb_txq; rc = -ENOMEM; if (nb_rxq) { /* Allocate memory for roc rq's and cq's */ @@ -1318,13 +1321,6 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto free_nix_lf; } dev->rqs = qs; - - qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_rxq, 0); - if (!qs) { - plt_err("Failed to alloc cqs"); - goto free_nix_lf; - } - dev->cqs = qs; } if (nb_txq) { @@ -1335,15 +1331,15 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto free_nix_lf; } dev->sqs = qs; + } - if (nix->tx_compl_ena) { - qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_txq, 0); - if (!qs) { - plt_err("Failed to alloc cqs"); - goto free_nix_lf; - } - dev->cqs = qs; + if (nb_cq) { + qs = plt_zmalloc(sizeof(struct roc_nix_cq) * nb_cq, 0); + if (!qs) { + plt_err("Failed to alloc cqs"); + goto free_nix_lf; } + dev->cqs = qs; } /* Re-enable NIX LF error interrupts */ From patchwork Fri Aug 11 08:57:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130135 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EEE043032; 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Fri, 11 Aug 2023 01:59:14 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:12 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:12 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 720443F706B; Fri, 11 Aug 2023 01:59:10 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 21/31] net/cnxk: fix issue with GCC 4.8 Date: Fri, 11 Aug 2023 14:27:55 +0530 Message-ID: <20230811085805.441256-21-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: FGYt142jMiW7hLl4tHnlvfyhxSSGEG_o X-Proofpoint-GUID: FGYt142jMiW7hLl4tHnlvfyhxSSGEG_o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix issue with GCC 4.8 cross compilation of ARM64 for flexible vector conversions. Fixes: ec28231ed260 ("net/cnxk: support reassembly of multi-segment packets") Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 8148866e44..0dc0b0595c 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -164,9 +164,9 @@ nix_sec_reass_frags_get(const struct cpt_parse_hdr_s *hdr, struct rte_mbuf **nex next_mbufs[1] = ((struct rte_mbuf *)vgetq_lane_u64(frags23, 0) - 1); next_mbufs[2] = ((struct rte_mbuf *)vgetq_lane_u64(frags23, 1) - 1); - fsz_w1 = vdup_n_u64(finfo->w1.u64); + fsz_w1 = vreinterpret_u16_u64(vdup_n_u64(finfo->w1.u64)); fsz_w1 = vrev16_u8(fsz_w1); - return vget_lane_u64(fsz_w1, 0); + return vget_lane_u64(vreinterpret_u64_u16(fsz_w1), 0); } static __rte_always_inline void @@ -174,7 +174,7 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const uint8_t *m_ipptr, uint64_t fsz, uint64_t cq_w1, uint16_t *ihl) { union nix_rx_parse_u *rx = (union nix_rx_parse_u *)((uintptr_t)(head + 1) + 8); - uint16_t fragx_sum = vaddv_u16(vdup_n_u64(fsz)); + uint16_t fragx_sum = vaddv_u16(vreinterpret_u16_u64(vdup_n_u64(fsz))); uint8_t lcptr = rx->lcptr; uint16_t tot_len; uint32_t cksum; From patchwork Fri Aug 11 08:57:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130136 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57C6D43032; Fri, 11 Aug 2023 11:00:23 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8844943273; Fri, 11 Aug 2023 10:59:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 325F543265 for ; Fri, 11 Aug 2023 10:59:18 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2Lhc011196 for ; Fri, 11 Aug 2023 01:59:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Bl5EUihgFJ6sSJVpzMeBCVRZYmLz4AK+L179F2wU0vk=; b=Q3C+eKvrG+OvxEkGU+iL03TeBty2vNBAE29KWaG9+7ZdiygJULJQLVg0zZ+jK8ET+2QR GCxVQDZEYa0JHWbnTmbIY4ru+LXFDMokQRNdzxI9wfmE2Q2qqQVWr35pFzkSaT8NBw6e Tb8Zxl5amvZhyYzaPpGOBRY3aBgrRxJaJ7g1gHx1jEEn0ccTWfFpnbKBsndawe5+JguN RoTgQoNg/FifA3fONgjFUOG4wSUA0sIosJJ4VsxTUbh+iPOEeSROfEPMOFV++a1fsJRg YdH9dvcQpmFZiXU0aTwLBH6WQ1reRjU35iflGPY40oi3n8d63QTFp3pyQMa6vMvxiqKb Gg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1gbj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:17 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:15 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 647503F706C; Fri, 11 Aug 2023 01:59:13 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 22/31] net/cnxk: add mapping of DMAC address indexes Date: Fri, 11 Aug 2023 14:27:56 +0530 Message-ID: <20230811085805.441256-22-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: J5w6g8jcy2UNmlQqhP2sKm5UgO36310A X-Proofpoint-GUID: J5w6g8jcy2UNmlQqhP2sKm5UgO36310A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Add support to map DMAC address indexes during mac address add and remove operation. Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 11 +++++++++++ drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_ethdev_ops.c | 4 +++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 46450088eb..bd161ad375 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1921,6 +1921,13 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) goto dev_fini; } + dev->dmac_idx_map = rte_zmalloc("dmac_idx_map", max_entries * sizeof(int), 0); + if (dev->dmac_idx_map == NULL) { + plt_err("Failed to allocate memory for dmac idx map"); + rc = -ENOMEM; + goto free_mac_addrs; + } + dev->max_mac_entries = max_entries; dev->dmac_filter_count = 1; @@ -1978,6 +1985,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) free_mac_addrs: rte_free(eth_dev->data->mac_addrs); + rte_free(dev->dmac_idx_map); dev_fini: roc_nix_dev_fini(nix); error: @@ -2095,6 +2103,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset) if (rc) plt_err("Failed to free nix lf, rc=%d", rc); + rte_free(dev->dmac_idx_map); + dev->dmac_idx_map = NULL; + rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index ed531fb277..8649f9e6f0 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -329,6 +329,7 @@ struct cnxk_eth_dev { uint8_t dmac_filter_count; uint8_t max_mac_entries; bool dmac_filter_enable; + int *dmac_idx_map; uint16_t flags; uint8_t ptype_disable; diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 3ade8eed36..5de2919047 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -474,6 +474,8 @@ cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr, return rc; } + dev->dmac_idx_map[index] = rc; + /* Enable promiscuous mode at NIX level */ roc_nix_npc_promisc_ena_dis(nix, true); dev->dmac_filter_enable = true; @@ -490,7 +492,7 @@ cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index) struct roc_nix *nix = &dev->nix; int rc; - rc = roc_nix_mac_addr_del(nix, index); + rc = roc_nix_mac_addr_del(nix, dev->dmac_idx_map[index]); if (rc) plt_err("Failed to delete mac address, rc=%d", rc); From patchwork Fri Aug 11 08:57:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130137 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5FCEC43032; Fri, 11 Aug 2023 11:00:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id F311643272; Fri, 11 Aug 2023 10:59:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id C51D743272 for ; Fri, 11 Aug 2023 10:59:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN32jB011977 for ; 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Fri, 11 Aug 2023 01:59:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:20 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4EC0B3F7085; Fri, 11 Aug 2023 01:59:16 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH 23/31] net/cnxk: support rate limit in PFC TM tree Date: Fri, 11 Aug 2023 14:27:57 +0530 Message-ID: <20230811085805.441256-23-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: gbsypSwy4GaZyfNHo7O5hhiBTqcmU9vc X-Proofpoint-GUID: gbsypSwy4GaZyfNHo7O5hhiBTqcmU9vc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao SQ rate limit was different in PFC tree compared to regular rate limit tree. Signed-off-by: Satha Rao --- drivers/net/cnxk/cnxk_tm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/cnxk/cnxk_tm.c b/drivers/net/cnxk/cnxk_tm.c index 9d8cd3f0a9..c799193cb8 100644 --- a/drivers/net/cnxk/cnxk_tm.c +++ b/drivers/net/cnxk/cnxk_tm.c @@ -765,6 +765,9 @@ cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev, if (queue_idx >= eth_dev->data->nb_tx_queues) goto exit; + if (roc_nix_tm_tree_type_get(nix) == ROC_NIX_TM_PFC) + return roc_nix_tm_pfc_rlimit_sq(nix, queue_idx, tx_rate); + if ((roc_nix_tm_tree_type_get(nix) != ROC_NIX_TM_RLIMIT) && eth_dev->data->nb_tx_queues > 1) { /* From patchwork Fri Aug 11 08:57:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130140 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 73FF543032; Fri, 11 Aug 2023 11:00:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B0CE043284; Fri, 11 Aug 2023 10:59:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F1E6743247 for ; Fri, 11 Aug 2023 10:59:37 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WV9011282 for ; Fri, 11 Aug 2023 01:59:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Eky7WpAHJeLiR91Ny8NQy6sCDTuzQQJPjEyifHXf6Q8=; b=ecws5sQGke6muuXWON0/9kieTDfV3qkzqyDY1YERvcv0omVi0PCuQK1tTarEGQbC3LLK KU01ZMTBWsNAjXqZAwgTNCj3+UpPj2GOzZqUrpbT8XqY8eGs6F9NLUqn3xIVJDZHBcWE pOQPMq+9dakiPZNDBLhge9n2GuShfqgQO0KnWFVqrVN4cw9JmPT9uXlj5PEKT5D0BKJG HaS/PVs7VEAqRcdyEOWWZmqLMNuuAgflXwBMDCDHjTtMdX5NRb77S12yItaHs2mRYES0 N2WS2oT08aAaaas8diNPvJsoRbUFTETcU3WCCcM8WRd0AmMyTiDlz383YtiBK31zx2Zu Yw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1gcd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:21 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 40F3A3F706A; Fri, 11 Aug 2023 01:59:18 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Srujana Challa Subject: [PATCH 24/31] net/cnxk: move MAC address set from init to configure Date: Fri, 11 Aug 2023 14:27:58 +0530 Message-ID: <20230811085805.441256-24-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ldTtkrEqlAoa08zVbuPgRazDLHkYjVfi X-Proofpoint-GUID: ldTtkrEqlAoa08zVbuPgRazDLHkYjVfi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Channel(rx_chan_base) is not available in the kernel at the time of nix probe. Hence, move the mac address set call from nix_device_init() to nix_device_configure(). This fixes the issue on cn10kb, where traffic was not getting received when promisc is disabled. Signed-off-by: Srujana Challa --- drivers/net/cnxk/cnxk_ethdev.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index bd161ad375..3b2ad5ff7d 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1301,6 +1301,15 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) goto fail_configure; } + if (!roc_nix_is_vf_or_sdp(nix)) { + /* Sync same MAC address to CGX/RPM table */ + rc = roc_nix_mac_addr_set(nix, dev->mac_addr); + if (rc) { + plt_err("Failed to set mac addr, rc=%d", rc); + goto fail_configure; + } + } + /* Check if ptp is enable in PF owning this VF*/ if (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix))) dev->ptp_en = roc_nix_ptp_is_enable(nix); @@ -1941,15 +1950,6 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev) /* Update the mac address */ memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN); - if (!roc_nix_is_vf_or_sdp(nix)) { - /* Sync same MAC address to CGX/RPM table */ - rc = roc_nix_mac_addr_set(nix, dev->mac_addr); - if (rc) { - plt_err("Failed to set mac addr, rc=%d", rc); - goto free_mac_addrs; - } - } - /* Union of all capabilities supported by CNXK. * Platform specific capabilities will be * updated later. From patchwork Fri Aug 11 08:57:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130141 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 595A043032; Fri, 11 Aug 2023 11:00:54 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B0289432A7; Fri, 11 Aug 2023 10:59:41 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 75AF143247 for ; Fri, 11 Aug 2023 10:59:38 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WVA011282 for ; Fri, 11 Aug 2023 01:59:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=xy3uN3Gw5QwVoaqPLaPDHGcz8tqaLcg6Aovw1l2r4lQ=; b=Elf525X5s0MjvX5m+6wHlfZ6mBh3fR8o3R73DynoECxIvUDASRd8pDxIGnH7Q1P5EK0r kBe8BanBTCqGWb6WjRzES9WRgQbp3C9UzVxdbpbh9N1TweRpnMrxI9/WJHVoSJQ6L00k isDz+0OfKG3iExZYU5xOEZS0uml6pKNJfUDyhUjznudYuZt0lPpYbyXL2Qb0XqWisfjC VLyt3kZm2919PkKBwJmO016PwZSivXNKnBGVwSOI9B/u7df2Zd3APBaa+2iC7C8jsBnL V39Hlv5zT7yg1JYahNub0v3FMWyNgn4jCkIKioqF5hKF/3i/8bw9ne1GFWwFZ+7hEW4M Dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1gcd-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:37 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:24 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 725A63F706C; Fri, 11 Aug 2023 01:59:22 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 25/31] net/cnxk: update different size bit operations Date: Fri, 11 Aug 2023 14:27:59 +0530 Message-ID: <20230811085805.441256-25-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: uJkP8Je-5TaROG4ZtQnLmSIiNpxm9_9- X-Proofpoint-GUID: uJkP8Je-5TaROG4ZtQnLmSIiNpxm9_9- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal Certain bitwise operations are done with different sized operands which causes warnings in static code analysis. The necessary operands are typecast to remove the warning. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_ethdev.c | 2 +- drivers/net/cnxk/cn10k_rx.h | 10 +++++----- drivers/net/cnxk/cn10k_tx.h | 12 ++++++------ 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 4c4acc7cf0..40437d2d73 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -262,7 +262,7 @@ cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, txq->cpt_desc = inl_lf->nb_desc * 0.7; txq->sa_base = (uint64_t)dev->outb.sa_base; - txq->sa_base |= eth_dev->data->port_id; + txq->sa_base |= (uint64_t)eth_dev->data->port_id; PLT_STATIC_ASSERT(ROC_NIX_INL_SA_BASE_ALIGN == BIT_ULL(16)); } diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 0dc0b0595c..a696427091 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -795,7 +795,7 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, /* Skip rx ol flags extraction for Security packets */ if ((!(flag & NIX_RX_SEC_REASSEMBLY_F) || !(w1 & BIT(11))) && flag & NIX_RX_OFFLOAD_CHECKSUM_F) - ol_flags |= nix_rx_olflags_get(lookup_mem, w1); + ol_flags |= (uint64_t)nix_rx_olflags_get(lookup_mem, w1); if (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) { if (rx->vtag0_gone) { @@ -1334,10 +1334,10 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, } if (flags & NIX_RX_OFFLOAD_CHECKSUM_F) { - ol_flags0 |= nix_rx_olflags_get(lookup_mem, cq0_w1); - ol_flags1 |= nix_rx_olflags_get(lookup_mem, cq1_w1); - ol_flags2 |= nix_rx_olflags_get(lookup_mem, cq2_w1); - ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1); + ol_flags0 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq0_w1); + ol_flags1 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq1_w1); + ol_flags2 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq2_w1); + ol_flags3 |= (uint64_t)nix_rx_olflags_get(lookup_mem, cq3_w1); } /* Translate meta to mbuf */ diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 298d243aac..04d02317b1 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -484,7 +484,7 @@ cn10k_nix_sec_steorl(uintptr_t io_addr, uint32_t lmt_id, uint8_t lnum, data &= ~(0x7ULL << 16); /* Update lines - 1 that contain valid data */ data |= ((uint64_t)(lnum + loff - 1)) << 12; - data |= lmt_id; + data |= (uint64_t)lmt_id; /* STEOR */ roc_lmt_submit_steorl(data, pa); @@ -577,7 +577,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1); nixtx += 16; - w0 |= cn10k_nix_tx_ext_subs(flags) + 1; + w0 |= cn10k_nix_tx_ext_subs(flags) + 1ULL; dptr += l2_len; ucode_cmd[1] = dptr; *cmd1 = vsetq_lane_u16(pkt_len + dlen_adj, *cmd1, 0); @@ -718,7 +718,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, nixtx = (nixtx - 1) & ~(BIT_ULL(7) - 1); nixtx += 16; - w0 |= cn10k_nix_tx_ext_subs(flags) + 1; + w0 |= cn10k_nix_tx_ext_subs(flags) + 1ULL; dptr += l2_len; ucode_cmd[1] = dptr; sg->seg1_size = pkt_len + dlen_adj; @@ -1421,7 +1421,7 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pkts, pa = io_addr | (data & 0x7) << 4; data &= ~0x7ULL; data |= ((uint64_t)(burst - 1)) << 12; - data |= lmt_id; + data |= (uint64_t)lmt_id; if (flags & NIX_TX_VWQE_F) cn10k_nix_vwqe_wait_fc(txq, burst); @@ -1583,7 +1583,7 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t *ws, data0 &= ~0x7ULL; /* Move lmtst1..15 sz to bits 63:19 */ data0 <<= 16; - data0 |= ((burst - 1) << 12); + data0 |= ((burst - 1ULL) << 12); data0 |= (uint64_t)lmt_id; if (flags & NIX_TX_VWQE_F) @@ -3193,7 +3193,7 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, wd.data[0] <<= 16; wd.data[0] |= ((uint64_t)(lnum - 1)) << 12; - wd.data[0] |= lmt_id; + wd.data[0] |= (uint64_t)lmt_id; if (flags & NIX_TX_VWQE_F) cn10k_nix_vwqe_wait_fc(txq, burst); From patchwork Fri Aug 11 08:58:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130138 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D40AC43032; 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Fri, 11 Aug 2023 01:59:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:28 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9ABDB3F706B; Fri, 11 Aug 2023 01:59:25 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 26/31] net/cnxk: fix uninitialized variable Date: Fri, 11 Aug 2023 14:28:00 +0530 Message-ID: <20230811085805.441256-26-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: wq0ork7XOP8WDFs9-prbUWEPXNYmEsxT X-Proofpoint-GUID: wq0ork7XOP8WDFs9-prbUWEPXNYmEsxT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal sa_base may be uninitialized in some remote case. It is better to initialize it. Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k") Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_rx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index a696427091..55ccf2023c 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -909,8 +909,8 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, struct nix_cqe_hdr_s *cq; struct rte_mbuf *mbuf; uint64_t aura_handle; + uint64_t sa_base = 0; uintptr_t cpth = 0; - uint64_t sa_base; uint16_t lmt_id; uint64_t laddr; @@ -1050,9 +1050,9 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, uint8x16_t f0, f1, f2, f3; uint16_t lmt_id, d_off; uint64_t lbase, laddr; + uintptr_t sa_base = 0; uint16_t packets = 0; uint16_t pkts_left; - uintptr_t sa_base; uint32_t head; uintptr_t cq0; From patchwork Fri Aug 11 08:58:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130139 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66E7B43032; Fri, 11 Aug 2023 11:00:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 812A24329E; Fri, 11 Aug 2023 10:59:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C1F1E43247 for ; Fri, 11 Aug 2023 10:59:36 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjx5j001610 for ; Fri, 11 Aug 2023 01:59:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=aUsexLW9prYlPTFSoQi+MpR/ebE4AZJounnNyPbSNOY=; b=UjBZD/IkEARBmCAE2y4pLuf1qR915Wt7LOZC49sjOS6vwNR8Lj1U1Wtosfj7xZHTMEz1 nFT9VHA6q3hWIbwx2A4ppzshw5ZHFGqPkUNA2XdFbDq24th85sMPq+xtUXc20oS1yDiU ZdTW+WKQl7U8c5GsJJeuExqxIw1anEkl/lcfiCB1Dsl4nGYcfvd74u7tLsl0sdqlzYp3 X7B92Hux0Y8D7+um6Vi9WOrGqkLZ+/xP18VxBPUl6vBe9etOk1MmIhYMa1CBPNvjzcM+ Db5l5y+bVwfJvGo9N0KFBwcBvbuiXzjLTq6Hgxcoj65+HmjlHbX+m2yVaLcxNc4wjynx Wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9rbj-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:35 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:31 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id BEF6F3F706A; Fri, 11 Aug 2023 01:59:28 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 27/31] net/cnxk: fix usage of mbuf rearm data Date: Fri, 11 Aug 2023 14:28:01 +0530 Message-ID: <20230811085805.441256-27-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 6OeycW9aU6TASo3QP3v9GYz4MKIWyRWz X-Proofpoint-GUID: 6OeycW9aU6TASo3QP3v9GYz4MKIWyRWz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal mbuf->rearm_data is a zero length array and it is being used to set data from that location. This shows an error in static code analysis. Hence it is typecast to a pointer which can be used to set values accordingly. Fixes: c062f5726f61 ("net/cnxk: support IP reassembly") Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_rx.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 55ccf2023c..982fd26045 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -510,6 +510,7 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa, (const struct cpt_parse_hdr_s *)cpth; uint64_t mbuf_init = vgetq_lane_u64(*rearm, 0); struct cn10k_inb_priv_data *inb_priv; + uintptr_t p; /* Clear checksum flags */ *ol_flags &= ~(RTE_MBUF_F_RX_L4_CKSUM_MASK | @@ -530,7 +531,8 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa, /* First frag len */ inner->pkt_len = vgetq_lane_u16(*rx_desc_field1, 2); inner->data_len = vgetq_lane_u16(*rx_desc_field1, 4); - *(uint64_t *)(&inner->rearm_data) = mbuf_init; + p = (uintptr_t)&inner->rearm_data; + *(uint64_t *)p = mbuf_init; /* Reassembly success */ nix_sec_reassemble_frags(hdr, inner, cq_w1, cq_w5, mbuf_init); @@ -545,7 +547,7 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uint64_t cq_w5, uintptr_t inb_sa, *rx_desc_field1, 4); /* Data offset might be updated */ - mbuf_init = *(uint64_t *)(&inner->rearm_data); + mbuf_init = *(uint64_t *)p; *rearm = vsetq_lane_u64(mbuf_init, *rearm, 0); } else { /* Reassembly failure */ @@ -628,6 +630,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t cq_w1; int64_t len; uint64_t sg; + uintptr_t p; cq_w1 = *(const uint64_t *)rx; if (flags & NIX_RX_REAS_F) @@ -703,7 +706,8 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, mbuf->data_len = sg_len; sg = sg >> 16; - *(uint64_t *)(&mbuf->rearm_data) = rearm & ~0xFFFF; + p = (uintptr_t)&mbuf->rearm_data; + *(uint64_t *)p = rearm & ~0xFFFF; nb_segs--; iova_list++; @@ -753,7 +757,8 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, head->nb_segs = nb_segs; } mbuf = next_frag; - *(uint64_t *)(&mbuf->rearm_data) = rearm + ldptr; + p = (uintptr_t)&mbuf->rearm_data; + *(uint64_t *)p = rearm + ldptr; mbuf->data_len = (sg & 0xFFFF) - ldptr - (flags & NIX_RX_OFFLOAD_TSTAMP_F ? CNXK_NIX_TIMESYNC_RX_OFFSET : 0); @@ -781,6 +786,7 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, const uint64_t w1 = *(const uint64_t *)rx; uint16_t len = rx->pkt_lenm1 + 1; uint64_t ol_flags = 0; + uintptr_t p; if (flag & NIX_RX_OFFLOAD_PTYPE_F) mbuf->packet_type = nix_ptype_get(lookup_mem, w1); @@ -818,7 +824,8 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, mbuf->ol_flags = ol_flags; mbuf->pkt_len = len; mbuf->data_len = len; - *(uint64_t *)(&mbuf->rearm_data) = val; + p = (uintptr_t)&mbuf->rearm_data; + *(uint64_t *)p = val; } if (flag & NIX_RX_MULTI_SEG_F) From patchwork Fri Aug 11 08:58:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130142 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD1BE43032; Fri, 11 Aug 2023 11:00:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C6E1643279; Fri, 11 Aug 2023 10:59:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id F212F43284 for ; Fri, 11 Aug 2023 10:59:38 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WVB011282 for ; Fri, 11 Aug 2023 01:59:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Xo1fgOjk4KVEQ+cVCzNgS4Et5beKg0yiuzQx7JSmiww=; b=Je+4xWgzwzE5CQeapiz2iNIepYCaeUlTXTybV19nSHIwAdyM59UVN5gQPNsfqtXC1KNG 7294IzSVpXuL7MNDjzUcUeioMvrev8GWvzxiYhu5NT2Vb1TXavSJ45tXmYOYlh+aiqTX pBmP+EqDbz+39BM39prlXA8C8Bez0ABZ7blKis24cbm2MpAlGdanxSo0dDWNofzCYJwn LlGLXPAeE2R4Z28iIsjDyPeMEHl4TzYhGiNt2YjgyGAa03VqUmf3odybXhe8IlsaXOoC G50pOo7a40BZQqs87YQ5SxPdCNK74v+XxGuXKhH7nvM54/PIYBKx4SrwYsuicixdTl7F +Q== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1gcd-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:38 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:34 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:34 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D7C653F706B; Fri, 11 Aug 2023 01:59:31 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 28/31] net/cnxk: fix uninitialized variable Date: Fri, 11 Aug 2023 14:28:02 +0530 Message-ID: <20230811085805.441256-28-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: B5JMj526mKWwb-0usxiOuH2Ms5e7G-LW X-Proofpoint-GUID: B5JMj526mKWwb-0usxiOuH2Ms5e7G-LW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal shift may be uninitialized in certain case. It is better to initialize. Fixes: 55bfac717c72 ("net/cnxk: support Tx security offload on cn10k") Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_tx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 04d02317b1..464cd9b401 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1999,6 +1999,7 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, uint64x2_t xmask01_w0, xmask23_w0; uint64x2_t xmask01_w1, xmask23_w1; rte_iova_t io_addr = txq->io_addr; + uint8_t lnum, shift = 0, loff = 0; uintptr_t laddr = txq->lmt_base; uint8_t c_lnum, c_shft, c_loff; struct nix_send_hdr_s send_hdr; @@ -2006,7 +2007,6 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, uint64x2_t xtmp128, ytmp128; uint64x2_t xmask01, xmask23; uintptr_t c_laddr = laddr; - uint8_t lnum, shift, loff = 0; rte_iova_t c_io_addr; uint64_t sa_base; union wdata { From patchwork Fri Aug 11 08:58:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130143 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CB33243032; Fri, 11 Aug 2023 11:01:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CD186432AE; Fri, 11 Aug 2023 10:59:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7DC764329C for ; Fri, 11 Aug 2023 10:59:39 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AN2WVC011282 for ; Fri, 11 Aug 2023 01:59:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=8yw6KObC2L5NQ4Ikk3RRkmTVZUn3F0w4SawKPKfe9qQ=; b=Njg4Zc1z8vlXYgWSbFrWvPC/ZNdw9XQDXVLIXK8nC2PVNQ9LP+e8WRAQVMa1ajajurUL 5tRsgSaIfx5ZPjwrPHQsubY6ufubWvNRuCZ3SFGYIi1VL1vdwgFTE0nW93BC+oULc83S 5Rk63IC2ciAuO+S30RjV8ZNfrJrHEObxppJWkgYvcxqaNOkvNU++G6XR8kmnbg25Ajef 1Ml/0Cs68spoRj36L74s+p0UMhVOdpqZvRioNiVZrU9J1w1Y1XxxDPtfds3QIIhHZvc+ oZz/GhJsoqa9Tz/ExiEMbfU+ygNPW/MFGJvYKhGDiHMu3SNCXNpgtGixk9/L+sr+skpX ew== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8ya1gcd-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:38 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:37 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 09C493F706F; Fri, 11 Aug 2023 01:59:34 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 29/31] net/cnxk: check returned value for null Date: Fri, 11 Aug 2023 14:28:03 +0530 Message-ID: <20230811085805.441256-29-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: MNNgrMRzwvDioj4bkKjaLltCyZaDz_kj X-Proofpoint-GUID: MNNgrMRzwvDioj4bkKjaLltCyZaDz_kj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal nix_mtr_find may return NULL in case mtr is not found. Hence checking the return value before using it. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cnxk_ethdev_mtr.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev_mtr.c b/drivers/net/cnxk/cnxk_ethdev_mtr.c index 27a6e4ef3d..edeca6dcc3 100644 --- a/drivers/net/cnxk/cnxk_ethdev_mtr.c +++ b/drivers/net/cnxk/cnxk_ethdev_mtr.c @@ -613,6 +613,11 @@ cnxk_nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t mtr_id, while ((mtr->prev_cnt) + 1) { mid_mtr = nix_mtr_find(dev, mtr->prev_id[mtr->prev_cnt]); + if (mid_mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, &mtr->prev_id[mtr->prev_cnt], + "Mid meter id is invalid."); + } rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_LEAF, mid_mtr->bpf_id, ROC_NIX_BPF_ID_INVALID); @@ -628,6 +633,11 @@ cnxk_nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t mtr_id, while (mtr->prev_cnt) { top_mtr = nix_mtr_find(dev, mtr->prev_id[mtr->prev_cnt]); + if (top_mtr == NULL) { + return -rte_mtr_error_set(error, ENOENT, + RTE_MTR_ERROR_TYPE_MTR_ID, &mtr->prev_id[mtr->prev_cnt], + "Top meter id is invalid."); + } rc = roc_nix_bpf_connect(nix, ROC_NIX_BPF_LEVEL_F_MID, top_mtr->bpf_id, ROC_NIX_BPF_ID_INVALID); @@ -1590,6 +1600,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, switch (*tree_level) { case 0: mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr == NULL) + return -EINVAL; if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { nix_mtr_level_update(eth_dev, cur_mtr_id, 0); nix_mtr_chain_update(eth_dev, cur_mtr_id, -1, @@ -1605,6 +1617,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, break; case 1: mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr == NULL) + return -EINVAL; if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { nix_mtr_level_update(eth_dev, cur_mtr_id, 1); prev_mtr_id = id; @@ -1635,6 +1649,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, switch (*tree_level) { case 0: mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr == NULL) + return -EINVAL; if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { nix_mtr_level_update(eth_dev, cur_mtr_id, 0); } else { @@ -1646,6 +1662,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, break; case 1: mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr == NULL) + return -EINVAL; if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { nix_mtr_level_update(eth_dev, cur_mtr_id, 1); prev_mtr_id = id; @@ -1666,6 +1684,8 @@ nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, break; case 2: mtr = nix_get_mtr(eth_dev, cur_mtr_id); + if (mtr == NULL) + return -EINVAL; if (mtr->level == ROC_NIX_BPF_LEVEL_IDX_INVALID) { nix_mtr_level_update(eth_dev, cur_mtr_id, 2); prev_mtr_id = *prev_id; From patchwork Fri Aug 11 08:58:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130144 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5495E43032; 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Fri, 11 Aug 2023 01:59:42 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:40 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 2088E3F706A; Fri, 11 Aug 2023 01:59:37 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Akhil Goyal Subject: [PATCH 30/31] net/cnxk: add flag check for extension header when used Date: Fri, 11 Aug 2023 14:28:04 +0530 Message-ID: <20230811085805.441256-30-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: swBP67d0mFhl469xNbTkvQPqYmrOwVR4 X-Proofpoint-GUID: swBP67d0mFhl469xNbTkvQPqYmrOwVR4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal send_hdr_ext is being used, but it may be null when the flag check for NIX_TX_NEED_EXT_HDR is not done. Hence added a check here to avoid null pointer dereference. Signed-off-by: Akhil Goyal --- drivers/net/cnxk/cn10k_tx.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 464cd9b401..fff7ae7fc9 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1011,7 +1011,8 @@ cn10k_nix_xmit_prepare(struct cn10k_eth_txq *txq, send_hdr_ext->w0.markptr = markptr; } - if (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) { + if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F && + (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) { uint16_t lso_sb; uint64_t mask; From patchwork Fri Aug 11 08:58:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 130145 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2C7CB43032; Fri, 11 Aug 2023 11:01:18 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 61117432B7; Fri, 11 Aug 2023 10:59:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 58675432C1 for ; Fri, 11 Aug 2023 10:59:46 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AMjx5m001610 for ; Fri, 11 Aug 2023 01:59:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=d86/S0LfLPzGWVOnHmErn2YHzyxWVkUsweLOfFW1CjA=; b=fu6DSfskCvMNA+C5APwyrmikz5DzuB9qzTNhX91tSse2cZs3+UNtDwpKH30LckpMttRO +x69A94XJxI+wdJU9p0ng5CjhIz58/uw+NJ2G9IiPJY19HErSvtdeLUvg/3m9Fan7m3Z FeXj2YFcPXqxKPAns3nbXh3AD1qbJ+5fEhUGXVWZywE3SiKHwXkrXxo1NDa9dJcVEVM7 ginFNjSRatQvOePB4JGrRD5oiV1sKd9hkcdLH007Oj4KdUhch5a9jaRUebpKkQCElrKQ LvXUFpPAaerWSPw7B9/HaTmI3T6XCpp8AILyHcwxcsEQg/FqsFnRQ8czs4PkpQwoRjnH JQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sd8yp9red-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 11 Aug 2023 01:59:45 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 11 Aug 2023 01:59:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 11 Aug 2023 01:59:43 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 522903F706B; Fri, 11 Aug 2023 01:59:41 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rahul Bhansali Subject: [PATCH 31/31] net/cnxk: fixes for IPv6 header in reassembly Date: Fri, 11 Aug 2023 14:28:05 +0530 Message-ID: <20230811085805.441256-31-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com> References: <20230811085805.441256-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Ojjcr1NNWNSfjjWoO3BJmsD6xA1TayDU X-Proofpoint-GUID: Ojjcr1NNWNSfjjWoO3BJmsD6xA1TayDU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali In reassembly path, next header field in IPv6 header is not updated correctly, hence reassembled packet is corrupted. This fix will consider IPv6 fragment header presence at start/mid/end in extension list and update the next header field accordingly. Fixes: ec28231ed260 ("net/cnxk: support reassembly of multi-segment packets") Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_rx.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 982fd26045..41d11349fd 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -205,26 +205,36 @@ nix_sec_reass_first_frag_update(struct rte_mbuf *head, const uint8_t *m_ipptr, struct rte_ipv6_hdr *hdr = (struct rte_ipv6_hdr *)ipptr; size_t ext_len = sizeof(struct rte_ipv6_hdr); uint8_t *nxt_hdr = (uint8_t *)hdr; + uint8_t *nxt_proto = &hdr->proto; int nh = hdr->proto; *ihl = 0; + tot_len = 0; while (nh != -EINVAL) { nxt_hdr += ext_len; *ihl += ext_len; + if (nh == IPPROTO_FRAGMENT) { + *nxt_proto = *nxt_hdr; + tot_len = *ihl; + } nh = rte_ipv6_get_next_ext(nxt_hdr, nh, &ext_len); + nxt_proto = nxt_hdr; } /* Remove the frag header by moving header 8 bytes forward */ hdr->payload_len = rte_cpu_to_be_16(fragx_sum + *ihl - 8 - sizeof(struct rte_ipv6_hdr)); + /* tot_len is sum of all IP header's length before fragment header */ rte_memcpy(rte_pktmbuf_mtod_offset(head, void *, 8), rte_pktmbuf_mtod(head, void *), - lcptr + sizeof(struct rte_ipv6_hdr)); + lcptr + tot_len); head->data_len -= 8; head->data_off += 8; head->pkt_len = lcptr + *ihl - 8 + fragx_sum; + /* ihl l3hdr size value should be up to fragment header for next frags */ + *ihl = tot_len + 8; } }