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Tue, 22 Aug 2023 03:36:11 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Erez Shitrit Subject: [PATCH 1/2] net/mlx5/hws: add support for random number match Date: Tue, 22 Aug 2023 13:35:59 +0300 Message-ID: <20230822103600.3247680-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230822103600.3247680-1-michaelba@nvidia.com> References: <20230822103600.3247680-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F0:EE_|DM6PR12MB4465:EE_ X-MS-Office365-Filtering-Correlation-Id: a6328fd1-10d6-45af-9ee9-08dba2fba44d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WQ1pPBgjSRHH7LBI0zyG2UFvfQQ990KQc+9atBj1XKtsk7PXvCnM91qxL7ILCUu0DGzCyRlTtBKV7lcjbYiOdzLBTpCD+FmLzjMrOOtFlZA8w27IArc4cuBo54tKZkqQaoalY4KP477Y9B3cTjkO1ornWlYb8QPRtERKiNYP5yhJyu/JybntRCFt0pBc/e4nE+wbt9MiK6nj7p6hZ12603JAAg1d+y+UD8vx9fQ8/ofShc0IT6gJA5BaqWVDvLvr2MTgx5hOHu/9Vq5pzHUfPQaNDr3SNBpApJ94Nt8PyE9fqyTMtWdSNl+w1JhlXDJ4vgCjJLJ+QGA+6mH+UWi1T+Zj8m/YK9XTMD5Wm8KVnmAheeGKzIR+Pt0qk7baOqs8okq1RulR3u+zbdKj5BiMH01LDZdc5WN8OrVn7f2Z0nSiAKg2stT3f1S+lVveFURLr7UyGap0oHwudJNic2rbdY/wDEpeFeU1yGwvLs0JK5PPd3PJZCJ3K0RjsGWyrFdyslkETvR1e/lv9qtkhVmWU2mlFsGE9TnK5yeaDuYRjHWwN/Fkh0em2L6g5Fc1ecLWT8EzeL5UgXewgE1/VP8AwohsRfnhzCRLM042XOAsdn5N3YF4gbLGj4WU+2VJ9AWL4Sb0lhulvzuY/cQPaOMAkdrTMBVT28yL6Bv+2/YJe6pniR7bNCy6pQ0+B7UqRdHw8rOos/TamnGxW7InSAXTdCmkHWVI6AIsN6RZdKX5YR4oksm5fVhGax3kJx3awHmF X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(396003)(136003)(376002)(346002)(39860400002)(1800799009)(186009)(451199024)(82310400011)(36840700001)(40470700004)(46966006)(54906003)(6916009)(70206006)(70586007)(316002)(8676002)(8936002)(2616005)(107886003)(4326008)(7636003)(40460700003)(36756003)(41300700001)(1076003)(82740400003)(356005)(478600001)(6666004)(55016003)(40480700001)(83380400001)(2906002)(86362001)(7696005)(47076005)(36860700001)(336012)(426003)(5660300002)(26005)(6286002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 10:36:27.9161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6328fd1-10d6-45af-9ee9-08dba2fba44d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4465 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit The HW adds a random number per each hash, this value can be used for statistic calculation over the packets, for example by setting one bit in the mask of that filed we will get half of the traffic in the flow, and so on with the rest of the mask. Signed-off-by: Erez Shitrit Acked-by: Ori Kam --- drivers/net/mlx5/hws/mlx5dr_definer.c | 35 ++++++++++++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_definer.h | 8 +++++- drivers/net/mlx5/mlx5_flow.h | 3 +++ 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 33d0f2d18e..a20ea73605 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -177,7 +177,8 @@ struct mlx5dr_definer_conv_data { X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \ X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \ X(SET, ib_l4_udp_port, UDP_ROCEV2_PORT, rte_flow_item_ib_bth) \ - X(SET, ib_l4_opcode, v->hdr.opcode, rte_flow_item_ib_bth) + X(SET, ib_l4_opcode, v->hdr.opcode, rte_flow_item_ib_bth) \ + X(SET, random_number, v->value, rte_flow_item_random) \ /* Item set function format */ #define X(set_type, func_name, value, item_type) \ @@ -1965,6 +1966,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_random *m = item->mask; + const struct rte_flow_item_random *l = item->last; + struct mlx5dr_definer_fc *fc; + + if (!m) + return 0; + + if (m->value != (m->value & UINT16_MAX)) { + DR_LOG(ERR, "Random value is 16 bits only"); + rte_errno = EINVAL; + return rte_errno; + } + + fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_random_number_set; + fc->is_range = l && l->value; + DR_CALC_SET_HDR(fc, random_number, random_number); + + return 0; +} + static int mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt, struct mlx5dr_definer_fc *fc, @@ -2016,6 +2044,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item) case RTE_FLOW_ITEM_TYPE_TAG: case RTE_FLOW_ITEM_TYPE_META: case MLX5_RTE_FLOW_ITEM_TYPE_TAG: + case RTE_FLOW_ITEM_TYPE_RANDOM: return 0; default: DR_LOG(ERR, "Range not supported over item type %d", item->type); @@ -2319,6 +2348,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_IB_BTH; break; + case RTE_FLOW_ITEM_TYPE_RANDOM: + ret = mlx5dr_definer_conv_item_random(&cd, items, i); + item_flags |= MLX5_FLOW_ITEM_RANDOM; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6b645f4cf0..1405c752b8 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -136,6 +136,7 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I, MLX5DR_DEFINER_FNAME_IB_L4_OPCODE, MLX5DR_DEFINER_FNAME_IB_L4_QPN, + MLX5DR_DEFINER_FNAME_RANDOM_NUM, MLX5DR_DEFINER_FNAME_MAX, }; @@ -392,6 +393,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits { u8 destination_address[0x20]; }; +struct mlx5_ifc_definer_hl_random_number_bits { + u8 random_number[0x10]; + u8 reserved[0x10]; +}; + struct mlx5_ifc_definer_hl_ipv6_addr_bits { u8 ipv6_address_127_96[0x20]; u8 ipv6_address_95_64[0x20]; @@ -501,7 +507,7 @@ struct mlx5_ifc_definer_hl_bits { struct mlx5_ifc_definer_hl_mpls_bits mpls_inner; u8 unsupported_config_headers_outer[0x80]; u8 unsupported_config_headers_inner[0x80]; - u8 unsupported_random_number[0x20]; + struct mlx5_ifc_definer_hl_random_number_bits random_number; struct mlx5_ifc_definer_hl_ipsec_bits ipsec; struct mlx5_ifc_definer_hl_metadata_bits metadata; u8 unsupported_utc_timestamp[0x40]; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 3a97975d69..8a9bd71692 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -233,6 +233,9 @@ enum mlx5_feature_name { /* IB BTH ITEM. */ #define MLX5_FLOW_ITEM_IB_BTH (1ull << 51) +/* Random ITEM */ +#define MLX5_FLOW_ITEM_RANDOM (1ull << 52) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) From patchwork Tue Aug 22 10:36:00 2023 Content-Type: text/plain; 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Tue, 22 Aug 2023 03:36:14 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH 2/2] net/mlx5: add random item support Date: Tue, 22 Aug 2023 13:36:00 +0300 Message-ID: <20230822103600.3247680-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230822103600.3247680-1-michaelba@nvidia.com> References: <20230822103600.3247680-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE33:EE_|MN2PR12MB4454:EE_ X-MS-Office365-Filtering-Correlation-Id: 2dfae625-7bd8-40fd-cbb0-08dba2fba478 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JfB9Or8XHt+55vv+Jdv39oALkrudagALTLJ8Pwp9bCUyxSTdEgHAwb/xQP4mmp3XTSgYk5UbGf3zkusUMHUyh57NPcda5eFsRcoYysLqA1tivPdlScztqLGFKrfLah0l9oXimBEFRYrnCqnHrawWbav/f3M7pCY4bSt/2W3Rl8Uo8gqA/mu+GjgzdJA+YlG60vbkG5NNl4qI5dEQOWy3ugwN9cIFkaUMD58hnGGPJ93Zna6SpHCJO2tGKLXAkIT2Bv+K0bSuCqChoXVzqXsWaJGVMcnbw+x6Q7oi3aBOslaXikRbsqntYZVMkZ66VAT18iaypzpsluqzxQM6Pq32Q8TFgiArQ8ocn8MItMKlN7/mi3V872BcGQ7zIhbJe7hqgMck9rw8OWulv+fES1c8zbXTt5cYVRs/2AVEZrLlx5bq7taYy82tiZz+E3gIqzT2YNkLYCqffCzl4dZgP8AuPOglL3dVSGgP+mwBeXcQhVtTrVPR4o9B6T1LxLo5uHpNspdLepA/7Syp6yVdnLcro1za+yYQ4Bc51y/yQhk0hqzJKlNNEVkMtarG2lXJG4opQUxiSyIoAhQPJ6LiVYwPQc29z+pR+4hWlGTv124lVolZcB9FPd7J+ch4ZAj6mdyIEriy+X++vvJTfuF40KhAV5NU9J4TSd7jvUQqHwxo+CKTwaA86shpgHgl3B+E3Pcl1fhNUxCtJXI/HZHoA3BdY4emLWXRyfDBf8PprguCKL2hsCKqQ62pKB/UuY+OTYA5 X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 10 +++++++++- doc/guides/rel_notes/release_23_11.rst | 4 ++++ drivers/net/mlx5/mlx5_flow_dv.c | 5 +++++ drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++ 5 files changed, 24 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index c0e0b779cf..5606f435f2 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -86,6 +86,7 @@ nvgre = Y port_id = Y port_representor = Y quota = Y +random = Y tag = Y tcp = Y udp = Y diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index eac67a7864..f754fab3e1 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -165,7 +165,7 @@ Features - Sub-Function. - Matching on represented port. - Matching on aggregated affinity. - +- Matching on random value. Limitations ----------- @@ -554,6 +554,7 @@ Limitations - Modification of the MPLS header is supported only in HWS and only to copy from, the encapsulation level is always 0. - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported. + - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported. - Encapsulation levels are not supported, can modify outermost header fields only. - Offsets cannot skip past the boundary of a field. - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE`` @@ -712,6 +713,13 @@ Limitations - The NIC egress flow rules on representor port are not supported. +- Match on random value: + + - Supported only with HW Steering enabled (``dv_flow_en`` = 2). + - Supported only in table with ``nb_flows=1``. + - NIC ingress flow in group 0 is not supported. + - Supports matching only 16 bits (LSB). + - During live migration to a new process set its flow engine as standby mode, the user should only program flow rules in group 0 (``fdb_def_rule_en=0``). Live migration is only supported under SWS (``dv_flow_en=1``). diff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst index 1e90bf83e7..8a4c04ed75 100644 --- a/doc/guides/rel_notes/release_23_11.rst +++ b/doc/guides/rel_notes/release_23_11.rst @@ -76,6 +76,10 @@ New Features Added ``RTE_FLOW_ITEM_RANDOM`` to match random value. +* **Updated NVIDIA mlx5 net driver.** + + * Added support for random value matching. + Removed Items ------------- diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index a8dd9920e6..1238d00073 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5385,6 +5385,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifications of the MPLS header " "is not supported"); + if (dst_data->field == RTE_FLOW_FIELD_RANDOM || + src_data->field == RTE_FLOW_FIELD_RANDOM) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "modifications of random value is not supported"); if (dst_data->field == RTE_FLOW_FIELD_MARK || src_data->field == RTE_FLOW_FIELD_MARK) if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 5395969eb0..6fe6103a37 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3893,6 +3893,10 @@ flow_hw_validate_action_modify_field(const struct rte_flow_action *action, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifying Geneve VNI is not supported"); + if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "modifying random value is not supported"); /* Due to HW bug, tunnel MPLS header is read only. */ if (action_conf->dst.field == RTE_FLOW_FIELD_MPLS) return rte_flow_error_set(error, EINVAL, @@ -5375,6 +5379,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_ESP: case RTE_FLOW_ITEM_TYPE_FLEX: case RTE_FLOW_ITEM_TYPE_IB_BTH: + case RTE_FLOW_ITEM_TYPE_RANDOM: break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: /*