From patchwork Thu Nov 2 09:39:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjing Qiao X-Patchwork-Id: 133780 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 47A344326D; Thu, 2 Nov 2023 10:41:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 38737402EB; Thu, 2 Nov 2023 10:41:10 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 18FE2402E5 for ; Thu, 2 Nov 2023 10:41:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698918069; x=1730454069; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=K3RnZk1lJb7Ll29goWmd0HBovce5UQ65vGmVVGUXCGs=; b=nqMCxxgEQJVLO0rRwx3cP9JiMiqjbgtN1anv2QCGUwe2CW17wLgwc9+o tG/HnR12mQNuiSZ/EO1f9+FBQSEIidehKiF+QLrka/aE6JrXOe61mz/Q1 uPeqkGRV4wavGENWUyDttcJ8fHJLGUOSA9Rd5Xs8Tgib3KyE7yhuGcLsK f22S9QdsGZxZDoqBvvuiyfuf/GWro1MuMtqldusx2XRp4AWJTWO2kk5OJ PcYGpVyDSU1rnmCgan1kX64Tt92JUH4pmBB7CkVMTKDyWqRGT/euN1Vh1 bbmKZc+jFg+fttOioGXWX353P0UB0OsInFqr/66+XuUdAuA1D6AWW3hK3 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10881"; a="452975215" X-IronPort-AV: E=Sophos;i="6.03,271,1694761200"; d="scan'208";a="452975215" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2023 02:41:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,271,1694761200"; d="scan'208";a="2487551" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.118.228]) by fmviesa002.fm.intel.com with ESMTP; 02 Nov 2023 02:41:07 -0700 From: wenjing.qiao@intel.com To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, yuying.zhang@intel.com, Wenjing Qiao Subject: [PATCH] net/cpfl: refine vxlan encap content Date: Thu, 2 Nov 2023 09:39:50 +0000 Message-Id: <20231102093949.484647-1-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Wenjing Qiao Refine vxlan encap content of all protocol headers with default configuration. Fixes: 6cc97c9971d7 ("net/cpfl: build action mapping rules from JSON") Signed-off-by: Wenjing Qiao --- drivers/net/cpfl/cpfl_flow_parser.c | 63 ++++++++++++++++++++++++++++- drivers/net/cpfl/cpfl_flow_parser.h | 11 +++++ 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/net/cpfl/cpfl_flow_parser.c b/drivers/net/cpfl/cpfl_flow_parser.c index 412f7feed0..9b2d6df150 100644 --- a/drivers/net/cpfl/cpfl_flow_parser.c +++ b/drivers/net/cpfl/cpfl_flow_parser.c @@ -1609,6 +1609,60 @@ cpfl_parse_mr_key_action(struct cpfl_flow_js_mr_key_action *key_acts, int size, return 0; } +static int +cpfl_translate_definition(struct rte_flow_item *definition, int def_length, + struct cpfl_action_vxlan_encap_data *encap_data) +{ + int i; + struct rte_flow_item *item; + + for (i = 0; i < def_length; i++) { + item = &encap_data->items[i]; + item->type = definition[i].type; + switch (item->type) { + case RTE_FLOW_ITEM_TYPE_ETH: + item->spec = &encap_data->item_eth; + memcpy(&encap_data->item_eth, definition[i].spec, + sizeof(struct rte_flow_item_eth)); + break; + case RTE_FLOW_ITEM_TYPE_VOID: + case RTE_FLOW_ITEM_TYPE_VLAN: + item->spec = &encap_data->item_vlan; + memcpy(&encap_data->item_vlan, definition[i].spec, + sizeof(struct rte_flow_item_vlan)); + break; + case RTE_FLOW_ITEM_TYPE_IPV4: + item->spec = &encap_data->item_ipv4; + memcpy(&encap_data->item_ipv4, definition[i].spec, + sizeof(struct rte_flow_item_ipv4)); + break; + case RTE_FLOW_ITEM_TYPE_UDP: + item->spec = &encap_data->item_udp; + memcpy(&encap_data->item_udp, definition[i].spec, + sizeof(struct rte_flow_item_udp)); + break; + case RTE_FLOW_ITEM_TYPE_VXLAN: + item->spec = &encap_data->item_vxlan; + memcpy(&encap_data->item_vxlan, definition[i].spec, + sizeof(struct rte_flow_item_vxlan)); + break; + case RTE_FLOW_ITEM_TYPE_END: + break; + default: + return -EINVAL; + } + encap_data->item_eth.hdr.ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4); + encap_data->item_ipv4.hdr.version_ihl = RTE_IPV4_VHL_DEF; + encap_data->item_ipv4.hdr.next_proto_id = IPPROTO_UDP; + encap_data->item_ipv4.hdr.time_to_live = IPDEFTTL; + encap_data->item_ipv4.hdr.hdr_checksum = rte_cpu_to_be_16(1); + encap_data->item_udp.hdr.dgram_cksum = RTE_BE16(0x01); + encap_data->item_vxlan.flags = 0x08; + } + + return 0; +} + /* output: uint8_t *buffer, uint16_t *byte_len */ static int cpfl_parse_layout(struct cpfl_flow_js_mr_layout *layouts, int layout_size, @@ -1640,12 +1694,19 @@ cpfl_parse_layout(struct cpfl_flow_js_mr_layout *layouts, int layout_size, if (temp->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP) { const struct rte_flow_action_vxlan_encap *action_vxlan_encap; struct rte_flow_item *definition; - int def_length, k; + int def_length, k, ret; + struct cpfl_action_vxlan_encap_data vxlan_encap_data = {0}; action_vxlan_encap = (const struct rte_flow_action_vxlan_encap *)temp->encap.action->conf; definition = action_vxlan_encap->definition; def_length = cpfl_get_items_length(definition); + ret = cpfl_translate_definition(definition, def_length, &vxlan_encap_data); + if (ret < 0) { + PMD_DRV_LOG(ERR, "vxlan_encap: can't translate definition items."); + return -EINVAL; + } + definition = vxlan_encap_data.items; for (k = 0; k < def_length - 1; k++) { if ((strcmp(hint, "eth") == 0 && definition[k].type == RTE_FLOW_ITEM_TYPE_ETH) || diff --git a/drivers/net/cpfl/cpfl_flow_parser.h b/drivers/net/cpfl/cpfl_flow_parser.h index 962667adc2..99b4b87d90 100644 --- a/drivers/net/cpfl/cpfl_flow_parser.h +++ b/drivers/net/cpfl/cpfl_flow_parser.h @@ -13,6 +13,7 @@ #define CPFL_MAX_SEM_FV_KEY_SIZE 64 #define CPFL_FLOW_JS_PROTO_SIZE 16 #define CPFL_MOD_KEY_NUM_MAX 8 +#define CPFL_VXLAN_ENCAP_ITEMS_NUM_MAX 6 /* Pattern Rules Storage */ enum cpfl_flow_pr_action_type { @@ -203,6 +204,16 @@ struct cpfl_flow_mr_key_action_vxlan_encap { const struct rte_flow_action *action; }; +/* Storage for struct rte_flow_action_vxlan_encap including external data. */ +struct cpfl_action_vxlan_encap_data { + struct rte_flow_item items[CPFL_VXLAN_ENCAP_ITEMS_NUM_MAX]; + struct rte_flow_item_eth item_eth; + struct rte_flow_item_vlan item_vlan; + struct rte_flow_item_ipv4 item_ipv4; + struct rte_flow_item_udp item_udp; + struct rte_flow_item_vxlan item_vxlan; +}; + struct cpfl_flow_mr_key_action { enum rte_flow_action_type type; union {