From patchwork Fri Nov 3 17:14:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 133848 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A34DB4327C; Fri, 3 Nov 2023 18:14:42 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 356C440263; Fri, 3 Nov 2023 18:14:42 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id B2E9E4014F; Fri, 3 Nov 2023 18:14:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699031681; x=1730567681; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=pHeWedwQlGruPE2OYCaQj7mBzsaIKSH6hjsy3JCLXjo=; b=RZwAI4DWnP5aKbgv+2VmpMUUyI9cvmF0qF3CWBr21i2vdOEzkBiu3VC8 DC6ZkqfzFK7N7Dtp0z2aFqr5hfoet/+/JGJzmWstxBIhUWWjHemRM7XsE etannGH4gEPgkwfewSuDSRuoaF+Iv4YEBAHAQobQ0G4ct0BCOYvgNnH38 DeCqD9uAHm6WhjGA1MPsSXYVj/MxcjnbTPyw7lY4d2dDn94lchqjyxuFB MLz/yABP3zdLLm2A1aSQZWYHJPUKb4M7E2DiiA5jNozNpKMk59+6+fVW0 8CRCNUbKg433ifGpvwffQDeIjcDIjO5zXt+mColfxCb/kjVHxUxe8Qo+g Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="392867580" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="392867580" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 10:14:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="711564387" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="711564387" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga003.jf.intel.com with ESMTP; 03 Nov 2023 10:14:38 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, Abdullah Sevincer , stable@dpdk.org Subject: [PATCH v4] event/dlb2: fix disable PASID Date: Fri, 3 Nov 2023 12:14:36 -0500 Message-Id: <20231103171436.2791832-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In vfio-pci driver when PASID is enabled by default DLB hardware puts DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly PASID needs to be disabled. In this commit this issue is addressed and PASID is disabled by writing a zero to PASID control register. Fixes: 5433956d5185 ("event/dlb2: add eventdev probe") Cc: stable@dpdk.org Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/dlb2_main.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index aa03e4c311..63a18df71c 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -514,6 +514,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } + /* Disable PASID incase it is enabled by default, which + * breaks the DLB if enabled. + */ + off = RTE_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL; + if (rte_pci_set_pasid(pdev, off, false)) { + DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", + __func__, (int)off); + return -1; + } + return 0; }