From patchwork Mon Nov 6 17:05:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdullah Sevincer X-Patchwork-Id: 133900 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7BD21432BB; Mon, 6 Nov 2023 18:05:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F05440DC9; Mon, 6 Nov 2023 18:05:32 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 268F14025D for ; Mon, 6 Nov 2023 18:05:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699290330; x=1730826330; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tAvifFIS1KgP2oAuFep7kawdkf8mXQHG/lbN3c+aoRs=; b=MPvNLo/c3KXw6TLFXt/tqiTbxFLy1Z+o9obiCdQJQPXSzKcf127k4Y9Q QDI/aEVqMvjEoEA2m3kZ+YSZWdkY5pX+4U/ei4wecnVxP2wyyOkebM8Uc 2rnsA5z7iC5v0DBvaTT0GDtWID0wNKbM59UIm1MlodMVmfnVSZ0rw0vxQ d4HWww+SVGR1xQqmDqfb8+jzlOrx799fvB7NhK1Imu6qS0DQ3MowptEKS rjIj2gZ/wuSHcotiATYJMan+4w+XofuH02udl4VUawazbZjEG5NzfkSYb 46ySgpvGcbBbWH5A/Zgpgvyl5N1LaidZmgLOjCJ6OvTH7Vp+RXS8wLbgk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="475553782" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="475553782" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 09:05:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="10512014" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by fmviesa001.fm.intel.com with ESMTP; 06 Nov 2023 09:05:25 -0800 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, Abdullah Sevincer Subject: [PATCH v7 1/2] bus/pci: support PASID control Date: Mon, 6 Nov 2023 11:05:20 -0600 Message-Id: <20231106170521.3064038-2-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231106170521.3064038-1-abdullah.sevincer@intel.com> References: <20231106170521.3064038-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add an internal API to control PASID for a given PCIe device. For kernels when PASID enabled by default it breaks DLB functionality, hence disabling PASID is required for DLB to function properly. PASID capability is not exposed to users hence offset can not be retrieved by rte_pci_find_ext_capability() api. Therefore, api implemented in this commit accepts an offset for PASID with an enable flag which is used to enable/disable PASID. Signed-off-by: Abdullah Sevincer --- drivers/bus/pci/pci_common.c | 7 +++++++ drivers/bus/pci/rte_bus_pci.h | 13 +++++++++++++ drivers/bus/pci/version.map | 1 + lib/pci/rte_pci.h | 4 ++++ 4 files changed, 25 insertions(+) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index 921d957bf6..ecf080c5d7 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -938,6 +938,13 @@ rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable) return 0; } +int +rte_pci_pasid_set_state(const struct rte_pci_device *dev, off_t offset, bool enable) +{ + uint16_t pasid = enable; + return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 ? -1 : 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index 21e234abf0..6d836e771a 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -295,6 +295,19 @@ void rte_pci_ioport_read(struct rte_pci_ioport *p, void rte_pci_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset); +/** + * Enable/Disable PASID. + * + * @param dev + * A pointer to a rte_pci_device structure. + * @param offset + * Offset of the PASID external capability. + * @param enable + * Flag to enable or disable PASID. + */ +__rte_internal +int rte_pci_pasid_set_state(const struct rte_pci_device *dev, off_t offset, bool enable); + #ifdef __cplusplus } #endif diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map index 74c5b075d5..9fad086bdf 100644 --- a/drivers/bus/pci/version.map +++ b/drivers/bus/pci/version.map @@ -37,5 +37,6 @@ INTERNAL { rte_pci_get_sysfs_path; rte_pci_register; + rte_pci_pasid_set_state; rte_pci_unregister; }; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 69e932d910..d195f01950 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,6 +101,10 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ + +/* Process Address Space ID */ +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */ From patchwork Mon Nov 6 17:05:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abdullah Sevincer X-Patchwork-Id: 133901 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44B0E432BB; Mon, 6 Nov 2023 18:05:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 38DA740DD8; Mon, 6 Nov 2023 18:05:37 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 6EEBE40E01; Mon, 6 Nov 2023 18:05:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699290335; x=1730826335; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cga2VCUwyfs1uu3uCbZxe2s5ay4rREOmZHOZ8qao2NE=; b=OnOK0pB7P458asN5uoXq3HemLjb36q5p82NGxDU3HTS3eGUd4LknxL7P ILU8swajHw91xwk0dtamARl7kPEdoe6Wj96iNP7avwUEZ55dhon1eOdyR RwWxa/vdX9exMQ+cjZcvRShiHyGaIfgd1tibYtaWFeGqm9E+8rhYUcZd9 sr4hESRQSXNVg7e4EaOkpCNOE6IFq6eeSsviX96gq9Mu/wu6DdCrFbf8b rhLsCUnldibMc1rv0jLy+r6mtMknySfBMHqK9V6IhU1mkaWx6X84Ov/23 KKW0l6R2HAnVikYFmgrQ++194/evAH9QuT2VTsoswdj/cbwejQwTX61jG Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="475553798" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="475553798" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 09:05:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="10512056" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by fmviesa001.fm.intel.com with ESMTP; 06 Nov 2023 09:05:32 -0800 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, Abdullah Sevincer , stable@dpdk.org Subject: [PATCH v7 2/2] event/dlb2: fix disable PASID Date: Mon, 6 Nov 2023 11:05:21 -0600 Message-Id: <20231106170521.3064038-3-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231106170521.3064038-1-abdullah.sevincer@intel.com> References: <20231106170521.3064038-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In vfio-pci driver when PASID is enabled by default DLB hardware puts DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly PASID needs to be disabled. In this commit this issue is addressed and PASID is disabled by writing a zero to PASID control register. Fixes: 5433956d5185 ("event/dlb2: add eventdev probe") Cc: stable@dpdk.org Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/dlb2_main.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index aa03e4c311..61a7b39eef 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -26,6 +26,7 @@ #define PF_ID_ZERO 0 /* PF ONLY! */ #define NO_OWNER_VF 0 /* PF ONLY! */ #define NOT_VF_REQ false /* PF ONLY! */ +#define DLB2_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offset */ static int dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev) @@ -514,6 +515,16 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } + /* Disable PASID if it is enabled by default, which + * breaks the DLB if enabled. + */ + off = DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL; + if (rte_pci_pasid_set_state(pdev, off, false)) { + DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", + __func__, (int)off); + return -1; + } + return 0; }