From patchwork Fri Dec 8 15:44:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Ellmann X-Patchwork-Id: 134975 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D137436AB; Fri, 8 Dec 2023 16:49:02 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3FA2540EE2; Fri, 8 Dec 2023 16:49:02 +0100 (CET) Received: from postout1.mail.lrz.de (postout1.mail.lrz.de [129.187.255.137]) by mails.dpdk.org (Postfix) with ESMTP id 5510840EE1 for ; Fri, 8 Dec 2023 16:49:00 +0100 (CET) Received: from lxmhs51.srv.lrz.de (localhost [127.0.0.1]) by postout1.mail.lrz.de (Postfix) with ESMTP id 4SmwY7443RzyTq; Fri, 8 Dec 2023 16:48:59 +0100 (CET) Authentication-Results: postout.lrz.de (amavisd-new); dkim=pass (2048-bit key) reason="pass (just generated, assumed good)" header.d=tum.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tum.de; h= content-transfer-encoding:mime-version:x-mailer:message-id:date :date:subject:subject:from:from:received:received; s= tu-postout21; t=1702050539; bh=j+epF6p3PF2OtlBuRdjUcStf9o7p83udG 86mhGvb9ZU=; b=at3I27jTy1/614LFZPr5SmHMxj559kr5GjBriH0K8yGLdR9Z5 XkaykrH+XI8wFv7F/ddZKU9s6LdPy/YwLBoZmXXSR9TSSIFz8unAo3DDaR3S5yzB mx8fcMp3jQUo3BykQdiE0RYDvhzojdgayoV8qXwwqhUvtm/jOs/TfJguZv6Mkvlb E5Ud39lhoozGELKVv/xmTyvLz5mEw7E1uTHG27+7UnaHwSybwFdDjDXP+APILWcj B1OdegsNDkyOS/yOYlOADy6AMigUEBUcPP+7b7qVFEaySS8bIG5uK7l6pLSdKhOj YUCGG1rXPxAYOvdHCQZePmbXj6kmT1f4O3GaQ== X-Virus-Scanned: by amavisd-new at lrz.de in lxmhs51.srv.lrz.de X-Spam-Flag: NO X-Spam-Score: -2.888 X-Spam-Level: X-Spam-Status: No, score=-2.888 tagged_above=-999 required=5 tests=[ALL_TRUSTED=-1, BAYES_00=-1.9, DMARC_ADKIM_RELAXED=0.001, DMARC_ASPF_RELAXED=0.001, DMARC_POLICY_NONE=0.001, LRZ_DMARC_FAIL=0.001, LRZ_DMARC_FAIL_NONE=0.001, LRZ_DMARC_POLICY=0.001, LRZ_DMARC_TUM_FAIL=0.001, LRZ_DMARC_TUM_REJECT=3.5, LRZ_DMARC_TUM_REJECT_PO=-3.5, LRZ_ENVFROM_FROM_MATCH=0.001, LRZ_ENVFROM_TUM_S=0.001, LRZ_FROM_ENVFROM_ALIGNED_STRICT=0.001, LRZ_FROM_HAS_A=0.001, LRZ_FROM_HAS_AAAA=0.001, LRZ_FROM_HAS_MDOM=0.001, LRZ_FROM_HAS_MX=0.001, LRZ_FROM_HOSTED_DOMAIN=0.001, LRZ_FROM_NAME_IN_ADDR=0.001, LRZ_FROM_PHRASE=0.001, LRZ_FROM_PRE_SUR=0.001, LRZ_FROM_PRE_SUR_PHRASE=0.001, LRZ_FROM_TUM_S=0.001, LRZ_HAS_MIME_VERSION=0.001, LRZ_HAS_SPF=0.001, T_SCC_BODY_TEXT_LINE=-0.01] autolearn=no autolearn_force=no Received: from postout1.mail.lrz.de ([127.0.0.1]) by lxmhs51.srv.lrz.de (lxmhs51.srv.lrz.de [127.0.0.1]) (amavisd-new, port 20024) with LMTP id ldM3MWQodc2f; Fri, 8 Dec 2023 16:48:59 +0100 (CET) Received: from deep-thought.localdomain (p5790127d.dip0.t-ipconnect.de [87.144.18.125]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by postout1.mail.lrz.de (Postfix) with ESMTPSA id 4SmwY664pZzyT7; Fri, 8 Dec 2023 16:48:58 +0100 (CET) From: Simon Ellmann To: qiming.yang@intel.com, wenjun1.wu@intel.com Cc: dev@dpdk.org, Simon Ellmann Subject: [PATCH] ixgbe: fix interrupt clear mask for eimc register Date: Fri, 8 Dec 2023 16:44:10 +0100 Message-ID: <20231208154410.14212-1-simon.ellmann@tum.de> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 32nd bit of the eimc register is reserved according to the datasheet Signed-off-by: Simon Ellmann --- drivers/net/ixgbe/base/ixgbe_type.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index 1094df5891..03b299cd10 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -2023,7 +2023,7 @@ enum { #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 /* Interrupt clear mask */ -#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF +#define IXGBE_IRQ_CLEAR_MASK 0x7FFFFFFF /* Interrupt Vector Allocation Registers */ #define IXGBE_IVAR_REG_NUM 25