From patchwork Thu Dec 21 11:19:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanumanth Pothula X-Patchwork-Id: 135427 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD71A43750; Thu, 21 Dec 2023 12:20:10 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF1B14027D; Thu, 21 Dec 2023 12:20:10 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 19BDE400D6 for ; Thu, 21 Dec 2023 12:20:08 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BL6IVfE019514 for ; Thu, 21 Dec 2023 03:20:08 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding:content-type; s=pfpt0220; bh=IhS82oHc bmmVsoDWJtqH8cYV6K3PZ8JQZytx21YYjrw=; b=FzPTb+Td1Rra3VQ1H5VzovVx cqno08PRy/5THzzAyCYwHeletoB0v6PARc9Imju2jtLCNHLBNXku/hclnOdt8YW3 pLymb09YyVTLH4WmsvDmfwgAOSUjuIu26u8FHxmyYYUXRD7Yid+wgt68QfHuHvQA pQaVSioAeLJYWCuxmED0IRiVwY8o6f4LRZlw23xlQjAtK0nWox89tKEuBY9nljAF gvQ9kR2QA/8o7tXrQSkCKvatVoQZEHz4t+bAKv+bRE1Mm77E1qnWR0CFlbOIILkq 8bYeroOxjlCLTdlSKhCf79zpJWfXfFnUustd3YSqA0d2V+GzK0ligkTuYjrFng== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3v4fyr1p9x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 21 Dec 2023 03:20:08 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 21 Dec 2023 03:20:06 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 21 Dec 2023 03:20:06 -0800 Received: from localhost.localdomain (unknown [10.28.36.155]) by maili.marvell.com (Postfix) with ESMTP id 91B453F708D; Thu, 21 Dec 2023 03:20:04 -0800 (PST) From: Hanumanth Pothula To: Jerin Jacob , Maciej Czekaj CC: , , Subject: [PATCH v1 1/1] net/thunderx: update dmac control register to appropriately Date: Thu, 21 Dec 2023 16:49:59 +0530 Message-ID: <20231221111959.61251-1-hpothula@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: yf232vXbpcbdw7czU0wewzx3Dy3mQZ6r X-Proofpoint-ORIG-GUID: yf232vXbpcbdw7czU0wewzx3Dy3mQZ6r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org By default dmac control register is set to reject packets on mac address match, leading all unicast packets to drop. Update DMAC control register to allow packets on MAC address match rather than dropping. Signed-off-by: Hanumanth Pothula --- drivers/net/thunderx/base/nicvf_mbox.c | 12 ++++++++++++ drivers/net/thunderx/base/nicvf_mbox.h | 10 ++++++++++ drivers/net/thunderx/nicvf_ethdev.c | 26 ++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/thunderx/base/nicvf_mbox.c b/drivers/net/thunderx/base/nicvf_mbox.c index 5993eec4e6..0e0176974d 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.c +++ b/drivers/net/thunderx/base/nicvf_mbox.c @@ -485,3 +485,15 @@ nicvf_mbox_reset_xcast(struct nicvf *nic) mbx.msg.msg = NIC_MBOX_MSG_RESET_XCAST; nicvf_mbox_send_msg_to_pf(nic, &mbx); } + +int +nicvf_mbox_set_xcast(struct nicvf *nic, uint8_t mode, uint64_t mac) +{ + struct nic_mbx mbx = { .msg = { 0 } }; + + mbx.xcast.msg = NIC_MBOX_MSG_SET_XCAST; + mbx.xcast.mode = mode; + mbx.xcast.mac = mac; + + return nicvf_mbox_send_msg_to_pf(nic, &mbx); +} diff --git a/drivers/net/thunderx/base/nicvf_mbox.h b/drivers/net/thunderx/base/nicvf_mbox.h index 322c8159cb..47f3d13755 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.h +++ b/drivers/net/thunderx/base/nicvf_mbox.h @@ -45,6 +45,8 @@ #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ #define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */ +#define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* ADD MAC to DCAM filters */ +#define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST Rx mode */ #define NIC_MBOX_MSG_MAX 0x100 /* Maximum number of messages */ /* Get vNIC VF configuration */ @@ -190,6 +192,12 @@ struct change_link_mode_msg { }; +struct xcast { + uint8_t msg; + uint8_t mode; + uint64_t mac:48; +}; + struct nic_mbx { /* 128 bit shared memory between PF and each VF */ union { @@ -209,6 +217,7 @@ union { struct reset_stat_cfg reset_stat; struct set_link_state set_link; struct change_link_mode_msg mode; + struct xcast xcast; }; }; @@ -239,5 +248,6 @@ void nicvf_mbox_cfg_done(struct nicvf *nic); void nicvf_mbox_link_change(struct nicvf *nic); void nicvf_mbox_reset_xcast(struct nicvf *nic); int nicvf_mbox_change_mode(struct nicvf *nic, struct change_link_mode *cfg); +int nicvf_mbox_set_xcast(struct nicvf *nic, uint8_t mode, uint64_t mac); #endif /* __THUNDERX_NICVF_MBOX__ */ diff --git a/drivers/net/thunderx/nicvf_ethdev.c b/drivers/net/thunderx/nicvf_ethdev.c index a504d41dfe..49016327a0 100644 --- a/drivers/net/thunderx/nicvf_ethdev.c +++ b/drivers/net/thunderx/nicvf_ethdev.c @@ -58,6 +58,10 @@ RTE_LOG_REGISTER_SUFFIX(nicvf_logtype_driver, driver, NOTICE); #define NICVF_QLM_MODE_SGMII 7 #define NICVF_QLM_MODE_XFI 12 +#define BCAST_ACCEPT 0x01 +#define CAM_ACCEPT (1 << 3) +#define BGX_MCAST_MODE(x) ((x) << 1) + enum nicvf_link_speed { NICVF_LINK_SPEED_SGMII, NICVF_LINK_SPEED_XAUI, @@ -2183,9 +2187,22 @@ nicvf_eth_dev_uninit(struct rte_eth_dev *dev) nicvf_dev_close(dev); return 0; } + +static inline uint64_t ether_addr_to_u64(uint8_t *addr) +{ + uint64_t u = 0; + int i; + + for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) + u = u << 8 | addr[i]; + + return u; +} + static int nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) { + uint8_t dmac_ctrl_reg = 0; int ret; struct rte_pci_device *pci_dev; struct nicvf *nic = nicvf_pmd_priv(eth_dev); @@ -2309,6 +2326,15 @@ nicvf_eth_dev_init(struct rte_eth_dev *eth_dev) goto malloc_fail; } + /* set DMAC CTRL reg to allow MAC */ + dmac_ctrl_reg = BCAST_ACCEPT | BGX_MCAST_MODE(2) | CAM_ACCEPT; + ret = nicvf_mbox_set_xcast(nic, dmac_ctrl_reg, + ether_addr_to_u64(nic->mac_addr)); + if (ret) { + PMD_INIT_LOG(ERR, "Failed to set mac addr"); + goto malloc_fail; + } + ret = nicvf_set_first_skip(eth_dev); if (ret) { PMD_INIT_LOG(ERR, "Failed to configure first skip");