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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000044F3.mail.protection.outlook.com (10.167.241.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.19 via Frontend Transport; Tue, 30 Jan 2024 06:49:45 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 29 Jan 2024 22:49:33 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 29 Jan 2024 22:49:30 -0800 From: Gavin Li To: , , , , CC: , , Subject: [PATCH V1] net/mlx5: store IPv6 TC detection result in physical device Date: Tue, 30 Jan 2024 08:49:13 +0200 Message-ID: <20240130064913.1916709-1-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|CH0PR12MB5026:EE_ X-MS-Office365-Filtering-Correlation-Id: 9eb50afb-0a39-4103-8b55-08dc215fa4e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2024 06:49:45.0518 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9eb50afb-0a39-4103-8b55-08dc215fa4e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5026 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Previously, discovering of IPv6 traffic class would happen on each device not sharing context with others. However, It's not necessary to repeat it on devices of the same physical device. A flow will be created and destroyed in the detection, which may trigger cache allocation and take more memory in scale cases. To solve the problem, store the discovering of IPv6 traffic class result in physical device, and do it only once per physical device. Fixes: 569b8340a012 ("net/mlx5: discover IPv6 traffic class support in RDMA core") Signed-off-by: Gavin Li Acked-by: Suanming Mou --- drivers/net/mlx5/linux/mlx5_os.c | 12 +++++++----- drivers/net/mlx5/mlx5.h | 13 ++++++++++++- drivers/net/mlx5/mlx5_flow_dv.c | 2 +- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index e47d0d0238..dd140e9934 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1602,11 +1602,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, goto error; } rte_rwlock_init(&priv->ind_tbls_lock); - if (!priv->sh->cdev->config.hca_attr.modify_outer_ipv6_traffic_class || - (sh->config.dv_flow_en == 1 && - !priv->sh->ipv6_tc_fallback && - mlx5_flow_discover_ipv6_tc_support(eth_dev))) - priv->sh->ipv6_tc_fallback = 1; + if (sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_UNKNOWN) { + if (!sh->cdev->config.hca_attr.modify_outer_ipv6_traffic_class || + (sh->config.dv_flow_en == 1 && mlx5_flow_discover_ipv6_tc_support(eth_dev))) + sh->phdev->config.ipv6_tc_fallback = MLX5_IPV6_TC_FALLBACK; + else + sh->phdev->config.ipv6_tc_fallback = MLX5_IPV6_TC_OK; + } if (priv->sh->config.dv_flow_en == 2) { #ifdef HAVE_MLX5_HWS_SUPPORT if (priv->sh->config.dv_esw_en) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 683029023e..ce9aa64a1d 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1421,6 +1421,17 @@ struct mlx5_dev_registers { struct mlx5_geneve_tlv_options; +enum mlx5_ipv6_tc_support { + MLX5_IPV6_TC_UNKNOWN = 0, + MLX5_IPV6_TC_FALLBACK, + MLX5_IPV6_TC_OK, +}; + +struct mlx5_common_nic_config { + enum mlx5_ipv6_tc_support ipv6_tc_fallback; + /* Whether ipv6 traffic class should use old value. */ +}; + /** * Physical device structure. * This device is created once per NIC to manage recourses shared by all ports @@ -1431,6 +1442,7 @@ struct mlx5_physical_device { struct mlx5_dev_ctx_shared *sh; /* Created on sherd context. */ uint64_t guid; /* System image guid, the uniq ID of physical device. */ struct mlx5_geneve_tlv_options *tlv_options; + struct mlx5_common_nic_config config; uint32_t refcnt; }; @@ -1459,7 +1471,6 @@ struct mlx5_dev_ctx_shared { uint32_t lag_rx_port_affinity_en:1; /* lag_rx_port_affinity is supported. */ uint32_t hws_max_log_bulk_sz:5; - uint32_t ipv6_tc_fallback:1; /* Log of minimal HWS counters created hard coded. */ uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */ uint32_t max_port; /* Maximal IB device port index. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 6998be107f..1d2fdd3391 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1608,7 +1608,7 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev, static inline bool mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) { - return !priv->sh->ipv6_tc_fallback; + return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK; } void