From patchwork Fri Mar 22 07:09:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138736 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A132243D1E; Fri, 22 Mar 2024 08:09:53 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A97A942E9B; Fri, 22 Mar 2024 08:09:33 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 7D2C942E5B for ; Fri, 22 Mar 2024 08:09:26 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4V1D0972NczwPsm; Fri, 22 Mar 2024 15:06:49 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id A2867140336; Fri, 22 Mar 2024 15:09:24 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 22 Mar 2024 15:09:24 +0800 From: Dengdui Huang To: CC: , , , , , , , , , , , , Subject: [PATCH v2 1/6] ethdev: support setting lanes Date: Fri, 22 Mar 2024 15:09:18 +0800 Message-ID: <20240322070923.244417-2-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some speeds can be achieved with different number of lanes. For example, 100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps. When use different lanes, the port cannot be up. This patch add support setting lanes and report lanes. In addition, add a device capability RTE_ETH_DEV_CAPA_SETTING_LANES When the device does not support it, if a speed supports different numbers of lanes, the application does not knowe which the lane number are used by the device. Signed-off-by: Dengdui Huang --- doc/guides/rel_notes/release_24_03.rst | 6 + drivers/net/bnxt/bnxt_ethdev.c | 3 +- drivers/net/hns3/hns3_ethdev.c | 1 + lib/ethdev/ethdev_linux_ethtool.c | 208 ++++++++++++------------- lib/ethdev/ethdev_private.h | 4 + lib/ethdev/ethdev_trace.h | 4 +- lib/ethdev/meson.build | 2 + lib/ethdev/rte_ethdev.c | 85 +++++++--- lib/ethdev/rte_ethdev.h | 75 ++++++--- lib/ethdev/version.map | 6 + 10 files changed, 250 insertions(+), 144 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 7bd9ceab27..4621689c68 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -76,6 +76,9 @@ New Features * Added a fath path function ``rte_eth_tx_queue_count`` to get the number of used descriptors of a Tx queue. +* **Support setting lanes for ethdev.** + * Support setting lanes by extended ``RTE_ETH_LINK_SPEED_*``. + * **Added hash calculation of an encapsulated packet as done by the HW.** Added function to calculate hash when doing tunnel encapsulation: @@ -254,6 +257,9 @@ ABI Changes * No ABI change that would break compatibility with 23.11. +* ethdev: Convert a numerical speed to a bitmap flag with lanes: + The function ``rte_eth_speed_bitflag`` add lanes parameters. + Known Issues ------------ diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index ba31ae9286..e881a7f3cc 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -711,7 +711,8 @@ static int bnxt_update_phy_setting(struct bnxt *bp) } /* convert to speedbit flag */ - curr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed, 1); + curr_speed_bit = rte_eth_speed_bitflag((uint32_t)link->link_speed, + RTE_ETH_LANES_UNKNOWN, 1); /* * Device is not obliged link down in certain scenarios, even diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index b10d1216d2..ecd3b2ef64 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -5969,6 +5969,7 @@ hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, for (i = 0; i < RTE_DIM(speed_fec_capa_tbl); i++) { speed_bit = rte_eth_speed_bitflag(speed_fec_capa_tbl[i].speed, + RTE_ETH_LANES_UNKNOWN, RTE_ETH_LINK_FULL_DUPLEX); if ((speed_capa & speed_bit) == 0) continue; diff --git a/lib/ethdev/ethdev_linux_ethtool.c b/lib/ethdev/ethdev_linux_ethtool.c index e792204b01..6412845161 100644 --- a/lib/ethdev/ethdev_linux_ethtool.c +++ b/lib/ethdev/ethdev_linux_ethtool.c @@ -7,6 +7,10 @@ #include "rte_ethdev.h" #include "ethdev_linux_ethtool.h" +#define RTE_ETH_LINK_MODES_INDEX_SPEED 0 +#define RTE_ETH_LINK_MODES_INDEX_DUPLEX 1 +#define RTE_ETH_LINK_MODES_INDEX_LANES 2 + /* Link modes sorted with index as defined in ethtool. * Values are speed in Mbps with LSB indicating duplex. * @@ -15,123 +19,119 @@ * and allows to compile with new bits included even on an old kernel. * * The array below is built from bit definitions with this shell command: - * sed -rn 's;.*(ETHTOOL_LINK_MODE_)([0-9]+)([0-9a-zA-Z_]*).*= *([0-9]*).*;'\ - * '[\4] = \2, /\* \1\2\3 *\/;p' /usr/include/linux/ethtool.h | - * awk '/_Half_/{$3=$3+1","}1' + * sed -rn 's;.*(ETHTOOL_LINK_MODE_)([0-9]+)([a-zA-Z]+)([0-9_]+)([0-9a-zA-Z_]*) + * .*= *([0-9]*).*;'\ '[\6] = {\2, 1, \4}, /\* \1\2\3\4\5 *\/;p' + * /usr/include/linux/ethtool.h | awk '/_Half_/{$4=0","}1' | + * awk '/, _}/{$5=1"},"}1' | awk '{sub(/_}/,"\}");}1' */ -static const uint32_t link_modes[] = { - [0] = 11, /* ETHTOOL_LINK_MODE_10baseT_Half_BIT */ - [1] = 10, /* ETHTOOL_LINK_MODE_10baseT_Full_BIT */ - [2] = 101, /* ETHTOOL_LINK_MODE_100baseT_Half_BIT */ - [3] = 100, /* ETHTOOL_LINK_MODE_100baseT_Full_BIT */ - [4] = 1001, /* ETHTOOL_LINK_MODE_1000baseT_Half_BIT */ - [5] = 1000, /* ETHTOOL_LINK_MODE_1000baseT_Full_BIT */ - [12] = 10000, /* ETHTOOL_LINK_MODE_10000baseT_Full_BIT */ - [15] = 2500, /* ETHTOOL_LINK_MODE_2500baseX_Full_BIT */ - [17] = 1000, /* ETHTOOL_LINK_MODE_1000baseKX_Full_BIT */ - [18] = 10000, /* ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT */ - [19] = 10000, /* ETHTOOL_LINK_MODE_10000baseKR_Full_BIT */ - [20] = 10000, /* ETHTOOL_LINK_MODE_10000baseR_FEC_BIT */ - [21] = 20000, /* ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT */ - [22] = 20000, /* ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT */ - [23] = 40000, /* ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT */ - [24] = 40000, /* ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT */ - [25] = 40000, /* ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT */ - [26] = 40000, /* ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT */ - [27] = 56000, /* ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT */ - [28] = 56000, /* ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT */ - [29] = 56000, /* ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT */ - [30] = 56000, /* ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT */ - [31] = 25000, /* ETHTOOL_LINK_MODE_25000baseCR_Full_BIT */ - [32] = 25000, /* ETHTOOL_LINK_MODE_25000baseKR_Full_BIT */ - [33] = 25000, /* ETHTOOL_LINK_MODE_25000baseSR_Full_BIT */ - [34] = 50000, /* ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT */ - [35] = 50000, /* ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT */ - [36] = 100000, /* ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT */ - [37] = 100000, /* ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT */ - [38] = 100000, /* ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT */ - [39] = 100000, /* ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT */ - [40] = 50000, /* ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT */ - [41] = 1000, /* ETHTOOL_LINK_MODE_1000baseX_Full_BIT */ - [42] = 10000, /* ETHTOOL_LINK_MODE_10000baseCR_Full_BIT */ - [43] = 10000, /* ETHTOOL_LINK_MODE_10000baseSR_Full_BIT */ - [44] = 10000, /* ETHTOOL_LINK_MODE_10000baseLR_Full_BIT */ - [45] = 10000, /* ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT */ - [46] = 10000, /* ETHTOOL_LINK_MODE_10000baseER_Full_BIT */ - [47] = 2500, /* ETHTOOL_LINK_MODE_2500baseT_Full_BIT */ - [48] = 5000, /* ETHTOOL_LINK_MODE_5000baseT_Full_BIT */ - [52] = 50000, /* ETHTOOL_LINK_MODE_50000baseKR_Full_BIT */ - [53] = 50000, /* ETHTOOL_LINK_MODE_50000baseSR_Full_BIT */ - [54] = 50000, /* ETHTOOL_LINK_MODE_50000baseCR_Full_BIT */ - [55] = 50000, /* ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT */ - [56] = 50000, /* ETHTOOL_LINK_MODE_50000baseDR_Full_BIT */ - [57] = 100000, /* ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT */ - [58] = 100000, /* ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT */ - [59] = 100000, /* ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT */ - [60] = 100000, /* ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT */ - [61] = 100000, /* ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT */ - [62] = 200000, /* ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT */ - [63] = 200000, /* ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT */ - [64] = 200000, /* ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT */ - [65] = 200000, /* ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT */ - [66] = 200000, /* ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT */ - [67] = 100, /* ETHTOOL_LINK_MODE_100baseT1_Full_BIT */ - [68] = 1000, /* ETHTOOL_LINK_MODE_1000baseT1_Full_BIT */ - [69] = 400000, /* ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT */ - [70] = 400000, /* ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT */ - [71] = 400000, /* ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT */ - [72] = 400000, /* ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT */ - [73] = 400000, /* ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT */ - [75] = 100000, /* ETHTOOL_LINK_MODE_100000baseKR_Full_BIT */ - [76] = 100000, /* ETHTOOL_LINK_MODE_100000baseSR_Full_BIT */ - [77] = 100000, /* ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT */ - [78] = 100000, /* ETHTOOL_LINK_MODE_100000baseCR_Full_BIT */ - [79] = 100000, /* ETHTOOL_LINK_MODE_100000baseDR_Full_BIT */ - [80] = 200000, /* ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT */ - [81] = 200000, /* ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT */ - [82] = 200000, /* ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT */ - [83] = 200000, /* ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT */ - [84] = 200000, /* ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT */ - [85] = 400000, /* ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT */ - [86] = 400000, /* ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT */ - [87] = 400000, /* ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT */ - [88] = 400000, /* ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT */ - [89] = 400000, /* ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT */ - [90] = 101, /* ETHTOOL_LINK_MODE_100baseFX_Half_BIT */ - [91] = 100, /* ETHTOOL_LINK_MODE_100baseFX_Full_BIT */ - [92] = 10, /* ETHTOOL_LINK_MODE_10baseT1L_Full_BIT */ - [93] = 800000, /* ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT */ - [94] = 800000, /* ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT */ - [95] = 800000, /* ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT */ - [96] = 800000, /* ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT */ - [97] = 800000, /* ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT */ - [98] = 800000, /* ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT */ - [99] = 10, /* ETHTOOL_LINK_MODE_10baseT1S_Full_BIT */ - [100] = 11, /* ETHTOOL_LINK_MODE_10baseT1S_Half_BIT */ - [101] = 11, /* ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT */ +static const uint32_t link_modes[][3] = { + [0] = {10, 0, 1}, /* ETHTOOL_LINK_MODE_10baseT_Half_BIT */ + [1] = {10, 1, 1}, /* ETHTOOL_LINK_MODE_10baseT_Full_BIT */ + [2] = {100, 0, 1}, /* ETHTOOL_LINK_MODE_100baseT_Half_BIT */ + [3] = {100, 1, 1}, /* ETHTOOL_LINK_MODE_100baseT_Full_BIT */ + [4] = {1000, 0, 1}, /* ETHTOOL_LINK_MODE_1000baseT_Half_BIT */ + [5] = {1000, 1, 1}, /* ETHTOOL_LINK_MODE_1000baseT_Full_BIT */ + [12] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseT_Full_BIT */ + [15] = {2500, 1, 1}, /* ETHTOOL_LINK_MODE_2500baseX_Full_BIT */ + [17] = {1000, 1, 1}, /* ETHTOOL_LINK_MODE_1000baseKX_Full_BIT */ + [18] = {10000, 1, 4}, /* ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT */ + [19] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseKR_Full_BIT */ + [20] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseR_FEC_BIT */ + [21] = {20000, 1, 2}, /* ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT */ + [22] = {20000, 1, 2}, /* ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT */ + [23] = {40000, 1, 4}, /* ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT */ + [24] = {40000, 1, 4}, /* ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT */ + [25] = {40000, 1, 4}, /* ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT */ + [26] = {40000, 1, 4}, /* ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT */ + [27] = {56000, 1, 4}, /* ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT */ + [28] = {56000, 1, 4}, /* ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT */ + [29] = {56000, 1, 4}, /* ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT */ + [30] = {56000, 1, 4}, /* ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT */ + [31] = {25000, 1, 1}, /* ETHTOOL_LINK_MODE_25000baseCR_Full_BIT */ + [32] = {25000, 1, 1}, /* ETHTOOL_LINK_MODE_25000baseKR_Full_BIT */ + [33] = {25000, 1, 1}, /* ETHTOOL_LINK_MODE_25000baseSR_Full_BIT */ + [34] = {50000, 1, 2}, /* ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT */ + [35] = {50000, 1, 2}, /* ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT */ + [36] = {100000, 1, 4}, /* ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT */ + [37] = {100000, 1, 4}, /* ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT */ + [38] = {100000, 1, 4}, /* ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT */ + [39] = {100000, 1, 4}, /* ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT */ + [40] = {50000, 1, 2}, /* ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT */ + [41] = {1000, 1, 1}, /* ETHTOOL_LINK_MODE_1000baseX_Full_BIT */ + [42] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseCR_Full_BIT */ + [43] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseSR_Full_BIT */ + [44] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseLR_Full_BIT */ + [45] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT */ + [46] = {10000, 1, 1}, /* ETHTOOL_LINK_MODE_10000baseER_Full_BIT */ + [47] = {2500, 1, 1}, /* ETHTOOL_LINK_MODE_2500baseT_Full_BIT */ + [48] = {5000, 1, 1}, /* ETHTOOL_LINK_MODE_5000baseT_Full_BIT */ + [52] = {50000, 1, 1}, /* ETHTOOL_LINK_MODE_50000baseKR_Full_BIT */ + [53] = {50000, 1, 1}, /* ETHTOOL_LINK_MODE_50000baseSR_Full_BIT */ + [54] = {50000, 1, 1}, /* ETHTOOL_LINK_MODE_50000baseCR_Full_BIT */ + [55] = {50000, 1, 1}, /* ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT */ + [56] = {50000, 1, 1}, /* ETHTOOL_LINK_MODE_50000baseDR_Full_BIT */ + [57] = {100000, 1, 2}, /* ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT */ + [58] = {100000, 1, 2}, /* ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT */ + [59] = {100000, 1, 2}, /* ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT */ + [60] = {100000, 1, 2}, /* ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT */ + [61] = {100000, 1, 2}, /* ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT */ + [62] = {200000, 1, 4}, /* ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT */ + [63] = {200000, 1, 4}, /* ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT */ + [64] = {200000, 1, 4}, /* ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT */ + [65] = {200000, 1, 4}, /* ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT */ + [66] = {200000, 1, 4}, /* ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT */ + [67] = {100, 1, 1}, /* ETHTOOL_LINK_MODE_100baseT1_Full_BIT */ + [68] = {1000, 1, 1}, /* ETHTOOL_LINK_MODE_1000baseT1_Full_BIT */ + [69] = {400000, 1, 8}, /* ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT */ + [70] = {400000, 1, 8}, /* ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT */ + [71] = {400000, 1, 8}, /* ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT */ + [72] = {400000, 1, 8}, /* ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT */ + [73] = {400000, 1, 8}, /* ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT */ + [75] = {100000, 1, 1}, /* ETHTOOL_LINK_MODE_100000baseKR_Full_BIT */ + [76] = {100000, 1, 1}, /* ETHTOOL_LINK_MODE_100000baseSR_Full_BIT */ + [77] = {100000, 1, 1}, /* ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT */ + [78] = {100000, 1, 1}, /* ETHTOOL_LINK_MODE_100000baseCR_Full_BIT */ + [79] = {100000, 1, 1}, /* ETHTOOL_LINK_MODE_100000baseDR_Full_BIT */ + [80] = {200000, 1, 2}, /* ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT */ + [81] = {200000, 1, 2}, /* ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT */ + [82] = {200000, 1, 2}, /* ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT */ + [83] = {200000, 1, 2}, /* ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT */ + [84] = {200000, 1, 2}, /* ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT */ + [85] = {400000, 1, 4}, /* ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT */ + [86] = {400000, 1, 4}, /* ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT */ + [87] = {400000, 1, 4}, /* ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT */ + [88] = {400000, 1, 4}, /* ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT */ + [89] = {400000, 1, 4}, /* ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT */ + [90] = {100, 0, 1}, /* ETHTOOL_LINK_MODE_100baseFX_Half_BIT */ + [91] = {100, 1, 1}, /* ETHTOOL_LINK_MODE_100baseFX_Full_BIT */ + [92] = {10, 1, 1}, /* ETHTOOL_LINK_MODE_10baseT1L_Full_BIT */ + [93] = {800000, 1, 8}, /* ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT */ + [94] = {800000, 1, 8}, /* ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT */ + [95] = {800000, 1, 8}, /* ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT */ + [96] = {800000, 1, 8}, /* ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT */ + [97] = {800000, 1, 8}, /* ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT */ + [98] = {800000, 1, 8}, /* ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT */ + [99] = {10, 1, 1}, /* ETHTOOL_LINK_MODE_10baseT1S_Full_BIT */ + [100] = {10, 0, 1}, /* ETHTOOL_LINK_MODE_10baseT1S_Half_BIT */ + [101] = {10, 0, 1}, /* ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT */ }; uint32_t rte_eth_link_speed_ethtool(enum ethtool_link_mode_bit_indices bit) { - uint32_t speed; - int duplex; + uint32_t speed, duplex, lanes; /* get mode from array */ if (bit >= RTE_DIM(link_modes)) return RTE_ETH_LINK_SPEED_AUTONEG; - speed = link_modes[bit]; - if (speed == 0) + if (link_modes[bit][RTE_ETH_LINK_MODES_INDEX_SPEED] == 0) return RTE_ETH_LINK_SPEED_AUTONEG; RTE_BUILD_BUG_ON(RTE_ETH_LINK_SPEED_AUTONEG != 0); - /* duplex is LSB */ - duplex = (speed & 1) ? - RTE_ETH_LINK_HALF_DUPLEX : - RTE_ETH_LINK_FULL_DUPLEX; - speed &= RTE_GENMASK32(31, 1); - - return rte_eth_speed_bitflag(speed, duplex); + speed = link_modes[bit][RTE_ETH_LINK_MODES_INDEX_SPEED]; + duplex = link_modes[bit][RTE_ETH_LINK_MODES_INDEX_DUPLEX]; + lanes = link_modes[bit][RTE_ETH_LINK_MODES_INDEX_LANES]; + return rte_eth_speed_bitflag(speed, duplex, lanes); } uint32_t diff --git a/lib/ethdev/ethdev_private.h b/lib/ethdev/ethdev_private.h index 0d36b9c30f..9092ab3a9e 100644 --- a/lib/ethdev/ethdev_private.h +++ b/lib/ethdev/ethdev_private.h @@ -79,4 +79,8 @@ void eth_dev_txq_release(struct rte_eth_dev *dev, uint16_t qid); int eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues); int eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues); +/* versioned functions */ +uint32_t rte_eth_speed_bitflag_v24(uint32_t speed, int duplex); +uint32_t rte_eth_speed_bitflag_v25(uint32_t speed, uint8_t lanes, int duplex); + #endif /* _ETH_PRIVATE_H_ */ diff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h index 3bec87bfdb..5547b49cab 100644 --- a/lib/ethdev/ethdev_trace.h +++ b/lib/ethdev/ethdev_trace.h @@ -183,8 +183,10 @@ RTE_TRACE_POINT( RTE_TRACE_POINT( rte_eth_trace_speed_bitflag, - RTE_TRACE_POINT_ARGS(uint32_t speed, int duplex, uint32_t ret), + RTE_TRACE_POINT_ARGS(uint32_t speed, uint8_t lanes, int duplex, + uint32_t ret), rte_trace_point_emit_u32(speed); + rte_trace_point_emit_u8(lanes); rte_trace_point_emit_int(duplex); rte_trace_point_emit_u32(ret); ) diff --git a/lib/ethdev/meson.build b/lib/ethdev/meson.build index f1d2586591..2c9588d0b3 100644 --- a/lib/ethdev/meson.build +++ b/lib/ethdev/meson.build @@ -62,3 +62,5 @@ endif if get_option('buildtype').contains('debug') cflags += ['-DRTE_FLOW_DEBUG'] endif + +use_function_versioning = true diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index f1c658f49e..6571116fbf 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "rte_ethdev.h" #include "rte_ethdev_trace_fp.h" @@ -991,63 +992,101 @@ rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id) return ret; } -uint32_t -rte_eth_speed_bitflag(uint32_t speed, int duplex) +uint32_t __vsym +rte_eth_speed_bitflag_v25(uint32_t speed, uint8_t lanes, int duplex) { - uint32_t ret; + uint32_t ret = 0; switch (speed) { case RTE_ETH_SPEED_NUM_10M: - ret = duplex ? RTE_ETH_LINK_SPEED_10M : RTE_ETH_LINK_SPEED_10M_HD; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = duplex ? RTE_ETH_LINK_SPEED_10M : RTE_ETH_LINK_SPEED_10M_HD; break; case RTE_ETH_SPEED_NUM_100M: - ret = duplex ? RTE_ETH_LINK_SPEED_100M : RTE_ETH_LINK_SPEED_100M_HD; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = duplex ? RTE_ETH_LINK_SPEED_100M : RTE_ETH_LINK_SPEED_100M_HD; break; case RTE_ETH_SPEED_NUM_1G: - ret = RTE_ETH_LINK_SPEED_1G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_1G; break; case RTE_ETH_SPEED_NUM_2_5G: - ret = RTE_ETH_LINK_SPEED_2_5G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_2_5G; break; case RTE_ETH_SPEED_NUM_5G: - ret = RTE_ETH_LINK_SPEED_5G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_5G; break; case RTE_ETH_SPEED_NUM_10G: - ret = RTE_ETH_LINK_SPEED_10G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_10G; + else if (lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_10G_4LANES; break; case RTE_ETH_SPEED_NUM_20G: - ret = RTE_ETH_LINK_SPEED_20G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_20G_2LANES; break; case RTE_ETH_SPEED_NUM_25G: - ret = RTE_ETH_LINK_SPEED_25G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_25G; break; case RTE_ETH_SPEED_NUM_40G: - ret = RTE_ETH_LINK_SPEED_40G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_40G_4LANES; break; case RTE_ETH_SPEED_NUM_50G: - ret = RTE_ETH_LINK_SPEED_50G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_50G; + else if (lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_50G_2LANES; break; case RTE_ETH_SPEED_NUM_56G: - ret = RTE_ETH_LINK_SPEED_56G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_56G_4LANES; break; case RTE_ETH_SPEED_NUM_100G: - ret = RTE_ETH_LINK_SPEED_100G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_1) + ret = RTE_ETH_LINK_SPEED_100G; + else if (lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_100G_2LANES; + else if (lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_100G_4LANES; break; case RTE_ETH_SPEED_NUM_200G: - ret = RTE_ETH_LINK_SPEED_200G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_200G_4LANES; + else if (lanes == RTE_ETH_LANES_2) + ret = RTE_ETH_LINK_SPEED_200G_2LANES; break; case RTE_ETH_SPEED_NUM_400G: - ret = RTE_ETH_LINK_SPEED_400G; + if (lanes == RTE_ETH_LANES_UNKNOWN || lanes == RTE_ETH_LANES_4) + ret = RTE_ETH_LINK_SPEED_400G_4LANES; + else if (lanes == RTE_ETH_LANES_8) + ret = RTE_ETH_LINK_SPEED_400G_8LANES; break; default: ret = 0; } - rte_eth_trace_speed_bitflag(speed, duplex, ret); + rte_eth_trace_speed_bitflag(speed, lanes, duplex, ret); return ret; } +uint32_t __vsym +rte_eth_speed_bitflag_v24(uint32_t speed, int duplex) +{ + return rte_eth_speed_bitflag_v25(speed, RTE_ETH_LANES_UNKNOWN, duplex); +} + +/* mark the v24 function as the older version, and v25 as the default version */ +VERSION_SYMBOL(rte_eth_speed_bitflag, _v24, 24); +BIND_DEFAULT_SYMBOL(rte_eth_speed_bitflag, _v25, 25); +MAP_STATIC_SYMBOL(uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex), + rte_eth_speed_bitflag_v25); + const char * rte_eth_dev_rx_offload_name(uint64_t offload) { @@ -3110,13 +3149,21 @@ rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link) if (eth_link->link_status == RTE_ETH_LINK_DOWN) ret = snprintf(str, len, "Link down"); - else + else if (eth_link->link_lanes == RTE_ETH_LANES_UNKNOWN) ret = snprintf(str, len, "Link up at %s %s %s", rte_eth_link_speed_to_str(eth_link->link_speed), (eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? "FDX" : "HDX", (eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ? "Autoneg" : "Fixed"); + else + ret = snprintf(str, len, "Link up at %s %u lanes %s %s", + rte_eth_link_speed_to_str(eth_link->link_speed), + eth_link->link_lanes, + (eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? + "FDX" : "HDX", + (eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ? + "Autoneg" : "Fixed"); rte_eth_trace_link_to_str(len, eth_link, str, ret); diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 147257d6a2..123b771046 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -288,24 +288,40 @@ struct rte_eth_stats { /**@{@name Link speed capabilities * Device supported speeds bitmap flags */ -#define RTE_ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */ -#define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */ -#define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */ -#define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */ -#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */ -#define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */ -#define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */ -#define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */ -#define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */ -#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ -#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps */ -#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ -#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps */ -#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ -#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps */ -#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ -#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps */ -#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps */ +#define RTE_ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */ +#define RTE_ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */ +#define RTE_ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */ +#define RTE_ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */ +#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */ +#define RTE_ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */ +#define RTE_ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */ +#define RTE_ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */ +#define RTE_ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */ +#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ +#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps 2lanes */ +#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ +#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ +#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ +#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_10G_4LANES RTE_BIT32(17) /**< 10 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_50G_2LANES RTE_BIT32(18) /**< 50 Gbps 2 lanes */ +#define RTE_ETH_LINK_SPEED_100G_2LANES RTE_BIT32(19) /**< 100 Gbps 2 lanes */ +#define RTE_ETH_LINK_SPEED_100G_4LANES RTE_BIT32(20) /**< 100 Gbps 4lanes */ +#define RTE_ETH_LINK_SPEED_200G_2LANES RTE_BIT32(21) /**< 200 Gbps 2lanes */ +#define RTE_ETH_LINK_SPEED_400G_8LANES RTE_BIT32(22) /**< 400 Gbps 8lanes */ +/**@}*/ + +/**@{@name Link speed capabilities + * Default lanes, use to compatible with earlier versions + */ +#define RTE_ETH_LINK_SPEED_20G_2LANES RTE_ETH_LINK_SPEED_20G +#define RTE_ETH_LINK_SPEED_40G_4LANES RTE_ETH_LINK_SPEED_40G +#define RTE_ETH_LINK_SPEED_56G_4LANES RTE_ETH_LINK_SPEED_56G +#define RTE_ETH_LINK_SPEED_200G_4LANES RTE_ETH_LINK_SPEED_200G +#define RTE_ETH_LINK_SPEED_400G_4LANES RTE_ETH_LINK_SPEED_400G /**@}*/ /**@{@name Link speed @@ -329,6 +345,16 @@ struct rte_eth_stats { #define RTE_ETH_SPEED_NUM_UNKNOWN UINT32_MAX /**< Unknown */ /**@}*/ +/**@{@name Link lane number + * Ethernet lane number + */ +#define RTE_ETH_LANES_UNKNOWN 0 /**< Unknown */ +#define RTE_ETH_LANES_1 1 /**< 1 lanes */ +#define RTE_ETH_LANES_2 2 /**< 2 lanes */ +#define RTE_ETH_LANES_4 4 /**< 4 lanes */ +#define RTE_ETH_LANES_8 8 /**< 8 lanes */ +/**@}*/ + /** * A structure used to retrieve link-level information of an Ethernet port. */ @@ -338,6 +364,7 @@ struct __rte_aligned(8) rte_eth_link { /**< aligned for atomic64 read/write */ uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ + uint16_t link_lanes : 4; /**< RTE_ETH_LANES_ */ }; /**@{@name Link negotiation @@ -1641,6 +1668,12 @@ struct rte_eth_conf { #define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP RTE_BIT64(3) /** Device supports keeping shared flow objects across restart. */ #define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP RTE_BIT64(4) +/** + * Device supports setting lanes. When the device does not support it, + * if a speed supports different numbers of lanes, the application does + * not knowe which the lane number are used by the device. + */ +#define RTE_ETH_DEV_CAPA_SETTING_LANES RTE_BIT64(5) /**@}*/ /* @@ -2301,12 +2334,16 @@ uint16_t rte_eth_dev_count_total(void); * * @param speed * Numerical speed value in Mbps + * @param lanes + * number of lanes (RTE_ETH_LANES_x) + * RTE_ETH_LANES_UNKNOWN is always used when the device does not support + * setting lanes * @param duplex * RTE_ETH_LINK_[HALF/FULL]_DUPLEX (only for 10/100M speeds) * @return * 0 if the speed cannot be mapped */ -uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex); +uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex); /** * Get RTE_ETH_RX_OFFLOAD_* flag name. diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index 79f6f5293b..9fa2439976 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -169,6 +169,12 @@ DPDK_24 { local: *; }; +DPDK_25 { + global: + + rte_eth_speed_bitflag; +} DPDK_24; + EXPERIMENTAL { global: From patchwork Fri Mar 22 07:09:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138734 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A4FB43D1E; Fri, 22 Mar 2024 08:09:39 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 32A3842E80; Fri, 22 Mar 2024 08:09:31 +0100 (CET) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 5C08C42DE9 for ; Fri, 22 Mar 2024 08:09:26 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4V1D2g3kFgz1GChk; Fri, 22 Mar 2024 15:08:59 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id C5B29140384; Fri, 22 Mar 2024 15:09:24 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 22 Mar 2024 15:09:24 +0800 From: Dengdui Huang To: CC: , , , , , , , , , , , , Subject: [PATCH v2 2/6] test: updated UT for setting lanes Date: Fri, 22 Mar 2024 15:09:19 +0800 Message-ID: <20240322070923.244417-3-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The lanes number is added to the ethdev link test case. Signed-off-by: Dengdui Huang --- app/test/test_ethdev_link.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/app/test/test_ethdev_link.c b/app/test/test_ethdev_link.c index f063a5fe26..1c31bc0448 100644 --- a/app/test/test_ethdev_link.c +++ b/app/test/test_ethdev_link.c @@ -17,14 +17,15 @@ test_link_status_up_default(void) .link_speed = RTE_ETH_SPEED_NUM_2_5G, .link_status = RTE_ETH_LINK_UP, .link_autoneg = RTE_ETH_LINK_AUTONEG, - .link_duplex = RTE_ETH_LINK_FULL_DUPLEX + .link_duplex = RTE_ETH_LINK_FULL_DUPLEX, + .link_lanes = RTE_ETH_LANES_1 }; char text[RTE_ETH_LINK_MAX_STR_LEN]; ret = rte_eth_link_to_str(text, sizeof(text), &link_status); RTE_TEST_ASSERT(ret > 0, "Failed to format default string\n"); printf("Default link up #1: %s\n", text); - TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at 2.5 Gbps FDX Autoneg", + TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at 2.5 Gbps 1 lanes FDX Autoneg", text, strlen(text), "Invalid default link status string"); link_status.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; @@ -33,7 +34,7 @@ test_link_status_up_default(void) ret = rte_eth_link_to_str(text, sizeof(text), &link_status); printf("Default link up #2: %s\n", text); RTE_TEST_ASSERT(ret > 0, "Failed to format default string\n"); - TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at 10 Mbps HDX Fixed", + TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at 10 Mbps 1 lanes HDX Fixed", text, strlen(text), "Invalid default link status " "string with HDX"); @@ -41,7 +42,7 @@ test_link_status_up_default(void) ret = rte_eth_link_to_str(text, sizeof(text), &link_status); printf("Default link up #3: %s\n", text); RTE_TEST_ASSERT(ret > 0, "Failed to format default string\n"); - TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at Unknown HDX Fixed", + TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at Unknown 1 lanes HDX Fixed", text, strlen(text), "Invalid default link status " "string with HDX"); @@ -49,7 +50,7 @@ test_link_status_up_default(void) ret = rte_eth_link_to_str(text, sizeof(text), &link_status); printf("Default link up #3: %s\n", text); RTE_TEST_ASSERT(ret > 0, "Failed to format default string\n"); - TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at None HDX Fixed", + TEST_ASSERT_BUFFERS_ARE_EQUAL("Link up at None 1 lanes HDX Fixed", text, strlen(text), "Invalid default link status " "string with HDX"); @@ -57,6 +58,7 @@ test_link_status_up_default(void) link_status.link_speed = RTE_ETH_SPEED_NUM_400G; link_status.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; link_status.link_autoneg = RTE_ETH_LINK_AUTONEG; + link_status.link_lanes = RTE_ETH_LANES_4; ret = rte_eth_link_to_str(text, sizeof(text), &link_status); printf("Default link up #4:len = %d, %s\n", ret, text); RTE_TEST_ASSERT(ret < RTE_ETH_LINK_MAX_STR_LEN, @@ -72,7 +74,8 @@ test_link_status_down_default(void) .link_speed = RTE_ETH_SPEED_NUM_2_5G, .link_status = RTE_ETH_LINK_DOWN, .link_autoneg = RTE_ETH_LINK_AUTONEG, - .link_duplex = RTE_ETH_LINK_FULL_DUPLEX + .link_duplex = RTE_ETH_LINK_FULL_DUPLEX, + .link_lanes = RTE_ETH_LANES_1 }; char text[RTE_ETH_LINK_MAX_STR_LEN]; @@ -92,7 +95,8 @@ test_link_status_invalid(void) .link_speed = 55555, .link_status = RTE_ETH_LINK_UP, .link_autoneg = RTE_ETH_LINK_AUTONEG, - .link_duplex = RTE_ETH_LINK_FULL_DUPLEX + .link_duplex = RTE_ETH_LINK_FULL_DUPLEX, + .link_lanes = RTE_ETH_LANES_UNKNOWN }; char text[RTE_ETH_LINK_MAX_STR_LEN]; From patchwork Fri Mar 22 07:09:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138733 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A35BF43D1E; Fri, 22 Mar 2024 08:09:33 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E631242E67; Fri, 22 Mar 2024 08:09:29 +0100 (CET) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mails.dpdk.org (Postfix) with ESMTP id 489174003C for ; Fri, 22 Mar 2024 08:09:26 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4V1D2g4x2hz1GChm; Fri, 22 Mar 2024 15:08:59 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id EE73718005F; Fri, 22 Mar 2024 15:09:24 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 22 Mar 2024 15:09:24 +0800 From: Dengdui Huang To: CC: , , , , , , , , , , , , Subject: [PATCH v2 3/6] ethdev: add function to parse link mode info Date: Fri, 22 Mar 2024 15:09:20 +0800 Message-ID: <20240322070923.244417-4-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added function rte_eth_link_mode_parse() to parse the speed number, lanes and duplex parameters from the Link speed apabilities bitmap flags. Signed-off-by: Dengdui Huang --- doc/guides/rel_notes/release_24_03.rst | 3 + lib/ethdev/rte_ethdev.c | 199 +++++++++++++++++++++++++ lib/ethdev/rte_ethdev.h | 29 ++++ lib/ethdev/version.map | 1 + 4 files changed, 232 insertions(+) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index 4621689c68..b41b0028b2 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -78,6 +78,9 @@ New Features * **Support setting lanes for ethdev.** * Support setting lanes by extended ``RTE_ETH_LINK_SPEED_*``. + * Added function to parse the speed number, lanes and duplex parameters from + * the Link speed apabilities bitmap flags: + ``rte_eth_link_mode_parse()`` * **Added hash calculation of an encapsulated packet as done by the HW.** diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c index 6571116fbf..bac7c652be 100644 --- a/lib/ethdev/rte_ethdev.c +++ b/lib/ethdev/rte_ethdev.c @@ -1105,6 +1105,205 @@ rte_eth_dev_rx_offload_name(uint64_t offload) return name; } +int +rte_eth_link_mode_parse(uint32_t link_speed, + struct rte_eth_link_mode_info *mode_onfo) +{ + const struct { + uint32_t speed_capa; + struct rte_eth_link_mode_info mode_onfo; + } speed_mode_onfo_map[] = { + { + RTE_ETH_LINK_SPEED_10M_HD, + { + RTE_ETH_SPEED_NUM_10M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_HALF_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_10M, + { + RTE_ETH_SPEED_NUM_10M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100M_HD, + { + RTE_ETH_SPEED_NUM_100M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_HALF_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100M, + { + RTE_ETH_SPEED_NUM_100M, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_1G, + { + RTE_ETH_SPEED_NUM_1G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_2_5G, + { + RTE_ETH_SPEED_NUM_2_5G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_5G, + { + RTE_ETH_SPEED_NUM_5G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_10G, + { + RTE_ETH_SPEED_NUM_10G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_20G_2LANES, + { + RTE_ETH_SPEED_NUM_20G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_25G, + { + RTE_ETH_SPEED_NUM_25G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_40G_4LANES, + { + RTE_ETH_SPEED_NUM_40G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_50G, + { + RTE_ETH_SPEED_NUM_50G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_56G_4LANES, + { + RTE_ETH_SPEED_NUM_56G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100G, + { + RTE_ETH_SPEED_NUM_100G, + RTE_ETH_LANES_1, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_200G_4LANES, + { + RTE_ETH_SPEED_NUM_200G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_400G_4LANES, + { + RTE_ETH_SPEED_NUM_400G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_10G_4LANES, + { + RTE_ETH_SPEED_NUM_10G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_50G_2LANES, + { + RTE_ETH_SPEED_NUM_50G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100G_2LANES, + { + RTE_ETH_SPEED_NUM_100G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_100G_4LANES, + { + RTE_ETH_SPEED_NUM_100G, + RTE_ETH_LANES_4, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_200G_2LANES, + { + RTE_ETH_SPEED_NUM_200G, + RTE_ETH_LANES_2, + RTE_ETH_LINK_FULL_DUPLEX + } + }, + { + RTE_ETH_LINK_SPEED_400G_8LANES, + { + RTE_ETH_SPEED_NUM_400G, + RTE_ETH_LANES_8, + RTE_ETH_LINK_FULL_DUPLEX + } + } + }; + uint32_t i; + + for (i = 0; i < RTE_DIM(speed_mode_onfo_map); i++) { + if (link_speed == speed_mode_onfo_map[i].speed_capa) { + mode_onfo->speed_num = speed_mode_onfo_map[i].mode_onfo.speed_num; + mode_onfo->lanes = speed_mode_onfo_map[i].mode_onfo.lanes; + mode_onfo->duplex = speed_mode_onfo_map[i].mode_onfo.duplex; + return 0; + } + } + + return -EINVAL; +} + const char * rte_eth_dev_tx_offload_name(uint64_t offload) { diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h index 123b771046..b7aacf6da8 100644 --- a/lib/ethdev/rte_ethdev.h +++ b/lib/ethdev/rte_ethdev.h @@ -355,6 +355,15 @@ struct rte_eth_stats { #define RTE_ETH_LANES_8 8 /**< 8 lanes */ /**@}*/ +/** + * A structure used to store information of link mode. + */ +struct rte_eth_link_mode_info { + uint32_t speed_num; /**< RTE_ETH_SPEED_NUM_ */ + uint8_t lanes; /**< RTE_ETH_LANES_ */ + uint8_t duplex; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ +}; + /** * A structure used to retrieve link-level information of an Ethernet port. */ @@ -2345,6 +2354,26 @@ uint16_t rte_eth_dev_count_total(void); */ uint32_t rte_eth_speed_bitflag(uint32_t speed, uint8_t lanes, int duplex); +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Parse the speed number, lanes and duplex parameters from the Link speed + * capabilities bitmap flags. + * + * @param link_speed + * speed capabilities bitmap flag (RTE_ETH_LINK_SPEED_) + * @param mode_onfo + * A pointer to a structure of type *rte_eth_link_mode_info* to be filled + * with the information of link mode. + * @return + * - (0) if successful. + * - (-EINVAL) if bad parameter. + */ +__rte_experimental +int rte_eth_link_mode_parse(uint32_t link_speed, + struct rte_eth_link_mode_info *mode_info); + /** * Get RTE_ETH_RX_OFFLOAD_* flag name. * diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map index 9fa2439976..5726498dd1 100644 --- a/lib/ethdev/version.map +++ b/lib/ethdev/version.map @@ -326,6 +326,7 @@ EXPERIMENTAL { # added in 24.03 __rte_eth_trace_tx_queue_count; rte_eth_find_rss_algo; + rte_eth_link_mode_parse; rte_flow_async_update_resized; rte_flow_calc_encap_hash; rte_flow_template_table_resizable; From patchwork Fri Mar 22 07:09:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138735 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E042243D1E; Fri, 22 Mar 2024 08:09:46 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 68A7842E8A; Fri, 22 Mar 2024 08:09:32 +0100 (CET) Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) by mails.dpdk.org (Postfix) with ESMTP id A581042E62 for ; Fri, 22 Mar 2024 08:09:26 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4V1D095XF8z1R7lC; Fri, 22 Mar 2024 15:06:49 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id 29127140133; Fri, 22 Mar 2024 15:09:25 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 22 Mar 2024 15:09:24 +0800 From: Dengdui Huang To: CC: , , , , , , , , , , , , Subject: [PATCH v2 4/6] net/hns3: use parse link mode info function Date: Fri, 22 Mar 2024 15:09:21 +0800 Message-ID: <20240322070923.244417-5-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch use the framework public function to replace the driver's private function. Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 51 +++++++--------------------------- 1 file changed, 10 insertions(+), 41 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index ecd3b2ef64..1b380ac75f 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -4810,45 +4810,6 @@ hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) return 0; } -static uint32_t -hns3_get_link_speed(uint32_t link_speeds) -{ - uint32_t speed = RTE_ETH_SPEED_NUM_NONE; - - if (link_speeds & RTE_ETH_LINK_SPEED_10M || - link_speeds & RTE_ETH_LINK_SPEED_10M_HD) - speed = RTE_ETH_SPEED_NUM_10M; - if (link_speeds & RTE_ETH_LINK_SPEED_100M || - link_speeds & RTE_ETH_LINK_SPEED_100M_HD) - speed = RTE_ETH_SPEED_NUM_100M; - if (link_speeds & RTE_ETH_LINK_SPEED_1G) - speed = RTE_ETH_SPEED_NUM_1G; - if (link_speeds & RTE_ETH_LINK_SPEED_10G) - speed = RTE_ETH_SPEED_NUM_10G; - if (link_speeds & RTE_ETH_LINK_SPEED_25G) - speed = RTE_ETH_SPEED_NUM_25G; - if (link_speeds & RTE_ETH_LINK_SPEED_40G) - speed = RTE_ETH_SPEED_NUM_40G; - if (link_speeds & RTE_ETH_LINK_SPEED_50G) - speed = RTE_ETH_SPEED_NUM_50G; - if (link_speeds & RTE_ETH_LINK_SPEED_100G) - speed = RTE_ETH_SPEED_NUM_100G; - if (link_speeds & RTE_ETH_LINK_SPEED_200G) - speed = RTE_ETH_SPEED_NUM_200G; - - return speed; -} - -static uint8_t -hns3_get_link_duplex(uint32_t link_speeds) -{ - if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) || - (link_speeds & RTE_ETH_LINK_SPEED_100M_HD)) - return RTE_ETH_LINK_HALF_DUPLEX; - else - return RTE_ETH_LINK_FULL_DUPLEX; -} - static int hns3_set_copper_port_link_speed(struct hns3_hw *hw, struct hns3_set_link_speed_cfg *cfg) @@ -4980,14 +4941,22 @@ static int hns3_apply_link_speed(struct hns3_hw *hw) { struct rte_eth_conf *conf = &hw->data->dev_conf; + struct rte_eth_link_mode_info mode_info = {0}; struct hns3_set_link_speed_cfg cfg; + int ret; memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ? RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED; if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) { - cfg.speed = hns3_get_link_speed(conf->link_speeds); - cfg.duplex = hns3_get_link_duplex(conf->link_speeds); + ret = rte_eth_link_mode_parse(conf->link_speeds, &mode_info); + if (ret) { + hns3_err(hw, "failed to parse link mode, ret = %d", ret); + return ret; + } + cfg.speed = mode_onfo.speed_num; + cfg.speed = mode_info.speed_num; + cfg.duplex = mode_info.duplex; } return hns3_set_port_link_speed(hw, &cfg); From patchwork Fri Mar 22 07:09:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138738 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0585D43D1E; Fri, 22 Mar 2024 08:10:09 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 867B042EB6; Fri, 22 Mar 2024 08:09:39 +0100 (CET) Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by mails.dpdk.org (Postfix) with ESMTP id 3102F42DE9 for ; Fri, 22 Mar 2024 08:09:28 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4V1D2G1zcKz1vx5R; Fri, 22 Mar 2024 15:08:38 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id 572C3140384; Fri, 22 Mar 2024 15:09:25 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 22 Mar 2024 15:09:25 +0800 From: Dengdui Huang To: CC: , , , , , , , , , , , , Subject: [PATCH v2 5/6] net/hns3: support setting lanes Date: Fri, 22 Mar 2024 15:09:22 +0800 Message-ID: <20240322070923.244417-6-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Some speeds can be achieved with different number of lanes. For example, 100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps. When use different lanes, the port cannot be up. This patch add support for setting lanes and report lanes. In addition, when reporting FEC capability, it is incorrect to calculate speed_num from the speed function when one speed supports a different number of lanes. This patch modifies it together. Signed-off-by: Dengdui Huang --- doc/guides/rel_notes/release_24_03.rst | 2 + drivers/net/hns3/hns3_cmd.h | 15 ++- drivers/net/hns3/hns3_common.c | 2 + drivers/net/hns3/hns3_ethdev.c | 158 ++++++++++++++++++------- drivers/net/hns3/hns3_ethdev.h | 2 + 5 files changed, 134 insertions(+), 45 deletions(-) diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index b41b0028b2..c9b8740323 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -193,6 +193,8 @@ New Features * Added power-saving during polling within the ``rte_event_dequeue_burst()`` API. * Added support for DMA adapter. +* **Added setting lanes for hns3 PF driver.** + * This feature add support for setting lanes and report lanes. Removed Items ------------- diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 79a8c1edad..31ff7b35d8 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -753,7 +753,9 @@ struct hns3_config_mac_mode_cmd { struct hns3_config_mac_speed_dup_cmd { uint8_t speed_dup; uint8_t mac_change_fec_en; - uint8_t rsv[22]; + uint8_t rsv[4]; + uint8_t lanes; + uint8_t rsv1[17]; }; #define HNS3_TQP_ENABLE_B 0 @@ -789,12 +791,15 @@ struct hns3_sfp_type { #define HNS3_FIBER_LINK_SPEED_1G_BIT BIT(0) #define HNS3_FIBER_LINK_SPEED_10G_BIT BIT(1) #define HNS3_FIBER_LINK_SPEED_25G_BIT BIT(2) -#define HNS3_FIBER_LINK_SPEED_50G_BIT BIT(3) -#define HNS3_FIBER_LINK_SPEED_100G_BIT BIT(4) +#define HNS3_FIBER_LINK_SPEED_50G_R2_BIT BIT(3) +#define HNS3_FIBER_LINK_SPEED_100G_R4_BIT BIT(4) #define HNS3_FIBER_LINK_SPEED_40G_BIT BIT(5) #define HNS3_FIBER_LINK_SPEED_100M_BIT BIT(6) #define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7) -#define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8) +#define HNS3_FIBER_LINK_SPEED_200G_EXT_BIT BIT(8) +#define HNS3_FIBER_LINK_SPEED_50G_R1_BIT BIT(9) +#define HNS3_FIBER_LINK_SPEED_100G_R2_BIT BIT(10) +#define HNS3_FIBER_LINK_SPEED_200G_R4_BIT BIT(11) #define HNS3_FIBER_FEC_AUTO_BIT BIT(0) #define HNS3_FIBER_FEC_BASER_BIT BIT(1) @@ -823,7 +828,7 @@ struct hns3_sfp_info_cmd { uint32_t supported_speed; /* speed supported by current media */ uint32_t module_type; uint8_t fec_ability; /* supported fec modes, see HNS3_FIBER_FEC_XXX_BIT */ - uint8_t rsv0; + uint8_t lanes; uint8_t pause_status; uint8_t rsv1[5]; }; diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 28c26b049c..b6db012993 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -93,6 +93,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP | RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; + if (!hns->is_vf) + info->dev_capa |= RTE_ETH_DEV_CAPA_SETTING_LANES; if (hns3_dev_get_support(hw, INDEP_TXRX)) info->dev_capa |= RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 1b380ac75f..7f36c193a6 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -63,12 +63,12 @@ struct hns3_intr_state { uint32_t hw_err_state; }; -#define HNS3_SPEEDS_SUPP_FEC (RTE_ETH_LINK_SPEED_10G | \ - RTE_ETH_LINK_SPEED_25G | \ - RTE_ETH_LINK_SPEED_40G | \ - RTE_ETH_LINK_SPEED_50G | \ - RTE_ETH_LINK_SPEED_100G | \ - RTE_ETH_LINK_SPEED_200G) +#define HNS3_SPEED_NUM_10G_BIT RTE_BIT32(1) +#define HNS3_SPEED_NUM_25G_BIT RTE_BIT32(2) +#define HNS3_SPEED_NUM_40G_BIT RTE_BIT32(3) +#define HNS3_SPEED_NUM_50G_BIT RTE_BIT32(4) +#define HNS3_SPEED_NUM_100G_BIT RTE_BIT32(5) +#define HNS3_SPEED_NUM_200G_BIT RTE_BIT32(6) static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | @@ -2234,13 +2234,17 @@ hns3_get_firber_port_speed_capa(uint32_t supported_speed) if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) speed_capa |= RTE_ETH_LINK_SPEED_25G; if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) - speed_capa |= RTE_ETH_LINK_SPEED_40G; - if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_40G_4LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_R1_BIT) speed_capa |= RTE_ETH_LINK_SPEED_50G; - if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) - speed_capa |= RTE_ETH_LINK_SPEED_100G; - if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) - speed_capa |= RTE_ETH_LINK_SPEED_200G; + if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_R2_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_50G_2LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_R4_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_100G_4LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_R2_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_100G_2LANES; + if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_R4_BIT) + speed_capa |= RTE_ETH_LINK_SPEED_200G_4LANES; return speed_capa; } @@ -2308,6 +2312,7 @@ hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, if (!mac->link_status) new_link->link_speed = RTE_ETH_SPEED_NUM_NONE; + new_link->link_lanes = mac->link_lanes; new_link->link_duplex = mac->link_duplex; new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; new_link->link_autoneg = mac->link_autoneg; @@ -2934,7 +2939,8 @@ hns3_map_tqp(struct hns3_hw *hw) } static int -hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) +hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t lanes, + uint8_t duplex) { struct hns3_config_mac_speed_dup_cmd *req; struct hns3_cmd_desc desc; @@ -2989,6 +2995,7 @@ hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) } hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); + req->lanes = lanes; ret = hns3_cmd_send(hw, &desc, 1); if (ret) @@ -3643,7 +3650,10 @@ hns3_mac_init(struct hns3_hw *hw) pf->support_sfp_query = true; mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; - ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); + /* If lane is set to 0, the firmware selects the default lane. */ + mac->link_lanes = RTE_ETH_LANES_UNKNOWN; + ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_lanes, + mac->link_duplex); if (ret) { PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); return ret; @@ -4052,6 +4062,7 @@ hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) return 0; mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); + mac_info->link_lanes = resp->lanes; /* * if resp->supported_speed is 0, it means it's an old version * firmware, do not update these params. @@ -4088,16 +4099,18 @@ hns3_check_speed_dup(uint8_t duplex, uint32_t speed) } static int -hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) +hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t lanes, + uint8_t duplex) { struct hns3_mac *mac = &hw->mac; int ret; duplex = hns3_check_speed_dup(duplex, speed); - if (mac->link_speed == speed && mac->link_duplex == duplex) + if (mac->link_speed == speed && mac->link_lanes == lanes && + mac->link_duplex == duplex) return 0; - ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); + ret = hns3_cfg_mac_speed_dup_hw(hw, speed, lanes, duplex); if (ret) return ret; @@ -4106,6 +4119,7 @@ hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) return ret; mac->link_speed = speed; + mac->link_lanes = lanes; mac->link_duplex = duplex; return 0; @@ -4150,6 +4164,7 @@ hns3_update_fiber_link_info(struct hns3_hw *hw) } mac->link_speed = mac_info.link_speed; + mac->link_lanes = mac_info.link_lanes; mac->supported_speed = mac_info.supported_speed; mac->support_autoneg = mac_info.support_autoneg; mac->link_autoneg = mac_info.link_autoneg; @@ -4161,7 +4176,7 @@ hns3_update_fiber_link_info(struct hns3_hw *hw) } /* Config full duplex for SFP */ - return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, + return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, mac_info.link_lanes, RTE_ETH_LINK_FULL_DUPLEX); } @@ -4512,11 +4527,11 @@ hns3_set_firber_default_support_speed(struct hns3_hw *hw) case RTE_ETH_SPEED_NUM_40G: return HNS3_FIBER_LINK_SPEED_40G_BIT; case RTE_ETH_SPEED_NUM_50G: - return HNS3_FIBER_LINK_SPEED_50G_BIT; + return HNS3_FIBER_LINK_SPEED_50G_R2_BIT; case RTE_ETH_SPEED_NUM_100G: - return HNS3_FIBER_LINK_SPEED_100G_BIT; + return HNS3_FIBER_LINK_SPEED_100G_R4_BIT; case RTE_ETH_SPEED_NUM_200G: - return HNS3_FIBER_LINK_SPEED_200G_BIT; + return HNS3_FIBER_LINK_SPEED_200G_R4_BIT; default: hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); return 0; @@ -4769,17 +4784,23 @@ hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) case RTE_ETH_LINK_SPEED_25G: speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; break; - case RTE_ETH_LINK_SPEED_40G: + case RTE_ETH_LINK_SPEED_40G_4LANES: speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; break; case RTE_ETH_LINK_SPEED_50G: - speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; + speed_bit = HNS3_FIBER_LINK_SPEED_50G_R1_BIT; break; - case RTE_ETH_LINK_SPEED_100G: - speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; + case RTE_ETH_LINK_SPEED_50G_2LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_50G_R2_BIT; break; - case RTE_ETH_LINK_SPEED_200G: - speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; + case RTE_ETH_LINK_SPEED_100G_4LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_100G_R4_BIT; + break; + case RTE_ETH_LINK_SPEED_100G_2LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_100G_R2_BIT; + break; + case RTE_ETH_LINK_SPEED_200G_4LANES: + speed_bit = HNS3_FIBER_LINK_SPEED_200G_R4_BIT; break; default: speed_bit = 0; @@ -4900,7 +4921,7 @@ hns3_set_fiber_port_link_speed(struct hns3_hw *hw, return 0; } - return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); + return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->lanes, cfg->duplex); } const char * @@ -4954,7 +4975,7 @@ hns3_apply_link_speed(struct hns3_hw *hw) hns3_err(hw, "failed to parse link mode, ret = %d", ret); return ret; } - cfg.speed = mode_onfo.speed_num; + cfg.lanes = mode_info.lanes; cfg.speed = mode_info.speed_num; cfg.duplex = mode_info.duplex; } @@ -5927,20 +5948,49 @@ hns3_reset_service(void *param) hns3_msix_process(hns, reset_level); } +static uint32_t +hns3_speed_num_capa_bit(uint32_t speed_num) +{ + uint32_t speed_bit; + + switch (speed_num) { + case RTE_ETH_SPEED_NUM_10G: + speed_bit = HNS3_SPEED_NUM_10G_BIT; + break; + case RTE_ETH_SPEED_NUM_25G: + speed_bit = HNS3_SPEED_NUM_25G_BIT; + break; + case RTE_ETH_SPEED_NUM_40G: + speed_bit = HNS3_SPEED_NUM_40G_BIT; + break; + case RTE_ETH_SPEED_NUM_50G: + speed_bit = HNS3_SPEED_NUM_50G_BIT; + break; + case RTE_ETH_SPEED_NUM_100G: + speed_bit = HNS3_SPEED_NUM_100G_BIT; + break; + case RTE_ETH_SPEED_NUM_200G: + speed_bit = HNS3_SPEED_NUM_200G_BIT; + break; + default: + speed_bit = 0; + break; + } + + return speed_bit; +} + static uint32_t hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, - uint32_t speed_capa) + uint32_t speed_num_capa) { uint32_t speed_bit; uint32_t num = 0; uint32_t i; for (i = 0; i < RTE_DIM(speed_fec_capa_tbl); i++) { - speed_bit = - rte_eth_speed_bitflag(speed_fec_capa_tbl[i].speed, - RTE_ETH_LANES_UNKNOWN, - RTE_ETH_LINK_FULL_DUPLEX); - if ((speed_capa & speed_bit) == 0) + speed_bit = hns3_speed_num_capa_bit(speed_fec_capa_tbl[i].speed); + if ((speed_num_capa & speed_bit) == 0) continue; speed_fec_capa[num].speed = speed_fec_capa_tbl[i].speed; @@ -5951,6 +6001,34 @@ hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, return num; } +static uint32_t +hns3_get_speed_num_capa(struct hns3_hw *hw) +{ + uint32_t speed_num_capa = 0; + uint32_t speed_capa; + + speed_capa = hns3_get_speed_capa(hw); + + if (speed_capa & RTE_ETH_LINK_SPEED_10G) + speed_num_capa |= HNS3_SPEED_NUM_10G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_25G) + speed_num_capa |= HNS3_SPEED_NUM_25G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_40G_4LANES) + speed_num_capa |= HNS3_SPEED_NUM_40G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_50G) + speed_num_capa |= HNS3_SPEED_NUM_50G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_50G_2LANES) + speed_num_capa |= HNS3_SPEED_NUM_50G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_100G_4LANES) + speed_num_capa |= HNS3_SPEED_NUM_100G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_100G_2LANES) + speed_num_capa |= HNS3_SPEED_NUM_100G_BIT; + if (speed_capa & RTE_ETH_LINK_SPEED_200G_4LANES) + speed_num_capa |= HNS3_SPEED_NUM_200G_BIT; + + return speed_num_capa; +} + static int hns3_fec_get_capability(struct rte_eth_dev *dev, struct rte_eth_fec_capa *speed_fec_capa, @@ -5958,11 +6036,11 @@ hns3_fec_get_capability(struct rte_eth_dev *dev, { struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); unsigned int speed_num; - uint32_t speed_capa; + uint32_t speed_num_capa; - speed_capa = hns3_get_speed_capa(hw); - /* speed_num counts number of speed capabilities */ - speed_num = rte_popcount32(speed_capa & HNS3_SPEEDS_SUPP_FEC); + speed_num_capa = hns3_get_speed_num_capa(hw); + /* speed_num counts number of speed number capabilities */ + speed_num = rte_popcount32(speed_num_capa); if (speed_num == 0) return -ENOTSUP; @@ -5975,7 +6053,7 @@ hns3_fec_get_capability(struct rte_eth_dev *dev, return -EINVAL; } - return hns3_get_speed_fec_capa(speed_fec_capa, speed_capa); + return hns3_get_speed_fec_capa(speed_fec_capa, speed_num_capa); } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 12d8299def..070fc76420 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -168,6 +168,7 @@ struct hns3_set_link_speed_cfg { uint32_t speed; uint8_t duplex : 1; uint8_t autoneg : 1; + uint8_t lanes : 4; }; /* mac media type */ @@ -190,6 +191,7 @@ struct hns3_mac { uint8_t link_autoneg : 1; /* RTE_ETH_LINK_[AUTONEG/FIXED] */ uint8_t link_status : 1; /* RTE_ETH_LINK_[DOWN/UP] */ uint32_t link_speed; /* RTE_ETH_SPEED_NUM_ */ + uint8_t link_lanes; /* RTE_ETH_LANES_ */ /* * Some firmware versions support only the SFP speed query. In addition * to the SFP speed query, some firmware supports the query of the speed From patchwork Fri Mar 22 07:09:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dengdui Huang X-Patchwork-Id: 138737 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A9A343D1E; Fri, 22 Mar 2024 08:10:01 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 38A7C42EA6; Fri, 22 Mar 2024 08:09:38 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id EB54F4003C for ; Fri, 22 Mar 2024 08:09:27 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4V1D061CmczXjTV; Fri, 22 Mar 2024 15:06:46 +0800 (CST) Received: from dggpeml500011.china.huawei.com (unknown [7.185.36.84]) by mail.maildlp.com (Postfix) with ESMTPS id 82A8B1400E4; Fri, 22 Mar 2024 15:09:25 +0800 (CST) Received: from localhost.huawei.com (10.50.165.33) by dggpeml500011.china.huawei.com (7.185.36.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Fri, 22 Mar 2024 15:09:25 +0800 From: Dengdui Huang To: CC: , , , , , , , , , , , , Subject: [PATCH v2 6/6] app/testpmd: support setting lanes Date: Fri, 22 Mar 2024 15:09:23 +0800 Message-ID: <20240322070923.244417-7-huangdengdui@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20240322070923.244417-1-huangdengdui@huawei.com> References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500011.china.huawei.com (7.185.36.84) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a command to config speed with lanes and added print the lane number for show info command. Signed-off-by: Dengdui Huang --- app/test-pmd/cmdline.c | 199 +++++++++++++------- app/test-pmd/config.c | 78 +++++--- doc/guides/testpmd_app_ug/testpmd_funcs.rst | 9 + 3 files changed, 194 insertions(+), 92 deletions(-) diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c index f521a1fe9e..413bf735a2 100644 --- a/app/test-pmd/cmdline.c +++ b/app/test-pmd/cmdline.c @@ -696,6 +696,11 @@ static void cmd_help_long_parsed(void *parsed_result, " duplex (half|full|auto)\n" " Set speed and duplex for all ports or port_id\n\n" + "port config (port_id|all)" + " speed (10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto)" + " lanes (lane_num) duplex (half|full|auto)\n" + " Set speed and duplex for all ports or port_id\n\n" + "port config (port_id|all) loopback (mode)\n" " Set loopback mode for all ports or port_id\n\n" @@ -1357,14 +1362,19 @@ struct cmd_config_speed_all { cmdline_fixed_string_t all; cmdline_fixed_string_t item1; cmdline_fixed_string_t item2; + cmdline_fixed_string_t item3; cmdline_fixed_string_t value1; - cmdline_fixed_string_t value2; + uint8_t value2; + cmdline_fixed_string_t value3; }; static int -parse_and_check_speed_duplex(char *speedstr, char *duplexstr, uint32_t *speed) +parse_and_check_speed_duplex(char *speedstr, uint8_t lanes, char *duplexstr, + uint32_t *speed) { + uint32_t speed_num; + char *endptr; int duplex; if (!strcmp(duplexstr, "half")) { @@ -1378,47 +1388,22 @@ parse_and_check_speed_duplex(char *speedstr, char *duplexstr, uint32_t *speed) return -1; } - if (!strcmp(speedstr, "10")) { - *speed = (duplex == RTE_ETH_LINK_HALF_DUPLEX) ? - RTE_ETH_LINK_SPEED_10M_HD : RTE_ETH_LINK_SPEED_10M; - } else if (!strcmp(speedstr, "100")) { - *speed = (duplex == RTE_ETH_LINK_HALF_DUPLEX) ? - RTE_ETH_LINK_SPEED_100M_HD : RTE_ETH_LINK_SPEED_100M; - } else { - if (duplex != RTE_ETH_LINK_FULL_DUPLEX) { - fprintf(stderr, "Invalid speed/duplex parameters\n"); - return -1; - } - if (!strcmp(speedstr, "1000")) { - *speed = RTE_ETH_LINK_SPEED_1G; - } else if (!strcmp(speedstr, "2500")) { - *speed = RTE_ETH_LINK_SPEED_2_5G; - } else if (!strcmp(speedstr, "5000")) { - *speed = RTE_ETH_LINK_SPEED_5G; - } else if (!strcmp(speedstr, "10000")) { - *speed = RTE_ETH_LINK_SPEED_10G; - } else if (!strcmp(speedstr, "25000")) { - *speed = RTE_ETH_LINK_SPEED_25G; - } else if (!strcmp(speedstr, "40000")) { - *speed = RTE_ETH_LINK_SPEED_40G; - } else if (!strcmp(speedstr, "50000")) { - *speed = RTE_ETH_LINK_SPEED_50G; - } else if (!strcmp(speedstr, "100000")) { - *speed = RTE_ETH_LINK_SPEED_100G; - } else if (!strcmp(speedstr, "200000")) { - *speed = RTE_ETH_LINK_SPEED_200G; - } else if (!strcmp(speedstr, "400000")) { - *speed = RTE_ETH_LINK_SPEED_400G; - } else if (!strcmp(speedstr, "auto")) { - *speed = RTE_ETH_LINK_SPEED_AUTONEG; - } else { - fprintf(stderr, "Unknown speed parameter\n"); - return -1; - } + if (!strcmp(speedstr, "auto")) { + *speed = RTE_ETH_LINK_SPEED_AUTONEG; + return 0; } - if (*speed != RTE_ETH_LINK_SPEED_AUTONEG) - *speed |= RTE_ETH_LINK_SPEED_FIXED; + speed_num = strtol(speedstr, &endptr, 10); + if (*endptr != '\0') { + fprintf(stderr, "Unknown speed parameter\n"); + return -1; + } + + *speed = rte_eth_speed_bitflag(speed_num, lanes, duplex); + if (*speed == 0) { + fprintf(stderr, "param error\n"); + return -1; + } return 0; } @@ -1426,22 +1411,37 @@ parse_and_check_speed_duplex(char *speedstr, char *duplexstr, uint32_t *speed) static void cmd_config_speed_all_parsed(void *parsed_result, __rte_unused struct cmdline *cl, - __rte_unused void *data) + void *data) { struct cmd_config_speed_all *res = parsed_result; + struct rte_eth_dev_info dev_info; uint32_t link_speed; portid_t pid; + int ret; if (!all_ports_stopped()) { fprintf(stderr, "Please stop all ports first\n"); return; } - if (parse_and_check_speed_duplex(res->value1, res->value2, - &link_speed) < 0) + if (data) + ret = parse_and_check_speed_duplex(res->value1, res->value2, + res->value3, &link_speed); + else + ret = parse_and_check_speed_duplex(res->value1, 0, res->value3, + &link_speed); + if (ret < 0) return; RTE_ETH_FOREACH_DEV(pid) { + ret = eth_dev_info_get_print_err(pid, &dev_info); + if (ret != 0) + return; + if ((dev_info.dev_capa & RTE_ETH_DEV_CAPA_SETTING_LANES) == 0 && data) { + fprintf(stderr, "The port (%d) does not support setting lane\n", + pid); + return; + } ports[pid].dev_conf.link_speeds = link_speed; } @@ -1460,26 +1460,51 @@ static cmdline_parse_token_string_t cmd_config_speed_all_item1 = static cmdline_parse_token_string_t cmd_config_speed_all_value1 = TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value1, "10#100#1000#2500#5000#10000#25000#40000#50000#100000#200000#400000#auto"); -static cmdline_parse_token_string_t cmd_config_speed_all_item2 = - TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item2, "duplex"); -static cmdline_parse_token_string_t cmd_config_speed_all_value2 = - TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value2, +static cmdline_parse_token_string_t cmd_config_speed_all__item2 = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item2, "lanes"); +static cmdline_parse_token_num_t cmd_config_speed_all_value2 = + TOKEN_NUM_INITIALIZER(struct cmd_config_speed_all, value2, + RTE_UINT8); +static cmdline_parse_token_string_t cmd_config_speed_all_item3 = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item3, "duplex"); +static cmdline_parse_token_string_t cmd_config_speed_all_value3 = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value3, "half#full#auto"); -static cmdline_parse_inst_t cmd_config_speed_all = { +static cmdline_parse_inst_t cmd_config_speed_lanes_all = { .f = cmd_config_speed_all_parsed, - .data = NULL, + .data = (void *)1, .help_str = "port config all speed " - "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto duplex " - "half|full|auto", + "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto" + " lanes duplex half|full|auto", .tokens = { (void *)&cmd_config_speed_all_port, (void *)&cmd_config_speed_all_keyword, (void *)&cmd_config_speed_all_all, (void *)&cmd_config_speed_all_item1, (void *)&cmd_config_speed_all_value1, - (void *)&cmd_config_speed_all_item2, + (void *)&cmd_config_speed_all__item2, (void *)&cmd_config_speed_all_value2, + (void *)&cmd_config_speed_all_item3, + (void *)&cmd_config_speed_all_value3, + NULL, + }, +}; + +static cmdline_parse_inst_t cmd_config_speed_all = { + .f = cmd_config_speed_all_parsed, + .data = (void *)0, + .help_str = "port config all speed " + "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto" + " duplex half|full|auto", + .tokens = { + (void *)&cmd_config_speed_all_port, + (void *)&cmd_config_speed_all_keyword, + (void *)&cmd_config_speed_all_all, + (void *)&cmd_config_speed_all_item1, + (void *)&cmd_config_speed_all_value1, + (void *)&cmd_config_speed_all_item3, + (void *)&cmd_config_speed_all_value3, NULL, }, }; @@ -1491,17 +1516,20 @@ struct cmd_config_speed_specific { portid_t id; cmdline_fixed_string_t item1; cmdline_fixed_string_t item2; + cmdline_fixed_string_t item3; cmdline_fixed_string_t value1; - cmdline_fixed_string_t value2; + uint8_t value2; + cmdline_fixed_string_t value3; }; static void cmd_config_speed_specific_parsed(void *parsed_result, - __rte_unused struct cmdline *cl, - __rte_unused void *data) + __rte_unused struct cmdline *cl, void *data) { struct cmd_config_speed_specific *res = parsed_result; + struct rte_eth_dev_info dev_info; uint32_t link_speed; + int ret; if (port_id_is_invalid(res->id, ENABLED_WARN)) return; @@ -1511,8 +1539,23 @@ cmd_config_speed_specific_parsed(void *parsed_result, return; } - if (parse_and_check_speed_duplex(res->value1, res->value2, - &link_speed) < 0) + ret = eth_dev_info_get_print_err(res->id, &dev_info); + if (ret != 0) + return; + + if ((dev_info.dev_capa & RTE_ETH_DEV_CAPA_SETTING_LANES) == 0 && data) { + fprintf(stderr, "The port (%d) does not support setting lanes\n", + res->id); + return; + } + + if (data) + ret = parse_and_check_speed_duplex(res->value1, res->value2, + res->value3, &link_speed); + else + ret = parse_and_check_speed_duplex(res->value1, 0, res->value3, + &link_speed); + if (ret < 0) return; ports[res->id].dev_conf.link_speeds = link_speed; @@ -1537,17 +1580,23 @@ static cmdline_parse_token_string_t cmd_config_speed_specific_value1 = "10#100#1000#2500#5000#10000#25000#40000#50000#100000#200000#400000#auto"); static cmdline_parse_token_string_t cmd_config_speed_specific_item2 = TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, item2, + "lanes"); +static cmdline_parse_token_num_t cmd_config_speed_specific_value2 = + TOKEN_NUM_INITIALIZER(struct cmd_config_speed_specific, value2, + RTE_UINT8); +static cmdline_parse_token_string_t cmd_config_speed_specific_item3 = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, item3, "duplex"); -static cmdline_parse_token_string_t cmd_config_speed_specific_value2 = - TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, value2, +static cmdline_parse_token_string_t cmd_config_speed_specific_value3 = + TOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, value3, "half#full#auto"); -static cmdline_parse_inst_t cmd_config_speed_specific = { +static cmdline_parse_inst_t cmd_config_speed_lanes_specific = { .f = cmd_config_speed_specific_parsed, - .data = NULL, + .data = (void *)1, .help_str = "port config speed " - "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto duplex " - "half|full|auto", + "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto" + " lanes duplex half|full|auto", .tokens = { (void *)&cmd_config_speed_specific_port, (void *)&cmd_config_speed_specific_keyword, @@ -1556,6 +1605,26 @@ static cmdline_parse_inst_t cmd_config_speed_specific = { (void *)&cmd_config_speed_specific_value1, (void *)&cmd_config_speed_specific_item2, (void *)&cmd_config_speed_specific_value2, + (void *)&cmd_config_speed_specific_item3, + (void *)&cmd_config_speed_specific_value3, + NULL, + }, +}; + +static cmdline_parse_inst_t cmd_config_speed_specific = { + .f = cmd_config_speed_specific_parsed, + .data = (void *)0, + .help_str = "port config speed " + "10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto" + " duplex half|full|auto", + .tokens = { + (void *)&cmd_config_speed_specific_port, + (void *)&cmd_config_speed_specific_keyword, + (void *)&cmd_config_speed_specific_id, + (void *)&cmd_config_speed_specific_item1, + (void *)&cmd_config_speed_specific_value1, + (void *)&cmd_config_speed_specific_item3, + (void *)&cmd_config_speed_specific_value3, NULL, }, }; @@ -13237,6 +13306,8 @@ static cmdline_parse_ctx_t builtin_ctx[] = { (cmdline_parse_inst_t *)&cmd_set_port_setup_on, (cmdline_parse_inst_t *)&cmd_config_speed_all, (cmdline_parse_inst_t *)&cmd_config_speed_specific, + (cmdline_parse_inst_t *)&cmd_config_speed_lanes_all, + (cmdline_parse_inst_t *)&cmd_config_speed_lanes_specific, (cmdline_parse_inst_t *)&cmd_config_loopback_all, (cmdline_parse_inst_t *)&cmd_config_loopback_specific, (cmdline_parse_inst_t *)&cmd_config_rx_tx, diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c index ba1007ace6..3f77f321a5 100644 --- a/app/test-pmd/config.c +++ b/app/test-pmd/config.c @@ -587,39 +587,51 @@ device_infos_display_speeds(uint32_t speed_capa) if (speed_capa == RTE_ETH_LINK_SPEED_AUTONEG) printf(" Autonegotiate (all speeds)"); if (speed_capa & RTE_ETH_LINK_SPEED_FIXED) - printf(" Disable autonegotiate (fixed speed) "); + printf(" Disable autonegotiate (fixed speed) /"); if (speed_capa & RTE_ETH_LINK_SPEED_10M_HD) - printf(" 10 Mbps half-duplex "); + printf(" 10Mbps_1lane_half-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_10M) - printf(" 10 Mbps full-duplex "); + printf(" 10Mbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_100M_HD) - printf(" 100 Mbps half-duplex "); + printf(" 100Mbps_lane_half-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_100M) - printf(" 100 Mbps full-duplex "); + printf(" 100Mbps_1lane_full-duplex /"); if (speed_capa & RTE_ETH_LINK_SPEED_1G) - printf(" 1 Gbps "); + printf(" 1Gbps_1lane /"); if (speed_capa & RTE_ETH_LINK_SPEED_2_5G) - printf(" 2.5 Gbps "); + printf(" 2.5Gbps_1lane /"); if (speed_capa & RTE_ETH_LINK_SPEED_5G) - printf(" 5 Gbps "); + printf(" 5Gbps_1lane /"); if (speed_capa & RTE_ETH_LINK_SPEED_10G) - printf(" 10 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_20G) - printf(" 20 Gbps "); + printf(" 10Gbps_1lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_10G_4LANES) + printf(" 10Gbps_4lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_20G_2LANES) + printf(" 20Gbps_2lane /"); if (speed_capa & RTE_ETH_LINK_SPEED_25G) - printf(" 25 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_40G) - printf(" 40 Gbps "); + printf(" 25Gbps_1lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_40G_4LANES) + printf(" 40Gbps_4lane /"); if (speed_capa & RTE_ETH_LINK_SPEED_50G) - printf(" 50 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_56G) - printf(" 56 Gbps "); + printf(" 50Gbps_1lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_50G_2LANES) + printf(" 50Gbps_2lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_56G_4LANES) + printf(" 56Gbps_4lane /"); if (speed_capa & RTE_ETH_LINK_SPEED_100G) - printf(" 100 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_200G) - printf(" 200 Gbps "); - if (speed_capa & RTE_ETH_LINK_SPEED_400G) - printf(" 400 Gbps "); + printf(" 100Gbps_1lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_100G_2LANES) + printf(" 100Gbps_2lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_100G_4LANES) + printf(" 100Gbps_4lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_200G_4LANES) + printf(" 200Gbps_4lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_200G_2LANES) + printf(" 200Gbps_2lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_400G_4LANES) + printf(" 400Gbps_4lane /"); + if (speed_capa & RTE_ETH_LINK_SPEED_400G_8LANES) + printf(" 400Gbps_8lane /"); } void @@ -828,6 +840,10 @@ port_infos_display(portid_t port_id) printf("\nLink status: %s\n", (link.link_status) ? ("up") : ("down")); printf("Link speed: %s\n", rte_eth_link_speed_to_str(link.link_speed)); + if (link.link_lanes == 0) + printf("Link lanes: unknown\n"); + else + printf("Link lanes: %u\n", link.link_lanes); printf("Link duplex: %s\n", (link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? ("full-duplex") : ("half-duplex")); printf("Autoneg status: %s\n", (link.link_autoneg == RTE_ETH_LINK_AUTONEG) ? @@ -962,8 +978,8 @@ port_summary_header_display(void) port_number = rte_eth_dev_count_avail(); printf("Number of available ports: %i\n", port_number); - printf("%-4s %-17s %-12s %-14s %-8s %s\n", "Port", "MAC Address", "Name", - "Driver", "Status", "Link"); + printf("%-4s %-17s %-12s %-14s %-8s %-8s %s\n", "Port", "MAC Address", "Name", + "Driver", "Status", "Link", "Lanes"); } void @@ -993,10 +1009,16 @@ port_summary_display(portid_t port_id) if (ret != 0) return; - printf("%-4d " RTE_ETHER_ADDR_PRT_FMT " %-12s %-14s %-8s %s\n", - port_id, RTE_ETHER_ADDR_BYTES(&mac_addr), name, - dev_info.driver_name, (link.link_status) ? ("up") : ("down"), - rte_eth_link_speed_to_str(link.link_speed)); + if (link.link_lanes == RTE_ETH_LANES_UNKNOWN) + printf("%-4d " RTE_ETHER_ADDR_PRT_FMT " %-12s %-14s %-8s %-8s %s\n", + port_id, RTE_ETHER_ADDR_BYTES(&mac_addr), name, + dev_info.driver_name, (link.link_status) ? ("up") : ("down"), + rte_eth_link_speed_to_str(link.link_speed), "unknown"); + else + printf("%-4d " RTE_ETHER_ADDR_PRT_FMT " %-12s %-14s %-8s %-8s %u\n", + port_id, RTE_ETHER_ADDR_BYTES(&mac_addr), name, + dev_info.driver_name, (link.link_status) ? ("up") : ("down"), + rte_eth_link_speed_to_str(link.link_speed), link.link_lanes); } void diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst index 2fbf9220d8..118a0956bc 100644 --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst @@ -190,6 +190,7 @@ For example: memory allocation on the socket: 0 Link status: up Link speed: 40000 Mbps + Link lanes: 4 Link duplex: full-duplex Promiscuous mode: enabled Allmulticast mode: disabled @@ -2067,6 +2068,14 @@ Set the speed and duplex mode for all ports or a specific port:: testpmd> port config (port_id|all) speed (10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto) \ duplex (half|full|auto) +port config - speed with lanes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Set the speed, lanes and duplex mode for all ports or a specific port:: + + testpmd> port config (port_id|all) speed (10|100|1000|2500|5000|10000|25000|40000|50000|100000|200000|400000|auto) \ + lanes (lane_num) duplex (half|full|auto) + port config - queues/descriptors ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~