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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1P190MB0974 X-BESS-ID: 1721223200-303537-12655-15872-2 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.11.105 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVuamxiZAVgZQ0CTV0NLY0iTR0t LczMTc1NDULNnILCnFODkxzcjC0tRQqTYWAPZNWipBAAAA X-BESS-Outbound-Spam-Score: 0.51 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan21-34.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.01 BSF_SC7_SG0146_1 META: Custom rule SG0146_1 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.51 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_SC7_SG0146_1, BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add initial ntnic ethdev skeleton and register PCI probe functions Update documentation: Device description and feature list Signed-off-by: Serhii Iliushyk Reviewed-by: Ferruh Yigit --- v6 * Remove unused includes * Remove EOF markers * Remove unnecesarry commpiller flags * Update documentation INI and RST files * Remove uncovered features * Add features according to DPDK reqirements * Add link on NT200A02 description * Rename res(short for result) to ret(short for return) * Fix unnecessary set of the driver name * The driver name is set by macro RTE_PMD_REGISTER_PCI * Set sentinel value for PCI id_table * NULL value can lead to the crush on function rte_pci_match * Remove unnecessary comments v7 * Move features list to the dedicated patches * Update release note file v9 * Marked driver features as Experimantal v10 * Use 8 spaces as indentation in meson --- .mailmap | 1 + MAINTAINERS | 7 ++++ doc/guides/nics/features/ntnic.ini | 8 +++++ doc/guides/nics/index.rst | 1 + doc/guides/nics/ntnic.rst | 39 ++++++++++++++++++++ doc/guides/rel_notes/release_24_07.rst | 10 ++++++ drivers/net/meson.build | 1 + drivers/net/ntnic/meson.build | 18 ++++++++++ drivers/net/ntnic/ntnic_ethdev.c | 49 ++++++++++++++++++++++++++ 9 files changed, 134 insertions(+) create mode 100644 doc/guides/nics/features/ntnic.ini create mode 100644 doc/guides/nics/ntnic.rst create mode 100644 drivers/net/ntnic/meson.build create mode 100644 drivers/net/ntnic/ntnic_ethdev.c diff --git a/.mailmap b/.mailmap index 3f3f0442e5..ee567cf16e 100644 --- a/.mailmap +++ b/.mailmap @@ -1321,6 +1321,7 @@ Sergey Madaminov Sergey Mironov Sergey Temerkhanov Sergio Gonzalez Monroy +Serhii Iliushyk Seth Arnold Seth Howell Shachar Beiser diff --git a/MAINTAINERS b/MAINTAINERS index c71ca2a28e..3e6bf0f8ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -856,6 +856,13 @@ F: drivers/net/octeon_ep/ F: doc/guides/nics/features/octeon_ep.ini F: doc/guides/nics/octeon_ep.rst +Napatech ntnic - EXPERIMENTAL +M: Christian Koue Muf +M: Serhii Iliushyk +F: drivers/net/ntnic/ +F: doc/guides/nics/ntnic.rst +F: doc/guides/nics/features/ntnic.ini + NVIDIA mlx4 M: Matan Azrad M: Viacheslav Ovsiienko diff --git a/doc/guides/nics/features/ntnic.ini b/doc/guides/nics/features/ntnic.ini new file mode 100644 index 0000000000..9ceb75a03b --- /dev/null +++ b/doc/guides/nics/features/ntnic.ini @@ -0,0 +1,8 @@ +; +; Supported features of the 'ntnic' network poll mode driver. +; +; Refer to default.ini for the full list of available PMD features. +; +[Features] +Linux = Y +x86-64 = Y diff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst index 7bfcac880f..c14bc7988a 100644 --- a/doc/guides/nics/index.rst +++ b/doc/guides/nics/index.rst @@ -53,6 +53,7 @@ Network Interface Controller Drivers nfb nfp ngbe + ntnic null octeon_ep octeontx diff --git a/doc/guides/nics/ntnic.rst b/doc/guides/nics/ntnic.rst new file mode 100644 index 0000000000..b150fe1481 --- /dev/null +++ b/doc/guides/nics/ntnic.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2024 Napatech A/S + +NTNIC Poll Mode Driver +====================== + +The NTNIC PMD provides poll mode driver support for Napatech smartNICs. + + +Design +------ + +The NTNIC PMD is designed as a pure user-space driver, and requires no special +Napatech kernel modules. + +The Napatech smartNIC presents one control PCI device (PF0). NTNIC PMD accesses +smartNIC PF0 via vfio-pci kernel driver. Access to PF0 for all purposes is +exclusive, so only one process should access it. The physical ports are located +behind PF0 as DPDK port 0 and 1. + + +Supported NICs +-------------- + +- NT200A02 2x100G SmartNIC + + - FPGA ID 9563 (Inline Flow Management) + +All information about NT200A02 can be found by link below: +https://www.napatech.com/products/nt200a02-smartnic-inline/ + +Limitations +~~~~~~~~~~~ + +Kernel versions before 5.7 are not supported. Kernel version 5.7 added vfio-pci +support for creating VFs from the PF which is required for the PMD to use +vfio-pci on the PF. This support has been back-ported to older Linux +distributions and they are also supported. If vfio-pci is not required kernel +version 4.18 is supported. diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst index cd4219efd2..058609b0f3 100644 --- a/doc/guides/rel_notes/release_24_07.rst +++ b/doc/guides/rel_notes/release_24_07.rst @@ -104,6 +104,16 @@ New Features * Updated base code with E610 device family support. +* **Added Napatech ntnic net driver [EXPERIMENTAL].** + + * Added the PMD driver for Napatech smartNIC + + - Ability to initialize the NIC (NT200A02) + - Supporting only one FPGA firmware (9563.55.39) + - Ability to bring up the 100G link + - Supporting QSFP/QSFP+/QSFP28 NIM + - Does not support datapath + * **Updated Marvell cnxk net driver.** * Added support disabling custom meta aura diff --git a/drivers/net/meson.build b/drivers/net/meson.build index bd38b533c5..fb6d34b782 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -45,6 +45,7 @@ drivers = [ 'nfb', 'nfp', 'ngbe', + 'ntnic', 'null', 'octeontx', 'octeon_ep', diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build new file mode 100644 index 0000000000..368fffa81b --- /dev/null +++ b/drivers/net/ntnic/meson.build @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2020-2023 Napatech A/S + +if not is_linux or not dpdk_conf.has('RTE_ARCH_X86_64') + build = false + reason = 'only supported on x86_64 Linux' + subdir_done() +endif + +# includes +includes = [ + include_directories('.'), +] + +# all sources +sources = files( + 'ntnic_ethdev.c', +) diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c new file mode 100644 index 0000000000..7e5231d2c1 --- /dev/null +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -0,0 +1,49 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include +#include + +static const struct rte_pci_id nthw_pci_id_map[] = { + { + .vendor_id = 0, + }, /* sentinel */ +}; + +static int +nthw_pci_dev_init(struct rte_pci_device *pci_dev __rte_unused) +{ + return 0; +} + +static int +nthw_pci_dev_deinit(struct rte_eth_dev *eth_dev __rte_unused) +{ + return 0; +} + +static int +nthw_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + int ret; + ret = nthw_pci_dev_init(pci_dev); + return ret; +} + +static int +nthw_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, nthw_pci_dev_deinit); +} + +static struct rte_pci_driver rte_nthw_pmd = { + .id_table = nthw_pci_id_map, + .probe = nthw_pci_probe, + .remove = nthw_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(net_ntnic, rte_nthw_pmd); From patchwork Wed Jul 17 13:32:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142460 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2706845635; 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NT NIC uses this logging abstraction layer to ensure that FPGA module implementations function both within and outside in DPDK environment Signed-off-by: Serhii Iliushyk --- v6 * Logging header file was moved * Default log type was set to NOTICE v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/meson.build | 2 ++ drivers/net/ntnic/ntlog/ntlog.c | 53 ++++++++++++++++++++++++++++++++ drivers/net/ntnic/ntlog/ntlog.h | 49 +++++++++++++++++++++++++++++ drivers/net/ntnic/ntnic_ethdev.c | 2 ++ 4 files changed, 106 insertions(+) create mode 100644 drivers/net/ntnic/ntlog/ntlog.c create mode 100644 drivers/net/ntnic/ntlog/ntlog.h diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 368fffa81b..44d59c34ae 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -10,9 +10,11 @@ endif # includes includes = [ include_directories('.'), + include_directories('ntlog'), ] # all sources sources = files( + 'ntlog/ntlog.c', 'ntnic_ethdev.c', ) diff --git a/drivers/net/ntnic/ntlog/ntlog.c b/drivers/net/ntnic/ntlog/ntlog.c new file mode 100644 index 0000000000..2e4fba799d --- /dev/null +++ b/drivers/net/ntnic/ntlog/ntlog.c @@ -0,0 +1,53 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include +#include +#include +#include +#include + +#include +#include + +#define NTLOG_HELPER_STR_SIZE_MAX (1024) + +RTE_LOG_REGISTER_DEFAULT(nt_logtype, NOTICE) + +char *ntlog_helper_str_alloc(const char *sinit) +{ + char *s = malloc(NTLOG_HELPER_STR_SIZE_MAX); + + if (!s) + return NULL; + + if (sinit) + snprintf(s, NTLOG_HELPER_STR_SIZE_MAX, "%s", sinit); + + else + s[0] = '\0'; + + return s; +} + +__rte_format_printf(2, 0) +void ntlog_helper_str_add(char *s, const char *format, ...) +{ + if (!s) + return; + + va_list args; + va_start(args, format); + int len = strlen(s); + vsnprintf(&s[len], (NTLOG_HELPER_STR_SIZE_MAX - 1 - len), format, args); + va_end(args); +} + +void ntlog_helper_str_free(char *s) +{ + free(s); +} diff --git a/drivers/net/ntnic/ntlog/ntlog.h b/drivers/net/ntnic/ntlog/ntlog.h new file mode 100644 index 0000000000..58dcce0580 --- /dev/null +++ b/drivers/net/ntnic/ntlog/ntlog.h @@ -0,0 +1,49 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTOSS_SYSTEM_NTLOG_H +#define NTOSS_SYSTEM_NTLOG_H + +#include +#include +#include + +extern int nt_logtype; + +#define NT_DRIVER_NAME "ntnic" + +#define NT_PMD_DRV_LOG(level, ...) \ + rte_log(RTE_LOG_ ## level, nt_logtype, \ + RTE_FMT(NT_DRIVER_NAME ": " \ + RTE_FMT_HEAD(__VA_ARGS__, ""), \ + RTE_FMT_TAIL(__VA_ARGS__, ""))) + + +#define NT_LOG_ERR(...) NT_PMD_DRV_LOG(ERR, __VA_ARGS__) +#define NT_LOG_WRN(...) NT_PMD_DRV_LOG(WARNING, __VA_ARGS__) +#define NT_LOG_INF(...) NT_PMD_DRV_LOG(INFO, __VA_ARGS__) +#define NT_LOG_DBG(...) NT_PMD_DRV_LOG(DEBUG, __VA_ARGS__) + +#define NT_LOG(level, module, ...) \ + NT_LOG_##level(#module ": " #level ":" __VA_ARGS__) + +#define NT_LOG_DBGX(level, module, ...) \ + rte_log(RTE_LOG_ ##level, nt_logtype, \ + RTE_FMT(NT_DRIVER_NAME #module ": [%s:%u]" \ + RTE_FMT_HEAD(__VA_ARGS__, ""), __func__, __LINE__, \ + RTE_FMT_TAIL(__VA_ARGS__, ""))) +/* + * nt log helper functions + * to create a string for NT_LOG usage to output a one-liner log + * to use when one single function call to NT_LOG is not optimal - that is + * you do not know the number of parameters at programming time or it is variable + */ +char *ntlog_helper_str_alloc(const char *sinit); + +void ntlog_helper_str_add(char *s, const char *format, ...); + +void ntlog_helper_str_free(char *s); + +#endif /* NTOSS_SYSTEM_NTLOG_H */ diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 7e5231d2c1..68df9be2ff 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -7,6 +7,8 @@ #include #include +#include "ntlog.h" + static const struct rte_pci_id nthw_pci_id_map[] = { { .vendor_id = 0, From patchwork Wed Jul 17 13:32:50 2024 Content-Type: text/plain; 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Signed-off-by: Serhii Iliushyk --- v6 * Add driver deinitialization * Add API rte_eth_dev_probing_finish * Add correct API for finishing probing the device * Remove duplicated calling 'rte_eth_copy_pci_info()' via 'eth_dev_pci_specific_init() * Remove unnecessary comments * Remove duplicatet initialization of the numa_node v9 Fix logs --- drivers/net/ntnic/ntnic_ethdev.c | 82 +++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 68df9be2ff..d5983cd0f8 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -3,6 +3,7 @@ * Copyright(c) 2023 Napatech A/S */ +#include #include #include #include @@ -16,14 +17,54 @@ static const struct rte_pci_id nthw_pci_id_map[] = { }; static int -nthw_pci_dev_init(struct rte_pci_device *pci_dev __rte_unused) +nthw_pci_dev_init(struct rte_pci_device *pci_dev) { + uint32_t n_port_mask = -1; /* All ports enabled by default */ + int n_phy_ports; + NT_LOG_DBGX(DEBUG, NTNIC, "Dev %s PF #%i Init : %02x:%02x:%i\n", pci_dev->name, + pci_dev->addr.function, pci_dev->addr.bus, pci_dev->addr.devid, + pci_dev->addr.function); + + n_phy_ports = 0; + + for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) { + struct rte_eth_dev *eth_dev = NULL; + char name[32]; + + if ((1 << n_intf_no) & ~n_port_mask) + continue; + + snprintf(name, sizeof(name), "ntnic%d", n_intf_no); + + eth_dev = rte_eth_dev_allocate(name); + + if (!eth_dev) { + NT_LOG_DBGX(ERR, NTNIC, "%s: %s: error=%d\n", + (pci_dev->name[0] ? pci_dev->name : "NA"), name, -1); + return -1; + } + + struct rte_eth_link pmd_link; + pmd_link.link_speed = RTE_ETH_SPEED_NUM_NONE; + pmd_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + pmd_link.link_status = RTE_ETH_LINK_DOWN; + pmd_link.link_autoneg = RTE_ETH_LINK_AUTONEG; + + eth_dev->device = &pci_dev->device; + eth_dev->data->dev_link = pmd_link; + eth_dev->dev_ops = NULL; + + eth_dev_pci_specific_init(eth_dev, pci_dev); + rte_eth_dev_probing_finish(eth_dev); + } + return 0; } static int nthw_pci_dev_deinit(struct rte_eth_dev *eth_dev __rte_unused) { + NT_LOG_DBGX(DEBUG, NTNIC, "PCI device deinitialization\n"); return 0; } @@ -32,13 +73,52 @@ nthw_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) { int ret; + + NT_LOG_DBGX(DEBUG, NTNIC, "pcidev: name: '%s'\n", pci_dev->name); + NT_LOG_DBGX(DEBUG, NTNIC, "devargs: name: '%s'\n", pci_dev->device.name); + + if (pci_dev->device.devargs) { + NT_LOG_DBGX(DEBUG, NTNIC, "devargs: args: '%s'\n", + (pci_dev->device.devargs->args ? pci_dev->device.devargs->args : "NULL")); + NT_LOG_DBGX(DEBUG, NTNIC, "devargs: data: '%s'\n", + (pci_dev->device.devargs->data ? pci_dev->device.devargs->data : "NULL")); + } + + const int n_rte_vfio_no_io_mmu_enabled = rte_vfio_noiommu_is_enabled(); + NT_LOG(DBG, NTNIC, "vfio_no_iommu_enabled=%d\n", n_rte_vfio_no_io_mmu_enabled); + + if (n_rte_vfio_no_io_mmu_enabled) { + NT_LOG(ERR, NTNIC, "vfio_no_iommu_enabled=%d: this PMD needs VFIO IOMMU\n", + n_rte_vfio_no_io_mmu_enabled); + return -1; + } + + const enum rte_iova_mode n_rte_io_va_mode = rte_eal_iova_mode(); + NT_LOG(DBG, NTNIC, "iova mode=%d\n", n_rte_io_va_mode); + + NT_LOG(DBG, NTNIC, + "busid=" PCI_PRI_FMT + " pciid=%04x:%04x_%04x:%04x locstr=%s @ numanode=%d: drv=%s drvalias=%s\n", + pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid, + pci_dev->addr.function, pci_dev->id.vendor_id, pci_dev->id.device_id, + pci_dev->id.subsystem_vendor_id, pci_dev->id.subsystem_device_id, + pci_dev->name[0] ? pci_dev->name : "NA", + pci_dev->device.numa_node, + pci_dev->driver->driver.name ? pci_dev->driver->driver.name : "NA", + pci_dev->driver->driver.alias ? pci_dev->driver->driver.alias : "NA"); + + ret = nthw_pci_dev_init(pci_dev); + + NT_LOG_DBGX(DEBUG, NTNIC, "leave: ret=%d\n", ret); return ret; } static int nthw_pci_remove(struct rte_pci_device *pci_dev) { + NT_LOG_DBGX(DEBUG, NTNIC); + return rte_eth_dev_pci_generic_remove(pci_dev, nthw_pci_dev_deinit); } From patchwork Wed Jul 17 13:32:51 2024 Content-Type: text/plain; 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Signed-off-by: Serhii Iliushyk --- v6 * NT utils header file was moved v10 * Remove "NT" from the commit message title * Use 8 spaces as indentation in meson --- drivers/net/ntnic/meson.build | 2 ++ drivers/net/ntnic/ntnic_ethdev.c | 2 ++ drivers/net/ntnic/ntutil/nt_util.c | 33 +++++++++++++++++++++++ drivers/net/ntnic/ntutil/nt_util.h | 43 ++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+) create mode 100644 drivers/net/ntnic/ntutil/nt_util.c create mode 100644 drivers/net/ntnic/ntutil/nt_util.h diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 44d59c34ae..6f645320b9 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -11,10 +11,12 @@ endif includes = [ include_directories('.'), include_directories('ntlog'), + include_directories('ntutil'), ] # all sources sources = files( 'ntlog/ntlog.c', + 'ntutil/nt_util.c', 'ntnic_ethdev.c', ) diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index d5983cd0f8..02b55e2780 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -10,6 +10,8 @@ #include "ntlog.h" +#include "nt_util.h" + static const struct rte_pci_id nthw_pci_id_map[] = { { .vendor_id = 0, diff --git a/drivers/net/ntnic/ntutil/nt_util.c b/drivers/net/ntnic/ntutil/nt_util.c new file mode 100644 index 0000000000..5395bf6993 --- /dev/null +++ b/drivers/net/ntnic/ntutil/nt_util.c @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include "ntlog.h" +#include "nt_util.h" + +/* uses usleep which schedules out the calling thread */ +void nt_os_wait_usec(int val) +{ + rte_delay_us_sleep(val); +} + +uint64_t nt_os_get_time_monotonic_counter(void) +{ + return rte_get_timer_cycles(); +} + +/* Allocation size matching minimum alignment of specified size */ +uint64_t nt_util_align_size(uint64_t size) +{ + return 1 << rte_log2_u64(size); +} diff --git a/drivers/net/ntnic/ntutil/nt_util.h b/drivers/net/ntnic/ntutil/nt_util.h new file mode 100644 index 0000000000..6dfd7428e1 --- /dev/null +++ b/drivers/net/ntnic/ntutil/nt_util.h @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTOSS_SYSTEM_NT_UTIL_H +#define NTOSS_SYSTEM_NT_UTIL_H + +#include + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) RTE_DIM(arr) +#endif + +#define PCIIDENT_TO_DOMAIN(pci_ident) ((uint16_t)(((unsigned int)(pci_ident) >> 16) & 0xFFFFU)) +#define PCIIDENT_TO_BUSNR(pci_ident) ((uint8_t)(((unsigned int)(pci_ident) >> 8) & 0xFFU)) +#define PCIIDENT_TO_DEVNR(pci_ident) ((uint8_t)(((unsigned int)(pci_ident) >> 3) & 0x1FU)) +#define PCIIDENT_TO_FUNCNR(pci_ident) ((uint8_t)(((unsigned int)(pci_ident) >> 0) & 0x7U)) +#define PCIIDENT_PRINT_STR "%04x:%02x:%02x.%x" +#define BDF_TO_PCIIDENT(dom, bus, dev, fnc) (((dom) << 16) | ((bus) << 8) | ((dev) << 3) | (fnc)) + +uint64_t nt_os_get_time_monotonic_counter(void); +void nt_os_wait_usec(int val); + +uint64_t nt_util_align_size(uint64_t size); + +struct nt_dma_s { + uint64_t iova; + uint64_t addr; + uint64_t size; +}; + +struct nt_dma_s *nt_dma_alloc(uint64_t size, uint64_t align, int numa); +void nt_dma_free(struct nt_dma_s *vfio_addr); + +struct nt_util_vfio_impl { + int (*vfio_dma_map)(int vf_num, void *virt_addr, uint64_t *iova_addr, uint64_t size); + int (*vfio_dma_unmap)(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size); +}; + +void nt_util_vfio_init(struct nt_util_vfio_impl *impl); + +#endif /* NTOSS_SYSTEM_NT_UTIL_H */ From patchwork Wed Jul 17 13:32:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142465 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5D22545635; 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The VFIO context is initialized during ntnic ethdev startup. Signed-off-by: Serhii Iliushyk --- v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/ntnic_ethdev.c | 22 +++ drivers/net/ntnic/ntnic_vfio.c | 235 +++++++++++++++++++++++++++++ drivers/net/ntnic/ntnic_vfio.h | 29 ++++ drivers/net/ntnic/ntutil/nt_util.c | 65 ++++++++ 5 files changed, 352 insertions(+) create mode 100644 drivers/net/ntnic/ntnic_vfio.c create mode 100644 drivers/net/ntnic/ntnic_vfio.h diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 6f645320b9..deeb0aca09 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -18,5 +18,6 @@ includes = [ sources = files( 'ntlog/ntlog.c', 'ntutil/nt_util.c', + 'ntnic_vfio.c', 'ntnic_ethdev.c', ) diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 02b55e2780..b838eb4d7a 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -8,10 +8,17 @@ #include #include +#include +#include +#include + #include "ntlog.h" +#include "ntnic_vfio.h" #include "nt_util.h" +#define EXCEPTION_PATH_HID 0 + static const struct rte_pci_id nthw_pci_id_map[] = { { .vendor_id = 0, @@ -21,12 +28,24 @@ static const struct rte_pci_id nthw_pci_id_map[] = { static int nthw_pci_dev_init(struct rte_pci_device *pci_dev) { + nt_vfio_init(); + uint32_t n_port_mask = -1; /* All ports enabled by default */ int n_phy_ports; NT_LOG_DBGX(DEBUG, NTNIC, "Dev %s PF #%i Init : %02x:%02x:%i\n", pci_dev->name, pci_dev->addr.function, pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function); + + /* Setup VFIO context */ + int vfio = nt_vfio_setup(pci_dev); + + if (vfio < 0) { + NT_LOG_DBGX(ERR, TNIC, "%s: vfio_setup error %d\n", + (pci_dev->name[0] ? pci_dev->name : "NA"), -1); + return -1; + } + n_phy_ports = 0; for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) { @@ -67,6 +86,8 @@ static int nthw_pci_dev_deinit(struct rte_eth_dev *eth_dev __rte_unused) { NT_LOG_DBGX(DEBUG, NTNIC, "PCI device deinitialization\n"); + + nt_vfio_remove(EXCEPTION_PATH_HID); return 0; } @@ -131,3 +152,4 @@ static struct rte_pci_driver rte_nthw_pmd = { }; RTE_PMD_REGISTER_PCI(net_ntnic, rte_nthw_pmd); +RTE_PMD_REGISTER_KMOD_DEP(net_ntnic, "* vfio-pci"); diff --git a/drivers/net/ntnic/ntnic_vfio.c b/drivers/net/ntnic/ntnic_vfio.c new file mode 100644 index 0000000000..f4433152b7 --- /dev/null +++ b/drivers/net/ntnic/ntnic_vfio.c @@ -0,0 +1,235 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include "ntnic_vfio.h" + +#define ONE_G_SIZE 0x40000000 +#define ONE_G_MASK (ONE_G_SIZE - 1) +#define START_VF_IOVA 0x220000000000 + +int +nt_vfio_vf_num(const struct rte_pci_device *pdev) +{ + return ((pdev->addr.devid & 0x1f) << 3) + ((pdev->addr.function) & 0x7); +} + +/* Internal API */ +struct vfio_dev { + int container_fd; + int group_fd; + int dev_fd; + uint64_t iova_addr; +}; + +static struct vfio_dev vfio_list[256]; + +static struct vfio_dev * +vfio_get(int vf_num) +{ + if (vf_num < 0 || vf_num > 255) + return NULL; + + return &vfio_list[vf_num]; +} + +/* External API */ +int +nt_vfio_setup(struct rte_pci_device *dev) +{ + char devname[RTE_DEV_NAME_MAX_LEN] = { 0 }; + int iommu_group_num; + int vf_num; + struct vfio_dev *vfio; + + NT_LOG(INF, NTNIC, "NT VFIO device setup %s\n", dev->name); + + vf_num = nt_vfio_vf_num(dev); + + vfio = vfio_get(vf_num); + + if (vfio == NULL) { + NT_LOG(ERR, NTNIC, "VFIO device setup failed. Illegal device id\n"); + return -1; + } + + vfio->dev_fd = -1; + vfio->group_fd = -1; + vfio->container_fd = -1; + vfio->iova_addr = START_VF_IOVA; + + rte_pci_device_name(&dev->addr, devname, RTE_DEV_NAME_MAX_LEN); + rte_vfio_get_group_num(rte_pci_get_sysfs_path(), devname, &iommu_group_num); + + if (vf_num == 0) { + /* use default container for pf0 */ + vfio->container_fd = RTE_VFIO_DEFAULT_CONTAINER_FD; + + } else { + vfio->container_fd = rte_vfio_container_create(); + + if (vfio->container_fd < 0) { + NT_LOG(ERR, NTNIC, + "VFIO device setup failed. VFIO container creation failed.\n"); + return -1; + } + } + + vfio->group_fd = rte_vfio_container_group_bind(vfio->container_fd, iommu_group_num); + + if (vfio->group_fd < 0) { + NT_LOG(ERR, NTNIC, + "VFIO device setup failed. VFIO container group bind failed.\n"); + goto err; + } + + if (vf_num > 0) { + if (rte_pci_map_device(dev)) { + NT_LOG(ERR, NTNIC, + "Map VFIO device failed. is the vfio-pci driver loaded?\n"); + goto err; + } + } + + vfio->dev_fd = rte_intr_dev_fd_get(dev->intr_handle); + + NT_LOG(DBG, NTNIC, + "%s: VFIO id=%d, dev_fd=%d, container_fd=%d, group_fd=%d, iommu_group_num=%d\n", + dev->name, vf_num, vfio->dev_fd, vfio->container_fd, vfio->group_fd, + iommu_group_num); + + return vf_num; + +err: + + if (vfio->container_fd != RTE_VFIO_DEFAULT_CONTAINER_FD) + rte_vfio_container_destroy(vfio->container_fd); + + return -1; +} + +int +nt_vfio_remove(int vf_num) +{ + struct vfio_dev *vfio; + + NT_LOG(DBG, NTNIC, "NT VFIO device remove VF=%d\n", vf_num); + + vfio = vfio_get(vf_num); + + if (!vfio) { + NT_LOG(ERR, NTNIC, "VFIO device remove failed. Illegal device id\n"); + return -1; + } + + rte_vfio_container_destroy(vfio->container_fd); + return 0; +} + +int +nt_vfio_dma_map(int vf_num, void *virt_addr, uint64_t *iova_addr, uint64_t size) +{ + uint64_t gp_virt_base; + uint64_t gp_offset; + + if (size == ONE_G_SIZE) { + gp_virt_base = (uint64_t)virt_addr & ~ONE_G_MASK; + gp_offset = (uint64_t)virt_addr & ONE_G_MASK; + + } else { + gp_virt_base = (uint64_t)virt_addr; + gp_offset = 0; + } + + struct vfio_dev *vfio; + + vfio = vfio_get(vf_num); + + if (vfio == NULL) { + NT_LOG(ERR, NTNIC, "VFIO MAP: VF number %d invalid\n", vf_num); + return -1; + } + + NT_LOG(DBG, NTNIC, + "VFIO MMAP VF=%d VirtAddr=%p HPA=%" PRIX64 " VirtBase=%" PRIX64 + " IOVA Addr=%" PRIX64 " size=%" PRIX64 "\n", + vf_num, virt_addr, rte_malloc_virt2iova(virt_addr), gp_virt_base, vfio->iova_addr, + size); + + int res = rte_vfio_container_dma_map(vfio->container_fd, gp_virt_base, vfio->iova_addr, + size); + + NT_LOG(DBG, NTNIC, "VFIO MMAP res %i, container_fd %i, vf_num %i\n", res, + vfio->container_fd, vf_num); + + if (res) { + NT_LOG(ERR, NTNIC, "rte_vfio_container_dma_map failed: res %d\n", res); + return -1; + } + + *iova_addr = vfio->iova_addr + gp_offset; + + vfio->iova_addr += ONE_G_SIZE; + + return 0; +} + +int +nt_vfio_dma_unmap(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size) +{ + uint64_t gp_virt_base; + struct vfio_dev *vfio; + + if (size == ONE_G_SIZE) { + uint64_t gp_offset; + gp_virt_base = (uint64_t)virt_addr & ~ONE_G_MASK; + gp_offset = (uint64_t)virt_addr & ONE_G_MASK; + iova_addr -= gp_offset; + + } else { + gp_virt_base = (uint64_t)virt_addr; + } + + vfio = vfio_get(vf_num); + + if (vfio == NULL) { + NT_LOG(ERR, NTNIC, "VFIO UNMAP: VF number %d invalid\n", vf_num); + return -1; + } + + if (vfio->container_fd == -1) + return 0; + + int res = rte_vfio_container_dma_unmap(vfio->container_fd, gp_virt_base, iova_addr, size); + + if (res != 0) { + NT_LOG(ERR, NTNIC, + "VFIO UNMMAP FAILED! res %i, container_fd %i, vf_num %i, virt_base=%" PRIX64 + ", IOVA=%" PRIX64 ", size=%" PRIX64 "\n", + res, vfio->container_fd, vf_num, gp_virt_base, iova_addr, size); + return -1; + } + + return 0; +} + +void +nt_vfio_init(void) +{ + struct nt_util_vfio_impl s = { .vfio_dma_map = nt_vfio_dma_map, + .vfio_dma_unmap = nt_vfio_dma_unmap + }; + nt_util_vfio_init(&s); +} diff --git a/drivers/net/ntnic/ntnic_vfio.h b/drivers/net/ntnic/ntnic_vfio.h new file mode 100644 index 0000000000..69fef7923d --- /dev/null +++ b/drivers/net/ntnic/ntnic_vfio.h @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NTNIC_VFIO_H_ +#define _NTNIC_VFIO_H_ + +#include +#include +#include + +void +nt_vfio_init(void); + +int +nt_vfio_setup(struct rte_pci_device *dev); +int +nt_vfio_remove(int vf_num); + +int +nt_vfio_dma_map(int vf_num, void *virt_addr, uint64_t *iova_addr, uint64_t size); +int +nt_vfio_dma_unmap(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size); + +/* Find device (PF/VF) number from device address */ +int +nt_vfio_vf_num(const struct rte_pci_device *dev); +#endif /* _NTNIC_VFIO_H_ */ diff --git a/drivers/net/ntnic/ntutil/nt_util.c b/drivers/net/ntnic/ntutil/nt_util.c index 5395bf6993..53c39ef112 100644 --- a/drivers/net/ntnic/ntutil/nt_util.c +++ b/drivers/net/ntnic/ntutil/nt_util.c @@ -15,6 +15,8 @@ #include "ntlog.h" #include "nt_util.h" +static struct nt_util_vfio_impl vfio_cb; + /* uses usleep which schedules out the calling thread */ void nt_os_wait_usec(int val) { @@ -31,3 +33,66 @@ uint64_t nt_util_align_size(uint64_t size) { return 1 << rte_log2_u64(size); } + +void nt_util_vfio_init(struct nt_util_vfio_impl *impl) +{ + vfio_cb = *impl; +} + +struct nt_dma_s *nt_dma_alloc(uint64_t size, uint64_t align, int numa) +{ + int res; + struct nt_dma_s *vfio_addr; + + vfio_addr = rte_malloc(NULL, sizeof(struct nt_dma_s), 0); + + if (!vfio_addr) { + NT_LOG(ERR, GENERAL, "VFIO rte_malloc failed\n"); + return NULL; + } + + void *addr = rte_malloc_socket(NULL, size, align, numa); + + if (!addr) { + rte_free(vfio_addr); + NT_LOG(ERR, GENERAL, "VFIO rte_malloc_socket failed\n"); + return NULL; + } + + res = vfio_cb.vfio_dma_map(0, addr, &vfio_addr->iova, nt_util_align_size(size)); + + if (res != 0) { + rte_free(addr); + rte_free(vfio_addr); + NT_LOG(ERR, GENERAL, "VFIO nt_dma_map failed\n"); + return NULL; + } + + vfio_addr->addr = (uint64_t)addr; + vfio_addr->size = nt_util_align_size(size); + + NT_LOG(DBG, GENERAL, + "VFIO DMA alloc addr=%" PRIX64 ", iova=%" PRIX64 + ", size=%" PRIX64 "align=0x%" PRIX64 "\n", + vfio_addr->addr, vfio_addr->iova, vfio_addr->size, align); + + return vfio_addr; +} + +void nt_dma_free(struct nt_dma_s *vfio_addr) +{ + NT_LOG(DBG, GENERAL, "VFIO DMA free addr=%" PRIX64 ", iova=%" PRIX64 ", size=%" PRIX64 "\n", + vfio_addr->addr, vfio_addr->iova, vfio_addr->size); + + int res = vfio_cb.vfio_dma_unmap(0, (void *)vfio_addr->addr, vfio_addr->iova, + vfio_addr->size); + + if (res != 0) { + NT_LOG(WRN, GENERAL, + "VFIO DMA free FAILED addr=%" PRIX64 ", iova=%" PRIX64 ", size=%" PRIX64 "\n", + vfio_addr->addr, vfio_addr->iova, vfio_addr->size); + } + + rte_free((void *)(vfio_addr->addr)); + rte_free(vfio_addr); +} From patchwork Wed Jul 17 13:32:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142462 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD9F645635; 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Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by AM3PEPF0000A799.mail.protection.outlook.com (10.167.16.104) with Microsoft SMTP Server id 15.20.7784.11 via Frontend Transport; Wed, 17 Jul 2024 13:33:20 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com Subject: [PATCH v10 06/21] net/ntnic: add basic eth dev ops Date: Wed, 17 Jul 2024 15:32:53 +0200 Message-ID: <20240717133313.3104239-6-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240717133313.3104239-1-sil-plv@napatech.com> References: <20240530144929.4127931-1-sil-plv@napatech.com> <20240717133313.3104239-1-sil-plv@napatech.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM3PEPF0000A799:EE_|DBAP190MB0888:EE_ X-MS-Office365-Filtering-Correlation-Id: bbc184ca-3a93-4455-d49e-08dca665060d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The internal structs of ntnic is also added and initialized. Signed-off-by: Serhii Iliushyk --- v6 * Replace if_index with n_intf_no * Unnecessry resources free was fixed * Fix typo * Useless vars were removed v9 * Remove if_index usage to n_intf_no * Make ops structure as const * Fix logs * Cleaup struct pmd_internals * Move back dev init count increasing v10 * Remove "to ntnic" from the commit message title * Use 8 spaces as indentation in meson --- drivers/net/ntnic/include/ntdrv_4ga.h | 17 ++ drivers/net/ntnic/include/ntos_drv.h | 30 ++++ drivers/net/ntnic/include/ntos_system.h | 19 +++ drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/ntnic_ethdev.c | 207 +++++++++++++++++++++++- 5 files changed, 273 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/include/ntdrv_4ga.h create mode 100644 drivers/net/ntnic/include/ntos_drv.h create mode 100644 drivers/net/ntnic/include/ntos_system.h diff --git a/drivers/net/ntnic/include/ntdrv_4ga.h b/drivers/net/ntnic/include/ntdrv_4ga.h new file mode 100644 index 0000000000..bcb7ddc242 --- /dev/null +++ b/drivers/net/ntnic/include/ntdrv_4ga.h @@ -0,0 +1,17 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTDRV_4GA_H__ +#define __NTDRV_4GA_H__ + + +typedef struct ntdrv_4ga_s { + uint32_t pciident; + char *p_drv_name; + + volatile bool b_shutdown; +} ntdrv_4ga_t; + +#endif /* __NTDRV_4GA_H__ */ diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h new file mode 100644 index 0000000000..3c0a62cc85 --- /dev/null +++ b/drivers/net/ntnic/include/ntos_drv.h @@ -0,0 +1,30 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTOS_DRV_H__ +#define __NTOS_DRV_H__ + +#include +#include +#include +#include + +#include + +#define NUM_MAC_ADDRS_PER_PORT (16U) +#define NUM_MULTICAST_ADDRS_PER_PORT (16U) + +#define NUM_ADAPTER_MAX (8) +#define NUM_ADAPTER_PORTS_MAX (128) + +struct pmd_internals { + const struct rte_pci_device *pci_dev; + char name[20]; + int n_intf_no; + struct drv_s *p_drv; + struct pmd_internals *next; +}; + +#endif /* __NTOS_DRV_H__ */ diff --git a/drivers/net/ntnic/include/ntos_system.h b/drivers/net/ntnic/include/ntos_system.h new file mode 100644 index 0000000000..01f1dc65f4 --- /dev/null +++ b/drivers/net/ntnic/include/ntos_system.h @@ -0,0 +1,19 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTOS_SYSTEM_H__ +#define __NTOS_SYSTEM_H__ + +#include "ntdrv_4ga.h" + +struct drv_s { + int adapter_no; + struct rte_pci_device *p_dev; + struct ntdrv_4ga_s ntdrv; + + int n_eth_dev_init_count; +}; + +#endif /* __NTOS_SYSTEM_H__ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index deeb0aca09..47c4b6357a 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -10,6 +10,7 @@ endif # includes includes = [ include_directories('.'), + include_directories('include'), include_directories('ntlog'), include_directories('ntutil'), ] diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index b838eb4d7a..504d6c6bcd 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -14,6 +14,9 @@ #include "ntlog.h" +#include "ntdrv_4ga.h" +#include "ntos_drv.h" +#include "ntos_system.h" #include "ntnic_vfio.h" #include "nt_util.h" @@ -25,30 +28,201 @@ static const struct rte_pci_id nthw_pci_id_map[] = { }, /* sentinel */ }; +static rte_spinlock_t hwlock = RTE_SPINLOCK_INITIALIZER; + +/* + * Store and get adapter info + */ + +static struct drv_s *_g_p_drv[NUM_ADAPTER_MAX] = { NULL }; + +static void +store_pdrv(struct drv_s *p_drv) +{ + if (p_drv->adapter_no > NUM_ADAPTER_MAX) { + NT_LOG(ERR, NTNIC, + "Internal error adapter number %u out of range. Max number of adapters: %u\n", + p_drv->adapter_no, NUM_ADAPTER_MAX); + return; + } + + if (_g_p_drv[p_drv->adapter_no] != 0) { + NT_LOG(WRN, NTNIC, + "Overwriting adapter structure for PCI " PCIIDENT_PRINT_STR + " with adapter structure for PCI " PCIIDENT_PRINT_STR "\n", + PCIIDENT_TO_DOMAIN(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident), + PCIIDENT_TO_BUSNR(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident), + PCIIDENT_TO_DEVNR(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident), + PCIIDENT_TO_FUNCNR(_g_p_drv[p_drv->adapter_no]->ntdrv.pciident), + PCIIDENT_TO_DOMAIN(p_drv->ntdrv.pciident), + PCIIDENT_TO_BUSNR(p_drv->ntdrv.pciident), + PCIIDENT_TO_DEVNR(p_drv->ntdrv.pciident), + PCIIDENT_TO_FUNCNR(p_drv->ntdrv.pciident)); + } + + rte_spinlock_lock(&hwlock); + _g_p_drv[p_drv->adapter_no] = p_drv; + rte_spinlock_unlock(&hwlock); +} + +static struct drv_s * +get_pdrv_from_pci(struct rte_pci_addr addr) +{ + int i; + struct drv_s *p_drv = NULL; + rte_spinlock_lock(&hwlock); + + for (i = 0; i < NUM_ADAPTER_MAX; i++) { + if (_g_p_drv[i]) { + if (PCIIDENT_TO_DOMAIN(_g_p_drv[i]->ntdrv.pciident) == addr.domain && + PCIIDENT_TO_BUSNR(_g_p_drv[i]->ntdrv.pciident) == addr.bus) { + p_drv = _g_p_drv[i]; + break; + } + } + } + + rte_spinlock_unlock(&hwlock); + return p_drv; +} + +static int +eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *dev_info) +{ + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + + dev_info->driver_name = internals->name; + + return 0; +} + +static int +eth_dev_configure(struct rte_eth_dev *eth_dev) +{ + NT_LOG_DBGX(DEBUG, NTNIC, "Called for eth_dev %p\n", eth_dev); + + /* The device is ALWAYS running promiscuous mode. */ + eth_dev->data->promiscuous ^= ~eth_dev->data->promiscuous; + return 0; +} + +static int +eth_dev_start(struct rte_eth_dev *eth_dev) +{ + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + + NT_LOG_DBGX(DEBUG, NTNIC, "Port %u\n", internals->n_intf_no); + + return 0; +} + +static int +eth_dev_stop(struct rte_eth_dev *eth_dev) +{ + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + + NT_LOG_DBGX(DEBUG, NTNIC, "Port %u\n", internals->n_intf_no); + + eth_dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; + return 0; +} + +static void +drv_deinit(struct drv_s *p_drv) +{ + if (p_drv == NULL) + return; + + /* clean memory */ + rte_free(p_drv); + p_drv = NULL; +} + +static int +eth_dev_close(struct rte_eth_dev *eth_dev) +{ + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + struct drv_s *p_drv = internals->p_drv; + + internals->p_drv = NULL; + + rte_eth_dev_release_port(eth_dev); + + /* decrease initialized ethernet devices */ + p_drv->n_eth_dev_init_count--; + + /* + * rte_pci_dev has no private member for p_drv + * wait until all rte_eth_dev's are closed - then close adapters via p_drv + */ + if (!p_drv->n_eth_dev_init_count && p_drv) + drv_deinit(p_drv); + + return 0; +} + +static const struct eth_dev_ops nthw_eth_dev_ops = { + .dev_configure = eth_dev_configure, + .dev_start = eth_dev_start, + .dev_stop = eth_dev_stop, + .dev_close = eth_dev_close, + .dev_infos_get = eth_dev_infos_get, +}; + static int nthw_pci_dev_init(struct rte_pci_device *pci_dev) { nt_vfio_init(); + struct drv_s *p_drv; + ntdrv_4ga_t *p_nt_drv; uint32_t n_port_mask = -1; /* All ports enabled by default */ + uint32_t nb_rx_queues = 1; + uint32_t nb_tx_queues = 1; int n_phy_ports; NT_LOG_DBGX(DEBUG, NTNIC, "Dev %s PF #%i Init : %02x:%02x:%i\n", pci_dev->name, pci_dev->addr.function, pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function); + /* alloc */ + p_drv = rte_zmalloc_socket(pci_dev->name, sizeof(struct drv_s), RTE_CACHE_LINE_SIZE, + pci_dev->device.numa_node); + + if (!p_drv) { + NT_LOG_DBGX(ERR, NTNIC, "%s: error %d\n", + (pci_dev->name[0] ? pci_dev->name : "NA"), -1); + return -1; + } + /* Setup VFIO context */ int vfio = nt_vfio_setup(pci_dev); if (vfio < 0) { NT_LOG_DBGX(ERR, TNIC, "%s: vfio_setup error %d\n", (pci_dev->name[0] ? pci_dev->name : "NA"), -1); + rte_free(p_drv); return -1; } + /* context */ + p_nt_drv = &p_drv->ntdrv; + + p_drv->p_dev = pci_dev; + + /* Set context for NtDrv */ + p_nt_drv->pciident = BDF_TO_PCIIDENT(pci_dev->addr.domain, pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function); + + p_nt_drv->b_shutdown = false; + + /* store context */ + store_pdrv(p_drv); + n_phy_ports = 0; for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) { + struct pmd_internals *internals = NULL; struct rte_eth_dev *eth_dev = NULL; char name[32]; @@ -57,6 +231,31 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) snprintf(name, sizeof(name), "ntnic%d", n_intf_no); + internals = rte_zmalloc_socket(name, sizeof(struct pmd_internals), + RTE_CACHE_LINE_SIZE, pci_dev->device.numa_node); + + if (!internals) { + NT_LOG_DBGX(ERR, NTNIC, "%s: %s: error=%d\n", + (pci_dev->name[0] ? pci_dev->name : "NA"), name, -1); + return -1; + } + + internals->pci_dev = pci_dev; + internals->n_intf_no = n_intf_no; + + /* Setup queue_ids */ + if (nb_rx_queues > 1) { + NT_LOG(DBG, NTNIC, + "(%i) NTNIC configured with Rx multi queues. %i queues\n", + internals->n_intf_no, nb_rx_queues); + } + + if (nb_tx_queues > 1) { + NT_LOG(DBG, NTNIC, + "(%i) NTNIC configured with Tx multi queues. %i queues\n", + internals->n_intf_no, nb_tx_queues); + } + eth_dev = rte_eth_dev_allocate(name); if (!eth_dev) { @@ -73,10 +272,13 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) eth_dev->device = &pci_dev->device; eth_dev->data->dev_link = pmd_link; - eth_dev->dev_ops = NULL; + eth_dev->dev_ops = &nthw_eth_dev_ops; eth_dev_pci_specific_init(eth_dev, pci_dev); rte_eth_dev_probing_finish(eth_dev); + + /* increase initialized ethernet devices - PF */ + p_drv->n_eth_dev_init_count++; } return 0; @@ -142,6 +344,9 @@ nthw_pci_remove(struct rte_pci_device *pci_dev) { NT_LOG_DBGX(DEBUG, NTNIC); + struct drv_s *p_drv = get_pdrv_from_pci(pci_dev->addr); + drv_deinit(p_drv); + return rte_eth_dev_pci_generic_remove(pci_dev, nthw_pci_dev_deinit); } From patchwork Wed Jul 17 13:32:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142463 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9EF3C45635; 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This is considered the first part of the skeleton of ntnic FPGA support Signed-off-by: Serhii Iliushyk --- v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/include/ntos_drv.h | 2 + drivers/net/ntnic/meson.build | 2 + drivers/net/ntnic/nthw/nthw_drv.h | 88 ++++++++++++++++++++++ drivers/net/ntnic/nthw/nthw_platform.c | 14 ++++ drivers/net/ntnic/nthw/nthw_platform_drv.h | 21 ++++++ 5 files changed, 127 insertions(+) create mode 100644 drivers/net/ntnic/nthw/nthw_drv.h create mode 100644 drivers/net/ntnic/nthw/nthw_platform.c create mode 100644 drivers/net/ntnic/nthw/nthw_platform_drv.h diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h index 3c0a62cc85..3f621143d9 100644 --- a/drivers/net/ntnic/include/ntos_drv.h +++ b/drivers/net/ntnic/include/ntos_drv.h @@ -13,6 +13,8 @@ #include +#include "nthw_drv.h" + #define NUM_MAC_ADDRS_PER_PORT (16U) #define NUM_MULTICAST_ADDRS_PER_PORT (16U) diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 47c4b6357a..04e31b4729 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -13,10 +13,12 @@ includes = [ include_directories('include'), include_directories('ntlog'), include_directories('ntutil'), + include_directories('nthw'), ] # all sources sources = files( + 'nthw/nthw_platform.c', 'ntlog/ntlog.c', 'ntutil/nt_util.c', 'ntnic_vfio.c', diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h new file mode 100644 index 0000000000..0b89a5c5a0 --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_drv.h @@ -0,0 +1,88 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_DRV_H__ +#define __NTHW_DRV_H__ + +#include +#include "nthw_platform_drv.h" + +typedef enum nt_meta_port_type_e { + PORT_TYPE_PHYSICAL, + PORT_TYPE_VIRTUAL, + PORT_TYPE_OVERRIDE, +} nt_meta_port_type_t; + +enum fpga_info_profile { + FPGA_INFO_PROFILE_UNKNOWN = 0, + FPGA_INFO_PROFILE_VSWITCH = 1, + FPGA_INFO_PROFILE_INLINE = 2, + FPGA_INFO_PROFILE_CAPTURE = 3, +}; + +typedef struct mcu_info_s { + int mn_mcu_type; + int mn_mcu_dram_size; +} mcu_info_t; + +typedef struct nthw_hw_info_s { + /* From FW */ + int hw_id; + int hw_id_emulated; + char hw_plat_id_str[32]; + + struct vpd_info_s { + int mn_mac_addr_count; + uint64_t mn_mac_addr_value; + uint8_t ma_mac_addr_octets[6]; + } vpd_info; +} nthw_hw_info_t; + +typedef struct fpga_info_s { + uint64_t n_fpga_ident; + + int n_fpga_type_id; + int n_fpga_prod_id; + int n_fpga_ver_id; + int n_fpga_rev_id; + + int n_fpga_build_time; + + int n_fpga_debug_mode; + + int n_phy_ports; + int n_phy_quads; + int n_rx_ports; + int n_tx_ports; + int n_vf_offset; + + enum fpga_info_profile profile; + + struct nthw_fpga_s *mp_fpga; + + struct nthw_rac *mp_nthw_rac; + struct nthw_hif *mp_nthw_hif; + struct nthw_pcie3 *mp_nthw_pcie3; + struct nthw_tsm *mp_nthw_tsm; + + uint8_t *bar0_addr; /* Needed for register read/write */ + size_t bar0_size; + + int adapter_no; /* Needed for nthw_rac DMA array indexing */ + uint32_t pciident; /* Needed for nthw_rac DMA memzone_reserve */ + int numa_node; /* Needed for nthw_rac DMA memzone_reserve */ + + char *mp_adapter_id_str;/* Pointer to string literal used in nthw log messages */ + + struct mcu_info_s mcu_info; + + struct nthw_hw_info_s nthw_hw_info; + + nthw_adapter_id_t n_nthw_adapter_id; + +} fpga_info_t; + + +#endif /* __NTHW_DRV_H__ */ diff --git a/drivers/net/ntnic/nthw/nthw_platform.c b/drivers/net/ntnic/nthw/nthw_platform.c new file mode 100644 index 0000000000..181330dd37 --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_platform.c @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nthw_platform_drv.h" + +nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id) +{ + switch (n_pci_device_id) { + default: + return NT_HW_ADAPTER_ID_UNKNOWN; + } +} diff --git a/drivers/net/ntnic/nthw/nthw_platform_drv.h b/drivers/net/ntnic/nthw/nthw_platform_drv.h new file mode 100644 index 0000000000..ab26d8149a --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_platform_drv.h @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_PLATFORM_DRV_H__ +#define __NTHW_PLATFORM_DRV_H__ + +#include + +#define NT_HW_PCI_VENDOR_ID (0x18f4) + +enum nthw_adapter_id_e { + NT_HW_ADAPTER_ID_UNKNOWN = 0, +}; + +typedef enum nthw_adapter_id_e nthw_adapter_id_t; + +nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id); + +#endif /* __NTHW_PLATFORM_DRV_H__ */ From patchwork Wed Jul 17 13:32:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142464 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FD1645635; 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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P190MB1252 X-BESS-ID: 1721223203-305921-12800-14951-1 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.17.104 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVoYmRmbGQGYGUNTcwDDZxNjY3N TQ1Nwg1cwwMcnc1MzYICk1ycAsxczAVKk2FgCrYbm/QgAAAA== X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan11-183.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add interfaces for initialize the adapter Add proper PCI device deinitialization Signed-off-by: Serhii Iliushyk --- v6 * Function for global var clearing was removed v9 * Fix PCI devide deinitialization * Fix p_hw_info usage v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/adapter/nt4ga_adapter.c | 145 ++++++++++++++++++++++ drivers/net/ntnic/include/nt4ga_adapter.h | 40 ++++++ drivers/net/ntnic/include/ntdrv_4ga.h | 2 + drivers/net/ntnic/meson.build | 2 + drivers/net/ntnic/ntnic_ethdev.c | 85 ++++++++++++- drivers/net/ntnic/ntnic_mod_reg.c | 20 +++ drivers/net/ntnic/ntnic_mod_reg.h | 27 ++++ 7 files changed, 320 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/adapter/nt4ga_adapter.c create mode 100644 drivers/net/ntnic/include/nt4ga_adapter.h create mode 100644 drivers/net/ntnic/ntnic_mod_reg.c create mode 100644 drivers/net/ntnic/ntnic_mod_reg.h diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c new file mode 100644 index 0000000000..42b3a98d21 --- /dev/null +++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c @@ -0,0 +1,145 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include + +#include "ntlog.h" +#include "nt_util.h" +#include "ntnic_mod_reg.h" + +static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *pfh) +{ + const char *const p_dev_name = p_adapter_info->p_dev_name; + const char *const p_adapter_id_str = p_adapter_info->mp_adapter_id_str; + fpga_info_t *p_fpga_info = &p_adapter_info->fpga_info; + hw_info_t *p_hw_info = &p_adapter_info->hw_info; + char a_pci_ident_str[32]; + + snprintf(a_pci_ident_str, sizeof(a_pci_ident_str), PCIIDENT_PRINT_STR, + PCIIDENT_TO_DOMAIN(p_fpga_info->pciident), + PCIIDENT_TO_BUSNR(p_fpga_info->pciident), + PCIIDENT_TO_DEVNR(p_fpga_info->pciident), + PCIIDENT_TO_FUNCNR(p_fpga_info->pciident)); + + fprintf(pfh, "%s: DeviceName: %s\n", p_adapter_id_str, (p_dev_name ? p_dev_name : "NA")); + fprintf(pfh, "%s: PCI Details:\n", p_adapter_id_str); + fprintf(pfh, "%s: %s: %08X: %04X:%04X %04X:%04X\n", p_adapter_id_str, a_pci_ident_str, + p_fpga_info->pciident, p_hw_info->pci_vendor_id, p_hw_info->pci_device_id, + p_hw_info->pci_sub_vendor_id, p_hw_info->pci_sub_device_id); + fprintf(pfh, "%s: FPGA Details:\n", p_adapter_id_str); + fprintf(pfh, "%s: %03d-%04d-%02d-%02d [%016" PRIX64 "] (%08X)\n", p_adapter_id_str, + p_fpga_info->n_fpga_type_id, p_fpga_info->n_fpga_prod_id, + p_fpga_info->n_fpga_ver_id, p_fpga_info->n_fpga_rev_id, p_fpga_info->n_fpga_ident, + p_fpga_info->n_fpga_build_time); + fprintf(pfh, "%s: FpgaDebugMode=0x%x\n", p_adapter_id_str, p_fpga_info->n_fpga_debug_mode); + fprintf(pfh, "%s: Hw=0x%02X_rev%d: %s\n", p_adapter_id_str, p_hw_info->hw_platform_id, + p_fpga_info->nthw_hw_info.hw_id, p_fpga_info->nthw_hw_info.hw_plat_id_str); + fprintf(pfh, "%s: MCU Details:\n", p_adapter_id_str); + + return 0; +} + +static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) +{ + char *const p_dev_name = malloc(24); + char *const p_adapter_id_str = malloc(24); + fpga_info_t *fpga_info = &p_adapter_info->fpga_info; + hw_info_t *p_hw_info = &p_adapter_info->hw_info; + + + p_hw_info->n_nthw_adapter_id = nthw_platform_get_nthw_adapter_id(p_hw_info->pci_device_id); + + fpga_info->n_nthw_adapter_id = p_hw_info->n_nthw_adapter_id; + /* ref: DN-0060 section 9 */ + p_hw_info->hw_product_type = p_hw_info->pci_device_id & 0x000f; + /* ref: DN-0060 section 9 */ + p_hw_info->hw_platform_id = (p_hw_info->pci_device_id >> 4) & 0x00ff; + /* ref: DN-0060 section 9 */ + p_hw_info->hw_reserved1 = (p_hw_info->pci_device_id >> 12) & 0x000f; + + p_adapter_info->p_dev_name = p_dev_name; + + if (p_dev_name) { + snprintf(p_dev_name, 24, PCIIDENT_PRINT_STR, + PCIIDENT_TO_DOMAIN(p_adapter_info->fpga_info.pciident), + PCIIDENT_TO_BUSNR(p_adapter_info->fpga_info.pciident), + PCIIDENT_TO_DEVNR(p_adapter_info->fpga_info.pciident), + PCIIDENT_TO_FUNCNR(p_adapter_info->fpga_info.pciident)); + NT_LOG(DBG, NTNIC, "%s: (0x%08X)\n", p_dev_name, + p_adapter_info->fpga_info.pciident); + } + + p_adapter_info->mp_adapter_id_str = p_adapter_id_str; + + p_adapter_info->fpga_info.mp_adapter_id_str = p_adapter_id_str; + + if (p_adapter_id_str) { + snprintf(p_adapter_id_str, 24, "PCI:" PCIIDENT_PRINT_STR, + PCIIDENT_TO_DOMAIN(p_adapter_info->fpga_info.pciident), + PCIIDENT_TO_BUSNR(p_adapter_info->fpga_info.pciident), + PCIIDENT_TO_DEVNR(p_adapter_info->fpga_info.pciident), + PCIIDENT_TO_FUNCNR(p_adapter_info->fpga_info.pciident)); + NT_LOG(DBG, NTNIC, "%s: %s\n", p_adapter_id_str, p_dev_name); + } + + { + int i; + + for (i = 0; i < (int)ARRAY_SIZE(p_adapter_info->mp_port_id_str); i++) { + char *p = malloc(32); + + if (p) { + snprintf(p, 32, "%s:intf_%d", + (p_adapter_id_str ? p_adapter_id_str : "NA"), i); + } + + p_adapter_info->mp_port_id_str[i] = p; + } + } + + return 0; +} + +static int nt4ga_adapter_deinit(struct adapter_info_s *p_adapter_info) +{ + fpga_info_t *fpga_info = &p_adapter_info->fpga_info; + int i; + int res = -1; + + + /* Free adapter port ident strings */ + for (i = 0; i < fpga_info->n_phy_ports; i++) { + if (p_adapter_info->mp_port_id_str[i]) { + free(p_adapter_info->mp_port_id_str[i]); + p_adapter_info->mp_port_id_str[i] = NULL; + } + } + + /* Free adapter ident string */ + if (p_adapter_info->mp_adapter_id_str) { + free(p_adapter_info->mp_adapter_id_str); + p_adapter_info->mp_adapter_id_str = NULL; + } + + /* Free devname ident string */ + if (p_adapter_info->p_dev_name) { + free(p_adapter_info->p_dev_name); + p_adapter_info->p_dev_name = NULL; + } + + return res; +} + +static const struct adapter_ops ops = { + .init = nt4ga_adapter_init, + .deinit = nt4ga_adapter_deinit, + + .show_info = nt4ga_adapter_show_info, +}; + +void adapter_init(void) +{ + register_adapter_ops(&ops); +} diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h new file mode 100644 index 0000000000..2c72583caf --- /dev/null +++ b/drivers/net/ntnic/include/nt4ga_adapter.h @@ -0,0 +1,40 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NT4GA_ADAPTER_H_ +#define _NT4GA_ADAPTER_H_ + +#include "ntos_drv.h" +typedef struct hw_info_s { + /* pciids */ + uint16_t pci_vendor_id; + uint16_t pci_device_id; + uint16_t pci_sub_vendor_id; + uint16_t pci_sub_device_id; + uint16_t pci_class_id; + + /* Derived from pciid */ + nthw_adapter_id_t n_nthw_adapter_id; + int hw_platform_id; + int hw_product_type; + int hw_reserved1; +} hw_info_t; + +typedef struct adapter_info_s { + struct hw_info_s hw_info; + struct fpga_info_s fpga_info; + + char *mp_port_id_str[NUM_ADAPTER_PORTS_MAX]; + char *mp_adapter_id_str; + char *p_dev_name; + volatile bool *pb_shutdown; + + int adapter_no; + int n_rx_host_buffers; + int n_tx_host_buffers; +} adapter_info_t; + + +#endif /* _NT4GA_ADAPTER_H_ */ diff --git a/drivers/net/ntnic/include/ntdrv_4ga.h b/drivers/net/ntnic/include/ntdrv_4ga.h index bcb7ddc242..8017aa4fc3 100644 --- a/drivers/net/ntnic/include/ntdrv_4ga.h +++ b/drivers/net/ntnic/include/ntdrv_4ga.h @@ -6,9 +6,11 @@ #ifndef __NTDRV_4GA_H__ #define __NTDRV_4GA_H__ +#include "nt4ga_adapter.h" typedef struct ntdrv_4ga_s { uint32_t pciident; + struct adapter_info_s adapter_info; char *p_drv_name; volatile bool b_shutdown; diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 04e31b4729..ee4853a737 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -18,9 +18,11 @@ includes = [ # all sources sources = files( + 'adapter/nt4ga_adapter.c', 'nthw/nthw_platform.c', 'ntlog/ntlog.c', 'ntutil/nt_util.c', + 'ntnic_mod_reg.c', 'ntnic_vfio.c', 'ntnic_ethdev.c', ) diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 504d6c6bcd..42df15bd53 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -18,6 +18,7 @@ #include "ntos_drv.h" #include "ntos_system.h" #include "ntnic_vfio.h" +#include "ntnic_mod_reg.h" #include "nt_util.h" #define EXCEPTION_PATH_HID 0 @@ -130,9 +131,21 @@ eth_dev_stop(struct rte_eth_dev *eth_dev) static void drv_deinit(struct drv_s *p_drv) { + const struct adapter_ops *adapter_ops = get_adapter_ops(); + + if (adapter_ops == NULL) { + NT_LOG(ERR, NTNIC, "Adapter module uninitialized\n"); + return; + } + if (p_drv == NULL) return; + ntdrv_4ga_t *p_nt_drv = &p_drv->ntdrv; + + /* stop adapter */ + adapter_ops->deinit(&p_nt_drv->adapter_info); + /* clean memory */ rte_free(p_drv); p_drv = NULL; @@ -174,6 +187,13 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) { nt_vfio_init(); + const struct adapter_ops *adapter_ops = get_adapter_ops(); + + if (adapter_ops == NULL) { + NT_LOG(ERR, NTNIC, "Adapter module uninitialized\n"); + return -1; + } + struct drv_s *p_drv; ntdrv_4ga_t *p_nt_drv; uint32_t n_port_mask = -1; /* All ports enabled by default */ @@ -213,23 +233,71 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) /* Set context for NtDrv */ p_nt_drv->pciident = BDF_TO_PCIIDENT(pci_dev->addr.domain, pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function); + p_nt_drv->adapter_info.n_rx_host_buffers = nb_rx_queues; + p_nt_drv->adapter_info.n_tx_host_buffers = nb_tx_queues; + + + p_nt_drv->adapter_info.hw_info.pci_class_id = pci_dev->id.class_id; + p_nt_drv->adapter_info.hw_info.pci_vendor_id = pci_dev->id.vendor_id; + p_nt_drv->adapter_info.hw_info.pci_device_id = pci_dev->id.device_id; + p_nt_drv->adapter_info.hw_info.pci_sub_vendor_id = pci_dev->id.subsystem_vendor_id; + p_nt_drv->adapter_info.hw_info.pci_sub_device_id = pci_dev->id.subsystem_device_id; + + NT_LOG(DBG, NTNIC, "%s: " PCIIDENT_PRINT_STR " %04X:%04X: %04X:%04X:\n", + p_nt_drv->adapter_info.mp_adapter_id_str, PCIIDENT_TO_DOMAIN(p_nt_drv->pciident), + PCIIDENT_TO_BUSNR(p_nt_drv->pciident), PCIIDENT_TO_DEVNR(p_nt_drv->pciident), + PCIIDENT_TO_FUNCNR(p_nt_drv->pciident), + p_nt_drv->adapter_info.hw_info.pci_vendor_id, + p_nt_drv->adapter_info.hw_info.pci_device_id, + p_nt_drv->adapter_info.hw_info.pci_sub_vendor_id, + p_nt_drv->adapter_info.hw_info.pci_sub_device_id); p_nt_drv->b_shutdown = false; + p_nt_drv->adapter_info.pb_shutdown = &p_nt_drv->b_shutdown; /* store context */ store_pdrv(p_drv); + /* initialize nt4ga nthw fpga module instance in drv */ + int err = adapter_ops->init(&p_nt_drv->adapter_info); + + if (err != 0) { + NT_LOG(ERR, NTNIC, "%s: Cannot initialize the adapter instance\n", + p_nt_drv->adapter_info.mp_adapter_id_str); + return -1; + } + + /* Start ctrl, monitor, stat thread only for primary process. */ + if (err == 0) { + /* mp_adapter_id_str is initialized after nt4ga_adapter_init(p_nt_drv) */ + const char *const p_adapter_id_str = p_nt_drv->adapter_info.mp_adapter_id_str; + (void)p_adapter_id_str; + + } else { + NT_LOG_DBGX(ERR, NTNIC, "%s: error=%d\n", + (pci_dev->name[0] ? pci_dev->name : "NA"), err); + return -1; + } + n_phy_ports = 0; for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) { + const char *const p_port_id_str = p_nt_drv->adapter_info.mp_port_id_str[n_intf_no]; + (void)p_port_id_str; struct pmd_internals *internals = NULL; struct rte_eth_dev *eth_dev = NULL; char name[32]; - if ((1 << n_intf_no) & ~n_port_mask) + if ((1 << n_intf_no) & ~n_port_mask) { + NT_LOG_DBGX(DEBUG, NTNIC, + "%s: interface #%d: skipping due to portmask 0x%02X\n", + p_port_id_str, n_intf_no, n_port_mask); continue; + } snprintf(name, sizeof(name), "ntnic%d", n_intf_no); + NT_LOG_DBGX(DEBUG, NTNIC, "%s: interface #%d: %s: '%s'\n", p_port_id_str, + n_intf_no, (pci_dev->name[0] ? pci_dev->name : "NA"), name); internals = rte_zmalloc_socket(name, sizeof(struct pmd_internals), RTE_CACHE_LINE_SIZE, pci_dev->device.numa_node); @@ -289,6 +357,21 @@ nthw_pci_dev_deinit(struct rte_eth_dev *eth_dev __rte_unused) { NT_LOG_DBGX(DEBUG, NTNIC, "PCI device deinitialization\n"); + int i; + char name[32]; + + struct pmd_internals *internals = eth_dev->data->dev_private; + ntdrv_4ga_t *p_ntdrv = &internals->p_drv->ntdrv; + fpga_info_t *fpga_info = &p_ntdrv->adapter_info.fpga_info; + const int n_phy_ports = fpga_info->n_phy_ports; + for (i = 0; i < n_phy_ports; i++) { + sprintf(name, "ntnic%d", i); + eth_dev = rte_eth_dev_allocated(name); + if (eth_dev == NULL) + continue; /* port already released */ + rte_eth_dev_release_port(eth_dev); + } + nt_vfio_remove(EXCEPTION_PATH_HID); return 0; } diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c new file mode 100644 index 0000000000..006221bbe3 --- /dev/null +++ b/drivers/net/ntnic/ntnic_mod_reg.c @@ -0,0 +1,20 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntnic_mod_reg.h" + +static const struct adapter_ops *adapter_ops; + +void register_adapter_ops(const struct adapter_ops *ops) +{ + adapter_ops = ops; +} + +const struct adapter_ops *get_adapter_ops(void) +{ + if (adapter_ops == NULL) + adapter_init(); + return adapter_ops; +} diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h new file mode 100644 index 0000000000..48a9f8f7b9 --- /dev/null +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -0,0 +1,27 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTNIC_MOD_REG_H__ +#define __NTNIC_MOD_REG_H__ + +#include +#include "nthw_platform_drv.h" +#include "nthw_drv.h" +#include "nt4ga_adapter.h" +#include "ntos_drv.h" + +struct adapter_ops { + int (*init)(struct adapter_info_s *p_adapter_info); + int (*deinit)(struct adapter_info_s *p_adapter_info); + + int (*show_info)(struct adapter_info_s *p_adapter_info, FILE *pfh); +}; + +void register_adapter_ops(const struct adapter_ops *ops); +const struct adapter_ops *get_adapter_ops(void); +void adapter_init(void); + + +#endif /* __NTNIC_MOD_REG_H__ */ From patchwork Wed Jul 17 13:32:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142479 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75D0645635; Wed, 17 Jul 2024 15:36:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4882D42E70; Wed, 17 Jul 2024 15:33:56 +0200 (CEST) Received: from egress-ip42a.ess.de.barracuda.com (egress-ip42a.ess.de.barracuda.com [18.185.115.201]) by mails.dpdk.org (Postfix) with ESMTP id 9CEFE42D28 for ; Wed, 17 Jul 2024 15:33:42 +0200 (CEST) Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05lp2169.outbound.protection.outlook.com [104.47.17.169]) by mx-outbound40-186.eu-central-1c.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); 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Signed-off-by: Serhii Iliushyk --- v6 * Remove unnecessary comments * Remove EOF markers and Auto-gen comments v10 * Remove "for NapaTech NIC" from the commit message title * Use 8 spaces as indentation in meson --- drivers/net/ntnic/include/fpga_model.h | 102 ++ drivers/net/ntnic/meson.build | 4 + .../net/ntnic/nthw/model/nthw_fpga_model.c | 1192 ++++++++++++++++ .../net/ntnic/nthw/model/nthw_fpga_model.h | 245 ++++ drivers/net/ntnic/nthw/nthw_register.h | 21 + .../supported/nthw_fpga_9563_055_039_0000.c | 1225 +++++++++++++++++ .../nthw/supported/nthw_fpga_instances.c | 4 + .../nthw/supported/nthw_fpga_instances.h | 5 + .../ntnic/nthw/supported/nthw_fpga_mod_defs.h | 28 + .../nthw/supported/nthw_fpga_mod_str_map.c | 19 + .../nthw/supported/nthw_fpga_mod_str_map.h | 9 + .../nthw/supported/nthw_fpga_param_defs.h | 224 +++ .../ntnic/nthw/supported/nthw_fpga_reg_defs.h | 27 + .../nthw/supported/nthw_fpga_reg_defs_gfg.h | 118 ++ .../nthw/supported/nthw_fpga_reg_defs_gmf.h | 60 + .../supported/nthw_fpga_reg_defs_gpio_phy.h | 40 + .../nthw/supported/nthw_fpga_reg_defs_hif.h | 71 + .../nthw/supported/nthw_fpga_reg_defs_i2cm.h | 30 + .../nthw/supported/nthw_fpga_reg_defs_iic.h | 88 ++ .../supported/nthw_fpga_reg_defs_mac_pcs.h | 290 ++++ .../supported/nthw_fpga_reg_defs_pci_rd_tg.h | 29 + .../supported/nthw_fpga_reg_defs_pci_wr_tg.h | 32 + .../nthw/supported/nthw_fpga_reg_defs_pcie3.h | 273 ++++ .../nthw/supported/nthw_fpga_reg_defs_rac.h | 64 + .../supported/nthw_fpga_reg_defs_rst9563.h | 51 + .../nthw/supported/nthw_fpga_reg_defs_sdc.h | 36 + drivers/net/ntnic/ntnic_ethdev.c | 1 + 27 files changed, 4288 insertions(+) create mode 100644 drivers/net/ntnic/include/fpga_model.h create mode 100644 drivers/net/ntnic/nthw/model/nthw_fpga_model.c create mode 100644 drivers/net/ntnic/nthw/model/nthw_fpga_model.h create mode 100644 drivers/net/ntnic/nthw/nthw_register.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h create mode 100644 drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h diff --git a/drivers/net/ntnic/include/fpga_model.h b/drivers/net/ntnic/include/fpga_model.h new file mode 100644 index 0000000000..d73cf168ed --- /dev/null +++ b/drivers/net/ntnic/include/fpga_model.h @@ -0,0 +1,102 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _FPGA_MODEL_H_ +#define _FPGA_MODEL_H_ + +#include +#include +#include + +typedef uint32_t nthw_id_t; + +enum nthw_fpga_bus_type { + NTHW_FPGA_BUS_TYPE_UNKNOWN = + 0, /* Unknown/uninitialized - keep this as the first enum element */ + NTHW_FPGA_BUS_TYPE_BAR, + NTHW_FPGA_BUS_TYPE_PCI, + NTHW_FPGA_BUS_TYPE_CCIP, + NTHW_FPGA_BUS_TYPE_RAB0, + NTHW_FPGA_BUS_TYPE_RAB1, + NTHW_FPGA_BUS_TYPE_RAB2, + NTHW_FPGA_BUS_TYPE_NMB, + NTHW_FPGA_BUS_TYPE_NDM, + NTHW_FPGA_BUS_TYPE_SPI0, + NTHW_FPGA_BUS_TYPE_SPI = NTHW_FPGA_BUS_TYPE_SPI0, +}; + +typedef enum nthw_fpga_bus_type nthw_fpga_bus_type_e; + +enum nthw_fpga_register_type { + NTHW_FPGA_REG_TYPE_UNKNOWN = + 0, /* Unknown/uninitialized - keep this as the first enum element */ + NTHW_FPGA_REG_TYPE_RW, + NTHW_FPGA_REG_TYPE_RO, + NTHW_FPGA_REG_TYPE_WO, + NTHW_FPGA_REG_TYPE_RC1, + NTHW_FPGA_REG_TYPE_MIXED, +}; + +typedef enum nthw_fpga_register_type nthw_fpga_register_type_e; + +struct nthw_fpga_field_init { + nthw_id_t id; + uint16_t bw; + uint16_t low; + uint64_t reset_val; +}; + +typedef struct nthw_fpga_field_init nthw_fpga_field_init_s; + +struct nthw_fpga_register_init { + nthw_id_t id; + uint32_t addr_rel; + uint16_t bw; + nthw_fpga_register_type_e type; + uint64_t reset_val; + int nb_fields; + struct nthw_fpga_field_init *fields; +}; + +typedef struct nthw_fpga_register_init nthw_fpga_register_init_s; + +struct nthw_fpga_module_init { + nthw_id_t id; + int instance; + nthw_id_t def_id; + int major_version; + int minor_version; + nthw_fpga_bus_type_e bus_id; + uint32_t addr_base; + int nb_registers; + struct nthw_fpga_register_init *registers; +}; + +typedef struct nthw_fpga_module_init nthw_fpga_module_init_s; + +struct nthw_fpga_prod_param { + const nthw_id_t id; + const int value; +}; + +typedef struct nthw_fpga_prod_param nthw_fpga_prod_param_s; + +struct nthw_fpga_prod_init { + int fpga_item_id; + int fpga_product_id; + int fpga_version; + int fpga_revision; + int fpga_patch_no; + int fpga_build_no; + uint32_t fpga_build_time; + int nb_prod_params; + struct nthw_fpga_prod_param *product_params; + int nb_modules; + struct nthw_fpga_module_init *modules; +}; + +typedef struct nthw_fpga_prod_init nthw_fpga_prod_init_s; + +#endif /* _FPGA_MODEL_H_ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index ee4853a737..399b616278 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -14,11 +14,15 @@ includes = [ include_directories('ntlog'), include_directories('ntutil'), include_directories('nthw'), + include_directories('nthw/supported'), ] # all sources sources = files( 'adapter/nt4ga_adapter.c', + 'nthw/supported/nthw_fpga_9563_055_039_0000.c', + 'nthw/supported/nthw_fpga_instances.c', + 'nthw/supported/nthw_fpga_mod_str_map.c', 'nthw/nthw_platform.c', 'ntlog/ntlog.c', 'ntutil/nt_util.c', diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.c b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c new file mode 100644 index 0000000000..8ed00248ea --- /dev/null +++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.c @@ -0,0 +1,1192 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include + +#include "nthw_drv.h" +#include "nthw_register.h" +#include "nthw_fpga_model.h" +#include "nthw_rac.h" +#include "ntlog.h" + +/* + * NOTE: this needs to be (manually) synced with enum nthw_fpga_bus_type + */ +static const char *const sa_nthw_fpga_bus_type_str[] = { + "ERR", /* NTHW_FPGA_BUS_TYPE_UNKNOWN, */ + "BAR", /* NTHW_FPGA_BUS_TYPE_BAR, */ + "PCI", /* NTHW_FPGA_BUS_TYPE_PCI, */ + "CCIP", /* NTHW_FPGA_BUS_TYPE_CCIP, */ + "RAB0", /* NTHW_FPGA_BUS_TYPE_RAB0, */ + "RAB1", /* NTHW_FPGA_BUS_TYPE_RAB1, */ + "RAB2", /* NTHW_FPGA_BUS_TYPE_RAB2, */ + "NMB", /* NTHW_FPGA_BUS_TYPE_NMB, */ + "NDM", /* NTHW_FPGA_BUS_TYPE_NDM, */ +}; + +static const char *get_bus_name(int n_bus_type_id) +{ + if (n_bus_type_id >= 1 && n_bus_type_id <= (int)ARRAY_SIZE(sa_nthw_fpga_bus_type_str)) + return sa_nthw_fpga_bus_type_str[n_bus_type_id]; + + else + return "ERR"; +} + +/* + * module name lookup by id from array + * Uses naive linear search as performance is not an issue here... + */ + +static const struct { + const nthw_id_t a; + const char *b; +} *sa_nthw_fpga_mod_str_map; + +static const char *nthw_fpga_mod_id_to_str(nthw_id_t n_fpga_mod_id) +{ + int i; + + if (sa_nthw_fpga_mod_str_map) { + for (i = 0; sa_nthw_fpga_mod_str_map[i].a && sa_nthw_fpga_mod_str_map[i].b; i++) + if ((nthw_id_t)sa_nthw_fpga_mod_str_map[i].a == n_fpga_mod_id) + return sa_nthw_fpga_mod_str_map[i].b; + } + + return "unknown"; +} + +static int nthw_read_data(struct fpga_info_s *p_fpga_info, bool trc, int n_bus_type_id, + uint32_t addr, uint32_t len, uint32_t *p_data) +{ + int rc = -1; + + assert(p_fpga_info); + assert(p_data); + assert(len >= 1); + + switch (n_bus_type_id) { + case NTHW_FPGA_BUS_TYPE_BAR: + case NTHW_FPGA_BUS_TYPE_PCI: + nthw_rac_bar0_read32(p_fpga_info, addr, len, p_data); + rc = 0; + break; + + case NTHW_FPGA_BUS_TYPE_RAB0: + assert(p_fpga_info->mp_nthw_rac); + rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 0, addr, len, p_data); + break; + + case NTHW_FPGA_BUS_TYPE_RAB1: + assert(p_fpga_info->mp_nthw_rac); + rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 1, addr, len, p_data); + break; + + case NTHW_FPGA_BUS_TYPE_RAB2: + assert(p_fpga_info->mp_nthw_rac); + rc = nthw_rac_rab_read32(p_fpga_info->mp_nthw_rac, trc, 2, addr, len, p_data); + break; + + default: + assert(false); + return -1; + } + + return rc; +} + +static int nthw_write_data(struct fpga_info_s *p_fpga_info, bool trc, int n_bus_type_id, + uint32_t addr, uint32_t len, const uint32_t *p_data) +{ + int rc = -1; + + assert(p_fpga_info); + assert(p_data); + assert(len >= 1); + + switch (n_bus_type_id) { + case NTHW_FPGA_BUS_TYPE_BAR: + case NTHW_FPGA_BUS_TYPE_PCI: + nthw_rac_bar0_write32(p_fpga_info, addr, len, p_data); + rc = 0; + break; + + case NTHW_FPGA_BUS_TYPE_RAB0: + assert(p_fpga_info->mp_nthw_rac); + rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 0, addr, len, p_data); + break; + + case NTHW_FPGA_BUS_TYPE_RAB1: + assert(p_fpga_info->mp_nthw_rac); + rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 1, addr, len, p_data); + break; + + case NTHW_FPGA_BUS_TYPE_RAB2: + assert(p_fpga_info->mp_nthw_rac); + rc = nthw_rac_rab_write32(p_fpga_info->mp_nthw_rac, trc, 2, addr, len, p_data); + break; + + default: + assert(false); + return -1; + } + + return rc; +} + +uint64_t nthw_fpga_read_ident(struct fpga_info_s *p_fpga_info) +{ + uint64_t n_fpga_ident; + uint32_t n_fpga_ident_lo, n_fpga_ident_hi; + nthw_rac_bar0_read32(p_fpga_info, 0x0, 1, &n_fpga_ident_lo); + nthw_rac_bar0_read32(p_fpga_info, 0x8, 1, &n_fpga_ident_hi); + n_fpga_ident = (((uint64_t)n_fpga_ident_hi << 32) | n_fpga_ident_lo); + return n_fpga_ident; +} + +uint32_t nthw_fpga_read_buildtime(struct fpga_info_s *p_fpga_info) +{ + uint32_t n_fpga_build_time; + nthw_rac_bar0_read32(p_fpga_info, 0x10, 1, &n_fpga_build_time); + return n_fpga_build_time; +} + +int nthw_fpga_extract_type_id(const uint64_t n_fpga_ident) +{ + return (uint16_t)(n_fpga_ident >> 32) & 0xFF; +} + +int nthw_fpga_extract_prod_id(const uint64_t n_fpga_ident) +{ + return (uint16_t)(n_fpga_ident >> 16) & 0xFFFF; +} + +int nthw_fpga_extract_ver_id(const uint64_t n_fpga_ident) +{ + return (uint16_t)((n_fpga_ident >> 8) & 0xFF); +} + +int nthw_fpga_extract_rev_id(const uint64_t n_fpga_ident) +{ + return (uint16_t)(n_fpga_ident & 0xFF); +} + +/* + * FpgaMgr + */ +nthw_fpga_mgr_t *nthw_fpga_mgr_new(void) +{ + nthw_fpga_mgr_t *p = malloc(sizeof(nthw_fpga_mgr_t)); + return p; +} + +void nthw_fpga_mgr_delete(nthw_fpga_mgr_t *p) +{ + memset(p, 0, sizeof(nthw_fpga_mgr_t)); + free(p); +} + +void nthw_fpga_mgr_init(nthw_fpga_mgr_t *p, struct nthw_fpga_prod_init **pa_nthw_fpga_instances, + const void *pa_mod_str_map) +{ + size_t i = 0; + + p->mpa_fpga_prod_init = pa_nthw_fpga_instances; + sa_nthw_fpga_mod_str_map = pa_mod_str_map; + + /* Count fpga instance in array */ + if (pa_nthw_fpga_instances) { + for (i = 0;; i++) + if (p->mpa_fpga_prod_init[i] == NULL) + break; + } + + p->mn_fpgas = (int)i; +} + +static nthw_fpga_t *nthw_fpga_mgr_lookup_fpga(nthw_fpga_mgr_t *p, uint64_t n_fpga_id, + struct fpga_info_s *p_fpga_info) +{ + const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_id); + const int n_fpga_ver = nthw_fpga_extract_ver_id(n_fpga_id); + const int n_fpga_rev = nthw_fpga_extract_rev_id(n_fpga_id); + int i; + + for (i = 0; i < p->mn_fpgas; i++) { + nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i]; + + if (p_init->fpga_product_id == n_fpga_prod_id && + p_init->fpga_version == n_fpga_ver && p_init->fpga_revision == n_fpga_rev) { + nthw_fpga_t *p_fpga = nthw_fpga_model_new(); + nthw_fpga_model_init(p_fpga, p_init, p_fpga_info); + return p_fpga; + } + } + + return NULL; +} + +nthw_fpga_t *nthw_fpga_mgr_query_fpga(nthw_fpga_mgr_t *p_fpga_mgr, uint64_t n_fpga_id, + struct fpga_info_s *p_fpga_info) +{ + const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_id); + const int n_fpga_ver = nthw_fpga_extract_ver_id(n_fpga_id); + const int n_fpga_rev = nthw_fpga_extract_rev_id(n_fpga_id); + + nthw_fpga_t *p_fpga = nthw_fpga_mgr_lookup_fpga(p_fpga_mgr, n_fpga_id, p_fpga_info); + + if (p_fpga) { + } else { + NT_LOG(ERR, NTHW, "FPGA Id 0x%" PRIX64 ": %04d: %d.%d: no match found\n", + n_fpga_id, n_fpga_prod_id, n_fpga_ver, n_fpga_rev); + } + + return p_fpga; +} + + +void nthw_fpga_mgr_log_dump(nthw_fpga_mgr_t *p) +{ + int i; + + NT_LOG_DBGX(DEBUG, NTHW, "fpgas=%d\n", p->mn_fpgas); + + for (i = 0; i < p->mn_fpgas; i++) { + nthw_fpga_prod_init_s *p_init = p->mpa_fpga_prod_init[i]; + (void)p_init; + NT_LOG_DBGX(DEBUG, NTHW, "fpga=%d/%d: %04d-%02d-%02d\n", i, p->mn_fpgas, + p_init->fpga_product_id, p_init->fpga_version, p_init->fpga_revision); + } +} + +/* + * Fpga + */ +nthw_fpga_t *nthw_fpga_model_new(void) +{ + nthw_fpga_t *p = malloc(sizeof(nthw_fpga_t)); + + if (p) + memset(p, 0, sizeof(nthw_fpga_t)); + + return p; +} + +void nthw_fpga_model_init(nthw_fpga_t *p, nthw_fpga_prod_init_s *p_init, + struct fpga_info_s *p_fpga_info) +{ + int i; + + p->p_fpga_info = p_fpga_info; + p->mp_init = p_init; + + p->mn_item_id = p_init->fpga_item_id; + p->mn_product_id = p_init->fpga_product_id; + p->mn_fpga_version = p_init->fpga_version; + p->mn_fpga_revision = p_init->fpga_revision; + p->mn_fpga_patch_no = p_init->fpga_patch_no; + p->mn_fpga_build_no = p_init->fpga_build_no; + p->mn_fpga_build_time = p_init->fpga_build_time; + + p->mn_params = p_init->nb_prod_params; + + if (p->mn_params) { + p->mpa_params = malloc(p->mn_params * sizeof(nthw_param_t *)); + + if (p->mpa_params) { + memset(p->mpa_params, 0, (p->mn_params * sizeof(nthw_param_t *))); + + for (i = 0; i < p->mn_params; i++) { + nthw_param_t *p_param = nthw_param_new(); + + nthw_param_init(p_param, p, &p_init->product_params[i]); + p->mpa_params[i] = p_param; + } + } + } + + p->mn_modules = p_init->nb_modules; + + if (p->mn_modules) { + p->mpa_modules = malloc(p_init->nb_modules * sizeof(nthw_module_t *)); + + if (p->mpa_modules) { + memset(p->mpa_modules, 0, (p->mn_modules * sizeof(nthw_module_t *))); + + for (i = 0; i < p->mn_modules; i++) { + nthw_module_t *p_mod = nthw_module_new(); + + nthw_module_init(p_mod, p, &p_init->modules[i]); + p->mpa_modules[i] = p_mod; + } + } + } +} + +void nthw_fpga_set_debug_mode(nthw_fpga_t *p, int debug_mode) +{ + int i; + + p->m_debug_mode = debug_mode; + + for (i = 0; i < p->mn_modules; i++) { + nthw_module_t *p_mod = p->mpa_modules[i]; + + if (p_mod) + nthw_module_set_debug_mode(p_mod, debug_mode); + } +} + +static nthw_module_t *nthw_fpga_lookup_module(const nthw_fpga_t *p, nthw_id_t id, int instance) +{ + int i; + + for (i = 0; i < p->mn_modules; i++) { + nthw_module_t *p_mod = p->mpa_modules[i]; + + if (p_mod->mn_mod_id == id && p_mod->mn_instance == instance) + return p_mod; + } + + return NULL; +} + +nthw_module_t *nthw_fpga_query_module(const nthw_fpga_t *p, nthw_id_t id, int instance) +{ + return nthw_fpga_lookup_module(p, id, instance); +} + +int nthw_fpga_get_product_param(const nthw_fpga_t *p, const nthw_id_t n_param_id, + const int n_default_value) +{ + int i; + + for (i = 0; i < p->mn_params; i++) { + nthw_param_t *p_param = p->mpa_params[i]; + + if (p_param->mn_param_id == n_param_id) + return p_param->mn_param_value; + } + + return n_default_value; +} + +int nthw_fpga_get_product_id(const nthw_fpga_t *p) +{ + return p->mn_product_id; +} + +/* + * Param + */ +nthw_param_t *nthw_param_new(void) +{ + nthw_param_t *p = malloc(sizeof(nthw_param_t)); + + return p; +} + +void nthw_param_init(nthw_param_t *p, nthw_fpga_t *p_fpga, nthw_fpga_prod_param_s *p_init) +{ + p->mp_owner = p_fpga; + p->mp_init = p_init; + + p->mn_param_id = p_init->id; + p->mn_param_value = p_init->value; +} + +/* + * Module + */ +nthw_module_t *nthw_module_new(void) +{ + nthw_module_t *p = malloc(sizeof(nthw_module_t)); + + return p; +} + +void nthw_module_init(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_fpga_module_init_s *p_init) +{ + int i; + + p->mp_owner = p_fpga; + p->mp_init = p_init; + + p->mn_mod_id = p_init->id; + p->mn_instance = p_init->instance; + + /* Copy debug mode from owner */ + if (p->mp_owner) + p->mn_debug_mode = p->mp_owner->m_debug_mode; + + else + p->mn_debug_mode = 0; + + p->mn_mod_def_id = p_init->def_id; + p->mn_major_version = p_init->major_version; + p->mn_minor_version = p_init->minor_version; + p->mn_bus = p_init->bus_id; + p->mn_addr_base = p_init->addr_base; + + p->mn_registers = p_init->nb_registers; + + if (p->mn_registers) { + p->mpa_registers = malloc(p->mn_registers * sizeof(nthw_register_t *)); + + if (p->mpa_registers) { + memset(p->mpa_registers, 0, (p->mn_registers * sizeof(nthw_register_t *))); + + for (i = 0; i < p->mn_registers; i++) { + nthw_register_t *p_reg = nthw_register_new(); + + nthw_register_init(p_reg, p, &p_init->registers[i]); + p->mpa_registers[i] = p_reg; + } + } + } +} + +int nthw_module_get_major_version(const nthw_module_t *p) +{ + return p->mn_major_version; +} + +int nthw_module_get_minor_version(const nthw_module_t *p) +{ + return p->mn_minor_version; +} + +uint64_t nthw_module_get_version_packed64(const nthw_module_t *p) +{ + return (((uint64_t)p->mn_major_version & 0xFFFFFFFF) << 32) | + (p->mn_minor_version & 0xFFFFFFFF); +} + +bool nthw_module_is_version_newer(const nthw_module_t *p, int major_version, int minor_version) +{ + if (major_version == p->mn_major_version) + return p->mn_minor_version >= minor_version; + + return p->mn_major_version >= major_version; +} + +static nthw_register_t *nthw_module_lookup_register(nthw_module_t *p, nthw_id_t id) +{ + int i; + nthw_register_t *p_register = NULL; + + for (i = 0; i < p->mn_registers; i++) { + if (p->mpa_registers[i]->mn_id == id) { + p_register = p->mpa_registers[i]; + break; + } + } + + return p_register; +} + +nthw_register_t *nthw_module_query_register(nthw_module_t *p, nthw_id_t id) +{ + return nthw_module_lookup_register(p, id); +} + +nthw_register_t *nthw_module_get_register(nthw_module_t *p, nthw_id_t id) +{ + nthw_register_t *p_register; + + if (p == NULL) { + NT_LOG(ERR, NTHW, "Illegal module context for register %u\n", id); + return NULL; + } + + p_register = nthw_module_lookup_register(p, id); + + if (!p_register) { + NT_LOG(ERR, NTHW, "Register %u not found in module: %s (%u)\n", id, + nthw_fpga_mod_id_to_str(p->mn_mod_id), p->mn_mod_id); + } + + return p_register; +} + +int nthw_module_get_debug_mode(const nthw_module_t *p) +{ + return p->mn_debug_mode; +} + +void nthw_module_set_debug_mode(nthw_module_t *p, unsigned int debug_mode) +{ + int i; + + p->mn_debug_mode = debug_mode; + + for (i = 0; i < p->mn_registers; i++) { + nthw_register_t *p_register = p->mpa_registers[i]; + + if (p_register) + nthw_register_set_debug_mode(p_register, debug_mode); + } +} + +int nthw_module_get_bus(const nthw_module_t *p) +{ + return p->mn_bus; +} + +/* + * Register + */ +nthw_register_t *nthw_register_new(void) +{ + nthw_register_t *p = malloc(sizeof(nthw_register_t)); + + return p; +} + +void nthw_register_init(nthw_register_t *p, nthw_module_t *p_module, + nthw_fpga_register_init_s *p_init) +{ + int i; + + p->mp_owner = p_module; + + p->mn_id = p_init->id; + p->mn_bit_width = p_init->bw; + p->mn_addr_rel = p_init->addr_rel; + p->mn_addr = p_module->mn_addr_base + p_init->addr_rel; + p->mn_type = p_init->type; + /* Old P200 registers have no bw at register level - default to BW=-1 */ + p->mn_len = ((p_init->bw != (uint16_t)-1) ? ((p_init->bw + 31) >> 5) : 1); + p->mn_debug_mode = p_module->mn_debug_mode; + + p->mn_fields = p_init->nb_fields; + + if (p->mn_fields) { + p->mpa_fields = malloc(p->mn_fields * sizeof(nthw_field_t *)); + + if (p->mpa_fields) { + memset(p->mpa_fields, 0, (p->mn_fields * sizeof(nthw_field_t *))); + + for (i = 0; i < p->mn_fields; i++) { + nthw_field_t *p_field = nthw_field_new(); + + nthw_field_init(p_field, p, &p_init->fields[i]); + p->mpa_fields[i] = p_field; + } + + p->mp_shadow = malloc(p->mn_len * sizeof(uint32_t)); + + if (p->mp_shadow) + memset(p->mp_shadow, 0x00, (p->mn_len * sizeof(uint32_t))); + + p->mp_dirty = malloc(p->mn_len * sizeof(bool)); + + if (p->mp_dirty) + memset(p->mp_dirty, 0x00, (p->mn_len * sizeof(bool))); + } + } +} + +uint32_t nthw_register_get_address(const nthw_register_t *p) +{ + return p->mn_addr; +} + +void nthw_register_reset(const nthw_register_t *p) +{ + int i; + nthw_field_t *p_field = NULL; + + for (i = 0; i < p->mn_fields; i++) { + p_field = p->mpa_fields[i]; + + if (p_field) + nthw_field_reset(p_field); + } +} + +static nthw_field_t *nthw_register_lookup_field(const nthw_register_t *p, nthw_id_t id) +{ + int i; + nthw_field_t *p_field = NULL; + + if (!p) + return NULL; + + for (i = 0; i < p->mn_fields; i++) { + if (p->mpa_fields[i]->mn_id == id) { + p_field = p->mpa_fields[i]; + break; + } + } + + return p_field; +} + +nthw_field_t *nthw_register_query_field(const nthw_register_t *p, nthw_id_t id) +{ + return nthw_register_lookup_field(p, id); +} + +nthw_field_t *nthw_register_get_field(const nthw_register_t *p, nthw_id_t id) +{ + nthw_field_t *p_field; + + if (p == NULL) { + NT_LOG(ERR, NTHW, "Illegal register context for field %u\n", id); + return NULL; + } + + p_field = nthw_register_lookup_field(p, id); + + if (!p_field) { + NT_LOG(ERR, NTHW, "Field %u not found in module: %s (%u)\n", id, + nthw_fpga_mod_id_to_str(p->mp_owner->mn_mod_id), p->mp_owner->mn_mod_id); + } + + return p_field; +} + +int nthw_register_get_bit_width(const nthw_register_t *p) +{ + return p->mn_bit_width; +} + +int nthw_register_get_debug_mode(const nthw_register_t *p) +{ + return p->mn_debug_mode; +} + +/* + * NOTE: do not set debug on fields - as register operation dumps typically are enough + */ +void nthw_register_set_debug_mode(nthw_register_t *p, unsigned int debug_mode) +{ + int i; + + p->mn_debug_mode = debug_mode; + + for (i = 0; i < p->mn_fields; i++) { + nthw_field_t *p_field = p->mpa_fields[i]; + + if (p_field) + nthw_field_set_debug_mode(p_field, debug_mode); + } +} + +static int nthw_register_read_data(const nthw_register_t *p) +{ + int rc = -1; + + const int n_bus_type_id = nthw_module_get_bus(p->mp_owner); + const uint32_t addr = p->mn_addr; + const uint32_t len = p->mn_len; + uint32_t *const p_data = p->mp_shadow; + const bool trc = (p->mn_debug_mode & NTHW_REG_TRACE_ON_READ); + + struct fpga_info_s *p_fpga_info = NULL; + + if (p && p->mp_owner && p->mp_owner->mp_owner) + p_fpga_info = p->mp_owner->mp_owner->p_fpga_info; + + assert(p_fpga_info); + assert(p_data); + + rc = nthw_read_data(p_fpga_info, trc, n_bus_type_id, addr, len, p_data); + return rc; +} + +static int nthw_register_write_data(const nthw_register_t *p, uint32_t cnt) +{ + int rc = -1; + + const int n_bus_type_id = nthw_module_get_bus(p->mp_owner); + const uint32_t addr = p->mn_addr; + const uint32_t len = p->mn_len; + uint32_t *const p_data = p->mp_shadow; + const bool trc = (p->mn_debug_mode & NTHW_REG_TRACE_ON_WRITE); + + struct fpga_info_s *p_fpga_info = NULL; + + if (p && p->mp_owner && p->mp_owner->mp_owner) + p_fpga_info = p->mp_owner->mp_owner->p_fpga_info; + + assert(p_fpga_info); + assert(p_data); + + rc = nthw_write_data(p_fpga_info, trc, n_bus_type_id, addr, (len * cnt), p_data); + + return rc; +} + +void nthw_register_get_val(const nthw_register_t *p, uint32_t *p_data, uint32_t len) +{ + uint32_t i; + + if (len == (uint32_t)-1 || len > p->mn_len) + len = p->mn_len; + + assert(len <= p->mn_len); + assert(p_data); + + for (i = 0; i < len; i++) + p_data[i] = p->mp_shadow[i]; +} + +uint32_t nthw_register_get_val32(const nthw_register_t *p) +{ + uint32_t val = 0; + + nthw_register_get_val(p, &val, 1); + return val; +} + +void nthw_register_update(const nthw_register_t *p) +{ + if (p && p->mn_type != NTHW_FPGA_REG_TYPE_WO) { + const char *const p_dev_name = "NA"; + (void)p_dev_name; + const int n_bus_type_id = nthw_module_get_bus(p->mp_owner); + const char *const p_bus_name = get_bus_name(n_bus_type_id); + (void)p_bus_name; + const uint32_t addr = p->mn_addr; + (void)addr; + const uint32_t len = p->mn_len; + uint32_t *const p_data = p->mp_shadow; + + nthw_register_read_data(p); + + if (p->mn_debug_mode & NTHW_REG_DEBUG_ON_READ) { + uint32_t i = len; + uint32_t *ptr = p_data; + (void)ptr; + char *tmp_string = ntlog_helper_str_alloc("Register::read"); + ntlog_helper_str_add(tmp_string, + "(Dev: %s, Bus: %s, Addr: 0x%08X, Cnt: %d, Data:", + p_dev_name, p_bus_name, addr, len); + + while (i--) + ntlog_helper_str_add(tmp_string, " 0x%08X", *ptr++); + + ntlog_helper_str_add(tmp_string, ")"); + NT_LOG(DBG, NTHW, "%s", tmp_string); + ntlog_helper_str_free(tmp_string); + } + } +} + +uint32_t nthw_register_get_val_updated32(const nthw_register_t *p) +{ + uint32_t val = 0; + + nthw_register_update(p); + nthw_register_get_val(p, &val, 1); + return val; +} + +void nthw_register_make_dirty(nthw_register_t *p) +{ + uint32_t i; + + for (i = 0; i < p->mn_len; i++) + p->mp_dirty[i] = true; +} + +void nthw_register_set_val(nthw_register_t *p, const uint32_t *p_data, uint32_t len) +{ + assert(len <= p->mn_len); + assert(p_data); + + if (len == (uint32_t)-1 || len > p->mn_len) + len = p->mn_len; + + if (p->mp_shadow != p_data) + memcpy(p->mp_shadow, p_data, (len * sizeof(uint32_t))); +} + +void nthw_register_flush(const nthw_register_t *p, uint32_t cnt) +{ + int rc; + + if (p->mn_type != NTHW_FPGA_REG_TYPE_RO) { + const char *const p_dev_name = "NA"; + const int n_bus_type_id = nthw_module_get_bus(p->mp_owner); + const char *p_bus_name = get_bus_name(n_bus_type_id); + const uint32_t addr = p->mn_addr; + const uint32_t len = p->mn_len; + uint32_t *const p_data = p->mp_shadow; + uint32_t i; + + assert(len * cnt <= 256); + + if (p->mn_debug_mode & NTHW_REG_DEBUG_ON_WRITE) { + uint32_t i = len * cnt; + uint32_t *ptr = p_data; + char *tmp_string = ntlog_helper_str_alloc("Register::write"); + + ntlog_helper_str_add(tmp_string, + "(Dev: %s, Bus: %s, Addr: 0x%08X, Cnt: %d, Data:", + p_dev_name, p_bus_name, addr, i); + + while (i--) + ntlog_helper_str_add(tmp_string, " 0x%08X", *ptr++); + + ntlog_helper_str_add(tmp_string, ")"); + NT_LOG(DBG, NTHW, "%s", tmp_string); + ntlog_helper_str_free(tmp_string); + } + + rc = nthw_register_write_data(p, cnt); + + if (rc) + NT_LOG(ERR, NTHW, "Register write error %d\n", rc); + + for (i = 0; i < cnt; i++) + p->mp_dirty[i] = false; + } +} + +void nthw_register_clr(nthw_register_t *p) +{ + memset(p->mp_shadow, 0, p->mn_len * sizeof(uint32_t)); + nthw_register_make_dirty(p); +} + +/* + * Field + */ +nthw_field_t *nthw_field_new(void) +{ + nthw_field_t *p = malloc(sizeof(nthw_field_t)); + + return p; +} + +void nthw_field_init(nthw_field_t *p, nthw_register_t *p_reg, const nthw_fpga_field_init_s *p_init) +{ + p->mp_owner = p_reg; + + p->mn_debug_mode = p_reg->mn_debug_mode; + + p->mn_id = p_init->id; + p->mn_bit_width = p_init->bw; + p->mn_bit_pos_low = p_init->low; + p->mn_reset_val = (uint32_t)p_init->reset_val; + p->mn_first_word = p_init->low / 32; + p->mn_first_bit = p_init->low % 32; + p->mn_front_mask = 0; + p->mn_body_length = 0; + p->mn_words = (p_init->bw + 0x1f) / 0x20; + p->mn_tail_mask = 0; + + { + int bits_remaining = p_init->bw; + int front_mask_length = 32 - p->mn_first_bit; + + if (front_mask_length > bits_remaining) + front_mask_length = bits_remaining; + + bits_remaining -= front_mask_length; + + p->mn_front_mask = + (uint32_t)(((1ULL << front_mask_length) - 1) << p->mn_first_bit); + + p->mn_body_length = bits_remaining / 32; + bits_remaining -= p->mn_body_length * 32; + p->mn_tail_mask = (1 << bits_remaining) - 1; + + if (p->mn_debug_mode >= 0x100) { + NT_LOG_DBGX(DEBUG, NTHW, + "fldid=%08d: [%08d:%08d] %08d/%08d: (%08d,%08d) (0x%08X,%08d,0x%08X)\n", + p_init->id, p_init->low, (p_init->low + p_init->bw), + p_init->bw, ((p_init->bw + 31) / 32), p->mn_first_word, + p->mn_first_bit, p->mn_front_mask, p->mn_body_length, + p->mn_tail_mask); + } + } +} + +int nthw_field_get_debug_mode(const nthw_field_t *p) +{ + return p->mn_debug_mode; +} + +void nthw_field_set_debug_mode(nthw_field_t *p, unsigned int debug_mode) +{ + p->mn_debug_mode = debug_mode; +} + +int nthw_field_get_bit_width(const nthw_field_t *p) +{ + return p->mn_bit_width; +} + +int nthw_field_get_bit_pos_low(const nthw_field_t *p) +{ + return p->mn_bit_pos_low; +} + +int nthw_field_get_bit_pos_high(const nthw_field_t *p) +{ + return p->mn_bit_pos_low + p->mn_bit_width - 1; +} + +uint32_t nthw_field_get_mask(const nthw_field_t *p) +{ + return p->mn_front_mask; +} + +void nthw_field_reset(const nthw_field_t *p) +{ + nthw_field_set_val32(p, (uint32_t)p->mn_reset_val); +} + +void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len) +{ + uint32_t i; + uint32_t data_index = 0; + uint32_t shadow_index = p->mn_first_word; + + union { + uint32_t w32[2]; + uint64_t w64; + } buf; + + (void)len; + assert(len <= p->mn_words); + + /* handle front */ + buf.w32[0] = p->mp_owner->mp_shadow[shadow_index++] & p->mn_front_mask; + + /* handle body */ + for (i = 0; i < p->mn_body_length; i++) { + buf.w32[1] = p->mp_owner->mp_shadow[shadow_index++]; + buf.w64 = buf.w64 >> (p->mn_first_bit); + assert(data_index < len); + p_data[data_index++] = buf.w32[0]; + buf.w64 = buf.w64 >> (32 - p->mn_first_bit); + } + + /* handle tail */ + if (p->mn_tail_mask) + buf.w32[1] = p->mp_owner->mp_shadow[shadow_index++] & p->mn_tail_mask; + + else + buf.w32[1] = 0; + + buf.w64 = buf.w64 >> (p->mn_first_bit); + p_data[data_index++] = buf.w32[0]; + + if (data_index < p->mn_words) + p_data[data_index++] = buf.w32[1]; +} + +void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len) +{ + uint32_t i; + uint32_t data_index = 0; + uint32_t shadow_index = p->mn_first_word; + + union { + uint32_t w32[2]; + uint64_t w64; + } buf; + + (void)len; + assert(len == p->mn_words); + + /* handle front */ + buf.w32[0] = 0; + buf.w32[1] = p_data[data_index++]; + buf.w64 = buf.w64 >> (32 - p->mn_first_bit); + p->mp_owner->mp_shadow[shadow_index] = + (p->mp_owner->mp_shadow[shadow_index] & ~p->mn_front_mask) | + (buf.w32[0] & p->mn_front_mask); + shadow_index++; + + /* handle body */ + for (i = 0; i < p->mn_body_length; i++) { + buf.w64 = buf.w64 >> (p->mn_first_bit); + assert(data_index < len); + buf.w32[1] = p_data[data_index++]; + buf.w64 = buf.w64 >> (32 - p->mn_first_bit); + p->mp_owner->mp_shadow[shadow_index++] = buf.w32[0]; + } + + /* handle tail */ + if (p->mn_tail_mask) { + buf.w64 = buf.w64 >> (p->mn_first_bit); + + if (data_index < len) + buf.w32[1] = p_data[data_index]; + + buf.w64 = buf.w64 >> (32 - p->mn_first_bit); + p->mp_owner->mp_shadow[shadow_index] = + (p->mp_owner->mp_shadow[shadow_index] & ~p->mn_tail_mask) | + (buf.w32[0] & p->mn_tail_mask); + } + + nthw_register_make_dirty(p->mp_owner); +} + +void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len) +{ + nthw_field_set_val(p, p_data, len); + nthw_field_flush_register(p); +} + +uint32_t nthw_field_get_val32(const nthw_field_t *p) +{ + uint32_t val; + + nthw_field_get_val(p, &val, 1); + return val; +} + +uint32_t nthw_field_get_updated(const nthw_field_t *p) +{ + uint32_t val; + + nthw_register_update(p->mp_owner); + nthw_field_get_val(p, &val, 1); + + return val; +} + +void nthw_field_update_register(const nthw_field_t *p) +{ + nthw_register_update(p->mp_owner); +} + +void nthw_field_flush_register(const nthw_field_t *p) +{ + nthw_register_flush(p->mp_owner, 1); +} + +void nthw_field_set_val32(const nthw_field_t *p, uint32_t val) +{ + nthw_field_set_val(p, &val, 1); +} + +void nthw_field_set_val_flush32(const nthw_field_t *p, uint32_t val) +{ + nthw_field_set_val(p, &val, 1); + nthw_register_flush(p->mp_owner, 1); +} + +void nthw_field_clr_all(const nthw_field_t *p) +{ + assert(p->mn_body_length == 0); + nthw_field_set_val32(p, 0); +} + +void nthw_field_clr_flush(const nthw_field_t *p) +{ + nthw_field_clr_all(p); + nthw_register_flush(p->mp_owner, 1); +} + +void nthw_field_set_all(const nthw_field_t *p) +{ + assert(p->mn_body_length == 0); + nthw_field_set_val32(p, ~0); +} + +void nthw_field_set_flush(const nthw_field_t *p) +{ + nthw_field_set_all(p); + nthw_register_flush(p->mp_owner, 1); +} + +enum nthw_field_match { + NTHW_FIELD_MATCH_CLR_ALL, + NTHW_FIELD_MATCH_SET_ALL, + NTHW_FIELD_MATCH_CLR_ANY, + NTHW_FIELD_MATCH_SET_ANY, +}; + +static int nthw_field_wait_cond32(const nthw_field_t *p, enum nthw_field_match e_match, + int n_poll_iterations, int n_poll_interval) +{ + const uint32_t n_mask = (1 << p->mn_bit_width) - 1; + + if (n_poll_iterations == -1) + n_poll_iterations = 10000; + + if (n_poll_interval == -1) + n_poll_interval = 100; /* usec */ + + if (p->mn_debug_mode) { + const char *const p_cond_name = + ((e_match == NTHW_FIELD_MATCH_SET_ALL) + ? "SetAll" + : ((e_match == NTHW_FIELD_MATCH_CLR_ALL) + ? "ClrAll" + : ((e_match == NTHW_FIELD_MATCH_CLR_ANY) ? "ClrAny" + : "SetAny"))); + (void)p_cond_name; + const char *const p_dev_name = "NA"; + (void)p_dev_name; + const char *const p_bus_name = + get_bus_name(nthw_module_get_bus(p->mp_owner->mp_owner)); + (void)p_bus_name; + uint32_t n_reg_addr = nthw_register_get_address(p->mp_owner); + (void)n_reg_addr; + uint32_t n_reg_mask = (((1 << p->mn_bit_width) - 1) << p->mn_bit_pos_low); + (void)n_reg_mask; + + NT_LOG(DBG, NTHW, + "Register::Field::wait%s32(Dev: %s, Bus: %s, Addr: 0x%08X, Mask: 0x%08X, Iterations: %d, Interval: %d)\n", + p_cond_name, p_dev_name, p_bus_name, n_reg_addr, n_reg_mask, + n_poll_iterations, n_poll_interval); + } + + while (true) { + uint32_t val = nthw_field_get_updated(p); + + if (e_match == NTHW_FIELD_MATCH_SET_ANY && val != 0) { + return 0; + + } else if (e_match == NTHW_FIELD_MATCH_SET_ALL && val == n_mask) { + return 0; + + } else if (e_match == NTHW_FIELD_MATCH_CLR_ALL && val == 0) { + return 0; + + } else if (e_match == NTHW_FIELD_MATCH_CLR_ANY) { + uint32_t mask = nthw_field_get_mask(p); + + if (val != mask) + return 0; + } + + n_poll_iterations--; + + if (n_poll_iterations <= 0) + return -1; + + nt_os_wait_usec(n_poll_interval); + } + + return 0; +} + +int nthw_field_wait_set_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval) +{ + return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_SET_ALL, n_poll_iterations, + n_poll_interval); +} + +int nthw_field_wait_clr_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval) +{ + return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_CLR_ALL, n_poll_iterations, + n_poll_interval); +} + +int nthw_field_wait_set_any32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval) +{ + return nthw_field_wait_cond32(p, NTHW_FIELD_MATCH_SET_ANY, n_poll_iterations, + n_poll_interval); +} diff --git a/drivers/net/ntnic/nthw/model/nthw_fpga_model.h b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h new file mode 100644 index 0000000000..7956f0689e --- /dev/null +++ b/drivers/net/ntnic/nthw/model/nthw_fpga_model.h @@ -0,0 +1,245 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NTHW_FPGA_MODEL_H_ +#define _NTHW_FPGA_MODEL_H_ + +#include +#include "fpga_model.h" + +#define VERSION_PACKED64(_major_, _minor_) \ + ((((uint64_t)(_major_) & (0xFFFFFFFF)) << 32) | ((_minor_) & (0xFFFFFFFF))) + +enum nthw_reg_debug_mode { + NTHW_REG_DEBUG_NONE = 0, + NTHW_REG_DEBUG_ON_READ = 1, + NTHW_REG_DEBUG_ON_WRITE = 2, + NTHW_REG_TRACE_ON_READ = 4, + NTHW_REG_TRACE_ON_WRITE = 8, +}; + +struct nthw_fpga_s; + +struct nthw_param_s; + +struct nthw_module_s; + +struct nthw_register_s; + +struct nthw_field_s; + +struct nthw_fpga_mgr_s { + int mn_fpgas; + struct nthw_fpga_prod_init **mpa_fpga_prod_init; +}; + +typedef struct nthw_fpga_mgr_s nthw_fpga_mgr_t; + +struct nthw_fpga_s { + struct fpga_info_s *p_fpga_info; + + int mn_item_id; + int mn_product_id; + int mn_fpga_version; + int mn_fpga_revision; + int mn_fpga_patch_no; + int mn_fpga_build_no; + uint32_t mn_fpga_build_time; + + int mn_params; + struct nthw_param_s **mpa_params; + + int mn_modules; + struct nthw_module_s **mpa_modules; + + nthw_fpga_prod_init_s *mp_init; + + int m_debug_mode; +}; + +typedef struct nthw_fpga_s nthw_fpga_t; + +struct nthw_param_s { + nthw_fpga_t *mp_owner; + + nthw_id_t mn_param_id; + int mn_param_value; + + nthw_fpga_prod_param_s *mp_init; +}; + +typedef struct nthw_param_s nthw_param_t; + +struct nthw_module_s { + nthw_fpga_t *mp_owner; + + nthw_id_t mn_mod_id; + + int mn_instance; + + int mn_mod_def_id; + int mn_major_version; + int mn_minor_version; + + int mn_bus; + uint32_t mn_addr_base; + + int mn_debug_mode; + + int mn_registers; + struct nthw_register_s **mpa_registers; + + nthw_fpga_module_init_s *mp_init; +}; + +typedef struct nthw_module_s nthw_module_t; + +struct nthw_register_s { + nthw_module_t *mp_owner; + + nthw_id_t mn_id; + + uint32_t mn_bit_width; + uint32_t mn_addr_rel; + uint32_t mn_addr; + uint32_t mn_type; + uint32_t mn_len; + + int mn_debug_mode; + + int mn_fields; + struct nthw_field_s **mpa_fields; + + uint32_t *mp_shadow; + bool *mp_dirty; + + nthw_fpga_register_init_s *mp_init; +}; + +typedef struct nthw_register_s nthw_register_t; + +struct nthw_field_s { + nthw_register_t *mp_owner; + + nthw_id_t mn_id; + + uint32_t mn_bit_width; + uint32_t mn_bit_pos_low; + uint32_t mn_reset_val; + uint32_t mn_first_word; + uint32_t mn_first_bit; + uint32_t mn_front_mask; + uint32_t mn_body_length; + uint32_t mn_words; + uint32_t mn_tail_mask; + + int mn_debug_mode; + + nthw_fpga_field_init_s *mp_init; +}; + +typedef struct nthw_field_s nthw_field_t; + +int nthw_fpga_extract_type_id(const uint64_t n_fpga_ident); +int nthw_fpga_extract_prod_id(const uint64_t n_fpga_ident); +int nthw_fpga_extract_ver_id(const uint64_t n_fpga_ident); +int nthw_fpga_extract_rev_id(const uint64_t n_fpga_ident); + +uint64_t nthw_fpga_read_ident(struct fpga_info_s *p_fpga_info); +uint32_t nthw_fpga_read_buildtime(struct fpga_info_s *p_fpga_info); + +nthw_fpga_mgr_t *nthw_fpga_mgr_new(void); +void nthw_fpga_mgr_init(nthw_fpga_mgr_t *p, struct nthw_fpga_prod_init **pa_nthw_fpga_instances, + const void *pa_mod_str_map); +void nthw_fpga_mgr_delete(nthw_fpga_mgr_t *p); +nthw_fpga_t *nthw_fpga_mgr_query_fpga(nthw_fpga_mgr_t *p, uint64_t n_fpga_id, + struct fpga_info_s *p_fpga_info); +void nthw_fpga_mgr_log_dump(nthw_fpga_mgr_t *p); + +nthw_fpga_t *nthw_fpga_model_new(void); +void nthw_fpga_model_init(nthw_fpga_t *p, nthw_fpga_prod_init_s *p_init, + struct fpga_info_s *p_fpga_info); + +int nthw_fpga_get_product_param(const nthw_fpga_t *p, const nthw_id_t n_param_id, + const int default_value); +int nthw_fpga_get_product_id(const nthw_fpga_t *p); + +nthw_module_t *nthw_fpga_query_module(const nthw_fpga_t *p, nthw_id_t id, int instance); +void nthw_fpga_set_debug_mode(nthw_fpga_t *p, int n_debug_mode); + +nthw_param_t *nthw_param_new(void); +void nthw_param_init(nthw_param_t *p, nthw_fpga_t *p_fpga, nthw_fpga_prod_param_s *p_init); + +nthw_module_t *nthw_module_new(void); +void nthw_module_init(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_fpga_module_init_s *p_init); +void nthw_module_init2(nthw_module_t *p, nthw_fpga_t *p_fpga, nthw_id_t mod_id, int instance, + int debug_mode); + +int nthw_module_get_major_version(const nthw_module_t *p); +int nthw_module_get_minor_version(const nthw_module_t *p); +uint64_t nthw_module_get_version_packed64(const nthw_module_t *p); +bool nthw_module_is_version_newer(const nthw_module_t *p, int major_version, int minor_version); + +int nthw_module_get_bus(const nthw_module_t *p); +nthw_register_t *nthw_module_query_register(nthw_module_t *p, nthw_id_t id); +nthw_register_t *nthw_module_get_register(nthw_module_t *p, nthw_id_t id); +int nthw_module_get_debug_mode(const nthw_module_t *p); +void nthw_module_set_debug_mode(nthw_module_t *p, unsigned int debug_mode); + +nthw_register_t *nthw_register_new(void); +void nthw_register_init(nthw_register_t *p, nthw_module_t *p_module, + nthw_fpga_register_init_s *p_init); + +nthw_field_t *nthw_register_query_field(const nthw_register_t *p, nthw_id_t id); +nthw_field_t *nthw_register_get_field(const nthw_register_t *p, nthw_id_t id); + +uint32_t nthw_register_get_address(const nthw_register_t *p); +int nthw_register_get_bit_width(const nthw_register_t *p); +int nthw_register_get_debug_mode(const nthw_register_t *p); +void nthw_register_set_debug_mode(nthw_register_t *p, unsigned int debug_mode); + +void nthw_register_get_val(const nthw_register_t *p, uint32_t *p_data, uint32_t len); +uint32_t nthw_register_get_val32(const nthw_register_t *p); +uint32_t nthw_register_get_val_updated32(const nthw_register_t *p); + +void nthw_register_set_val(nthw_register_t *p, const uint32_t *p_data, uint32_t len); + +void nthw_register_make_dirty(nthw_register_t *p); +void nthw_register_update(const nthw_register_t *p); +void nthw_register_reset(const nthw_register_t *p); +void nthw_register_flush(const nthw_register_t *p, uint32_t cnt); +void nthw_register_clr(nthw_register_t *p); + +nthw_field_t *nthw_field_new(void); +void nthw_field_init(nthw_field_t *p, nthw_register_t *p_reg, + const nthw_fpga_field_init_s *p_init); + +int nthw_field_get_debug_mode(const nthw_field_t *p); +void nthw_field_set_debug_mode(nthw_field_t *p, unsigned int n_debug_mode); +int nthw_field_get_bit_width(const nthw_field_t *p); +int nthw_field_get_bit_pos_low(const nthw_field_t *p); +int nthw_field_get_bit_pos_high(const nthw_field_t *p); +uint32_t nthw_field_get_mask(const nthw_field_t *p); +void nthw_field_reset(const nthw_field_t *p); +void nthw_field_get_val(const nthw_field_t *p, uint32_t *p_data, uint32_t len); +void nthw_field_set_val(const nthw_field_t *p, const uint32_t *p_data, uint32_t len); +void nthw_field_set_val_flush(const nthw_field_t *p, const uint32_t *p_data, uint32_t len); +uint32_t nthw_field_get_val32(const nthw_field_t *p); +uint32_t nthw_field_get_updated(const nthw_field_t *p); +void nthw_field_update_register(const nthw_field_t *p); +void nthw_field_flush_register(const nthw_field_t *p); +void nthw_field_set_val32(const nthw_field_t *p, uint32_t val); +void nthw_field_set_val_flush32(const nthw_field_t *p, uint32_t val); +void nthw_field_clr_all(const nthw_field_t *p); +void nthw_field_clr_flush(const nthw_field_t *p); +void nthw_field_set_all(const nthw_field_t *p); +void nthw_field_set_flush(const nthw_field_t *p); + +int nthw_field_wait_clr_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval); +int nthw_field_wait_set_all32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval); + +int nthw_field_wait_set_any32(const nthw_field_t *p, int n_poll_iterations, int n_poll_interval); + +#endif /* _NTHW_FPGA_MODEL_H_ */ diff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h new file mode 100644 index 0000000000..db006fcf72 --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_register.h @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTHW_REGISTER_H_ +#define NTHW_REGISTER_H_ + +#include +#include +#include +#include + + +#include "fpga_model.h" + +#include "nthw_fpga_mod_defs.h" +#include "nthw_fpga_param_defs.h" +#include "nthw_fpga_reg_defs.h" + +#endif /* NTHW_REGISTER_H_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c new file mode 100644 index 0000000000..03b827bc10 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_9563_055_039_0000.c @@ -0,0 +1,1225 @@ +/* + * Auto-generated file - do *NOT* edit + */ + +#include "nthw_register.h" + +static nthw_fpga_field_init_s gfg_burstsize0_fields[] = { + { GFG_BURSTSIZE0_VAL, 24, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_burstsize1_fields[] = { + { GFG_BURSTSIZE1_VAL, 24, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_ctrl0_fields[] = { + { GFG_CTRL0_ENABLE, 1, 0, 0 }, + { GFG_CTRL0_MODE, 3, 1, 0 }, + { GFG_CTRL0_PRBS_EN, 1, 4, 0 }, + { GFG_CTRL0_SIZE, 14, 16, 64 }, +}; + +static nthw_fpga_field_init_s gfg_ctrl1_fields[] = { + { GFG_CTRL1_ENABLE, 1, 0, 0 }, + { GFG_CTRL1_MODE, 3, 1, 0 }, + { GFG_CTRL1_PRBS_EN, 1, 4, 0 }, + { GFG_CTRL1_SIZE, 14, 16, 64 }, +}; + +static nthw_fpga_field_init_s gfg_run0_fields[] = { + { GFG_RUN0_RUN, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_run1_fields[] = { + { GFG_RUN1_RUN, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_sizemask0_fields[] = { + { GFG_SIZEMASK0_VAL, 14, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_sizemask1_fields[] = { + { GFG_SIZEMASK1_VAL, 14, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_streamid0_fields[] = { + { GFG_STREAMID0_VAL, 8, 0, 0 }, +}; + +static nthw_fpga_field_init_s gfg_streamid1_fields[] = { + { GFG_STREAMID1_VAL, 8, 0, 1 }, +}; + +static nthw_fpga_register_init_s gfg_registers[] = { + { GFG_BURSTSIZE0, 3, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_burstsize0_fields }, + { GFG_BURSTSIZE1, 8, 24, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_burstsize1_fields }, + { GFG_CTRL0, 0, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, gfg_ctrl0_fields }, + { GFG_CTRL1, 5, 30, NTHW_FPGA_REG_TYPE_WO, 4194304, 4, gfg_ctrl1_fields }, + { GFG_RUN0, 1, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run0_fields }, + { GFG_RUN1, 6, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_run1_fields }, + { GFG_SIZEMASK0, 4, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_sizemask0_fields }, + { GFG_SIZEMASK1, 9, 14, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_sizemask1_fields }, + { GFG_STREAMID0, 2, 8, NTHW_FPGA_REG_TYPE_WO, 0, 1, gfg_streamid0_fields }, + { GFG_STREAMID1, 7, 8, NTHW_FPGA_REG_TYPE_WO, 1, 1, gfg_streamid1_fields }, +}; + +static nthw_fpga_field_init_s gmf_ctrl_fields[] = { + { GMF_CTRL_ENABLE, 1, 0, 0 }, + { GMF_CTRL_FCS_ALWAYS, 1, 1, 0 }, + { GMF_CTRL_IFG_AUTO_ADJUST_ENABLE, 1, 7, 0 }, + { GMF_CTRL_IFG_ENABLE, 1, 2, 0 }, + { GMF_CTRL_IFG_TX_NOW_ALWAYS, 1, 3, 0 }, + { GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE, 1, 5, 0 }, + { GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK, 1, 6, 0 }, + { GMF_CTRL_IFG_TX_ON_TS_ALWAYS, 1, 4, 0 }, + { GMF_CTRL_TS_INJECT_ALWAYS, 1, 8, 0 }, + { GMF_CTRL_TS_INJECT_DUAL_STEP, 1, 9, 0 }, +}; + +static nthw_fpga_field_init_s gmf_debug_lane_marker_fields[] = { + { GMF_DEBUG_LANE_MARKER_COMPENSATION, 16, 0, 16384 }, +}; + +static nthw_fpga_field_init_s gmf_ifg_max_adjust_slack_fields[] = { + { GMF_IFG_MAX_ADJUST_SLACK_SLACK, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_fields[] = { + { GMF_IFG_SET_CLOCK_DELTA_DELTA, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_ifg_set_clock_delta_adjust_fields[] = { + { GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_ifg_tx_now_on_ts_fields[] = { + { GMF_IFG_TX_NOW_ON_TS_TS, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_speed_fields[] = { + { GMF_SPEED_IFG_SPEED, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_stat_data_buffer_fields[] = { + { GMF_STAT_DATA_BUFFER_USED, 15, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s gmf_stat_max_delayed_pkt_fields[] = { + { GMF_STAT_MAX_DELAYED_PKT_NS, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_stat_next_pkt_fields[] = { + { GMF_STAT_NEXT_PKT_NS, 64, 0, 0 }, +}; + +static nthw_fpga_field_init_s gmf_stat_sticky_fields[] = { + { GMF_STAT_STICKY_DATA_UNDERFLOWED, 1, 0, 0 }, + { GMF_STAT_STICKY_IFG_ADJUSTED, 1, 1, 0 }, +}; + +static nthw_fpga_field_init_s gmf_ts_inject_fields[] = { + { GMF_TS_INJECT_OFFSET, 14, 0, 0 }, + { GMF_TS_INJECT_POS, 2, 14, 0 }, +}; + +static nthw_fpga_register_init_s gmf_registers[] = { + { GMF_CTRL, 0, 10, NTHW_FPGA_REG_TYPE_WO, 0, 10, gmf_ctrl_fields }, + { + GMF_DEBUG_LANE_MARKER, 7, 16, NTHW_FPGA_REG_TYPE_WO, 16384, 1, + gmf_debug_lane_marker_fields + }, + { + GMF_IFG_MAX_ADJUST_SLACK, 4, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, + gmf_ifg_max_adjust_slack_fields + }, + { + GMF_IFG_SET_CLOCK_DELTA, 2, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, + gmf_ifg_set_clock_delta_fields + }, + { + GMF_IFG_SET_CLOCK_DELTA_ADJUST, 3, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, + gmf_ifg_set_clock_delta_adjust_fields + }, + { GMF_IFG_TX_NOW_ON_TS, 5, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, gmf_ifg_tx_now_on_ts_fields }, + { GMF_SPEED, 1, 64, NTHW_FPGA_REG_TYPE_WO, 0, 1, gmf_speed_fields }, + { GMF_STAT_DATA_BUFFER, 9, 15, NTHW_FPGA_REG_TYPE_RO, 0, 1, gmf_stat_data_buffer_fields }, + { + GMF_STAT_MAX_DELAYED_PKT, 11, 64, NTHW_FPGA_REG_TYPE_RC1, 0, 1, + gmf_stat_max_delayed_pkt_fields + }, + { GMF_STAT_NEXT_PKT, 10, 64, NTHW_FPGA_REG_TYPE_RO, 0, 1, gmf_stat_next_pkt_fields }, + { GMF_STAT_STICKY, 8, 2, NTHW_FPGA_REG_TYPE_RC1, 0, 2, gmf_stat_sticky_fields }, + { GMF_TS_INJECT, 6, 16, NTHW_FPGA_REG_TYPE_WO, 0, 2, gmf_ts_inject_fields }, +}; + +static nthw_fpga_field_init_s gpio_phy_cfg_fields[] = { + { GPIO_PHY_CFG_E_PORT0_RXLOS, 1, 8, 0 }, { GPIO_PHY_CFG_E_PORT1_RXLOS, 1, 9, 0 }, + { GPIO_PHY_CFG_PORT0_INT_B, 1, 1, 1 }, { GPIO_PHY_CFG_PORT0_LPMODE, 1, 0, 0 }, + { GPIO_PHY_CFG_PORT0_MODPRS_B, 1, 3, 1 }, { GPIO_PHY_CFG_PORT0_RESET_B, 1, 2, 0 }, + { GPIO_PHY_CFG_PORT1_INT_B, 1, 5, 1 }, { GPIO_PHY_CFG_PORT1_LPMODE, 1, 4, 0 }, + { GPIO_PHY_CFG_PORT1_MODPRS_B, 1, 7, 1 }, { GPIO_PHY_CFG_PORT1_RESET_B, 1, 6, 0 }, +}; + +static nthw_fpga_field_init_s gpio_phy_gpio_fields[] = { + { GPIO_PHY_GPIO_E_PORT0_RXLOS, 1, 8, 0 }, { GPIO_PHY_GPIO_E_PORT1_RXLOS, 1, 9, 0 }, + { GPIO_PHY_GPIO_PORT0_INT_B, 1, 1, 0x0000 }, { GPIO_PHY_GPIO_PORT0_LPMODE, 1, 0, 1 }, + { GPIO_PHY_GPIO_PORT0_MODPRS_B, 1, 3, 0x0000 }, { GPIO_PHY_GPIO_PORT0_RESET_B, 1, 2, 0 }, + { GPIO_PHY_GPIO_PORT1_INT_B, 1, 5, 0x0000 }, { GPIO_PHY_GPIO_PORT1_LPMODE, 1, 4, 1 }, + { GPIO_PHY_GPIO_PORT1_MODPRS_B, 1, 7, 0x0000 }, { GPIO_PHY_GPIO_PORT1_RESET_B, 1, 6, 0 }, +}; + +static nthw_fpga_register_init_s gpio_phy_registers[] = { + { GPIO_PHY_CFG, 0, 10, NTHW_FPGA_REG_TYPE_RW, 170, 10, gpio_phy_cfg_fields }, + { GPIO_PHY_GPIO, 1, 10, NTHW_FPGA_REG_TYPE_RW, 17, 10, gpio_phy_gpio_fields }, +}; + +static nthw_fpga_field_init_s hif_build_time_fields[] = { + { HIF_BUILD_TIME_TIME, 32, 0, 1713859545 }, +}; + +static nthw_fpga_field_init_s hif_config_fields[] = { + { HIF_CONFIG_EXT_TAG, 1, 6, 0x0000 }, + { HIF_CONFIG_MAX_READ, 3, 3, 0x0000 }, + { HIF_CONFIG_MAX_TLP, 3, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s hif_control_fields[] = { + { HIF_CONTROL_BLESSED, 8, 4, 0 }, + { HIF_CONTROL_FSR, 1, 12, 1 }, + { HIF_CONTROL_WRAW, 4, 0, 1 }, +}; + +static nthw_fpga_field_init_s hif_prod_id_ex_fields[] = { + { HIF_PROD_ID_EX_LAYOUT, 1, 31, 0 }, + { HIF_PROD_ID_EX_LAYOUT_VERSION, 8, 0, 1 }, + { HIF_PROD_ID_EX_RESERVED, 23, 8, 0 }, +}; + +static nthw_fpga_field_init_s hif_prod_id_lsb_fields[] = { + { HIF_PROD_ID_LSB_GROUP_ID, 16, 16, 9563 }, + { HIF_PROD_ID_LSB_REV_ID, 8, 0, 39 }, + { HIF_PROD_ID_LSB_VER_ID, 8, 8, 55 }, +}; + +static nthw_fpga_field_init_s hif_prod_id_msb_fields[] = { + { HIF_PROD_ID_MSB_BUILD_NO, 10, 12, 0 }, + { HIF_PROD_ID_MSB_TYPE_ID, 12, 0, 200 }, +}; + +static nthw_fpga_field_init_s hif_sample_time_fields[] = { + { HIF_SAMPLE_TIME_SAMPLE_TIME, 1, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s hif_status_fields[] = { + { HIF_STATUS_RD_ERR, 1, 9, 0 }, + { HIF_STATUS_TAGS_IN_USE, 8, 0, 0 }, + { HIF_STATUS_WR_ERR, 1, 8, 0 }, +}; + +static nthw_fpga_field_init_s hif_stat_ctrl_fields[] = { + { HIF_STAT_CTRL_STAT_ENA, 1, 1, 0 }, + { HIF_STAT_CTRL_STAT_REQ, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s hif_stat_refclk_fields[] = { + { HIF_STAT_REFCLK_REFCLK250, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s hif_stat_rx_fields[] = { + { HIF_STAT_RX_COUNTER, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s hif_stat_tx_fields[] = { + { HIF_STAT_TX_COUNTER, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s hif_test0_fields[] = { + { HIF_TEST0_DATA, 32, 0, 287454020 }, +}; + +static nthw_fpga_field_init_s hif_test1_fields[] = { + { HIF_TEST1_DATA, 32, 0, 2864434397 }, +}; + +static nthw_fpga_field_init_s hif_uuid0_fields[] = { + { HIF_UUID0_UUID0, 32, 0, 1237800326 }, +}; + +static nthw_fpga_field_init_s hif_uuid1_fields[] = { + { HIF_UUID1_UUID1, 32, 0, 3057550372 }, +}; + +static nthw_fpga_field_init_s hif_uuid2_fields[] = { + { HIF_UUID2_UUID2, 32, 0, 2445752330 }, +}; + +static nthw_fpga_field_init_s hif_uuid3_fields[] = { + { HIF_UUID3_UUID3, 32, 0, 1864147557 }, +}; + +static nthw_fpga_register_init_s hif_registers[] = { + { HIF_BUILD_TIME, 16, 32, NTHW_FPGA_REG_TYPE_RO, 1713859545, 1, hif_build_time_fields }, + { HIF_CONFIG, 24, 7, NTHW_FPGA_REG_TYPE_RW, 0, 3, hif_config_fields }, + { HIF_CONTROL, 40, 13, NTHW_FPGA_REG_TYPE_MIXED, 4097, 3, hif_control_fields }, + { HIF_PROD_ID_EX, 112, 32, NTHW_FPGA_REG_TYPE_RO, 1, 3, hif_prod_id_ex_fields }, + { HIF_PROD_ID_LSB, 0, 32, NTHW_FPGA_REG_TYPE_RO, 626734887, 3, hif_prod_id_lsb_fields }, + { HIF_PROD_ID_MSB, 8, 22, NTHW_FPGA_REG_TYPE_RO, 200, 2, hif_prod_id_msb_fields }, + { HIF_SAMPLE_TIME, 96, 1, NTHW_FPGA_REG_TYPE_WO, 0, 1, hif_sample_time_fields }, + { HIF_STATUS, 32, 10, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, hif_status_fields }, + { HIF_STAT_CTRL, 64, 2, NTHW_FPGA_REG_TYPE_WO, 0, 2, hif_stat_ctrl_fields }, + { HIF_STAT_REFCLK, 72, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_refclk_fields }, + { HIF_STAT_RX, 88, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_rx_fields }, + { HIF_STAT_TX, 80, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, hif_stat_tx_fields }, + { HIF_TEST0, 48, 32, NTHW_FPGA_REG_TYPE_RW, 287454020, 1, hif_test0_fields }, + { HIF_TEST1, 56, 32, NTHW_FPGA_REG_TYPE_RW, 2864434397, 1, hif_test1_fields }, + { HIF_UUID0, 128, 32, NTHW_FPGA_REG_TYPE_RO, 1237800326, 1, hif_uuid0_fields }, + { HIF_UUID1, 144, 32, NTHW_FPGA_REG_TYPE_RO, 3057550372, 1, hif_uuid1_fields }, + { HIF_UUID2, 160, 32, NTHW_FPGA_REG_TYPE_RO, 2445752330, 1, hif_uuid2_fields }, + { HIF_UUID3, 176, 32, NTHW_FPGA_REG_TYPE_RO, 1864147557, 1, hif_uuid3_fields }, +}; + +static nthw_fpga_field_init_s iic_adr_fields[] = { + { IIC_ADR_SLV_ADR, 7, 1, 0 }, +}; + +static nthw_fpga_field_init_s iic_cr_fields[] = { + { IIC_CR_EN, 1, 0, 0 }, { IIC_CR_GC_EN, 1, 6, 0 }, { IIC_CR_MSMS, 1, 2, 0 }, + { IIC_CR_RST, 1, 7, 0 }, { IIC_CR_RSTA, 1, 5, 0 }, { IIC_CR_TX, 1, 3, 0 }, + { IIC_CR_TXAK, 1, 4, 0 }, { IIC_CR_TXFIFO_RESET, 1, 1, 0 }, +}; + +static nthw_fpga_field_init_s iic_dgie_fields[] = { + { IIC_DGIE_GIE, 1, 31, 0 }, +}; + +static nthw_fpga_field_init_s iic_gpo_fields[] = { + { IIC_GPO_GPO_VAL, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_ier_fields[] = { + { IIC_IER_INT0, 1, 0, 0 }, { IIC_IER_INT1, 1, 1, 0 }, { IIC_IER_INT2, 1, 2, 0 }, + { IIC_IER_INT3, 1, 3, 0 }, { IIC_IER_INT4, 1, 4, 0 }, { IIC_IER_INT5, 1, 5, 0 }, + { IIC_IER_INT6, 1, 6, 0 }, { IIC_IER_INT7, 1, 7, 0 }, +}; + +static nthw_fpga_field_init_s iic_isr_fields[] = { + { IIC_ISR_INT0, 1, 0, 0 }, { IIC_ISR_INT1, 1, 1, 0 }, { IIC_ISR_INT2, 1, 2, 0 }, + { IIC_ISR_INT3, 1, 3, 0 }, { IIC_ISR_INT4, 1, 4, 0 }, { IIC_ISR_INT5, 1, 5, 0 }, + { IIC_ISR_INT6, 1, 6, 0 }, { IIC_ISR_INT7, 1, 7, 0 }, +}; + +static nthw_fpga_field_init_s iic_rx_fifo_fields[] = { + { IIC_RX_FIFO_RXDATA, 8, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_rx_fifo_ocy_fields[] = { + { IIC_RX_FIFO_OCY_OCY_VAL, 4, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_rx_fifo_pirq_fields[] = { + { IIC_RX_FIFO_PIRQ_CMP_VAL, 4, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_softr_fields[] = { + { IIC_SOFTR_RKEY, 4, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s iic_sr_fields[] = { + { IIC_SR_AAS, 1, 1, 0 }, { IIC_SR_ABGC, 1, 0, 0 }, { IIC_SR_BB, 1, 2, 0 }, + { IIC_SR_RXFIFO_EMPTY, 1, 6, 1 }, { IIC_SR_RXFIFO_FULL, 1, 5, 0 }, { IIC_SR_SRW, 1, 3, 0 }, + { IIC_SR_TXFIFO_EMPTY, 1, 7, 1 }, { IIC_SR_TXFIFO_FULL, 1, 4, 0 }, +}; + +static nthw_fpga_field_init_s iic_tbuf_fields[] = { + { IIC_TBUF_TBUF_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_ten_adr_fields[] = { + { IIC_TEN_ADR_MSB_SLV_ADR, 3, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_thddat_fields[] = { + { IIC_THDDAT_THDDAT_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_thdsta_fields[] = { + { IIC_THDSTA_THDSTA_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_thigh_fields[] = { + { IIC_THIGH_THIGH_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_tlow_fields[] = { + { IIC_TLOW_TLOW_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_tsudat_fields[] = { + { IIC_TSUDAT_TSUDAT_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_tsusta_fields[] = { + { IIC_TSUSTA_TSUSTA_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_tsusto_fields[] = { + { IIC_TSUSTO_TSUSTO_VAL, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_tx_fifo_fields[] = { + { IIC_TX_FIFO_START, 1, 8, 0 }, + { IIC_TX_FIFO_STOP, 1, 9, 0 }, + { IIC_TX_FIFO_TXDATA, 8, 0, 0 }, +}; + +static nthw_fpga_field_init_s iic_tx_fifo_ocy_fields[] = { + { IIC_TX_FIFO_OCY_OCY_VAL, 4, 0, 0 }, +}; + +static nthw_fpga_register_init_s iic_registers[] = { + { IIC_ADR, 68, 8, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_adr_fields }, + { IIC_CR, 64, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_cr_fields }, + { IIC_DGIE, 7, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_dgie_fields }, + { IIC_GPO, 73, 1, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_gpo_fields }, + { IIC_IER, 10, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_ier_fields }, + { IIC_ISR, 8, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, iic_isr_fields }, + { IIC_RX_FIFO, 67, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_rx_fifo_fields }, + { IIC_RX_FIFO_OCY, 70, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_rx_fifo_ocy_fields }, + { IIC_RX_FIFO_PIRQ, 72, 4, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_rx_fifo_pirq_fields }, + { IIC_SOFTR, 16, 4, NTHW_FPGA_REG_TYPE_WO, 0, 1, iic_softr_fields }, + { IIC_SR, 65, 8, NTHW_FPGA_REG_TYPE_RO, 192, 8, iic_sr_fields }, + { IIC_TBUF, 78, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tbuf_fields }, + { IIC_TEN_ADR, 71, 3, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_ten_adr_fields }, + { IIC_THDDAT, 81, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thddat_fields }, + { IIC_THDSTA, 76, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thdsta_fields }, + { IIC_THIGH, 79, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_thigh_fields }, + { IIC_TLOW, 80, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tlow_fields }, + { IIC_TSUDAT, 77, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsudat_fields }, + { IIC_TSUSTA, 74, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsusta_fields }, + { IIC_TSUSTO, 75, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, iic_tsusto_fields }, + { IIC_TX_FIFO, 66, 10, NTHW_FPGA_REG_TYPE_WO, 0, 3, iic_tx_fifo_fields }, + { IIC_TX_FIFO_OCY, 69, 4, NTHW_FPGA_REG_TYPE_RO, 0, 1, iic_tx_fifo_ocy_fields }, +}; + +static nthw_fpga_field_init_s mac_pcs_bad_code_fields[] = { + { MAC_PCS_BAD_CODE_CODE_ERR, 16, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_bip_err_fields[] = { + { MAC_PCS_BIP_ERR_BIP_ERR, 640, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_block_lock_fields[] = { + { MAC_PCS_BLOCK_LOCK_LOCK, 20, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_block_lock_chg_fields[] = { + { MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG, 20, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_debounce_ctrl_fields[] = { + { MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY, 8, 8, 10 }, + { MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN, 1, 16, 0 }, + { MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY, 8, 0, 10 }, + { MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL, 2, 17, 2 }, +}; + +static nthw_fpga_field_init_s mac_pcs_drp_ctrl_fields[] = { + { MAC_PCS_DRP_CTRL_ADR, 10, 16, 0 }, { MAC_PCS_DRP_CTRL_DATA, 16, 0, 0 }, + { MAC_PCS_DRP_CTRL_DBG_BUSY, 1, 30, 0x0000 }, { MAC_PCS_DRP_CTRL_DONE, 1, 31, 0x0000 }, + { MAC_PCS_DRP_CTRL_MOD_ADR, 3, 26, 0 }, { MAC_PCS_DRP_CTRL_WREN, 1, 29, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_ctrl_fields[] = { + { MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN, 5, 0, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_cw_cnt_fields[] = { + { MAC_PCS_FEC_CW_CNT_CW_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_0_fields[] = { + { MAC_PCS_FEC_ERR_CNT_0_ERR_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_1_fields[] = { + { MAC_PCS_FEC_ERR_CNT_1_ERR_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_2_fields[] = { + { MAC_PCS_FEC_ERR_CNT_2_ERR_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_err_cnt_3_fields[] = { + { MAC_PCS_FEC_ERR_CNT_3_ERR_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_0_fields[] = { + { MAC_PCS_FEC_LANE_DLY_0_DLY, 14, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_1_fields[] = { + { MAC_PCS_FEC_LANE_DLY_1_DLY, 14, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_2_fields[] = { + { MAC_PCS_FEC_LANE_DLY_2_DLY, 14, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_lane_dly_3_fields[] = { + { MAC_PCS_FEC_LANE_DLY_3_DLY, 14, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_lane_map_fields[] = { + { MAC_PCS_FEC_LANE_MAP_MAPPING, 8, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_stat_fields[] = { + { MAC_PCS_FEC_STAT_AM_LOCK, 1, 10, 0x0000 }, + { MAC_PCS_FEC_STAT_AM_LOCK_0, 1, 3, 0x0000 }, + { MAC_PCS_FEC_STAT_AM_LOCK_1, 1, 4, 0x0000 }, + { MAC_PCS_FEC_STAT_AM_LOCK_2, 1, 5, 0x0000 }, + { MAC_PCS_FEC_STAT_AM_LOCK_3, 1, 6, 0x0000 }, + { MAC_PCS_FEC_STAT_BLOCK_LOCK, 1, 9, 0x0000 }, + { MAC_PCS_FEC_STAT_BYPASS, 1, 0, 0x0000 }, + { MAC_PCS_FEC_STAT_FEC_LANE_ALGN, 1, 7, 0x0000 }, + { MAC_PCS_FEC_STAT_HI_SER, 1, 2, 0x0000 }, + { MAC_PCS_FEC_STAT_PCS_LANE_ALGN, 1, 8, 0x0000 }, + { MAC_PCS_FEC_STAT_VALID, 1, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_fec_ucw_cnt_fields[] = { + { MAC_PCS_FEC_UCW_CNT_UCW_CNT, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_ctl_rx_fields[] = { + { MAC_PCS_GTY_CTL_RX_CDR_HOLD_0, 1, 24, 0 }, { MAC_PCS_GTY_CTL_RX_CDR_HOLD_1, 1, 25, 0 }, + { MAC_PCS_GTY_CTL_RX_CDR_HOLD_2, 1, 26, 0 }, { MAC_PCS_GTY_CTL_RX_CDR_HOLD_3, 1, 27, 0 }, + { MAC_PCS_GTY_CTL_RX_EQUA_RST_0, 1, 20, 0 }, { MAC_PCS_GTY_CTL_RX_EQUA_RST_1, 1, 21, 0 }, + { MAC_PCS_GTY_CTL_RX_EQUA_RST_2, 1, 22, 0 }, { MAC_PCS_GTY_CTL_RX_EQUA_RST_3, 1, 23, 0 }, + { MAC_PCS_GTY_CTL_RX_LPM_EN_0, 1, 16, 0 }, { MAC_PCS_GTY_CTL_RX_LPM_EN_1, 1, 17, 0 }, + { MAC_PCS_GTY_CTL_RX_LPM_EN_2, 1, 18, 0 }, { MAC_PCS_GTY_CTL_RX_LPM_EN_3, 1, 19, 0 }, + { MAC_PCS_GTY_CTL_RX_POLARITY_0, 1, 0, 0 }, { MAC_PCS_GTY_CTL_RX_POLARITY_1, 1, 1, 0 }, + { MAC_PCS_GTY_CTL_RX_POLARITY_2, 1, 2, 0 }, { MAC_PCS_GTY_CTL_RX_POLARITY_3, 1, 3, 0 }, + { MAC_PCS_GTY_CTL_RX_RATE_0, 3, 4, 0 }, { MAC_PCS_GTY_CTL_RX_RATE_1, 3, 7, 0 }, + { MAC_PCS_GTY_CTL_RX_RATE_2, 3, 10, 0 }, { MAC_PCS_GTY_CTL_RX_RATE_3, 3, 13, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_ctl_tx_fields[] = { + { MAC_PCS_GTY_CTL_TX_INHIBIT_0, 1, 4, 0 }, { MAC_PCS_GTY_CTL_TX_INHIBIT_1, 1, 5, 0 }, + { MAC_PCS_GTY_CTL_TX_INHIBIT_2, 1, 6, 0 }, { MAC_PCS_GTY_CTL_TX_INHIBIT_3, 1, 7, 0 }, + { MAC_PCS_GTY_CTL_TX_POLARITY_0, 1, 0, 0 }, { MAC_PCS_GTY_CTL_TX_POLARITY_1, 1, 1, 0 }, + { MAC_PCS_GTY_CTL_TX_POLARITY_2, 1, 2, 0 }, { MAC_PCS_GTY_CTL_TX_POLARITY_3, 1, 3, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_diff_ctl_fields[] = { + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0, 5, 0, 24 }, + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1, 5, 5, 24 }, + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2, 5, 10, 24 }, + { MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3, 5, 15, 24 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_loop_fields[] = { + { MAC_PCS_GTY_LOOP_GT_LOOP_0, 3, 0, 0 }, + { MAC_PCS_GTY_LOOP_GT_LOOP_1, 3, 3, 0 }, + { MAC_PCS_GTY_LOOP_GT_LOOP_2, 3, 6, 0 }, + { MAC_PCS_GTY_LOOP_GT_LOOP_3, 3, 9, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_post_cursor_fields[] = { + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0, 5, 0, 20 }, + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1, 5, 5, 20 }, + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2, 5, 10, 20 }, + { MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3, 5, 15, 20 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_prbs_sel_fields[] = { + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0, 4, 16, 0 }, + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1, 4, 20, 0 }, + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2, 4, 24, 0 }, + { MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3, 4, 28, 0 }, + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0, 4, 0, 0 }, + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1, 4, 4, 0 }, + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2, 4, 8, 0 }, + { MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3, 4, 12, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_pre_cursor_fields[] = { + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0, 5, 0, 0 }, + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1, 5, 5, 0 }, + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2, 5, 10, 0 }, + { MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3, 5, 15, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_rx_buf_stat_fields[] = { + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0, 3, 0, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1, 3, 3, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2, 3, 6, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3, 3, 9, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0, 3, 12, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1, 3, 15, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2, 3, 18, 0x0000 }, + { MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3, 3, 21, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_scan_ctl_fields[] = { + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0, 1, 0, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1, 1, 1, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2, 1, 2, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3, 1, 3, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0, 1, 4, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1, 1, 5, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2, 1, 6, 0 }, + { MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3, 1, 7, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0, 1, 12, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1, 1, 13, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2, 1, 14, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3, 1, 15, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0, 1, 8, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1, 1, 9, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2, 1, 10, 0 }, + { MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3, 1, 11, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_scan_stat_fields[] = { + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0, 1, 0, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1, 1, 1, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2, 1, 2, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3, 1, 3, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0, 1, 4, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1, 1, 5, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2, 1, 6, 0x0000 }, + { MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3, 1, 7, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_gty_stat_fields[] = { + { MAC_PCS_GTY_STAT_RX_RST_DONE_0, 1, 4, 0x0000 }, + { MAC_PCS_GTY_STAT_RX_RST_DONE_1, 1, 5, 0x0000 }, + { MAC_PCS_GTY_STAT_RX_RST_DONE_2, 1, 6, 0x0000 }, + { MAC_PCS_GTY_STAT_RX_RST_DONE_3, 1, 7, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_BUF_STAT_0, 2, 8, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_BUF_STAT_1, 2, 10, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_BUF_STAT_2, 2, 12, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_BUF_STAT_3, 2, 14, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_RST_DONE_0, 1, 0, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_RST_DONE_1, 1, 1, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_RST_DONE_2, 1, 2, 0x0000 }, + { MAC_PCS_GTY_STAT_TX_RST_DONE_3, 1, 3, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_link_summary_fields[] = { + { MAC_PCS_LINK_SUMMARY_ABS, 1, 0, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_LH_ABS, 1, 2, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT, 1, 13, 0 }, + { MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT, 1, 14, 0 }, + { MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT, 8, 4, 0 }, + { MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE, 1, 3, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_LOCAL_FAULT, 1, 17, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_NIM_INTERR, 1, 12, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE, 1, 1, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_REMOTE_FAULT, 1, 18, 0x0000 }, + { MAC_PCS_LINK_SUMMARY_RESERVED, 2, 15, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_mac_pcs_config_fields[] = { + { MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST, 1, 3, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE, 1, 5, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC, 1, 6, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST, 1, 1, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN, 1, 7, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST, 1, 2, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE, 1, 8, 1 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE, 1, 4, 1 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST, 1, 0, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE, 1, 9, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI, 1, 10, 0 }, + { MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN, 1, 11, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_max_pkt_len_fields[] = { + { MAC_PCS_MAX_PKT_LEN_MAX_LEN, 14, 0, 10000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_phymac_misc_fields[] = { + { MAC_PCS_PHYMAC_MISC_TS_EOP, 1, 3, 1 }, + { MAC_PCS_PHYMAC_MISC_TX_MUX_STATE, 4, 4, 0x0000 }, + { MAC_PCS_PHYMAC_MISC_TX_SEL_HOST, 1, 0, 1 }, + { MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP, 1, 2, 0 }, + { MAC_PCS_PHYMAC_MISC_TX_SEL_TFG, 1, 1, 0 }, +}; + +static nthw_fpga_field_init_s mac_pcs_phy_stat_fields[] = { + { MAC_PCS_PHY_STAT_ALARM, 1, 2, 0x0000 }, + { MAC_PCS_PHY_STAT_MOD_PRS, 1, 1, 0x0000 }, + { MAC_PCS_PHY_STAT_RX_LOS, 1, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_fields[] = { + { MAC_PCS_STAT_PCS_RX_ALIGNED, 1, 1, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_ALIGNED_ERR, 1, 2, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS, 1, 9, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_HI_BER, 1, 8, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LOCAL_FAULT, 1, 6, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_MISALIGNED, 1, 3, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_REMOTE_FAULT, 1, 7, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_STATUS, 1, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_stat_pcs_rx_latch_fields[] = { + { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED, 1, 1, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR, 1, 2, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS, 1, 9, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_HI_BER, 1, 8, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT, 1, 4, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT, 1, 6, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED, 1, 3, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT, 1, 5, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT, 1, 7, 0x0000 }, + { MAC_PCS_STAT_PCS_RX_LATCH_STATUS, 1, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_stat_pcs_tx_fields[] = { + { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT, 1, 0, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED, 1, 5, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR, 1, 4, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED, 1, 9, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR, 1, 3, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED, 1, 8, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_TX_OVFOUT, 1, 2, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED, 1, 7, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_TX_UNFOUT, 1, 1, 0x0000 }, + { MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED, 1, 6, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_synced_fields[] = { + { MAC_PCS_SYNCED_SYNC, 20, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_synced_err_fields[] = { + { MAC_PCS_SYNCED_ERR_SYNC_ERROR, 20, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_test_err_fields[] = { + { MAC_PCS_TEST_ERR_CODE_ERR, 16, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_timestamp_comp_fields[] = { + { MAC_PCS_TIMESTAMP_COMP_RX_DLY, 16, 0, 1451 }, + { MAC_PCS_TIMESTAMP_COMP_TX_DLY, 16, 16, 1440 }, +}; + +static nthw_fpga_field_init_s mac_pcs_vl_demuxed_fields[] = { + { MAC_PCS_VL_DEMUXED_LOCK, 20, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s mac_pcs_vl_demuxed_chg_fields[] = { + { MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG, 20, 0, 0x0000 }, +}; + +static nthw_fpga_register_init_s mac_pcs_registers[] = { + { MAC_PCS_BAD_CODE, 26, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_bad_code_fields }, + { MAC_PCS_BIP_ERR, 31, 640, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_bip_err_fields }, + { MAC_PCS_BLOCK_LOCK, 27, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_block_lock_fields }, + { + MAC_PCS_BLOCK_LOCK_CHG, 28, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_block_lock_chg_fields + }, + { + MAC_PCS_DEBOUNCE_CTRL, 1, 19, NTHW_FPGA_REG_TYPE_RW, 264714, 4, + mac_pcs_debounce_ctrl_fields + }, + { MAC_PCS_DRP_CTRL, 43, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 6, mac_pcs_drp_ctrl_fields }, + { MAC_PCS_FEC_CTRL, 2, 5, NTHW_FPGA_REG_TYPE_RW, 0, 1, mac_pcs_fec_ctrl_fields }, + { MAC_PCS_FEC_CW_CNT, 9, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_cw_cnt_fields }, + { + MAC_PCS_FEC_ERR_CNT_0, 11, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_err_cnt_0_fields + }, + { + MAC_PCS_FEC_ERR_CNT_1, 12, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_err_cnt_1_fields + }, + { + MAC_PCS_FEC_ERR_CNT_2, 13, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_err_cnt_2_fields + }, + { + MAC_PCS_FEC_ERR_CNT_3, 14, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_err_cnt_3_fields + }, + { + MAC_PCS_FEC_LANE_DLY_0, 5, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_lane_dly_0_fields + }, + { + MAC_PCS_FEC_LANE_DLY_1, 6, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_lane_dly_1_fields + }, + { + MAC_PCS_FEC_LANE_DLY_2, 7, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_lane_dly_2_fields + }, + { + MAC_PCS_FEC_LANE_DLY_3, 8, 14, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_fec_lane_dly_3_fields + }, + { MAC_PCS_FEC_LANE_MAP, 4, 8, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_lane_map_fields }, + { MAC_PCS_FEC_STAT, 3, 11, NTHW_FPGA_REG_TYPE_RO, 0, 11, mac_pcs_fec_stat_fields }, + { MAC_PCS_FEC_UCW_CNT, 10, 32, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_fec_ucw_cnt_fields }, + { MAC_PCS_GTY_CTL_RX, 38, 28, NTHW_FPGA_REG_TYPE_RW, 0, 20, mac_pcs_gty_ctl_rx_fields }, + { MAC_PCS_GTY_CTL_TX, 39, 8, NTHW_FPGA_REG_TYPE_RW, 0, 8, mac_pcs_gty_ctl_tx_fields }, + { + MAC_PCS_GTY_DIFF_CTL, 35, 20, NTHW_FPGA_REG_TYPE_RW, 811800, 4, + mac_pcs_gty_diff_ctl_fields + }, + { MAC_PCS_GTY_LOOP, 20, 12, NTHW_FPGA_REG_TYPE_RW, 0, 4, mac_pcs_gty_loop_fields }, + { + MAC_PCS_GTY_POST_CURSOR, 36, 20, NTHW_FPGA_REG_TYPE_RW, 676500, 4, + mac_pcs_gty_post_cursor_fields + }, + { MAC_PCS_GTY_PRBS_SEL, 40, 32, NTHW_FPGA_REG_TYPE_RW, 0, 8, mac_pcs_gty_prbs_sel_fields }, + { + MAC_PCS_GTY_PRE_CURSOR, 37, 20, NTHW_FPGA_REG_TYPE_RW, 0, 4, + mac_pcs_gty_pre_cursor_fields + }, + { + MAC_PCS_GTY_RX_BUF_STAT, 34, 24, NTHW_FPGA_REG_TYPE_RO, 0, 8, + mac_pcs_gty_rx_buf_stat_fields + }, + { + MAC_PCS_GTY_SCAN_CTL, 41, 16, NTHW_FPGA_REG_TYPE_RW, 0, 16, + mac_pcs_gty_scan_ctl_fields + }, + { + MAC_PCS_GTY_SCAN_STAT, 42, 8, NTHW_FPGA_REG_TYPE_RO, 0, 8, + mac_pcs_gty_scan_stat_fields + }, + { MAC_PCS_GTY_STAT, 33, 16, NTHW_FPGA_REG_TYPE_RO, 0, 12, mac_pcs_gty_stat_fields }, + { MAC_PCS_LINK_SUMMARY, 0, 19, NTHW_FPGA_REG_TYPE_RO, 0, 11, mac_pcs_link_summary_fields }, + { + MAC_PCS_MAC_PCS_CONFIG, 19, 12, NTHW_FPGA_REG_TYPE_RW, 272, 12, + mac_pcs_mac_pcs_config_fields + }, + { + MAC_PCS_MAX_PKT_LEN, 17, 14, NTHW_FPGA_REG_TYPE_RW, 10000, 1, + mac_pcs_max_pkt_len_fields + }, + { MAC_PCS_PHYMAC_MISC, 16, 8, NTHW_FPGA_REG_TYPE_MIXED, 9, 5, mac_pcs_phymac_misc_fields }, + { MAC_PCS_PHY_STAT, 15, 3, NTHW_FPGA_REG_TYPE_RO, 0, 3, mac_pcs_phy_stat_fields }, + { MAC_PCS_STAT_PCS_RX, 21, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, mac_pcs_stat_pcs_rx_fields }, + { + MAC_PCS_STAT_PCS_RX_LATCH, 22, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, + mac_pcs_stat_pcs_rx_latch_fields + }, + { MAC_PCS_STAT_PCS_TX, 23, 10, NTHW_FPGA_REG_TYPE_RO, 0, 10, mac_pcs_stat_pcs_tx_fields }, + { MAC_PCS_SYNCED, 24, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_synced_fields }, + { MAC_PCS_SYNCED_ERR, 25, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_synced_err_fields }, + { MAC_PCS_TEST_ERR, 32, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_test_err_fields }, + { + MAC_PCS_TIMESTAMP_COMP, 18, 32, NTHW_FPGA_REG_TYPE_RW, 94373291, 2, + mac_pcs_timestamp_comp_fields + }, + { MAC_PCS_VL_DEMUXED, 29, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, mac_pcs_vl_demuxed_fields }, + { + MAC_PCS_VL_DEMUXED_CHG, 30, 20, NTHW_FPGA_REG_TYPE_RO, 0, 1, + mac_pcs_vl_demuxed_chg_fields + }, +}; + +static nthw_fpga_field_init_s pci_rd_tg_tg_ctrl_fields[] = { + { PCI_RD_TG_TG_CTRL_TG_RD_RDY, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_rd_tg_tg_rdaddr_fields[] = { + { PCI_RD_TG_TG_RDADDR_RAM_ADDR, 9, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata0_fields[] = { + { PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata1_fields[] = { + { PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_rd_tg_tg_rddata2_fields[] = { + { PCI_RD_TG_TG_RDDATA2_REQ_HID, 6, 22, 0 }, + { PCI_RD_TG_TG_RDDATA2_REQ_SIZE, 22, 0, 0 }, + { PCI_RD_TG_TG_RDDATA2_WAIT, 1, 30, 0 }, + { PCI_RD_TG_TG_RDDATA2_WRAP, 1, 31, 0 }, +}; + +static nthw_fpga_field_init_s pci_rd_tg_tg_rd_run_fields[] = { + { PCI_RD_TG_TG_RD_RUN_RD_ITERATION, 16, 0, 0 }, +}; + +static nthw_fpga_register_init_s pci_rd_tg_registers[] = { + { PCI_RD_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_rd_tg_tg_ctrl_fields }, + { PCI_RD_TG_TG_RDADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rdaddr_fields }, + { PCI_RD_TG_TG_RDDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rddata0_fields }, + { PCI_RD_TG_TG_RDDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rddata1_fields }, + { PCI_RD_TG_TG_RDDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 4, pci_rd_tg_tg_rddata2_fields }, + { PCI_RD_TG_TG_RD_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_rd_tg_tg_rd_run_fields }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_ctrl_fields[] = { + { PCI_WR_TG_TG_CTRL_TG_WR_RDY, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_seq_fields[] = { + { PCI_WR_TG_TG_SEQ_SEQUENCE, 16, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_wraddr_fields[] = { + { PCI_WR_TG_TG_WRADDR_RAM_ADDR, 9, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata0_fields[] = { + { PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata1_fields[] = { + { PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_wrdata2_fields[] = { + { PCI_WR_TG_TG_WRDATA2_INC_MODE, 1, 29, 0 }, { PCI_WR_TG_TG_WRDATA2_REQ_HID, 6, 22, 0 }, + { PCI_WR_TG_TG_WRDATA2_REQ_SIZE, 22, 0, 0 }, { PCI_WR_TG_TG_WRDATA2_WAIT, 1, 30, 0 }, + { PCI_WR_TG_TG_WRDATA2_WRAP, 1, 31, 0 }, +}; + +static nthw_fpga_field_init_s pci_wr_tg_tg_wr_run_fields[] = { + { PCI_WR_TG_TG_WR_RUN_WR_ITERATION, 16, 0, 0 }, +}; + +static nthw_fpga_register_init_s pci_wr_tg_registers[] = { + { PCI_WR_TG_TG_CTRL, 5, 1, NTHW_FPGA_REG_TYPE_RO, 0, 1, pci_wr_tg_tg_ctrl_fields }, + { PCI_WR_TG_TG_SEQ, 6, 16, NTHW_FPGA_REG_TYPE_RW, 0, 1, pci_wr_tg_tg_seq_fields }, + { PCI_WR_TG_TG_WRADDR, 3, 9, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wraddr_fields }, + { PCI_WR_TG_TG_WRDATA0, 0, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wrdata0_fields }, + { PCI_WR_TG_TG_WRDATA1, 1, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wrdata1_fields }, + { PCI_WR_TG_TG_WRDATA2, 2, 32, NTHW_FPGA_REG_TYPE_WO, 0, 5, pci_wr_tg_tg_wrdata2_fields }, + { PCI_WR_TG_TG_WR_RUN, 4, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, pci_wr_tg_tg_wr_run_fields }, +}; + +static nthw_fpga_field_init_s rac_dbg_ctrl_fields[] = { + { RAC_DBG_CTRL_C, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s rac_dbg_data_fields[] = { + { RAC_DBG_DATA_D, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s rac_rab_buf_free_fields[] = { + { RAC_RAB_BUF_FREE_IB_FREE, 9, 0, 511 }, { RAC_RAB_BUF_FREE_IB_OVF, 1, 12, 0 }, + { RAC_RAB_BUF_FREE_OB_FREE, 9, 16, 511 }, { RAC_RAB_BUF_FREE_OB_OVF, 1, 28, 0 }, + { RAC_RAB_BUF_FREE_TIMEOUT, 1, 31, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_buf_used_fields[] = { + { RAC_RAB_BUF_USED_FLUSH, 1, 31, 0 }, + { RAC_RAB_BUF_USED_IB_USED, 9, 0, 0 }, + { RAC_RAB_BUF_USED_OB_USED, 9, 16, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ib_hi_fields[] = { + { RAC_RAB_DMA_IB_HI_PHYADDR, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ib_lo_fields[] = { + { RAC_RAB_DMA_IB_LO_PHYADDR, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ib_rd_fields[] = { + { RAC_RAB_DMA_IB_RD_PTR, 16, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ib_wr_fields[] = { + { RAC_RAB_DMA_IB_WR_PTR, 16, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ob_hi_fields[] = { + { RAC_RAB_DMA_OB_HI_PHYADDR, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ob_lo_fields[] = { + { RAC_RAB_DMA_OB_LO_PHYADDR, 32, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_dma_ob_wr_fields[] = { + { RAC_RAB_DMA_OB_WR_PTR, 16, 0, 0 }, +}; + +static nthw_fpga_field_init_s rac_rab_ib_data_fields[] = { + { RAC_RAB_IB_DATA_D, 32, 0, 0x0000 }, +}; + +static nthw_fpga_field_init_s rac_rab_init_fields[] = { + { RAC_RAB_INIT_RAB, 3, 0, 7 }, +}; + +static nthw_fpga_field_init_s rac_rab_ob_data_fields[] = { + { RAC_RAB_OB_DATA_D, 32, 0, 0x0000 }, +}; + +static nthw_fpga_register_init_s rac_registers[] = { + { RAC_DBG_CTRL, 4200, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, rac_dbg_ctrl_fields }, + { RAC_DBG_DATA, 4208, 32, NTHW_FPGA_REG_TYPE_RW, 0, 1, rac_dbg_data_fields }, + { + RAC_RAB_BUF_FREE, 4176, 32, NTHW_FPGA_REG_TYPE_MIXED, 33489407, 5, + rac_rab_buf_free_fields + }, + { RAC_RAB_BUF_USED, 4184, 32, NTHW_FPGA_REG_TYPE_MIXED, 0, 3, rac_rab_buf_used_fields }, + { RAC_RAB_DMA_IB_HI, 4360, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_hi_fields }, + { RAC_RAB_DMA_IB_LO, 4352, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_lo_fields }, + { RAC_RAB_DMA_IB_RD, 4424, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, rac_rab_dma_ib_rd_fields }, + { RAC_RAB_DMA_IB_WR, 4416, 16, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ib_wr_fields }, + { RAC_RAB_DMA_OB_HI, 4376, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ob_hi_fields }, + { RAC_RAB_DMA_OB_LO, 4368, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_dma_ob_lo_fields }, + { RAC_RAB_DMA_OB_WR, 4480, 16, NTHW_FPGA_REG_TYPE_RO, 0, 1, rac_rab_dma_ob_wr_fields }, + { RAC_RAB_IB_DATA, 4160, 32, NTHW_FPGA_REG_TYPE_WO, 0, 1, rac_rab_ib_data_fields }, + { RAC_RAB_INIT, 4192, 3, NTHW_FPGA_REG_TYPE_RW, 7, 1, rac_rab_init_fields }, + { RAC_RAB_OB_DATA, 4168, 32, NTHW_FPGA_REG_TYPE_RC1, 0, 1, rac_rab_ob_data_fields }, +}; + +static nthw_fpga_field_init_s rst9563_ctrl_fields[] = { + { RST9563_CTRL_PTP_MMCM_CLKSEL, 1, 2, 1 }, + { RST9563_CTRL_TS_CLKSEL, 1, 1, 1 }, + { RST9563_CTRL_TS_CLKSEL_OVERRIDE, 1, 0, 1 }, +}; + +static nthw_fpga_field_init_s rst9563_power_fields[] = { + { RST9563_POWER_PU_NSEB, 1, 1, 0 }, + { RST9563_POWER_PU_PHY, 1, 0, 0 }, +}; + +static nthw_fpga_field_init_s rst9563_rst_fields[] = { + { RST9563_RST_CORE_MMCM, 1, 15, 0 }, { RST9563_RST_DDR4, 3, 3, 7 }, + { RST9563_RST_MAC_RX, 2, 9, 3 }, { RST9563_RST_PERIPH, 1, 13, 0 }, + { RST9563_RST_PHY, 2, 7, 3 }, { RST9563_RST_PTP, 1, 11, 1 }, + { RST9563_RST_PTP_MMCM, 1, 16, 0 }, { RST9563_RST_RPP, 1, 2, 1 }, + { RST9563_RST_SDC, 1, 6, 1 }, { RST9563_RST_SYS, 1, 0, 1 }, + { RST9563_RST_SYS_MMCM, 1, 14, 0 }, { RST9563_RST_TMC, 1, 1, 1 }, + { RST9563_RST_TS, 1, 12, 1 }, { RST9563_RST_TS_MMCM, 1, 17, 0 }, +}; + +static nthw_fpga_field_init_s rst9563_stat_fields[] = { + { RST9563_STAT_CORE_MMCM_LOCKED, 1, 5, 0x0000 }, + { RST9563_STAT_DDR4_MMCM_LOCKED, 1, 2, 0x0000 }, + { RST9563_STAT_DDR4_PLL_LOCKED, 1, 3, 0x0000 }, + { RST9563_STAT_PTP_MMCM_LOCKED, 1, 0, 0x0000 }, + { RST9563_STAT_SYS_MMCM_LOCKED, 1, 4, 0x0000 }, + { RST9563_STAT_TS_MMCM_LOCKED, 1, 1, 0x0000 }, +}; + +static nthw_fpga_field_init_s rst9563_sticky_fields[] = { + { RST9563_STICKY_CORE_MMCM_UNLOCKED, 1, 5, 0x0000 }, + { RST9563_STICKY_DDR4_MMCM_UNLOCKED, 1, 2, 0x0000 }, + { RST9563_STICKY_DDR4_PLL_UNLOCKED, 1, 3, 0x0000 }, + { RST9563_STICKY_PTP_MMCM_UNLOCKED, 1, 0, 0x0000 }, + { RST9563_STICKY_SYS_MMCM_UNLOCKED, 1, 4, 0x0000 }, + { RST9563_STICKY_TS_MMCM_UNLOCKED, 1, 1, 0x0000 }, +}; + +static nthw_fpga_register_init_s rst9563_registers[] = { + { RST9563_CTRL, 1, 3, NTHW_FPGA_REG_TYPE_RW, 7, 3, rst9563_ctrl_fields }, + { RST9563_POWER, 4, 2, NTHW_FPGA_REG_TYPE_RW, 0, 2, rst9563_power_fields }, + { RST9563_RST, 0, 18, NTHW_FPGA_REG_TYPE_RW, 8191, 14, rst9563_rst_fields }, + { RST9563_STAT, 2, 6, NTHW_FPGA_REG_TYPE_RO, 0, 6, rst9563_stat_fields }, + { RST9563_STICKY, 3, 6, NTHW_FPGA_REG_TYPE_RC1, 0, 6, rst9563_sticky_fields }, +}; + +static nthw_fpga_module_init_s fpga_modules[] = { + { MOD_GFG, 0, MOD_GFG, 1, 1, NTHW_FPGA_BUS_TYPE_RAB2, 8704, 10, gfg_registers }, + { MOD_GMF, 0, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9216, 12, gmf_registers }, + { MOD_GMF, 1, MOD_GMF, 2, 5, NTHW_FPGA_BUS_TYPE_RAB2, 9728, 12, gmf_registers }, + { + MOD_GPIO_PHY, 0, MOD_GPIO_PHY, 1, 0, NTHW_FPGA_BUS_TYPE_RAB0, 16386, 2, + gpio_phy_registers + }, + { MOD_HIF, 0, MOD_HIF, 0, 0, NTHW_FPGA_BUS_TYPE_PCI, 0, 18, hif_registers }, + { MOD_IIC, 0, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 768, 22, iic_registers }, + { MOD_IIC, 1, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 896, 22, iic_registers }, + { MOD_IIC, 2, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24832, 22, iic_registers }, + { MOD_IIC, 3, MOD_IIC, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 24960, 22, iic_registers }, + { + MOD_MAC_PCS, 0, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 10240, 44, + mac_pcs_registers + }, + { + MOD_MAC_PCS, 1, MOD_MAC_PCS, 0, 2, NTHW_FPGA_BUS_TYPE_RAB2, 11776, 44, + mac_pcs_registers + }, + { + MOD_PCI_RD_TG, 0, MOD_PCI_RD_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2320, 6, + pci_rd_tg_registers + }, + { + MOD_PCI_WR_TG, 0, MOD_PCI_WR_TG, 0, 1, NTHW_FPGA_BUS_TYPE_RAB0, 2304, 7, + pci_wr_tg_registers + }, + { MOD_RAC, 0, MOD_RAC, 3, 0, NTHW_FPGA_BUS_TYPE_PCI, 8192, 14, rac_registers }, + { MOD_RST9563, 0, MOD_RST9563, 0, 5, NTHW_FPGA_BUS_TYPE_RAB0, 1024, 5, rst9563_registers }, +}; + +static nthw_fpga_prod_param_s product_parameters[] = { + { NT_BUILD_NUMBER, 0 }, + { NT_BUILD_TIME, 1713859545 }, + { NT_CATEGORIES, 64 }, + { NT_CAT_DCT_PRESENT, 0 }, + { NT_CAT_END_OFS_SUPPORT, 0 }, + { NT_CAT_FUNCS, 64 }, + { NT_CAT_KCC_BANKS, 3 }, + { NT_CAT_KCC_PRESENT, 0 }, + { NT_CAT_KCC_SIZE, 1536 }, + { NT_CAT_KM_IF_CNT, 2 }, + { NT_CAT_KM_IF_M0, 0 }, + { NT_CAT_KM_IF_M1, 1 }, + { NT_CAT_N_CMP, 8 }, + { NT_CAT_N_EXT, 4 }, + { NT_CAT_N_LEN, 8 }, + { NT_CB_DEBUG, 0 }, + { NT_COR_CATEGORIES, 16 }, + { NT_COR_PRESENT, 0 }, + { NT_CSU_PRESENT, 1 }, + { NT_DBS_PRESENT, 1 }, + { NT_DBS_RX_QUEUES, 128 }, + { NT_DBS_TX_PORTS, 2 }, + { NT_DBS_TX_QUEUES, 128 }, + { NT_DDP_PRESENT, 0 }, + { NT_DDP_TBL_DEPTH, 4096 }, + { NT_EMI_SPLIT_STEPS, 16 }, + { NT_EOF_TIMESTAMP_ONLY, 1 }, + { NT_EPP_CATEGORIES, 32 }, + { NT_FLM_CACHE, 1 }, + { NT_FLM_CATEGORIES, 32 }, + { NT_FLM_ENTRY_SIZE, 64 }, + { NT_FLM_LOAD_APS_MAX, 260000000 }, + { NT_FLM_LOAD_LPS_MAX, 300000000 }, + { NT_FLM_PRESENT, 1 }, + { NT_FLM_PRIOS, 4 }, + { NT_FLM_PST_PROFILES, 16 }, + { NT_FLM_SCRUB_PROFILES, 16 }, + { NT_FLM_SIZE_MB, 12288 }, + { NT_FLM_STATEFUL, 1 }, + { NT_FLM_VARIANT, 2 }, + { NT_GFG_PRESENT, 1 }, + { NT_GFG_TX_LIVE_RECONFIG_SUPPORT, 1 }, + { NT_GMF_FCS_PRESENT, 0 }, + { NT_GMF_IFG_SPEED_DIV, 33 }, + { NT_GMF_IFG_SPEED_DIV100G, 33 }, + { NT_GMF_IFG_SPEED_MUL, 20 }, + { NT_GMF_IFG_SPEED_MUL100G, 20 }, + { NT_GROUP_ID, 9563 }, + { NT_HFU_PRESENT, 1 }, + { NT_HIF_MSIX_BAR, 1 }, + { NT_HIF_MSIX_PBA_OFS, 8192 }, + { NT_HIF_MSIX_PRESENT, 1 }, + { NT_HIF_MSIX_TBL_OFS, 0 }, + { NT_HIF_MSIX_TBL_SIZE, 8 }, + { NT_HIF_PER_PS, 4000 }, + { NT_HIF_SRIOV_PRESENT, 1 }, + { NT_HIF_VF_OFFSET, 4 }, + { NT_HSH_CATEGORIES, 16 }, + { NT_HSH_TOEPLITZ, 1 }, + { NT_HST_CATEGORIES, 32 }, + { NT_HST_PRESENT, 0 }, + { NT_IOA_CATEGORIES, 1024 }, + { NT_IOA_PRESENT, 0 }, + { NT_IPF_PRESENT, 0 }, + { NT_KM_CAM_BANKS, 3 }, + { NT_KM_CAM_RECORDS, 2048 }, + { NT_KM_CAM_REC_WORDS, 6 }, + { NT_KM_CATEGORIES, 32 }, + { NT_KM_END_OFS_SUPPORT, 0 }, + { NT_KM_EXT_EXTRACTORS, 1 }, + { NT_KM_FLOW_TYPES, 16 }, + { NT_KM_PRESENT, 1 }, + { NT_KM_SWX_PRESENT, 0 }, + { NT_KM_SYNERGY_MATCH, 0 }, + { NT_KM_TCAM_BANKS, 12 }, + { NT_KM_TCAM_BANK_WIDTH, 72 }, + { NT_KM_TCAM_HIT_QUAL, 0 }, + { NT_KM_TCAM_KEYWAY, 1 }, + { NT_KM_WIDE, 1 }, + { NT_LR_PRESENT, 1 }, + { NT_MCU_PRESENT, 0 }, + { NT_MDG_DEBUG_FLOW_CONTROL, 0 }, + { NT_MDG_DEBUG_REG_READ_BACK, 0 }, + { NT_MSK_CATEGORIES, 32 }, + { NT_MSK_PRESENT, 0 }, + { NT_NFV_OVS_PRODUCT, 0 }, + { NT_NIMS, 2 }, + { NT_PCI_DEVICE_ID, 453 }, + { NT_PCI_TA_TG_PRESENT, 1 }, + { NT_PCI_VENDOR_ID, 6388 }, + { NT_PDB_CATEGORIES, 16 }, + { NT_PHY_ANEG_PRESENT, 0 }, + { NT_PHY_KRFEC_PRESENT, 0 }, + { NT_PHY_PORTS, 2 }, + { NT_PHY_PORTS_PER_QUAD, 1 }, + { NT_PHY_QUADS, 2 }, + { NT_PHY_RSFEC_PRESENT, 1 }, + { NT_QM_CELLS, 2097152 }, + { NT_QM_CELL_SIZE, 6144 }, + { NT_QM_PRESENT, 0 }, + { NT_QSL_CATEGORIES, 32 }, + { NT_QSL_COLOR_SEL_BW, 7 }, + { NT_QSL_QST_SIZE, 4096 }, + { NT_QUEUES, 128 }, + { NT_RAC_RAB_INTERFACES, 3 }, + { NT_RAC_RAB_OB_UPDATE, 0 }, + { NT_REVISION_ID, 39 }, + { NT_RMC_LAG_GROUPS, 1 }, + { NT_RMC_PRESENT, 1 }, + { NT_ROA_CATEGORIES, 1024 }, + { NT_ROA_PRESENT, 0 }, + { NT_RPF_MATURING_DEL_DEFAULT, -150 }, + { NT_RPF_PRESENT, 0 }, + { NT_RPP_PER_PS, 3333 }, + { NT_RTX_PRESENT, 0 }, + { NT_RX_HOST_BUFFERS, 128 }, + { NT_RX_PORTS, 2 }, + { NT_RX_PORT_REPLICATE, 0 }, + { NT_SLB_PRESENT, 0 }, + { NT_SLC_LR_PRESENT, 1 }, + { NT_SLC_PRESENT, 0 }, + { NT_STA_COLORS, 64 }, + { NT_STA_LOAD_AVG_RX, 1 }, + { NT_STA_LOAD_AVG_TX, 1 }, + { NT_STA_RX_PORTS, 2 }, + { NT_TBH_DEBUG_DLN, 1 }, + { NT_TBH_PRESENT, 0 }, + { NT_TFD_PRESENT, 1 }, + { NT_TPE_CATEGORIES, 16 }, + { NT_TSM_OST_ONLY, 0 }, + { NT_TS_APPEND, 0 }, + { NT_TS_INJECT_PRESENT, 0 }, + { NT_TX_CPY_PACKET_READERS, 0 }, + { NT_TX_CPY_PRESENT, 1 }, + { NT_TX_CPY_SIDEBAND_READERS, 7 }, + { NT_TX_CPY_VARIANT, 0 }, + { NT_TX_CPY_WRITERS, 6 }, + { NT_TX_HOST_BUFFERS, 128 }, + { NT_TX_INS_OFS_ZERO, 1 }, + { NT_TX_INS_PRESENT, 1 }, + { NT_TX_MTU_PROFILE_IFR, 16 }, + { NT_TX_ON_TIMESTAMP, 1 }, + { NT_TX_PORTS, 2 }, + { NT_TX_PORT_REPLICATE, 1 }, + { NT_TX_RPL_DEPTH, 4096 }, + { NT_TX_RPL_EXT_CATEGORIES, 1024 }, + { NT_TX_RPL_OFS_ZERO, 1 }, + { NT_TX_RPL_PRESENT, 1 }, + { NT_TYPE_ID, 200 }, + { NT_USE_TRIPLE_SPEED, 0 }, + { NT_VERSION_ID, 55 }, + { NT_VLI_PRESENT, 0 }, + { 0, -1 }, /* END */ +}; + +nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000 = { + 200, 9563, 55, 39, 0, 0, 1713859545, 152, product_parameters, 15, fpga_modules, +}; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c new file mode 100644 index 0000000000..ff6efc6e75 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.c @@ -0,0 +1,4 @@ + + +#include "nthw_fpga_instances.h" +nthw_fpga_prod_init_s *nthw_fpga_instances[] = { &nthw_fpga_9563_055_039_0000, NULL }; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h new file mode 100644 index 0000000000..05c0b94bbe --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_instances.h @@ -0,0 +1,5 @@ + + +#include "fpga_model.h" +extern nthw_fpga_prod_init_s *nthw_fpga_instances[]; +extern nthw_fpga_prod_init_s nthw_fpga_9563_055_039_0000; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h new file mode 100644 index 0000000000..0c746f8f53 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_defs.h @@ -0,0 +1,28 @@ +/* + * nthw_fpga_mod_defs.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_MOD_DEFS_H_ +#define _NTHW_FPGA_MOD_DEFS_H_ + +#define MOD_UNKNOWN (0L)/* Unknown/uninitialized - keep this as the first element */ +#define MOD_GFG (0xfc423807UL) +#define MOD_GMF (0x68b1d15aUL) +#define MOD_GPIO_PHY (0xbbe81659UL) +#define MOD_HIF (0x7815363UL) +#define MOD_I2CM (0x93bc7780UL) +#define MOD_IIC (0x7629cddbUL) +#define MOD_MAC_PCS (0x7abe24c7UL) +#define MOD_PCIE3 (0xfbc48c18UL) +#define MOD_PCI_RD_TG (0x9ad9eed2UL) +#define MOD_PCI_WR_TG (0x274b69e1UL) +#define MOD_RAC (0xae830b42UL) +#define MOD_RST9563 (0x385d6d1dUL) +#define MOD_SDC (0xd2369530UL) +#define MOD_IDX_COUNT (14) + +/* aliases - only aliases go below this point */ +#endif /* _NTHW_FPGA_MOD_DEFS_H_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c new file mode 100644 index 0000000000..d7bc686fe8 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.c @@ -0,0 +1,19 @@ + + +#include "nthw_fpga_mod_str_map.h" +const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[] = { + { MOD_GFG, "GFG" }, + { MOD_GMF, "GMF" }, + { MOD_GPIO_PHY, "GPIO_PHY" }, + { MOD_HIF, "HIF" }, + { MOD_I2CM, "I2CM" }, + { MOD_IIC, "IIC" }, + { MOD_MAC_PCS, "MAC_PCS" }, + { MOD_PCIE3, "PCIE3" }, + { MOD_PCI_RD_TG, "PCI_RD_TG" }, + { MOD_PCI_WR_TG, "PCI_WR_TG" }, + { MOD_RAC, "RAC" }, + { MOD_RST9563, "RST9563" }, + { MOD_SDC, "SDC" }, + { 0UL, NULL } +}; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h new file mode 100644 index 0000000000..13971d5d4e --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_mod_str_map.h @@ -0,0 +1,9 @@ + + +#include "nthw_fpga_mod_defs.h" +#include "fpga_model.h" +struct nthw_fpga_mod_str_s { + const nthw_id_t a; + const char *b; +}; +extern const struct nthw_fpga_mod_str_s sa_nthw_fpga_mod_str_map[]; diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h new file mode 100644 index 0000000000..37ade07013 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_param_defs.h @@ -0,0 +1,224 @@ +/* + * nthw_fpga_param_defs.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_PARAM_DEFS_ +#define _NTHW_FPGA_PARAM_DEFS_ + +#define NTHW_PARAM_UNKNOWN (0UL) +#define NT_BUILD_NUMBER (0x489b50fbUL) +#define NT_BUILD_TIME (0x6e66771fUL) +#define NT_CATEGORIES (0xfdbcebdcUL) +#define NT_CAT_CCT_SIZE (0x3a505ddaUL) +#define NT_CAT_CTE_SIZE (0x50a32ea4UL) +#define NT_CAT_CTS_SIZE (0x852ccf22UL) +#define NT_CAT_DCT_PRESENT (0x898c5638UL) +#define NT_CAT_DCT_SIZE (0x309554c3UL) +#define NT_CAT_END_OFS_SUPPORT (0x925f11d9UL) +#define NT_CAT_FPC (0x417fd17bUL) +#define NT_CAT_FTE_SIZE (0x184320c0UL) +#define NT_CAT_FUNCS (0x6af66e16UL) +#define NT_CAT_KCC_BANKS (0x426534f3UL) +#define NT_CAT_KCC_PRESENT (0xd2d58d46UL) +#define NT_CAT_KCC_SIZE (0xf766744cUL) +#define NT_CAT_KCE_SIZE (0x213f9751UL) +#define NT_CAT_KM_IF_CNT (0x8c934524UL) +#define NT_CAT_KM_IF_M0 (0x666dd699UL) +#define NT_CAT_KM_IF_M1 (0x116ae60fUL) +#define NT_CAT_N_CMP (0x3a692ad4UL) +#define NT_CAT_N_EXT (0xe3c746bUL) +#define NT_CAT_N_LEN (0x3e3da82UL) +#define NT_CAT_RCK_SIZE (0x78c1dc21UL) +#define NT_CAT_VALUES (0xec523dbbUL) +#define NT_CB_DEBUG (0xa0bccd31UL) +#define NT_COR_CATEGORIES (0x7392b58dUL) +#define NT_COR_PRESENT (0xbe0d1fdeUL) +#define NT_CPY_MASK_MEM (0x24f85e48UL) +#define NT_CSU_PRESENT (0xe7fe1371UL) +#define NT_DBS_PRESENT (0x75b395aeUL) +#define NT_DBS_RX_QUEUES (0x927069fUL) +#define NT_DBS_TX_PORTS (0xae2d6250UL) +#define NT_DBS_TX_QUEUES (0x7a3d7f15UL) +#define NT_DDP_PRESENT (0x4120d92cUL) +#define NT_DDP_TBL_DEPTH (0xf52e011UL) +#define NT_EMI_SPLIT_STEPS (0xe4b3210fUL) +#define NT_EOF_TIMESTAMP_ONLY (0xe476891bUL) +#define NT_EPP_CATEGORIES (0xf41c134bUL) +#define NT_EXT_MEM_NUM (0x43a48169UL) +#define NT_EXT_MEM_SINGLE_SIZE_GB (0x1817e71eUL) +#define NT_FLM_CACHE (0x414157e4UL) +#define NT_FLM_CATEGORIES (0x3477c5a3UL) +#define NT_FLM_ENTRY_SIZE (0x9ca7f0b6UL) +#define NT_FLM_LOAD_APS_MAX (0xe4d4f4edUL) +#define NT_FLM_LOAD_LPS_MAX (0x8503952dUL) +#define NT_FLM_PRESENT (0x5714853fUL) +#define NT_FLM_PRIOS (0x92afe487UL) +#define NT_FLM_PST_PROFILES (0xf4a0d627UL) +#define NT_FLM_SCRUB_PROFILES (0x6b6f6b21UL) +#define NT_FLM_SIZE_MB (0x5667a5deUL) +#define NT_FLM_STATEFUL (0xc8bf17a8UL) +#define NT_FLM_VARIANT (0x5beb9485UL) +#define NT_GFG_PRESENT (0x149640a8UL) +#define NT_GFG_TX_LIVE_RECONFIG_SUPPORT (0x7b5ad1e0UL) +#define NT_GMF_FCS_PRESENT (0xc15365efUL) +#define NT_GMF_IFG_SPEED_DIV (0xc06cdcbdUL) +#define NT_GMF_IFG_SPEED_DIV100G (0x43e1fb80UL) +#define NT_GMF_IFG_SPEED_DIV100M (0xa334129eUL) +#define NT_GMF_IFG_SPEED_DIV10G (0x49197e96UL) +#define NT_GMF_IFG_SPEED_DIV1G (0xb1324f18UL) +#define NT_GMF_IFG_SPEED_DIV2 (0xafc51de0UL) +#define NT_GMF_IFG_SPEED_DIV25G (0x3628348aUL) +#define NT_GMF_IFG_SPEED_DIV3 (0xd8c22d76UL) +#define NT_GMF_IFG_SPEED_DIV4 (0x46a6b8d5UL) +#define NT_GMF_IFG_SPEED_DIV40G (0x4fd2bc7dUL) +#define NT_GMF_IFG_SPEED_DIV50G (0x4e10d64aUL) +#define NT_GMF_IFG_SPEED_MUL (0xd4a84315UL) +#define NT_GMF_IFG_SPEED_MUL100G (0x883df390UL) +#define NT_GMF_IFG_SPEED_MUL100M (0x68e81a8eUL) +#define NT_GMF_IFG_SPEED_MUL10G (0xf4a2e226UL) +#define NT_GMF_IFG_SPEED_MUL1G (0xb75ce3e8UL) +#define NT_GMF_IFG_SPEED_MUL2 (0x77dcf2a5UL) +#define NT_GMF_IFG_SPEED_MUL25G (0x8b93a83aUL) +#define NT_GMF_IFG_SPEED_MUL3 (0xdbc233UL) +#define NT_GMF_IFG_SPEED_MUL4 (0x9ebf5790UL) +#define NT_GMF_IFG_SPEED_MUL40G (0xf26920cdUL) +#define NT_GMF_IFG_SPEED_MUL50G (0xf3ab4afaUL) +#define NT_GROUP_ID (0x113978c5UL) +#define NT_HFU_PRESENT (0x558de99UL) +#define NT_HIF_MSIX_BAR (0xc10014e9UL) +#define NT_HIF_MSIX_PBA_OFS (0x900307fbUL) +#define NT_HIF_MSIX_PRESENT (0x77a98665UL) +#define NT_HIF_MSIX_TBL_OFS (0x9cdce759UL) +#define NT_HIF_MSIX_TBL_SIZE (0x6ce7b76UL) +#define NT_HIF_PER_PS (0x38c954b1UL) +#define NT_HIF_SRIOV_PRESENT (0x49f8c203UL) +#define NT_HIF_VF_OFFSET (0x9fb3c9b0UL) +#define NT_HSH_CATEGORIES (0xf43894dcUL) +#define NT_HSH_TOEPLITZ (0x603f96a3UL) +#define NT_HST_CATEGORIES (0xfd2a34a1UL) +#define NT_HST_PRESENT (0xd3a48076UL) +#define NT_IOA_CATEGORIES (0xda23501aUL) +#define NT_IOA_PRESENT (0xc9ef39eeUL) +#define NT_IPF_PRESENT (0x7b2b8e42UL) +#define NT_KM_CAM_BANKS (0x3cad3371UL) +#define NT_KM_CAM_RECORDS (0x24256ab5UL) +#define NT_KM_CAM_REC_WORDS (0xe8e0ef3UL) +#define NT_KM_CATEGORIES (0x4d2a4c96UL) +#define NT_KM_END_OFS_SUPPORT (0x4a90ff33UL) +#define NT_KM_EXT_EXTRACTORS (0xf135193cUL) +#define NT_KM_FLOW_SETS (0x359cddf3UL) +#define NT_KM_FLOW_TYPES (0xb79ff984UL) +#define NT_KM_PRESENT (0xb54eaee3UL) +#define NT_KM_SWX_PRESENT (0x2715aebeUL) +#define NT_KM_SYNERGY_MATCH (0x935e5b7fUL) +#define NT_KM_TCAM_BANKS (0x6f6f0894UL) +#define NT_KM_TCAM_BANK_WIDTH (0x4c5015aeUL) +#define NT_KM_TCAM_HIT_QUAL (0xd3fb2aafUL) +#define NT_KM_TCAM_KEYWAY (0x45318c61UL) +#define NT_KM_WIDE (0x7ba773c4UL) +#define NT_LR_PRESENT (0x24eb383aUL) +#define NT_LTX_CATEGORIES (0x9cfff063UL) +#define NT_MCU_DRAM_SIZE (0xe33d7922UL) +#define NT_MCU_PRESENT (0x9226b99fUL) +#define NT_MCU_TYPE (0xce45b840UL) +#define NT_MDG_DEBUG_FLOW_CONTROL (0x4f199a18UL) +#define NT_MDG_DEBUG_REG_READ_BACK (0xc674095UL) +#define NT_MSK_CATEGORIES (0x7052841UL) +#define NT_MSK_PRESENT (0xd18aa194UL) +#define NT_NAME (0x224bb693UL) +#define NT_NFV_OVS_PRODUCT (0xd8223124UL) +#define NT_NIMS (0xd88c527aUL) +#define NT_PATCH_NUMBER (0xecd14417UL) +#define NT_PCI_DEVICE_ID (0x254dede8UL) +#define NT_PCI_INT_AVR (0x40c50ef1UL) +#define NT_PCI_INT_EQM (0x85853d1fUL) +#define NT_PCI_INT_IIC0 (0xbf363717UL) +#define NT_PCI_INT_IIC1 (0xc8310781UL) +#define NT_PCI_INT_IIC2 (0x5138563bUL) +#define NT_PCI_INT_IIC3 (0x263f66adUL) +#define NT_PCI_INT_IIC4 (0xb85bf30eUL) +#define NT_PCI_INT_IIC5 (0xcf5cc398UL) +#define NT_PCI_INT_PORT (0x8facd5e1UL) +#define NT_PCI_INT_PORT0 (0x2359a11aUL) +#define NT_PCI_INT_PORT1 (0x545e918cUL) +#define NT_PCI_INT_PPS (0x7c7c50a6UL) +#define NT_PCI_INT_QSPI (0x731ce6cbUL) +#define NT_PCI_INT_SPIM (0x473efd18UL) +#define NT_PCI_INT_SPIS (0xbd31c07bUL) +#define NT_PCI_INT_STA (0xe9ef5ab3UL) +#define NT_PCI_INT_TIMER (0x14ad9f2fUL) +#define NT_PCI_INT_TINT (0xe2346359UL) +#define NT_PCI_TA_TG_PRESENT (0x3cc176a0UL) +#define NT_PCI_VENDOR_ID (0x47eac44fUL) +#define NT_PDB_CATEGORIES (0x8290fe65UL) +#define NT_PHY_ANEG_PRESENT (0x626ddda5UL) +#define NT_PHY_KRFEC_PRESENT (0x8ab2cf25UL) +#define NT_PHY_PORTS (0x41986112UL) +#define NT_PHY_PORTS_PER_QUAD (0xf4b396e6UL) +#define NT_PHY_QUADS (0x17fef021UL) +#define NT_PHY_RSFEC_PRESENT (0x22852f78UL) +#define NT_PORTS (0x32e8ff06UL) +#define NT_PROD_ID_LAYOUT_VERSION (0x42106495UL) +#define NT_QM_BLOCKS (0xb735e210UL) +#define NT_QM_CELLS (0x510e07f1UL) +#define NT_QM_CELL_SIZE (0xbddf0f74UL) +#define NT_QM_PRESENT (0x85c2bfc2UL) +#define NT_QSL_CATEGORIES (0x3fda6c8fUL) +#define NT_QSL_COLOR_SEL_BW (0x549c264dUL) +#define NT_QSL_QST_SIZE (0x41d03837UL) +#define NT_QUEUES (0xf8a94e49UL) +#define NT_RAC_RAB_INTERFACES (0x7b742b2bUL) +#define NT_RAC_RAB_OB_UPDATE (0x3a44d066UL) +#define NT_REVISION_ID (0xd212229fUL) +#define NT_RMC_LAG_GROUPS (0xa7d5b2fbUL) +#define NT_RMC_PRESENT (0x6e3b82daUL) +#define NT_ROA_CATEGORIES (0xf3a9579bUL) +#define NT_ROA_PRESENT (0x44387a61UL) +#define NT_RPF_MATURING_DEL_DEFAULT (0xd4e7e4d2UL) +#define NT_RPF_PRESENT (0xf6fccdcdUL) +#define NT_RPP_PER_PS (0xb2f28916UL) +#define NT_RTX_PRESENT (0x9b15f454UL) +#define NT_RX_HOST_BUFFERS (0x9207c413UL) +#define NT_RX_PORTS (0x3639a86eUL) +#define NT_RX_PORT_REPLICATE (0xed09d794UL) +#define NT_SLB_PRESENT (0x570c2267UL) +#define NT_SLC_LR_PRESENT (0xe600975aUL) +#define NT_SLC_PRESENT (0x40773624UL) +#define NT_STA_COLORS (0xe1e90b5bUL) +#define NT_STA_LOAD_AVG_RX (0x94efbfa1UL) +#define NT_STA_LOAD_AVG_TX (0xc2b51827UL) +#define NT_STA_RX_PORTS (0x75da30f9UL) +#define NT_TBH_DEBUG_DLN (0x1faf2e1dUL) +#define NT_TBH_PRESENT (0xf5d08dc9UL) +#define NT_TFD_PRESENT (0x1a0fdea7UL) +#define NT_TPE_CATEGORIES (0x9b1a54bdUL) +#define NT_TSM_OST_ONLY (0x4899103aUL) +#define NT_TS_APPEND (0x4544c692UL) +#define NT_TS_INJECT_PRESENT (0xb2aa4f0eUL) +#define NT_TX_CPY_PACKET_READERS (0x37f470f0UL) +#define NT_TX_CPY_PRESENT (0xe54af81cUL) +#define NT_TX_CPY_SIDEBAND_READERS (0x52220d68UL) +#define NT_TX_CPY_VARIANT (0xe9b5e9a6UL) +#define NT_TX_CPY_WRITERS (0xd9dbd4UL) +#define NT_TX_HOST_BUFFERS (0xb0fd10e1UL) +#define NT_TX_INS_OFS_ZERO (0x5510aa2dUL) +#define NT_TX_INS_PRESENT (0xabac9b5dUL) +#define NT_TX_MTU_PROFILE_IFR (0x8d313bc2UL) +#define NT_TX_ON_TIMESTAMP (0x51d7fce0UL) +#define NT_TX_PORTS (0xf056a1e9UL) +#define NT_TX_PORT_REPLICATE (0x4a3d609cUL) +#define NT_TX_RPL_DEPTH (0x61f86eb9UL) +#define NT_TX_RPL_EXT_CATEGORIES (0x421e973cUL) +#define NT_TX_RPL_OFS_ZERO (0x2bfd677UL) +#define NT_TX_RPL_PRESENT (0x6c65e429UL) +#define NT_TYPE_ID (0xd03446b2UL) +#define NT_USE_TRIPLE_SPEED (0x54350589UL) +#define NT_UUID (0xad179833UL) +#define NT_VERSION (0x92295f02UL) +#define NT_VERSION_ID (0xb4becc51UL) +#define NT_VLI_PRESENT (0xa40e10f8UL) + +#endif /* _NTHW_FPGA_PARAM_DEFS_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h new file mode 100644 index 0000000000..aeb564349e --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs.h @@ -0,0 +1,27 @@ +/* + * nthw_fpga_reg_defs.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_ +#define _NTHW_FPGA_REG_DEFS_ + +#include "nthw_fpga_reg_defs_gfg.h" +#include "nthw_fpga_reg_defs_gmf.h" +#include "nthw_fpga_reg_defs_gpio_phy.h" +#include "nthw_fpga_reg_defs_hif.h" +#include "nthw_fpga_reg_defs_i2cm.h" +#include "nthw_fpga_reg_defs_iic.h" +#include "nthw_fpga_reg_defs_mac_pcs.h" +#include "nthw_fpga_reg_defs_pcie3.h" +#include "nthw_fpga_reg_defs_pci_rd_tg.h" +#include "nthw_fpga_reg_defs_pci_wr_tg.h" +#include "nthw_fpga_reg_defs_rac.h" +#include "nthw_fpga_reg_defs_rst9563.h" +#include "nthw_fpga_reg_defs_sdc.h" + +/* aliases */ + +#endif /* NTHW_FPGA_REG_DEFS_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h new file mode 100644 index 0000000000..6ed9758247 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gfg.h @@ -0,0 +1,118 @@ +/* + * nthw_fpga_reg_defs_gfg.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_GFG_ +#define _NTHW_FPGA_REG_DEFS_GFG_ + +/* GFG */ +#define NTHW_MOD_GFG (0xfc423807UL) +#define GFG_BURSTSIZE0 (0xd62af404UL) +#define GFG_BURSTSIZE0_VAL (0xa2e4d17eUL) +#define GFG_BURSTSIZE1 (0xa12dc492UL) +#define GFG_BURSTSIZE1_VAL (0x9f84f8ceUL) +#define GFG_BURSTSIZE2 (0x38249528UL) +#define GFG_BURSTSIZE2_VAL (0xd824821eUL) +#define GFG_BURSTSIZE3 (0x4f23a5beUL) +#define GFG_BURSTSIZE3_VAL (0xe544abaeUL) +#define GFG_BURSTSIZE4 (0xd147301dUL) +#define GFG_BURSTSIZE4_VAL (0x576477beUL) +#define GFG_BURSTSIZE5 (0xa640008bUL) +#define GFG_BURSTSIZE5_VAL (0x6a045e0eUL) +#define GFG_BURSTSIZE6 (0x3f495131UL) +#define GFG_BURSTSIZE6_VAL (0x2da424deUL) +#define GFG_BURSTSIZE7 (0x484e61a7UL) +#define GFG_BURSTSIZE7_VAL (0x10c40d6eUL) +#define GFG_CTRL0 (0xc3e26c0fUL) +#define GFG_CTRL0_ENABLE (0xfe65937UL) +#define GFG_CTRL0_MODE (0x81d94c52UL) +#define GFG_CTRL0_PRBS_EN (0xb43e6c6UL) +#define GFG_CTRL0_SIZE (0xe1d32f93UL) +#define GFG_CTRL1 (0xb4e55c99UL) +#define GFG_CTRL1_ENABLE (0xc34c59a9UL) +#define GFG_CTRL1_MODE (0x4a859ff7UL) +#define GFG_CTRL1_PRBS_EN (0x1c38f285UL) +#define GFG_CTRL1_SIZE (0x2a8ffc36UL) +#define GFG_CTRL2 (0x2dec0d23UL) +#define GFG_CTRL2_ENABLE (0x4dc35e4aUL) +#define GFG_CTRL2_MODE (0xcc11ed59UL) +#define GFG_CTRL2_PRBS_EN (0x25b5ce40UL) +#define GFG_CTRL2_SIZE (0xac1b8e98UL) +#define GFG_CTRL3 (0x5aeb3db5UL) +#define GFG_CTRL3_ENABLE (0x81695ed4UL) +#define GFG_CTRL3_MODE (0x74d3efcUL) +#define GFG_CTRL3_PRBS_EN (0x32ceda03UL) +#define GFG_CTRL3_SIZE (0x67475d3dUL) +#define GFG_CTRL4 (0xc48fa816UL) +#define GFG_CTRL4_ENABLE (0x8bac57cdUL) +#define GFG_CTRL4_MODE (0x1a480e44UL) +#define GFG_CTRL4_PRBS_EN (0x56afb7caUL) +#define GFG_CTRL4_SIZE (0x7a426d85UL) +#define GFG_CTRL5 (0xb3889880UL) +#define GFG_CTRL5_ENABLE (0x47065753UL) +#define GFG_CTRL5_MODE (0xd114dde1UL) +#define GFG_CTRL5_PRBS_EN (0x41d4a389UL) +#define GFG_CTRL5_SIZE (0xb11ebe20UL) +#define GFG_CTRL6 (0x2a81c93aUL) +#define GFG_CTRL6_ENABLE (0xc98950b0UL) +#define GFG_CTRL6_MODE (0x5780af4fUL) +#define GFG_CTRL6_PRBS_EN (0x78599f4cUL) +#define GFG_CTRL6_SIZE (0x378acc8eUL) +#define GFG_CTRL7 (0x5d86f9acUL) +#define GFG_CTRL7_ENABLE (0x523502eUL) +#define GFG_CTRL7_MODE (0x9cdc7ceaUL) +#define GFG_CTRL7_PRBS_EN (0x6f228b0fUL) +#define GFG_CTRL7_SIZE (0xfcd61f2bUL) +#define GFG_RUN0 (0xb72be46cUL) +#define GFG_RUN0_RUN (0xa457d3c8UL) +#define GFG_RUN1 (0xc02cd4faUL) +#define GFG_RUN1_RUN (0x9937fa78UL) +#define GFG_RUN2 (0x59258540UL) +#define GFG_RUN2_RUN (0xde9780a8UL) +#define GFG_RUN3 (0x2e22b5d6UL) +#define GFG_RUN3_RUN (0xe3f7a918UL) +#define GFG_RUN4 (0xb0462075UL) +#define GFG_RUN4_RUN (0x51d77508UL) +#define GFG_RUN5 (0xc74110e3UL) +#define GFG_RUN5_RUN (0x6cb75cb8UL) +#define GFG_RUN6 (0x5e484159UL) +#define GFG_RUN6_RUN (0x2b172668UL) +#define GFG_RUN7 (0x294f71cfUL) +#define GFG_RUN7_RUN (0x16770fd8UL) +#define GFG_SIZEMASK0 (0x7015abe3UL) +#define GFG_SIZEMASK0_VAL (0xe9c7ed93UL) +#define GFG_SIZEMASK1 (0x7129b75UL) +#define GFG_SIZEMASK1_VAL (0xd4a7c423UL) +#define GFG_SIZEMASK2 (0x9e1bcacfUL) +#define GFG_SIZEMASK2_VAL (0x9307bef3UL) +#define GFG_SIZEMASK3 (0xe91cfa59UL) +#define GFG_SIZEMASK3_VAL (0xae679743UL) +#define GFG_SIZEMASK4 (0x77786ffaUL) +#define GFG_SIZEMASK4_VAL (0x1c474b53UL) +#define GFG_SIZEMASK5 (0x7f5f6cUL) +#define GFG_SIZEMASK5_VAL (0x212762e3UL) +#define GFG_SIZEMASK6 (0x99760ed6UL) +#define GFG_SIZEMASK6_VAL (0x66871833UL) +#define GFG_SIZEMASK7 (0xee713e40UL) +#define GFG_SIZEMASK7_VAL (0x5be73183UL) +#define GFG_STREAMID0 (0xbd4ba9aeUL) +#define GFG_STREAMID0_VAL (0x42d077caUL) +#define GFG_STREAMID1 (0xca4c9938UL) +#define GFG_STREAMID1_VAL (0x7fb05e7aUL) +#define GFG_STREAMID2 (0x5345c882UL) +#define GFG_STREAMID2_VAL (0x381024aaUL) +#define GFG_STREAMID3 (0x2442f814UL) +#define GFG_STREAMID3_VAL (0x5700d1aUL) +#define GFG_STREAMID4 (0xba266db7UL) +#define GFG_STREAMID4_VAL (0xb750d10aUL) +#define GFG_STREAMID5 (0xcd215d21UL) +#define GFG_STREAMID5_VAL (0x8a30f8baUL) +#define GFG_STREAMID6 (0x54280c9bUL) +#define GFG_STREAMID6_VAL (0xcd90826aUL) +#define GFG_STREAMID7 (0x232f3c0dUL) +#define GFG_STREAMID7_VAL (0xf0f0abdaUL) + +#endif /* _NTHW_FPGA_REG_DEFS_GFG_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h new file mode 100644 index 0000000000..98b85ee674 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gmf.h @@ -0,0 +1,60 @@ +/* + * nthw_fpga_reg_defs_gmf.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_GMF_ +#define _NTHW_FPGA_REG_DEFS_GMF_ + +/* GMF */ +#define NTHW_MOD_GMF (0x68b1d15aUL) +#define GMF_CTRL (0x28d359b4UL) +#define GMF_CTRL_ENABLE (0xe41c837cUL) +#define GMF_CTRL_FCS_ALWAYS (0x8f36cec1UL) +#define GMF_CTRL_IFG_AUTO_ADJUST_ENABLE (0x5b5669b0UL) +#define GMF_CTRL_IFG_ENABLE (0x995f1bfbUL) +#define GMF_CTRL_IFG_TX_NOW_ALWAYS (0xb11744c2UL) +#define GMF_CTRL_IFG_TX_NOW_ON_TS_ENABLE (0xe9e4ee2aUL) +#define GMF_CTRL_IFG_TX_ON_TS_ADJUST_ON_SET_CLOCK (0x32dc6426UL) +#define GMF_CTRL_IFG_TX_ON_TS_ALWAYS (0x21dcad67UL) +#define GMF_CTRL_TS_INJECT_ALWAYS (0x353fa4aaUL) +#define GMF_CTRL_TS_INJECT_DUAL_STEP (0xc4c0195cUL) +#define GMF_DEBUG_LANE_MARKER (0xa51eb8a9UL) +#define GMF_DEBUG_LANE_MARKER_COMPENSATION (0x4f44f92aUL) +#define GMF_IFG_MAX_ADJUST_SLACK (0xe49f3408UL) +#define GMF_IFG_MAX_ADJUST_SLACK_SLACK (0x9a2de1f7UL) +#define GMF_IFG_SET_CLOCK_DELTA (0x8a614d6fUL) +#define GMF_IFG_SET_CLOCK_DELTA_DELTA (0x1da821d6UL) +#define GMF_IFG_SET_CLOCK_DELTA_ADJUST (0xaa468304UL) +#define GMF_IFG_SET_CLOCK_DELTA_ADJUST_DELTA (0x2c165992UL) +#define GMF_IFG_TX_NOW_ON_TS (0xd32fab5eUL) +#define GMF_IFG_TX_NOW_ON_TS_TS (0x612771f4UL) +#define GMF_SPEED (0x48bec0a1UL) +#define GMF_SPEED_IFG_SPEED (0x273c8281UL) +#define GMF_STAT (0xa49d7efUL) +#define GMF_STAT_CTRL_EMPTY (0x3f6e8adcUL) +#define GMF_STAT_DATA_CTRL_EMPTY (0xc18fc6e9UL) +#define GMF_STAT_SB_EMPTY (0x99314d52UL) +#define GMF_STAT_CTRL (0xfd31633eUL) +#define GMF_STAT_CTRL_FILL_LEVEL (0xe8cd56d6UL) +#define GMF_STAT_DATA0 (0x51838aabUL) +#define GMF_STAT_DATA0_EMPTY (0xcfcad9c0UL) +#define GMF_STAT_DATA1 (0x2684ba3dUL) +#define GMF_STAT_DATA1_EMPTY (0x69bdd274UL) +#define GMF_STAT_DATA_BUFFER (0xa6431f34UL) +#define GMF_STAT_DATA_BUFFER_FREE (0x3476e461UL) +#define GMF_STAT_DATA_BUFFER_USED (0x1f46b1UL) +#define GMF_STAT_MAX_DELAYED_PKT (0x3fb5c76dUL) +#define GMF_STAT_MAX_DELAYED_PKT_NS (0x2eb58efbUL) +#define GMF_STAT_NEXT_PKT (0x558ee30dUL) +#define GMF_STAT_NEXT_PKT_NS (0x26814d33UL) +#define GMF_STAT_STICKY (0x5a0f2ef7UL) +#define GMF_STAT_STICKY_DATA_UNDERFLOWED (0x9a3dfcb6UL) +#define GMF_STAT_STICKY_IFG_ADJUSTED (0xea849a5fUL) +#define GMF_TS_INJECT (0x66e57281UL) +#define GMF_TS_INJECT_OFFSET (0x8c2c9cb6UL) +#define GMF_TS_INJECT_POS (0xdded481UL) + +#endif /* _NTHW_FPGA_REG_DEFS_GMF_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h new file mode 100644 index 0000000000..8d160af298 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_gpio_phy.h @@ -0,0 +1,40 @@ +/* + * nthw_fpga_reg_defs_gpio_phy.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_GPIO_PHY_ +#define _NTHW_FPGA_REG_DEFS_GPIO_PHY_ + +/* GPIO_PHY */ +#define NTHW_MOD_GPIO_PHY (0xbbe81659UL) +#define GPIO_PHY_CFG (0x39548432UL) +#define GPIO_PHY_CFG_E_PORT0_RXLOS (0x2dfe5bUL) +#define GPIO_PHY_CFG_E_PORT1_RXLOS (0xa65af5efUL) +#define GPIO_PHY_CFG_PORT0_INT_B (0xa882887cUL) +#define GPIO_PHY_CFG_PORT0_LPMODE (0x65df41beUL) +#define GPIO_PHY_CFG_PORT0_MODPRS_B (0x6aef8e94UL) +#define GPIO_PHY_CFG_PORT0_PLL_INTR (0xbf1f8c5dUL) +#define GPIO_PHY_CFG_PORT0_RESET_B (0x1ef06a6cUL) +#define GPIO_PHY_CFG_PORT1_INT_B (0xef583c8UL) +#define GPIO_PHY_CFG_PORT1_LPMODE (0xa9754120UL) +#define GPIO_PHY_CFG_PORT1_MODPRS_B (0x852de5aaUL) +#define GPIO_PHY_CFG_PORT1_PLL_INTR (0x50dde763UL) +#define GPIO_PHY_CFG_PORT1_RESET_B (0x98b7e2fUL) +#define GPIO_PHY_GPIO (0xf5c5d393UL) +#define GPIO_PHY_GPIO_E_PORT0_RXLOS (0xfb05c9faUL) +#define GPIO_PHY_GPIO_E_PORT1_RXLOS (0x5d72c24eUL) +#define GPIO_PHY_GPIO_PORT0_INT_B (0x6aceab27UL) +#define GPIO_PHY_GPIO_PORT0_LPMODE (0x99a485e1UL) +#define GPIO_PHY_GPIO_PORT0_MODPRS_B (0xcbc535ddUL) +#define GPIO_PHY_GPIO_PORT0_PLL_INTR (0x1e353714UL) +#define GPIO_PHY_GPIO_PORT0_RESET_B (0xe5d85dcdUL) +#define GPIO_PHY_GPIO_PORT1_INT_B (0xccb9a093UL) +#define GPIO_PHY_GPIO_PORT1_LPMODE (0x550e857fUL) +#define GPIO_PHY_GPIO_PORT1_MODPRS_B (0x24075ee3UL) +#define GPIO_PHY_GPIO_PORT1_PLL_INTR (0xf1f75c2aUL) +#define GPIO_PHY_GPIO_PORT1_RESET_B (0xf2a3498eUL) + +#endif /* _NTHW_FPGA_REG_DEFS_GPIO_PHY_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h new file mode 100644 index 0000000000..ebd1b2eef8 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_hif.h @@ -0,0 +1,71 @@ +/* + * nthw_fpga_reg_defs_hif.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_HIF_ +#define _NTHW_FPGA_REG_DEFS_HIF_ + +/* HIF */ +#define NTHW_MOD_HIF (0x7815363UL) +#define HIF_BUILD_TIME (0x1eaf6ab8UL) +#define HIF_BUILD_TIME_TIME (0xb2dfbda5UL) +#define HIF_CONFIG (0xb64b595cUL) +#define HIF_CONFIG_EXT_TAG (0x57e685bUL) +#define HIF_CONFIG_MAX_READ (0x7d56ce45UL) +#define HIF_CONFIG_MAX_TLP (0xe1c563e4UL) +#define HIF_CONTROL (0xedb9ed3dUL) +#define HIF_CONTROL_BLESSED (0x680018b7UL) +#define HIF_CONTROL_FSR (0x498a2097UL) +#define HIF_CONTROL_WRAW (0xc1a7bc42UL) +#define HIF_PROD_ID_EX (0xc9c9efb2UL) +#define HIF_PROD_ID_EX_LAYOUT (0xc6564c80UL) +#define HIF_PROD_ID_EX_LAYOUT_VERSION (0x9803a0e2UL) +#define HIF_PROD_ID_EX_RESERVED (0x1189af8aUL) +#define HIF_PROD_ID_EXT (0x9ba2612fUL) +#define HIF_PROD_ID_EXT_LAYOUT (0xe315afa1UL) +#define HIF_PROD_ID_EXT_LAYOUT_VERSION (0x1f7aa616UL) +#define HIF_PROD_ID_EXT_RESERVED (0xa4152ce8UL) +#define HIF_PROD_ID_LSB (0x8353363aUL) +#define HIF_PROD_ID_LSB_GROUP_ID (0xbb9614f7UL) +#define HIF_PROD_ID_LSB_REV_ID (0x5458192eUL) +#define HIF_PROD_ID_LSB_VER_ID (0x40abcc6fUL) +#define HIF_PROD_ID_MSB (0x82915c0dUL) +#define HIF_PROD_ID_MSB_BUILD_NO (0x1135f11bUL) +#define HIF_PROD_ID_MSB_PATCH_NO (0xcbf446bcUL) +#define HIF_PROD_ID_MSB_TYPE_ID (0xb49af41cUL) +#define HIF_SAMPLE_TIME (0xad0472aaUL) +#define HIF_SAMPLE_TIME_SAMPLE_TIME (0x56bd0a0bUL) +#define HIF_STATUS (0x19c1133cUL) +#define HIF_STATUS_RD_ERR (0x15e9f376UL) +#define HIF_STATUS_TAGS_IN_USE (0x9789b255UL) +#define HIF_STATUS_WR_ERR (0xaa8400e7UL) +#define HIF_STAT_CTRL (0xd9478d74UL) +#define HIF_STAT_CTRL_STAT_ENA (0xf26c834cUL) +#define HIF_STAT_CTRL_STAT_REQ (0x1546ff16UL) +#define HIF_STAT_REFCLK (0x656cf83fUL) +#define HIF_STAT_REFCLK_REFCLK250 (0xb9dd01fcUL) +#define HIF_STAT_RX (0x8c483f48UL) +#define HIF_STAT_RX_COUNTER (0xd99bc360UL) +#define HIF_STAT_TX (0xda1298ceUL) +#define HIF_STAT_TX_COUNTER (0xd485b327UL) +#define HIF_TEST0 (0xdab033c0UL) +#define HIF_TEST0_DATA (0xb7f3cba2UL) +#define HIF_TEST1 (0xadb70356UL) +#define HIF_TEST1_DATA (0x7caf1807UL) +#define HIF_TEST2 (0x34be52ecUL) +#define HIF_TEST2_DATA (0xfa3b6aa9UL) +#define HIF_TEST3 (0x43b9627aUL) +#define HIF_TEST3_DATA (0x3167b90cUL) +#define HIF_UUID0 (0xecba7918UL) +#define HIF_UUID0_UUID0 (0x84b3f35eUL) +#define HIF_UUID1 (0x9bbd498eUL) +#define HIF_UUID1_UUID1 (0x55c3c87cUL) +#define HIF_UUID2 (0x2b41834UL) +#define HIF_UUID2_UUID2 (0xfd22835bUL) +#define HIF_UUID3 (0x75b328a2UL) +#define HIF_UUID3_UUID3 (0x2c52b879UL) + +#endif /* _NTHW_FPGA_REG_DEFS_HIF_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h new file mode 100644 index 0000000000..4ef618e2e1 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_i2cm.h @@ -0,0 +1,30 @@ +/* + * nthw_fpga_reg_defs_i2cm.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_I2CM_ +#define _NTHW_FPGA_REG_DEFS_I2CM_ + +/* I2CM */ +#define NTHW_MOD_I2CM (0x93bc7780UL) +#define I2CM_CMD_STATUS (0xcb66305bUL) +#define I2CM_CMD_STATUS_CMD_STATUS (0x9c9460a9UL) +#define I2CM_CTRL (0x7c06d3b0UL) +#define I2CM_CTRL_EN (0x57d0a8aaUL) +#define I2CM_CTRL_IEN (0x9fdc39ebUL) +#define I2CM_DATA (0xd3d751a9UL) +#define I2CM_DATA_DATA (0x2ea487faUL) +#define I2CM_IO_EXP (0xe8dfa320UL) +#define I2CM_IO_EXP_INT_B (0x85e5ff3fUL) +#define I2CM_IO_EXP_RST (0x207c9928UL) +#define I2CM_PRER_HIGH (0xf1139b49UL) +#define I2CM_PRER_HIGH_PRER_HIGH (0xc6ff6431UL) +#define I2CM_PRER_LOW (0x84f76481UL) +#define I2CM_PRER_LOW_PRER_LOW (0x396755aaUL) +#define I2CM_SELECT (0xecd56d8eUL) +#define I2CM_SELECT_SELECT (0xb9d992d8UL) + +#endif /* _NTHW_FPGA_REG_DEFS_I2CM_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h new file mode 100644 index 0000000000..7744dc14c6 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_iic.h @@ -0,0 +1,88 @@ +/* + * nthw_fpga_reg_defs_iic.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_IIC_ +#define _NTHW_FPGA_REG_DEFS_IIC_ + +/* IIC */ +#define NTHW_MOD_IIC (0x7629cddbUL) +#define IIC_ADR (0x94832a56UL) +#define IIC_ADR_SLV_ADR (0xe34a95b4UL) +#define IIC_CR (0x2e99752eUL) +#define IIC_CR_EN (0x38b0a8b8UL) +#define IIC_CR_GC_EN (0x6a93c608UL) +#define IIC_CR_MSMS (0xd3370cefUL) +#define IIC_CR_RST (0x9d83289fUL) +#define IIC_CR_RSTA (0xb3f49376UL) +#define IIC_CR_TX (0x9fbd3ef9UL) +#define IIC_CR_TXAK (0x4daa2c41UL) +#define IIC_CR_TXFIFO_RESET (0x9d442d45UL) +#define IIC_DGIE (0xca86a888UL) +#define IIC_DGIE_GIE (0xda9f5b68UL) +#define IIC_GPO (0xdda6ed68UL) +#define IIC_GPO_GPO_VAL (0x6c51285eUL) +#define IIC_IER (0x838b4aafUL) +#define IIC_IER_INT0 (0x27d5f60eUL) +#define IIC_IER_INT1 (0x50d2c698UL) +#define IIC_IER_INT2 (0xc9db9722UL) +#define IIC_IER_INT3 (0xbedca7b4UL) +#define IIC_IER_INT4 (0x20b83217UL) +#define IIC_IER_INT5 (0x57bf0281UL) +#define IIC_IER_INT6 (0xceb6533bUL) +#define IIC_IER_INT7 (0xb9b163adUL) +#define IIC_ISR (0x9f13ff78UL) +#define IIC_ISR_INT0 (0x23db5ffaUL) +#define IIC_ISR_INT1 (0x54dc6f6cUL) +#define IIC_ISR_INT2 (0xcdd53ed6UL) +#define IIC_ISR_INT3 (0xbad20e40UL) +#define IIC_ISR_INT4 (0x24b69be3UL) +#define IIC_ISR_INT5 (0x53b1ab75UL) +#define IIC_ISR_INT6 (0xcab8facfUL) +#define IIC_ISR_INT7 (0xbdbfca59UL) +#define IIC_RX_FIFO (0x46f255afUL) +#define IIC_RX_FIFO_RXDATA (0x90c24f9dUL) +#define IIC_RX_FIFO_OCY (0xc6457d11UL) +#define IIC_RX_FIFO_OCY_OCY_VAL (0xee6b4716UL) +#define IIC_RX_FIFO_PIRQ (0x4201f0b4UL) +#define IIC_RX_FIFO_PIRQ_CMP_VAL (0xc5121291UL) +#define IIC_SOFTR (0xfb3f55bfUL) +#define IIC_SOFTR_RKEY (0x8c9a6beeUL) +#define IIC_SR (0x645b677fUL) +#define IIC_SR_AAS (0x66a5d25dUL) +#define IIC_SR_ABGC (0x4831e30UL) +#define IIC_SR_BB (0x1ea7e5d6UL) +#define IIC_SR_RXFIFO_EMPTY (0xe419563UL) +#define IIC_SR_RXFIFO_FULL (0x60ecb95aUL) +#define IIC_SR_SRW (0x1f8520c8UL) +#define IIC_SR_TXFIFO_EMPTY (0xe17c3083UL) +#define IIC_SR_TXFIFO_FULL (0x88597319UL) +#define IIC_TBUF (0xe32a311bUL) +#define IIC_TBUF_TBUF_VAL (0xd48a5ee6UL) +#define IIC_TEN_ADR (0xb5d88814UL) +#define IIC_TEN_ADR_MSB_SLV_ADR (0x1bf3647bUL) +#define IIC_THDDAT (0x9dc42de9UL) +#define IIC_THDDAT_THDDAT_VAL (0xa4fe6780UL) +#define IIC_THDSTA (0xdec59ae3UL) +#define IIC_THDSTA_THDSTA_VAL (0xc3705793UL) +#define IIC_THIGH (0x43194ec3UL) +#define IIC_THIGH_THIGH_VAL (0x320d9d1bUL) +#define IIC_TLOW (0x3329c638UL) +#define IIC_TLOW_TLOW_VAL (0x167c1ff3UL) +#define IIC_TSUDAT (0x6251bb80UL) +#define IIC_TSUDAT_TSUDAT_VAL (0x7b1fdb1dUL) +#define IIC_TSUSTA (0x21500c8aUL) +#define IIC_TSUSTA_TSUSTA_VAL (0x1c91eb0eUL) +#define IIC_TSUSTO (0xc6e8218dUL) +#define IIC_TSUSTO_TSUSTO_VAL (0x4a908671UL) +#define IIC_TX_FIFO (0x25226095UL) +#define IIC_TX_FIFO_START (0xc24fb6c4UL) +#define IIC_TX_FIFO_STOP (0xe7ae5f6cUL) +#define IIC_TX_FIFO_TXDATA (0xbe59e736UL) +#define IIC_TX_FIFO_OCY (0x2ef0b752UL) +#define IIC_TX_FIFO_OCY_OCY_VAL (0x73b74c05UL) + +#endif /* _NTHW_FPGA_REG_DEFS_IIC_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h new file mode 100644 index 0000000000..4a5e141647 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_mac_pcs.h @@ -0,0 +1,290 @@ +/* + * nthw_fpga_reg_defs_mac_pcs.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_MAC_PCS_ +#define _NTHW_FPGA_REG_DEFS_MAC_PCS_ + +/* MAC_PCS */ +#define NTHW_MOD_MAC_PCS (0x7abe24c7UL) +#define MAC_PCS_BAD_CODE (0x10d9fce5UL) +#define MAC_PCS_BAD_CODE_CODE_ERR (0xb08ecc3fUL) +#define MAC_PCS_BIP_ERR (0x7aead929UL) +#define MAC_PCS_BIP_ERR_BIP_ERR (0x7e06ff82UL) +#define MAC_PCS_BLOCK_LOCK (0xa44a8a0bUL) +#define MAC_PCS_BLOCK_LOCK_LOCK (0x6adfd96bUL) +#define MAC_PCS_BLOCK_LOCK_CHG (0xf0603b66UL) +#define MAC_PCS_BLOCK_LOCK_CHG_LOCK_CHG (0x9ef4519dUL) +#define MAC_PCS_CLKRX_FRQ (0x999882b5UL) +#define MAC_PCS_CLKRX_FRQ_RX_FREQ (0x8b935059UL) +#define MAC_PCS_CLKTX_FRQ (0x4fc161a8UL) +#define MAC_PCS_CLKTX_FRQ_TX_FREQ (0x10812ed5UL) +#define MAC_PCS_DEBOUNCE_CTRL (0x37a3bb69UL) +#define MAC_PCS_DEBOUNCE_CTRL_NT_DEBOUNCE_LATENCY (0xf5845748UL) +#define MAC_PCS_DEBOUNCE_CTRL_NT_FORCE_LINK_DOWN (0x1a8a9237UL) +#define MAC_PCS_DEBOUNCE_CTRL_NT_LINKUP_LATENCY (0xaceccbf4UL) +#define MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL (0x7f66469eUL) +#define MAC_PCS_DRP_CONFIG (0x1281f4d8UL) +#define MAC_PCS_DRP_CONFIG_DRP_ADR (0x398caa76UL) +#define MAC_PCS_DRP_CONFIG_DRP_DI (0x83b54c6fUL) +#define MAC_PCS_DRP_CONFIG_DRP_EN (0x4cae88dUL) +#define MAC_PCS_DRP_CONFIG_DRP_MOD_ADR (0xc24d1deaUL) +#define MAC_PCS_DRP_CONFIG_DRP_WREN (0x926388aeUL) +#define MAC_PCS_DRP_CTRL (0x6df0725eUL) +#define MAC_PCS_DRP_CTRL_ADR (0x5a9962c8UL) +#define MAC_PCS_DRP_CTRL_DATA (0x2173d834UL) +#define MAC_PCS_DRP_CTRL_DBG_BUSY (0x26dd3668UL) +#define MAC_PCS_DRP_CTRL_DONE (0x9cadcbfcUL) +#define MAC_PCS_DRP_CTRL_MOD_ADR (0x4352354dUL) +#define MAC_PCS_DRP_CTRL_WREN (0xbed903edUL) +#define MAC_PCS_DRP_DATA (0xc221f047UL) +#define MAC_PCS_DRP_DATA_DRP_DO (0xbeb48b96UL) +#define MAC_PCS_DRP_DATA_DRP_RDY (0x2238822eUL) +#define MAC_PCS_FEC_CTRL (0x8eea756UL) +#define MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN (0xd0c0525eUL) +#define MAC_PCS_FEC_CW_CNT (0x59e0c4deUL) +#define MAC_PCS_FEC_CW_CNT_CW_CNT (0xd0b8ee0UL) +#define MAC_PCS_FEC_ERR_CNT_0 (0xee88619cUL) +#define MAC_PCS_FEC_ERR_CNT_0_ERR_CNT (0x4fdf126bUL) +#define MAC_PCS_FEC_ERR_CNT_1 (0x998f510aUL) +#define MAC_PCS_FEC_ERR_CNT_1_ERR_CNT (0x58a40628UL) +#define MAC_PCS_FEC_ERR_CNT_2 (0x8600b0UL) +#define MAC_PCS_FEC_ERR_CNT_2_ERR_CNT (0x61293aedUL) +#define MAC_PCS_FEC_ERR_CNT_3 (0x77813026UL) +#define MAC_PCS_FEC_ERR_CNT_3_ERR_CNT (0x76522eaeUL) +#define MAC_PCS_FEC_LANE_DLY_0 (0xc18f945eUL) +#define MAC_PCS_FEC_LANE_DLY_0_DLY (0xd9f1d54bUL) +#define MAC_PCS_FEC_LANE_DLY_1 (0xb688a4c8UL) +#define MAC_PCS_FEC_LANE_DLY_1_DLY (0xe491fcfbUL) +#define MAC_PCS_FEC_LANE_DLY_2 (0x2f81f572UL) +#define MAC_PCS_FEC_LANE_DLY_2_DLY (0xa331862bUL) +#define MAC_PCS_FEC_LANE_DLY_3 (0x5886c5e4UL) +#define MAC_PCS_FEC_LANE_DLY_3_DLY (0x9e51af9bUL) +#define MAC_PCS_FEC_LANE_MAP (0x21d4bd54UL) +#define MAC_PCS_FEC_LANE_MAP_MAPPING (0x87d12932UL) +#define MAC_PCS_FEC_STAT (0x2a74290dUL) +#define MAC_PCS_FEC_STAT_AM_LOCK (0x289b2822UL) +#define MAC_PCS_FEC_STAT_AM_LOCK_0 (0xc824a589UL) +#define MAC_PCS_FEC_STAT_AM_LOCK_1 (0xbf23951fUL) +#define MAC_PCS_FEC_STAT_AM_LOCK_2 (0x262ac4a5UL) +#define MAC_PCS_FEC_STAT_AM_LOCK_3 (0x512df433UL) +#define MAC_PCS_FEC_STAT_BLOCK_LOCK (0x6a7d0f5fUL) +#define MAC_PCS_FEC_STAT_BYPASS (0x2e754185UL) +#define MAC_PCS_FEC_STAT_FEC_LANE_ALGN (0xfd302594UL) +#define MAC_PCS_FEC_STAT_HI_SER (0xc3501768UL) +#define MAC_PCS_FEC_STAT_PCS_LANE_ALGN (0xa8193db8UL) +#define MAC_PCS_FEC_STAT_VALID (0x90dd6fe1UL) +#define MAC_PCS_FEC_UCW_CNT (0xd1354660UL) +#define MAC_PCS_FEC_UCW_CNT_UCW_CNT (0xf90f900UL) +#define MAC_PCS_FRAMING_ERR (0x73b6341dUL) +#define MAC_PCS_FRAMING_ERR_FRAMING_ERR (0xd4bfdbf4UL) +#define MAC_PCS_GTY_CTL (0x325263edUL) +#define MAC_PCS_GTY_CTL_CDR_HOLD_0 (0x423e0e64UL) +#define MAC_PCS_GTY_CTL_CDR_HOLD_1 (0x35393ef2UL) +#define MAC_PCS_GTY_CTL_CDR_HOLD_2 (0xac306f48UL) +#define MAC_PCS_GTY_CTL_CDR_HOLD_3 (0xdb375fdeUL) +#define MAC_PCS_GTY_CTL_RX (0x1f131df2UL) +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_0 (0x3c2aeb81UL) +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_1 (0x4b2ddb17UL) +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_2 (0xd2248aadUL) +#define MAC_PCS_GTY_CTL_RX_CDR_HOLD_3 (0xa523ba3bUL) +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_0 (0x78b8f7dbUL) +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_1 (0xfbfc74dUL) +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_2 (0x96b696f7UL) +#define MAC_PCS_GTY_CTL_RX_EQUA_RST_3 (0xe1b1a661UL) +#define MAC_PCS_GTY_CTL_RX_LPM_EN_0 (0xce64b22bUL) +#define MAC_PCS_GTY_CTL_RX_LPM_EN_1 (0xb96382bdUL) +#define MAC_PCS_GTY_CTL_RX_LPM_EN_2 (0x206ad307UL) +#define MAC_PCS_GTY_CTL_RX_LPM_EN_3 (0x576de391UL) +#define MAC_PCS_GTY_CTL_RX_POLARITY_0 (0x80681033UL) +#define MAC_PCS_GTY_CTL_RX_POLARITY_1 (0xf76f20a5UL) +#define MAC_PCS_GTY_CTL_RX_POLARITY_2 (0x6e66711fUL) +#define MAC_PCS_GTY_CTL_RX_POLARITY_3 (0x19614189UL) +#define MAC_PCS_GTY_CTL_RX_RATE_0 (0x6c6c737dUL) +#define MAC_PCS_GTY_CTL_RX_RATE_1 (0x1b6b43ebUL) +#define MAC_PCS_GTY_CTL_RX_RATE_2 (0x82621251UL) +#define MAC_PCS_GTY_CTL_RX_RATE_3 (0xf56522c7UL) +#define MAC_PCS_GTY_CTL_TX (0x4949ba74UL) +#define MAC_PCS_GTY_CTL_TX_INHIBIT_0 (0xd2423364UL) +#define MAC_PCS_GTY_CTL_TX_INHIBIT_1 (0xa54503f2UL) +#define MAC_PCS_GTY_CTL_TX_INHIBIT_2 (0x3c4c5248UL) +#define MAC_PCS_GTY_CTL_TX_INHIBIT_3 (0x4b4b62deUL) +#define MAC_PCS_GTY_CTL_TX_POLARITY_0 (0x208dcfeeUL) +#define MAC_PCS_GTY_CTL_TX_POLARITY_1 (0x578aff78UL) +#define MAC_PCS_GTY_CTL_TX_POLARITY_2 (0xce83aec2UL) +#define MAC_PCS_GTY_CTL_TX_POLARITY_3 (0xb9849e54UL) +#define MAC_PCS_GTY_DIFF_CTL (0x8756c12fUL) +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0 (0xf08ceefdUL) +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1 (0x878bde6bUL) +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2 (0x1e828fd1UL) +#define MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3 (0x6985bf47UL) +#define MAC_PCS_GTY_LOOP (0x4dd7ddbUL) +#define MAC_PCS_GTY_LOOP_GT_LOOP_0 (0xd55e5438UL) +#define MAC_PCS_GTY_LOOP_GT_LOOP_1 (0xa25964aeUL) +#define MAC_PCS_GTY_LOOP_GT_LOOP_2 (0x3b503514UL) +#define MAC_PCS_GTY_LOOP_GT_LOOP_3 (0x4c570582UL) +#define MAC_PCS_GTY_POST_CURSOR (0x4699c607UL) +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0 (0x23ff66e9UL) +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1 (0x54f8567fUL) +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2 (0xcdf107c5UL) +#define MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3 (0xbaf63753UL) +#define MAC_PCS_GTY_PRBS_SEL (0x6610ec4eUL) +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_0 (0xb535fd56UL) +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_1 (0xc232cdc0UL) +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_2 (0x5b3b9c7aUL) +#define MAC_PCS_GTY_PRBS_SEL_RX_PRBS_SEL_3 (0x2c3cacecUL) +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_0 (0x15d0228bUL) +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_1 (0x62d7121dUL) +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_2 (0xfbde43a7UL) +#define MAC_PCS_GTY_PRBS_SEL_TX_PRBS_SEL_3 (0x8cd97331UL) +#define MAC_PCS_GTY_PRE_CURSOR (0x989e0463UL) +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0 (0x264242bdUL) +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1 (0x5145722bUL) +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2 (0xc84c2391UL) +#define MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3 (0xbf4b1307UL) +#define MAC_PCS_GTY_RX_BUF_STAT (0xf37901e8UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_0 (0xab8b9404UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_1 (0xdc8ca492UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_2 (0x4585f528UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_3 (0x3282c5beUL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_0 (0x476782c4UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_1 (0x3060b252UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_2 (0xa969e3e8UL) +#define MAC_PCS_GTY_RX_BUF_STAT_RX_BUF_STAT_CHANGED_3 (0xde6ed37eUL) +#define MAC_PCS_GTY_SCAN_CTL (0x782ddd2aUL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_0 (0xc2791c66UL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_1 (0xb57e2cf0UL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_2 (0x2c777d4aUL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_RST_3 (0x5b704ddcUL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_0 (0xebe5938aUL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_1 (0x9ce2a31cUL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_2 (0x5ebf2a6UL) +#define MAC_PCS_GTY_SCAN_CTL_EYE_SCAN_TRG_3 (0x72ecc230UL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_0 (0x3243ecaeUL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_1 (0x4544dc38UL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_2 (0xdc4d8d82UL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_ERR_INS_3 (0xab4abd14UL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_0 (0xf77381daUL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_1 (0x8074b14cUL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_2 (0x197de0f6UL) +#define MAC_PCS_GTY_SCAN_CTL_PRBS_RST_3 (0x6e7ad060UL) +#define MAC_PCS_GTY_SCAN_STAT (0x8070b7b9UL) +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_0 (0xe5ddd3f9UL) +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_1 (0x92dae36fUL) +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_2 (0xbd3b2d5UL) +#define MAC_PCS_GTY_SCAN_STAT_EYE_SCAN_ERR_3 (0x7cd48243UL) +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_0 (0xb0217badUL) +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_1 (0xc7264b3bUL) +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_2 (0x5e2f1a81UL) +#define MAC_PCS_GTY_SCAN_STAT_PRBS_ERR_3 (0x29282a17UL) +#define MAC_PCS_GTY_STAT (0x853a9f14UL) +#define MAC_PCS_GTY_STAT_RX_RST_DONE_0 (0x71cda8d6UL) +#define MAC_PCS_GTY_STAT_RX_RST_DONE_1 (0x6ca9840UL) +#define MAC_PCS_GTY_STAT_RX_RST_DONE_2 (0x9fc3c9faUL) +#define MAC_PCS_GTY_STAT_RX_RST_DONE_3 (0xe8c4f96cUL) +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_0 (0xf766f49eUL) +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_1 (0x8061c408UL) +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_2 (0x196895b2UL) +#define MAC_PCS_GTY_STAT_TX_BUF_STAT_3 (0x6e6fa524UL) +#define MAC_PCS_GTY_STAT_TX_RST_DONE_0 (0xd128770bUL) +#define MAC_PCS_GTY_STAT_TX_RST_DONE_1 (0xa62f479dUL) +#define MAC_PCS_GTY_STAT_TX_RST_DONE_2 (0x3f261627UL) +#define MAC_PCS_GTY_STAT_TX_RST_DONE_3 (0x482126b1UL) +#define MAC_PCS_LANE_ALIGNER_FILL (0x7f7c92b4UL) +#define MAC_PCS_LANE_ALIGNER_FILL_FILL (0x5d03a992UL) +#define MAC_PCS_LINK_SUMMARY (0x7506c2cfUL) +#define MAC_PCS_LINK_SUMMARY_ABS (0xeaec5364UL) +#define MAC_PCS_LINK_SUMMARY_LH_ABS (0x75386439UL) +#define MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT (0xfe0a1d22UL) +#define MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT (0xe891aedUL) +#define MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT (0x91098b1fUL) +#define MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE (0x66c65523UL) +#define MAC_PCS_LINK_SUMMARY_LOCAL_FAULT (0x87148e11UL) +#define MAC_PCS_LINK_SUMMARY_NIM_INTERR (0x3d95c18UL) +#define MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE (0x27ce6435UL) +#define MAC_PCS_LINK_SUMMARY_REMOTE_FAULT (0xb1206568UL) +#define MAC_PCS_LINK_SUMMARY_RESERVED (0x254bc0e3UL) +#define MAC_PCS_MAC_PCS_CONFIG (0x1534e5c0UL) +#define MAC_PCS_MAC_PCS_CONFIG_RX_CORE_RST (0xe964d0f5UL) +#define MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE (0x3301c934UL) +#define MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC (0xf01103aUL) +#define MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST (0x65a6baccUL) +#define MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN (0xf932af1bUL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_CORE_RST (0x1d11ab6UL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE (0x401bb0beUL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_FCS_REMOVE (0x25816398UL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST (0x8d13708fUL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE (0xbcff1ba5UL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI (0xc4dd154eUL) +#define MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN (0xdbc87be9UL) +#define MAC_PCS_MAX_PKT_LEN (0x396b0d64UL) +#define MAC_PCS_MAX_PKT_LEN_MAX_LEN (0x6d95b01fUL) +#define MAC_PCS_MF_ERR (0xb0be669dUL) +#define MAC_PCS_MF_ERR_MF_ERR (0x6c7b7561UL) +#define MAC_PCS_MF_LEN_ERR (0x559f33efUL) +#define MAC_PCS_MF_LEN_ERR_MF_LEN_ERR (0x196e21f6UL) +#define MAC_PCS_MF_REPEAT_ERR (0xc7dedbb3UL) +#define MAC_PCS_MF_REPEAT_ERR_MF_REPEAT_ERR (0xb5be34c7UL) +#define MAC_PCS_PHYMAC_MISC (0x4d213de4UL) +#define MAC_PCS_PHYMAC_MISC_TS_EOP (0xc9232087UL) +#define MAC_PCS_PHYMAC_MISC_TX_MUX_STATE (0x761f1c74UL) +#define MAC_PCS_PHYMAC_MISC_TX_SEL_HOST (0xb50087a5UL) +#define MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP (0xbe5ce3b1UL) +#define MAC_PCS_PHYMAC_MISC_TX_SEL_TFG (0x106d1efUL) +#define MAC_PCS_PHY_STAT (0x533a519cUL) +#define MAC_PCS_PHY_STAT_ALARM (0x57360efaUL) +#define MAC_PCS_PHY_STAT_MOD_PRS (0x5d9d2135UL) +#define MAC_PCS_PHY_STAT_RX_LOS (0xf9354fecUL) +#define MAC_PCS_STAT_PCS_RX (0xb11d1a0cUL) +#define MAC_PCS_STAT_PCS_RX_ALIGNED (0xc04d3946UL) +#define MAC_PCS_STAT_PCS_RX_ALIGNED_ERR (0x82e5aacbUL) +#define MAC_PCS_STAT_PCS_RX_GOT_SIGNAL_OS (0xe2ebace5UL) +#define MAC_PCS_STAT_PCS_RX_HI_BER (0x44ed301UL) +#define MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT (0xd302122UL) +#define MAC_PCS_STAT_PCS_RX_LOCAL_FAULT (0x2fd7a554UL) +#define MAC_PCS_STAT_PCS_RX_MISALIGNED (0x4f8958c8UL) +#define MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT (0xce46c6b2UL) +#define MAC_PCS_STAT_PCS_RX_REMOTE_FAULT (0xb73e135cUL) +#define MAC_PCS_STAT_PCS_RX_STATUS (0x6087afc3UL) +#define MAC_PCS_STAT_PCS_RX_LATCH (0x12a96a4UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED (0xffeb7af8UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_ALIGNED_ERR (0x43af96a9UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_GOT_SIGNAL_OS (0x9a4f180dUL) +#define MAC_PCS_STAT_PCS_RX_LATCH_HI_BER (0x170bb0a7UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_INTERNAL_LOCAL_FAULT (0x97082914UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_LOCAL_FAULT (0xee9d9936UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_MISALIGNED (0x64a891f6UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_RECEIVED_LOCAL_FAULT (0x547ece84UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_REMOTE_FAULT (0x14435914UL) +#define MAC_PCS_STAT_PCS_RX_LATCH_STATUS (0x73c2cc65UL) +#define MAC_PCS_STAT_PCS_TX (0xe747bd8aUL) +#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT (0xd715eee2UL) +#define MAC_PCS_STAT_PCS_TX_LOCAL_FAULT_CHANGED (0x125aedaaUL) +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR (0x892ad851UL) +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_READ_ERROR_CHANGED (0xf39f6854UL) +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR (0x6075c4dfUL) +#define MAC_PCS_STAT_PCS_TX_PTP_FIFO_WRITE_ERROR_CHANGED (0xcd4c168aUL) +#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT (0x4483a41fUL) +#define MAC_PCS_STAT_PCS_TX_TX_OVFOUT_CHANGED (0xcbd66e98UL) +#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT (0xb65e59a1UL) +#define MAC_PCS_STAT_PCS_TX_TX_UNFOUT_CHANGED (0x9157fdd8UL) +#define MAC_PCS_SYNCED (0x76ad78aaUL) +#define MAC_PCS_SYNCED_SYNC (0xbff0beadUL) +#define MAC_PCS_SYNCED_ERR (0x136856e9UL) +#define MAC_PCS_SYNCED_ERR_SYNC_ERROR (0x16c52dc7UL) +#define MAC_PCS_TEST_ERR (0xbf52be89UL) +#define MAC_PCS_TEST_ERR_CODE_ERR (0x33a662cUL) +#define MAC_PCS_TIMESTAMP_COMP (0x3054d1fcUL) +#define MAC_PCS_TIMESTAMP_COMP_RX_DLY (0xa6496d75UL) +#define MAC_PCS_TIMESTAMP_COMP_TX_DLY (0x70108e68UL) +#define MAC_PCS_VL_DEMUXED (0xe1a41659UL) +#define MAC_PCS_VL_DEMUXED_LOCK (0xf1e85d36UL) +#define MAC_PCS_VL_DEMUXED_CHG (0xa326d6a6UL) +#define MAC_PCS_VL_DEMUXED_CHG_LOCK_CHG (0x9327587fUL) +#define MAC_PCS_VL_NUMBER (0x149d9e3UL) +#define MAC_PCS_VL_NUMBER_VL_NUMBER (0x3b87c706UL) + +#endif /* _NTHW_FPGA_REG_DEFS_MAC_PCS_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h new file mode 100644 index 0000000000..4f8e41f261 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_rd_tg.h @@ -0,0 +1,29 @@ +/* + * nthw_fpga_reg_defs_pci_rd_tg.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ +#define _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ + +/* PCI_RD_TG */ +#define NTHW_MOD_PCI_RD_TG (0x9ad9eed2UL) +#define PCI_RD_TG_TG_CTRL (0x5a899dc8UL) +#define PCI_RD_TG_TG_CTRL_TG_RD_RDY (0x66c70bffUL) +#define PCI_RD_TG_TG_RDADDR (0x39e1af65UL) +#define PCI_RD_TG_TG_RDADDR_RAM_ADDR (0xf6b0ecd1UL) +#define PCI_RD_TG_TG_RDDATA0 (0x4bcd36f9UL) +#define PCI_RD_TG_TG_RDDATA0_PHYS_ADDR_LOW (0xa4479fe8UL) +#define PCI_RD_TG_TG_RDDATA1 (0x3cca066fUL) +#define PCI_RD_TG_TG_RDDATA1_PHYS_ADDR_HIGH (0x6b3563dfUL) +#define PCI_RD_TG_TG_RDDATA2 (0xa5c357d5UL) +#define PCI_RD_TG_TG_RDDATA2_REQ_HID (0x5dab4bc3UL) +#define PCI_RD_TG_TG_RDDATA2_REQ_SIZE (0x85dd8d92UL) +#define PCI_RD_TG_TG_RDDATA2_WAIT (0x85ba70b2UL) +#define PCI_RD_TG_TG_RDDATA2_WRAP (0x546e238aUL) +#define PCI_RD_TG_TG_RD_RUN (0xd6542f54UL) +#define PCI_RD_TG_TG_RD_RUN_RD_ITERATION (0xcdc6e166UL) + +#endif /* _NTHW_FPGA_REG_DEFS_PCI_RD_TG_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h new file mode 100644 index 0000000000..59bb1b2613 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pci_wr_tg.h @@ -0,0 +1,32 @@ +/* + * nthw_fpga_reg_defs_pci_wr_tg.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ +#define _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ + +/* PCI_WR_TG */ +#define NTHW_MOD_PCI_WR_TG (0x274b69e1UL) +#define PCI_WR_TG_TG_CTRL (0xa48366c7UL) +#define PCI_WR_TG_TG_CTRL_TG_WR_RDY (0x9983a3e8UL) +#define PCI_WR_TG_TG_SEQ (0x8b3e0bd6UL) +#define PCI_WR_TG_TG_SEQ_SEQUENCE (0xebf1c760UL) +#define PCI_WR_TG_TG_WRADDR (0x2b7b95a5UL) +#define PCI_WR_TG_TG_WRADDR_RAM_ADDR (0x5fdc2aceUL) +#define PCI_WR_TG_TG_WRDATA0 (0xd0bb6e73UL) +#define PCI_WR_TG_TG_WRDATA0_PHYS_ADDR_LOW (0x97cb1c89UL) +#define PCI_WR_TG_TG_WRDATA1 (0xa7bc5ee5UL) +#define PCI_WR_TG_TG_WRDATA1_PHYS_ADDR_HIGH (0x51b3be92UL) +#define PCI_WR_TG_TG_WRDATA2 (0x3eb50f5fUL) +#define PCI_WR_TG_TG_WRDATA2_INC_MODE (0x5be5577UL) +#define PCI_WR_TG_TG_WRDATA2_REQ_HID (0xf4c78ddcUL) +#define PCI_WR_TG_TG_WRDATA2_REQ_SIZE (0x87ceca1UL) +#define PCI_WR_TG_TG_WRDATA2_WAIT (0xb29cb8ffUL) +#define PCI_WR_TG_TG_WRDATA2_WRAP (0x6348ebc7UL) +#define PCI_WR_TG_TG_WR_RUN (0xc4ce1594UL) +#define PCI_WR_TG_TG_WR_RUN_WR_ITERATION (0xe83c0a22UL) + +#endif /* _NTHW_FPGA_REG_DEFS_PCI_WR_TG_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h new file mode 100644 index 0000000000..641716af9e --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_pcie3.h @@ -0,0 +1,273 @@ +/* + * nthw_fpga_reg_defs_pcie3.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_PCIE3_ +#define _NTHW_FPGA_REG_DEFS_PCIE3_ + +/* PCIE3 */ +#define NTHW_MOD_PCIE3 (0xfbc48c18UL) +#define PCIE3_BUILD_SEED (0x7a6457c5UL) +#define PCIE3_BUILD_SEED_BUILD_SEED (0x626b816fUL) +#define PCIE3_BUILD_TIME (0x51772c86UL) +#define PCIE3_BUILD_TIME_TIME (0xe6ca8be1UL) +#define PCIE3_CONFIG (0xe7ef0d51UL) +#define PCIE3_CONFIG_EXT_TAG (0xce1f05adUL) +#define PCIE3_CONFIG_MAX_READ (0x2943f801UL) +#define PCIE3_CONFIG_MAX_TLP (0x2aa40e12UL) +#define PCIE3_CONTROL (0x935935d4UL) +#define PCIE3_CONTROL_RD_ATTR (0xc59aa0a3UL) +#define PCIE3_CONTROL_WRAW (0x1fdd0c42UL) +#define PCIE3_CONTROL_WR_ATTR (0x422d6e82UL) +#define PCIE3_CORESPEED (0x5cbe0925UL) +#define PCIE3_CORESPEED_CORESPEED (0x52ed2515UL) +#define PCIE3_CORESPEED_DDR3SPEED (0xb69dba56UL) +#define PCIE3_DRP_COMMON (0xffd331a2UL) +#define PCIE3_DRP_COMMON_DRP_ADDR (0xbbfbc2fbUL) +#define PCIE3_DRP_COMMON_DRP_RDY (0x8289f931UL) +#define PCIE3_DRP_COMMON_GTH_SEL (0x40ac636fUL) +#define PCIE3_DRP_COMMON_WR (0xbe76449eUL) +#define PCIE3_DRP_DATE (0xeaae0e97UL) +#define PCIE3_DRP_DATE_DRP_DATA (0xa27d4522UL) +#define PCIE3_EP_TO_RP_ERR (0x3784de0fUL) +#define PCIE3_EP_TO_RP_ERR_ERR_COR (0x3bb2d717UL) +#define PCIE3_EP_TO_RP_ERR_ERR_FATAL (0xe6571da2UL) +#define PCIE3_EP_TO_RP_ERR_ERR_NONFATAL (0xb3be48faUL) +#define PCIE3_INT_CLR (0xcde216faUL) +#define PCIE3_INT_CLR_AVR (0x1982c8eUL) +#define PCIE3_INT_CLR_FHM (0x5d9e0821UL) +#define PCIE3_INT_CLR_INT_0 (0x6cabf375UL) +#define PCIE3_INT_CLR_INT_1 (0x1bacc3e3UL) +#define PCIE3_INT_CLR_INT_10 (0xcdc3c020UL) +#define PCIE3_INT_CLR_INT_11 (0xbac4f0b6UL) +#define PCIE3_INT_CLR_INT_12 (0x23cda10cUL) +#define PCIE3_INT_CLR_INT_13 (0x54ca919aUL) +#define PCIE3_INT_CLR_INT_14 (0xcaae0439UL) +#define PCIE3_INT_CLR_INT_15 (0xbda934afUL) +#define PCIE3_INT_CLR_INT_16 (0x24a06515UL) +#define PCIE3_INT_CLR_INT_17 (0x53a75583UL) +#define PCIE3_INT_CLR_INT_18 (0xc3184812UL) +#define PCIE3_INT_CLR_INT_19 (0xb41f7884UL) +#define PCIE3_INT_CLR_INT_2 (0x82a59259UL) +#define PCIE3_INT_CLR_INT_20 (0xe6ee93e3UL) +#define PCIE3_INT_CLR_INT_21 (0x91e9a375UL) +#define PCIE3_INT_CLR_INT_22 (0x8e0f2cfUL) +#define PCIE3_INT_CLR_INT_23 (0x7fe7c259UL) +#define PCIE3_INT_CLR_INT_24 (0xe18357faUL) +#define PCIE3_INT_CLR_INT_25 (0x9684676cUL) +#define PCIE3_INT_CLR_INT_26 (0xf8d36d6UL) +#define PCIE3_INT_CLR_INT_27 (0x788a0640UL) +#define PCIE3_INT_CLR_INT_28 (0xe8351bd1UL) +#define PCIE3_INT_CLR_INT_29 (0x9f322b47UL) +#define PCIE3_INT_CLR_INT_3 (0xf5a2a2cfUL) +#define PCIE3_INT_CLR_INT_30 (0xfff5a2a2UL) +#define PCIE3_INT_CLR_INT_31 (0x88f29234UL) +#define PCIE3_INT_CLR_INT_4 (0x6bc6376cUL) +#define PCIE3_INT_CLR_INT_5 (0x1cc107faUL) +#define PCIE3_INT_CLR_INT_6 (0x85c85640UL) +#define PCIE3_INT_CLR_INT_7 (0xf2cf66d6UL) +#define PCIE3_INT_CLR_INT_8 (0x62707b47UL) +#define PCIE3_INT_CLR_INT_9 (0x15774bd1UL) +#define PCIE3_INT_CLR_PORT (0x4f57e46eUL) +#define PCIE3_INT_CLR_PPS (0x3d2172d9UL) +#define PCIE3_INT_CLR_QSPI (0xb3e7d744UL) +#define PCIE3_INT_CLR_SPIM (0x87c5cc97UL) +#define PCIE3_INT_CLR_SPIS (0x7dcaf1f4UL) +#define PCIE3_INT_CLR_STA (0xa8b278ccUL) +#define PCIE3_INT_CLR_TIMER (0x696afaafUL) +#define PCIE3_INT_FORC (0x55ea48d8UL) +#define PCIE3_INT_FORC_AVR (0x5b8cd9ffUL) +#define PCIE3_INT_FORC_FHM (0x78afd50UL) +#define PCIE3_INT_FORC_INT_0 (0x9758e745UL) +#define PCIE3_INT_FORC_INT_1 (0xe05fd7d3UL) +#define PCIE3_INT_FORC_INT_10 (0xebe10398UL) +#define PCIE3_INT_FORC_INT_11 (0x9ce6330eUL) +#define PCIE3_INT_FORC_INT_12 (0x5ef62b4UL) +#define PCIE3_INT_FORC_INT_13 (0x72e85222UL) +#define PCIE3_INT_FORC_INT_14 (0xec8cc781UL) +#define PCIE3_INT_FORC_INT_15 (0x9b8bf717UL) +#define PCIE3_INT_FORC_INT_16 (0x282a6adUL) +#define PCIE3_INT_FORC_INT_17 (0x7585963bUL) +#define PCIE3_INT_FORC_INT_18 (0xe53a8baaUL) +#define PCIE3_INT_FORC_INT_19 (0x923dbb3cUL) +#define PCIE3_INT_FORC_INT_2 (0x79568669UL) +#define PCIE3_INT_FORC_INT_20 (0xc0cc505bUL) +#define PCIE3_INT_FORC_INT_21 (0xb7cb60cdUL) +#define PCIE3_INT_FORC_INT_22 (0x2ec23177UL) +#define PCIE3_INT_FORC_INT_23 (0x59c501e1UL) +#define PCIE3_INT_FORC_INT_24 (0xc7a19442UL) +#define PCIE3_INT_FORC_INT_25 (0xb0a6a4d4UL) +#define PCIE3_INT_FORC_INT_26 (0x29aff56eUL) +#define PCIE3_INT_FORC_INT_27 (0x5ea8c5f8UL) +#define PCIE3_INT_FORC_INT_28 (0xce17d869UL) +#define PCIE3_INT_FORC_INT_29 (0xb910e8ffUL) +#define PCIE3_INT_FORC_INT_3 (0xe51b6ffUL) +#define PCIE3_INT_FORC_INT_30 (0xd9d7611aUL) +#define PCIE3_INT_FORC_INT_31 (0xaed0518cUL) +#define PCIE3_INT_FORC_INT_4 (0x9035235cUL) +#define PCIE3_INT_FORC_INT_5 (0xe73213caUL) +#define PCIE3_INT_FORC_INT_6 (0x7e3b4270UL) +#define PCIE3_INT_FORC_INT_7 (0x93c72e6UL) +#define PCIE3_INT_FORC_INT_8 (0x99836f77UL) +#define PCIE3_INT_FORC_INT_9 (0xee845fe1UL) +#define PCIE3_INT_FORC_PORT (0x680fb131UL) +#define PCIE3_INT_FORC_PPS (0x673587a8UL) +#define PCIE3_INT_FORC_QSPI (0x94bf821bUL) +#define PCIE3_INT_FORC_SPIM (0xa09d99c8UL) +#define PCIE3_INT_FORC_SPIS (0x5a92a4abUL) +#define PCIE3_INT_FORC_STA (0xf2a68dbdUL) +#define PCIE3_INT_FORC_TIMER (0x9299ee9fUL) +#define PCIE3_INT_MASK (0x9fb55ba0UL) +#define PCIE3_INT_MASK_AVR (0xadf52690UL) +#define PCIE3_INT_MASK_FHM (0xf1f3023fUL) +#define PCIE3_INT_MASK_IIC0 (0x856e56f1UL) +#define PCIE3_INT_MASK_IIC1 (0xf2696667UL) +#define PCIE3_INT_MASK_IIC2 (0x6b6037ddUL) +#define PCIE3_INT_MASK_IIC3 (0x1c67074bUL) +#define PCIE3_INT_MASK_IIC4 (0x820392e8UL) +#define PCIE3_INT_MASK_IIC5 (0xf504a27eUL) +#define PCIE3_INT_MASK_INT_0 (0x583f89d9UL) +#define PCIE3_INT_MASK_INT_1 (0x2f38b94fUL) +#define PCIE3_INT_MASK_INT_10 (0x1297bb99UL) +#define PCIE3_INT_MASK_INT_11 (0x65908b0fUL) +#define PCIE3_INT_MASK_INT_12 (0xfc99dab5UL) +#define PCIE3_INT_MASK_INT_13 (0x8b9eea23UL) +#define PCIE3_INT_MASK_INT_14 (0x15fa7f80UL) +#define PCIE3_INT_MASK_INT_15 (0x62fd4f16UL) +#define PCIE3_INT_MASK_INT_16 (0xfbf41eacUL) +#define PCIE3_INT_MASK_INT_17 (0x8cf32e3aUL) +#define PCIE3_INT_MASK_INT_18 (0x1c4c33abUL) +#define PCIE3_INT_MASK_INT_19 (0x6b4b033dUL) +#define PCIE3_INT_MASK_INT_2 (0xb631e8f5UL) +#define PCIE3_INT_MASK_INT_20 (0x39bae85aUL) +#define PCIE3_INT_MASK_INT_21 (0x4ebdd8ccUL) +#define PCIE3_INT_MASK_INT_22 (0xd7b48976UL) +#define PCIE3_INT_MASK_INT_23 (0xa0b3b9e0UL) +#define PCIE3_INT_MASK_INT_24 (0x3ed72c43UL) +#define PCIE3_INT_MASK_INT_25 (0x49d01cd5UL) +#define PCIE3_INT_MASK_INT_26 (0xd0d94d6fUL) +#define PCIE3_INT_MASK_INT_27 (0xa7de7df9UL) +#define PCIE3_INT_MASK_INT_28 (0x37616068UL) +#define PCIE3_INT_MASK_INT_29 (0x406650feUL) +#define PCIE3_INT_MASK_INT_3 (0xc136d863UL) +#define PCIE3_INT_MASK_INT_30 (0x20a1d91bUL) +#define PCIE3_INT_MASK_INT_31 (0x57a6e98dUL) +#define PCIE3_INT_MASK_INT_4 (0x5f524dc0UL) +#define PCIE3_INT_MASK_INT_5 (0x28557d56UL) +#define PCIE3_INT_MASK_INT_6 (0xb15c2cecUL) +#define PCIE3_INT_MASK_INT_7 (0xc65b1c7aUL) +#define PCIE3_INT_MASK_INT_8 (0x56e401ebUL) +#define PCIE3_INT_MASK_INT_9 (0x21e3317dUL) +#define PCIE3_INT_MASK_PORT (0xb5f4b407UL) +#define PCIE3_INT_MASK_PPS (0x914c78c7UL) +#define PCIE3_INT_MASK_QSPI (0x4944872dUL) +#define PCIE3_INT_MASK_SPIM (0x7d669cfeUL) +#define PCIE3_INT_MASK_SPIS (0x8769a19dUL) +#define PCIE3_INT_MASK_STA (0x4df72d2UL) +#define PCIE3_INT_MASK_TIMER (0x5dfe8003UL) +#define PCIE3_LAT_CTRL (0x5c509767UL) +#define PCIE3_LAT_CTRL_CLEAR_RAM (0x8a124a71UL) +#define PCIE3_LAT_CTRL_ENABLE (0x47ce18e9UL) +#define PCIE3_LAT_CTRL_PRESCAL (0x471e1378UL) +#define PCIE3_LAT_CTRL_RAM_VLD (0x8efd11f9UL) +#define PCIE3_LAT_CTRL_READ_RAM (0x9cfa1247UL) +#define PCIE3_LAT_CTRL_STATUS (0xcf6eb5c7UL) +#define PCIE3_LAT_MAX (0x316931d1UL) +#define PCIE3_LAT_MAX_MAX (0xcb993f8fUL) +#define PCIE3_LAT_RAMADR (0x745612a7UL) +#define PCIE3_LAT_RAMADR_ADR (0x7516436aUL) +#define PCIE3_LAT_RAMDATA (0xfc506b8dUL) +#define PCIE3_LAT_RAMDATA_DATA (0x73152393UL) +#define PCIE3_LINK_STATUS (0xab303a44UL) +#define PCIE3_LINK_STATUS_CLEAR (0x2fda333UL) +#define PCIE3_LINK_STATUS_RETRAIN_CNT (0xd32d9b1dUL) +#define PCIE3_MARKADR_LSB (0xbf66115UL) +#define PCIE3_MARKADR_LSB_ADR (0xfa67c336UL) +#define PCIE3_MARKADR_MSB (0xa340b22UL) +#define PCIE3_MARKADR_MSB_ADR (0x5c10c882UL) +#define PCIE3_PB_INTERVAL (0x6d0029bfUL) +#define PCIE3_PB_INTERVAL_INTERVAL (0xd3638bc4UL) +#define PCIE3_PB_MAX_RD (0x14d4cfd0UL) +#define PCIE3_PB_MAX_RD_PB (0xafae2778UL) +#define PCIE3_PB_MAX_WR (0x9d778ec4UL) +#define PCIE3_PB_MAX_WR_PB (0x123ca04bUL) +#define PCIE3_PCIE_CTRL (0x6a657a79UL) +#define PCIE3_PCIE_CTRL_EXT_TAG_ENA (0xc0feaf2UL) +#define PCIE3_PCI_ENDPOINT (0xef3fb5fcUL) +#define PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK (0x96497384UL) +#define PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK (0xdec3febUL) +#define PCIE3_PCI_ENDPOINT_GET_MSG (0x8d574999UL) +#define PCIE3_PCI_ENDPOINT_IF_ID (0xe093c118UL) +#define PCIE3_PCI_ENDPOINT_SEND_MSG (0x3c6e3993UL) +#define PCIE3_PCI_TEST0 (0x9035b95dUL) +#define PCIE3_PCI_TEST0_DATA (0xf1e900b8UL) +#define PCIE3_PCI_TEST1 (0xe73289cbUL) +#define PCIE3_PCI_TEST1_DATA (0x3ab5d31dUL) +#define PCIE3_PCI_TEST2 (0x7e3bd871UL) +#define PCIE3_PCI_TEST2_DATA (0xbc21a1b3UL) +#define PCIE3_PCI_TEST3 (0x93ce8e7UL) +#define PCIE3_PCI_TEST3_DATA (0x777d7216UL) +#define PCIE3_PROD_ID_EX (0x8611a98cUL) +#define PCIE3_PROD_ID_EX_LAYOUT (0x9df9070dUL) +#define PCIE3_PROD_ID_EX_LAYOUT_VERSION (0xb1b84c8bUL) +#define PCIE3_PROD_ID_EX_RESERVED (0x7eaa8a3bUL) +#define PCIE3_PROD_ID_LSB (0x427df3d7UL) +#define PCIE3_PROD_ID_LSB_GROUP_ID (0x79fb4c8UL) +#define PCIE3_PROD_ID_LSB_REV_ID (0xc70a49f8UL) +#define PCIE3_PROD_ID_LSB_VER_ID (0xd3f99cb9UL) +#define PCIE3_PROD_ID_MSB (0x43bf99e0UL) +#define PCIE3_PROD_ID_MSB_BUILD_NO (0xad3c5124UL) +#define PCIE3_PROD_ID_MSB_PATCH_NO (0x77fde683UL) +#define PCIE3_PROD_ID_MSB_TYPE_ID (0xdbb9d1adUL) +#define PCIE3_RESET_CTRL (0xcc9a6c8bUL) +#define PCIE3_RESET_CTRL_MASK (0xf060fbbcUL) +#define PCIE3_RP_TO_EP_ERR (0x51d7e85fUL) +#define PCIE3_RP_TO_EP_ERR_ERR_COR (0x394f4c0dUL) +#define PCIE3_RP_TO_EP_ERR_ERR_FATAL (0x31a7af48UL) +#define PCIE3_RP_TO_EP_ERR_ERR_NONFATAL (0x7c85237dUL) +#define PCIE3_SAMPLE_TIME (0x6c2ab747UL) +#define PCIE3_SAMPLE_TIME_SAMPLE_TIME (0xae51ac57UL) +#define PCIE3_STATUS (0x48654731UL) +#define PCIE3_STATUS_RD_ERR (0x153789c6UL) +#define PCIE3_STATUS_TAGS_IN_USE (0x4dbe283UL) +#define PCIE3_STATUS_WR_ERR (0xaa5a7a57UL) +#define PCIE3_STATUS0 (0xa54dba5cUL) +#define PCIE3_STATUS0_TAGS_IN_USE (0x67828096UL) +#define PCIE3_STATUS0_UR_ADDR (0xcbf0c755UL) +#define PCIE3_STATUS0_UR_DWORD (0x3e60a758UL) +#define PCIE3_STATUS0_UR_FBE (0xba0c2851UL) +#define PCIE3_STATUS0_UR_FMT (0x5724146cUL) +#define PCIE3_STATUS0_UR_LBE (0xb79bad87UL) +#define PCIE3_STATUS0_UR_REG (0x6cd416UL) +#define PCIE3_STAT_CTRL (0xdef3e1d7UL) +#define PCIE3_STAT_CTRL_STAT_ENA (0x613ed39aUL) +#define PCIE3_STAT_CTRL_STAT_REQ (0x8614afc0UL) +#define PCIE3_STAT_REFCLK (0xa4423dd2UL) +#define PCIE3_STAT_REFCLK_REFCLK250 (0xf072561UL) +#define PCIE3_STAT_RQ_RDY (0x3ab72682UL) +#define PCIE3_STAT_RQ_RDY_COUNTER (0xbbf817faUL) +#define PCIE3_STAT_RQ_VLD (0x9661688fUL) +#define PCIE3_STAT_RQ_VLD_COUNTER (0x457981aaUL) +#define PCIE3_STAT_RX (0xf2a8e7a1UL) +#define PCIE3_STAT_RX_COUNTER (0x8d8ef524UL) +#define PCIE3_STAT_TX (0xa4f24027UL) +#define PCIE3_STAT_TX_COUNTER (0x80908563UL) +#define PCIE3_TEST0 (0xa0e404f1UL) +#define PCIE3_TEST0_DATA (0xf82b8d9cUL) +#define PCIE3_TEST1 (0xd7e33467UL) +#define PCIE3_TEST1_DATA (0x33775e39UL) +#define PCIE3_TEST2_DATA (0x7151e5e8UL) +#define PCIE3_TEST3_DATA (0xba0d364dUL) +#define PCIE3_UUID0 (0x96ee4e29UL) +#define PCIE3_UUID0_UUID0 (0x459d36b3UL) +#define PCIE3_UUID1 (0xe1e97ebfUL) +#define PCIE3_UUID1_UUID1 (0x94ed0d91UL) +#define PCIE3_UUID2 (0x78e02f05UL) +#define PCIE3_UUID2_UUID2 (0x3c0c46b6UL) +#define PCIE3_UUID3 (0xfe71f93UL) +#define PCIE3_UUID3_UUID3 (0xed7c7d94UL) + +#endif /* _NTHW_FPGA_REG_DEFS_PCIE3_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h new file mode 100644 index 0000000000..a4071c0029 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rac.h @@ -0,0 +1,64 @@ +/* + * nthw_fpga_reg_defs_rac.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_RAC_ +#define _NTHW_FPGA_REG_DEFS_RAC_ + +/* RAC */ +#define NTHW_MOD_RAC (0xae830b42UL) +#define RAC_DBG_CTRL (0x587273e2UL) +#define RAC_DBG_CTRL_C (0x4fe263UL) +#define RAC_DBG_DATA (0xf7a3f1fbUL) +#define RAC_DBG_DATA_D (0x69d9305UL) +#define RAC_DUMMY0 (0xd8e9ed5bUL) +#define RAC_DUMMY1 (0xafeeddcdUL) +#define RAC_DUMMY2 (0x36e78c77UL) +#define RAC_NDM_REGISTER (0x36b9e7d0UL) +#define RAC_NDM_REGISTER_NDM (0xf791ef23UL) +#define RAC_NMB_DATA (0xc0e60c69UL) +#define RAC_NMB_DATA_NMB_DATA (0x21f71466UL) +#define RAC_NMB_RD_ADR (0x274e1df2UL) +#define RAC_NMB_RD_ADR_ADR (0xf2e063d0UL) +#define RAC_NMB_RD_ADR_RES (0x829c7f2eUL) +#define RAC_NMB_STATUS (0x2070b64UL) +#define RAC_NMB_STATUS_BUS_TIMEOUT (0x7b220848UL) +#define RAC_NMB_STATUS_NMB_READY (0xe67a182bUL) +#define RAC_NMB_WR_ADR (0x9823ee63UL) +#define RAC_NMB_WR_ADR_ADR (0xcb13936fUL) +#define RAC_NMB_WR_ADR_RES (0xbb6f8f91UL) +#define RAC_RAB_BUF_FREE (0x60f7f2d8UL) +#define RAC_RAB_BUF_FREE_IB_FREE (0x4ddd870fUL) +#define RAC_RAB_BUF_FREE_IB_OVF (0x92388832UL) +#define RAC_RAB_BUF_FREE_OB_FREE (0x2e0db235UL) +#define RAC_RAB_BUF_FREE_OB_OVF (0x44616b2fUL) +#define RAC_RAB_BUF_FREE_TIMEOUT (0x1d0ae34eUL) +#define RAC_RAB_BUF_USED (0x549e5008UL) +#define RAC_RAB_BUF_USED_FLUSH (0xeb99f9baUL) +#define RAC_RAB_BUF_USED_IB_USED (0xd4c7d150UL) +#define RAC_RAB_BUF_USED_OB_USED (0xb717e46aUL) +#define RAC_RAB_DMA_IB_HI (0x3adf4e92UL) +#define RAC_RAB_DMA_IB_HI_PHYADDR (0x482070e9UL) +#define RAC_RAB_DMA_IB_LO (0xb7d02ea3UL) +#define RAC_RAB_DMA_IB_LO_PHYADDR (0x32d1a919UL) +#define RAC_RAB_DMA_IB_RD (0xf443c8f4UL) +#define RAC_RAB_DMA_IB_RD_PTR (0xa19bede2UL) +#define RAC_RAB_DMA_IB_WR (0x7de089e0UL) +#define RAC_RAB_DMA_IB_WR_PTR (0x1ef61e73UL) +#define RAC_RAB_DMA_OB_HI (0xb59fbb32UL) +#define RAC_RAB_DMA_OB_HI_PHYADDR (0xe8c5af34UL) +#define RAC_RAB_DMA_OB_LO (0x3890db03UL) +#define RAC_RAB_DMA_OB_LO_PHYADDR (0x923476c4UL) +#define RAC_RAB_DMA_OB_WR (0xf2a07c40UL) +#define RAC_RAB_DMA_OB_WR_PTR (0x6dec67f9UL) +#define RAC_RAB_IB_DATA (0xea524b52UL) +#define RAC_RAB_IB_DATA_D (0x52ecd3c6UL) +#define RAC_RAB_INIT (0x47d5556eUL) +#define RAC_RAB_INIT_RAB (0xda582a35UL) +#define RAC_RAB_OB_DATA (0x89827e68UL) +#define RAC_RAB_OB_DATA_D (0x21f6aa4cUL) + +#endif /* _NTHW_FPGA_REG_DEFS_RAC_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h new file mode 100644 index 0000000000..cd0668751c --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_rst9563.h @@ -0,0 +1,51 @@ +/* + * nthw_fpga_reg_defs_rst9563.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_RST9563_ +#define _NTHW_FPGA_REG_DEFS_RST9563_ + +/* RST9563 */ +#define NTHW_MOD_RST9563 (0x385d6d1dUL) +#define RST9563_CTRL (0x8fe7585fUL) +#define RST9563_CTRL_PTP_MMCM_CLKSEL (0xf441b405UL) +#define RST9563_CTRL_TS_CLKSEL (0x210e9a78UL) +#define RST9563_CTRL_TS_CLKSEL_OVERRIDE (0x304bbf3UL) +#define RST9563_POWER (0xdb6d3006UL) +#define RST9563_POWER_PU_NSEB (0x68a55de6UL) +#define RST9563_POWER_PU_PHY (0xdc0b7719UL) +#define RST9563_RST (0x366a2a03UL) +#define RST9563_RST_CORE_MMCM (0x4055af70UL) +#define RST9563_RST_DDR4 (0x367cad64UL) +#define RST9563_RST_MAC_RX (0x46da79e6UL) +#define RST9563_RST_PERIPH (0xd39d53bdUL) +#define RST9563_RST_PHY (0x50c57f90UL) +#define RST9563_RST_PTP (0xcf6e9a69UL) +#define RST9563_RST_PTP_MMCM (0xf69029c8UL) +#define RST9563_RST_RPP (0xa8868b03UL) +#define RST9563_RST_SDC (0x35477bfUL) +#define RST9563_RST_SYS (0xe18f0bc7UL) +#define RST9563_RST_SYS_MMCM (0x9f5c3d45UL) +#define RST9563_RST_TMC (0xd7d9da73UL) +#define RST9563_RST_TS (0x216dd0e7UL) +#define RST9563_RST_TSM_REF_MMCM (0x664f1a24UL) +#define RST9563_RST_TS_MMCM (0xce54ff59UL) +#define RST9563_STAT (0xad7dd604UL) +#define RST9563_STAT_CORE_MMCM_LOCKED (0xfd6d0a5aUL) +#define RST9563_STAT_DDR4_MMCM_LOCKED (0xb902f1d0UL) +#define RST9563_STAT_DDR4_PLL_LOCKED (0xe8a6d1b9UL) +#define RST9563_STAT_PTP_MMCM_LOCKED (0x4e4fd2a9UL) +#define RST9563_STAT_SYS_MMCM_LOCKED (0x5502a445UL) +#define RST9563_STAT_TS_MMCM_LOCKED (0xe6405b02UL) +#define RST9563_STICKY (0x97e2efe3UL) +#define RST9563_STICKY_CORE_MMCM_UNLOCKED (0xac340bb6UL) +#define RST9563_STICKY_DDR4_MMCM_UNLOCKED (0x4737148cUL) +#define RST9563_STICKY_DDR4_PLL_UNLOCKED (0xf9857d1bUL) +#define RST9563_STICKY_PTP_MMCM_UNLOCKED (0x2a4e9819UL) +#define RST9563_STICKY_SYS_MMCM_UNLOCKED (0x61e3ebbdUL) +#define RST9563_STICKY_TS_MMCM_UNLOCKED (0x7e9f941eUL) + +#endif /* _NTHW_FPGA_REG_DEFS_RST9563_ */ diff --git a/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h new file mode 100644 index 0000000000..d9cfff4128 --- /dev/null +++ b/drivers/net/ntnic/nthw/supported/nthw_fpga_reg_defs_sdc.h @@ -0,0 +1,36 @@ +/* + * nthw_fpga_reg_defs_sdc.h + * + * Auto-generated file - do *NOT* edit + * + */ + +#ifndef _NTHW_FPGA_REG_DEFS_SDC_ +#define _NTHW_FPGA_REG_DEFS_SDC_ + +/* SDC */ +#define NTHW_MOD_SDC (0xd2369530UL) +#define SDC_CELL_CNT (0xc6d82110UL) +#define SDC_CELL_CNT_CELL_CNT (0xdd4de629UL) +#define SDC_CELL_CNT_PERIOD (0x8dfef1d4UL) +#define SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD (0x2b5819c1UL) +#define SDC_CTRL (0x1577b205UL) +#define SDC_CTRL_INIT (0x70e62104UL) +#define SDC_CTRL_RESET_POINTERS (0xec1c0f9cUL) +#define SDC_CTRL_RUN_TEST (0x2efbe98eUL) +#define SDC_CTRL_STOP_CLIENT (0xb11ebe2dUL) +#define SDC_CTRL_TEST_EN (0xaa1fa4UL) +#define SDC_FILL_LVL (0xd3b30232UL) +#define SDC_FILL_LVL_FILL_LVL (0xc97281acUL) +#define SDC_MAX_FILL_LVL (0x326de743UL) +#define SDC_MAX_FILL_LVL_MAX_FILL_LVL (0x915fbf73UL) +#define SDC_STAT (0x37ed3c5eUL) +#define SDC_STAT_CALIB (0x27122e80UL) +#define SDC_STAT_CELL_CNT_STOPPED (0x517d5cafUL) +#define SDC_STAT_ERR_FOUND (0x3bb6bd0UL) +#define SDC_STAT_INIT_DONE (0x1dc2e095UL) +#define SDC_STAT_MMCM_LOCK (0xd9aac1c2UL) +#define SDC_STAT_PLL_LOCK (0x3bcab6ebUL) +#define SDC_STAT_RESETTING (0xa85349c1UL) + +#endif /* _NTHW_FPGA_REG_DEFS_SDC_ */ diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 42df15bd53..5d154c8e38 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -17,6 +17,7 @@ #include "ntdrv_4ga.h" #include "ntos_drv.h" #include "ntos_system.h" +#include "nthw_fpga_instances.h" #include "ntnic_vfio.h" #include "ntnic_mod_reg.h" #include "nt_util.h" From patchwork Wed Jul 17 13:32:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142468 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with 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account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org New ntnic FPGA modules: - Host Interface (HIF): Basic FPGA info such as prod ID and build time. - Inter-Integrated Circuit Controller (IIC): Use the FPGA to access the other integrated circuits on the ntnic. - PCI Express Gen3 (PCIE3): The FPGA part of PCIe3 initialization, speed tests, and configuration. Signed-off-by: Serhii Iliushyk --- v6 * Remove unnecessary comments v10 * Use 8 spaces as indentation in meson DVO: Remove unnecessary comments --- drivers/net/ntnic/meson.build | 1 + .../net/ntnic/nthw/core/include/nthw_core.h | 16 + .../net/ntnic/nthw/core/include/nthw_hif.h | 151 ++++ .../net/ntnic/nthw/core/include/nthw_iic.h | 100 +++ .../net/ntnic/nthw/core/include/nthw_pcie3.h | 96 +++ drivers/net/ntnic/nthw/core/nthw_hif.c | 312 +++++++ drivers/net/ntnic/nthw/core/nthw_iic.c | 527 ++++++++++++ drivers/net/ntnic/nthw/core/nthw_pcie3.c | 259 ++++++ drivers/net/ntnic/nthw/nthw_drv.h | 3 +- drivers/net/ntnic/nthw/nthw_rac.c | 784 ++++++++++++++++++ drivers/net/ntnic/nthw/nthw_rac.h | 153 ++++ 11 files changed, 2400 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_core.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_hif.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_iic.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_pcie3.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_hif.c create mode 100644 drivers/net/ntnic/nthw/core/nthw_iic.c create mode 100644 drivers/net/ntnic/nthw/core/nthw_pcie3.c create mode 100644 drivers/net/ntnic/nthw/nthw_rac.c create mode 100644 drivers/net/ntnic/nthw/nthw_rac.h diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 399b616278..a3522ca20b 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -13,6 +13,7 @@ includes = [ include_directories('include'), include_directories('ntlog'), include_directories('ntutil'), + include_directories('nthw/core/include'), include_directories('nthw'), include_directories('nthw/supported'), ] diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h new file mode 100644 index 0000000000..c2602e396f --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -0,0 +1,16 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_CORE_H__ +#define __NTHW_CORE_H__ + +#include +#include +#include + +#include "nthw_platform_drv.h" + + +#endif /* __NTHW_CORE_H__ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_hif.h b/drivers/net/ntnic/nthw/core/include/nthw_hif.h new file mode 100644 index 0000000000..c8f4669f83 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_hif.h @@ -0,0 +1,151 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_HIF_H__ +#define __NTHW_HIF_H__ + +#define NTHW_TG_CNT_SIZE (4ULL) + +struct nthw_hif { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_hif; + int mn_instance; + + nthw_register_t *mp_reg_ctrl; + nthw_field_t *mp_fld_ctrl_fsr; + + nthw_register_t *mp_reg_prod_id_lsb; + nthw_field_t *mp_fld_prod_id_lsb_rev_id; + nthw_field_t *mp_fld_prod_id_lsb_ver_id; + nthw_field_t *mp_fld_prod_id_lsb_group_id; + + nthw_register_t *mp_reg_prod_id_msb; + nthw_field_t *mp_fld_prod_id_msb_type_id; + nthw_field_t *mp_fld_prod_id_msb_build_no; + + nthw_register_t *mp_reg_build_time; + nthw_field_t *mp_fld_build_time; + + nthw_register_t *mp_reg_build_seed; + nthw_field_t *mp_fld_build_seed; + + nthw_register_t *mp_reg_core_speed; + nthw_field_t *mp_fld_core_speed; + nthw_field_t *mp_fld_ddr3_speed; + + nthw_register_t *mp_reg_int_mask; + nthw_field_t *mp_fld_int_mask_timer; + nthw_field_t *mp_fld_int_mask_port; + nthw_field_t *mp_fld_int_mask_pps; + + nthw_register_t *mp_reg_int_clr; + nthw_field_t *mp_fld_int_clr_timer; + nthw_field_t *mp_fld_int_clr_port; + nthw_field_t *mp_fld_int_clr_pps; + + nthw_register_t *mp_reg_int_force; + nthw_field_t *mp_fld_int_force_timer; + nthw_field_t *mp_fld_int_force_port; + nthw_field_t *mp_fld_int_force_pps; + + nthw_register_t *mp_reg_sample_time; + nthw_field_t *mp_fld_sample_time; + + nthw_register_t *mp_reg_status; + nthw_field_t *mp_fld_status_tags_in_use; + nthw_field_t *mp_fld_status_wr_err; + nthw_field_t *mp_fld_status_rd_err; + + nthw_register_t *mp_reg_stat_ctrl; + nthw_field_t *mp_fld_stat_ctrl_ena; + nthw_field_t *mp_fld_stat_ctrl_req; + + nthw_register_t *mp_reg_stat_rx; + nthw_field_t *mp_fld_stat_rx_counter; + + nthw_register_t *mp_reg_stat_tx; + nthw_field_t *mp_fld_stat_tx_counter; + + nthw_register_t *mp_reg_stat_ref_clk; + nthw_field_t *mp_fld_stat_ref_clk_ref_clk; + + nthw_register_t *mp_reg_pci_test0; + nthw_field_t *mp_fld_pci_test0; + + nthw_register_t *mp_reg_pci_test1; + nthw_field_t *mp_fld_pci_test1; + + nthw_register_t *mp_reg_pci_test2; + nthw_field_t *mp_fld_pci_test2; + + nthw_register_t *mp_reg_pci_test3; + nthw_field_t *mp_fld_pci_test3; + + nthw_register_t *mp_reg_config; + nthw_field_t *mp_fld_max_tlp; + nthw_field_t *mp_fld_max_read; + nthw_field_t *mp_fld_ext_tag; + + int mn_fpga_id_item; + int mn_fpga_id_prod; + int mn_fpga_id_ver; + int mn_fpga_id_rev; + int mn_fpga_id_build_no; + + int mn_fpga_param_hif_per_ps; + uint32_t mn_fpga_hif_ref_clk_freq; +}; + +typedef struct nthw_hif nthw_hif_t; + +struct nthw_hif_end_point_err_counters { + uint32_t n_err_correctable, n_err_non_fatal, n_err_fatal; +}; + +struct nthw_hif_end_point_counters { + int n_numa_node; + + int n_tg_direction; + int n_tg_pkt_size; + int n_tg_num_pkts; + int n_tg_delay; + + uint64_t cur_rx, cur_tx; + uint64_t cur_pci_nt_util, cur_pci_xil_util; + uint64_t n_ref_clk_cnt; + + uint64_t n_tags_in_use; + uint64_t n_rd_err; + uint64_t n_wr_err; + + struct nthw_hif_end_point_err_counters s_rc_ep_pre, s_rc_ep_post, s_rc_ep_delta; + struct nthw_hif_end_point_err_counters s_ep_rc_pre, s_ep_rc_post, s_ep_rc_delta; + + int bo_error; +}; + +struct nthw_hif_end_points { + struct nthw_hif_end_point_counters pri, sla; +}; + +nthw_hif_t *nthw_hif_new(void); +void nthw_hif_delete(nthw_hif_t *p); +int nthw_hif_init(nthw_hif_t *p, nthw_fpga_t *p_fpga, int n_instance); + +int nthw_hif_trigger_sample_time(nthw_hif_t *p); + +int nthw_hif_stat_req_enable(nthw_hif_t *p); +int nthw_hif_stat_req_disable(nthw_hif_t *p); + +int nthw_hif_get_stat(nthw_hif_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt, + uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq, + uint64_t *p_tags_in_use, uint64_t *p_rd_err, uint64_t *p_wr_err); +int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate, + uint64_t *p_ref_clk_cnt, uint64_t *p_tags_in_use, + uint64_t *p_rd_err_cnt, uint64_t *p_wr_err_cnt); + +int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_counters *epc); + +#endif /* __NTHW_HIF_H__ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_iic.h b/drivers/net/ntnic/nthw/core/include/nthw_iic.h new file mode 100644 index 0000000000..41574f51f3 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_iic.h @@ -0,0 +1,100 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_IIC_H__ +#define __NTHW_IIC_H__ + +#include "nthw_fpga_model.h" + +struct nthw_iic { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_iic; + int mn_iic_instance; + + uint32_t mn_iic_cycle_time; + int mn_poll_delay; + int mn_bus_ready_retry; + int mn_data_ready_retry; + int mn_read_data_retry; + int mn_write_data_retry; + + nthw_register_t *mp_reg_tsusta; + nthw_field_t *mp_fld_tsusta; + + nthw_register_t *mp_reg_tsusto; + nthw_field_t *mp_fld_tsusto; + + nthw_register_t *mp_reg_thdsta; + nthw_field_t *mp_fld_thdsta; + + nthw_register_t *mp_reg_tsudat; + nthw_field_t *mp_fld_tsudat; + + nthw_register_t *mp_reg_tbuf; + nthw_field_t *mp_fld_tbuf; + + nthw_register_t *mp_reg_thigh; + nthw_field_t *mp_fld_thigh; + + nthw_register_t *mp_reg_tlow; + nthw_field_t *mp_fld_tlow; + + nthw_register_t *mp_reg_thddat; + nthw_field_t *mp_fld_thddat; + + nthw_register_t *mp_reg_cr; + nthw_field_t *mp_fld_cr_en; + nthw_field_t *mp_fld_cr_msms; + nthw_field_t *mp_fld_cr_txfifo_reset; + nthw_field_t *mp_fld_cr_txak; + + nthw_register_t *mp_reg_sr; + nthw_field_t *mp_fld_sr_bb; + nthw_field_t *mp_fld_sr_rxfifo_full; + nthw_field_t *mp_fld_sr_rxfifo_empty; + nthw_field_t *mp_fld_sr_txfifo_full; + nthw_field_t *mp_fld_sr_txfifo_empty; + + nthw_register_t *mp_reg_tx_fifo; + nthw_field_t *mp_fld_tx_fifo_txdata; + nthw_field_t *mp_fld_tx_fifo_start; + nthw_field_t *mp_fld_tx_fifo_stop; + + nthw_register_t *mp_reg_rx_fifo_pirq; + nthw_field_t *mp_fld_rx_fifo_pirq_cmp_val; + + nthw_register_t *mp_reg_rx_fifo; + nthw_field_t *mp_fld_rx_fifo_rxdata; + + nthw_register_t *mp_reg_softr; + nthw_field_t *mp_fld_softr_rkey; +}; + +typedef struct nthw_iic nthw_iic_t; + +nthw_iic_t *nthw_iic_new(void); +int nthw_iic_init(nthw_iic_t *p, nthw_fpga_t *p_fpga, int n_iic_instance, + uint32_t n_iic_cycle_time); +void nthw_iic_delete(nthw_iic_t *p); + +int nthw_iic_set_retry_params(nthw_iic_t *p, const int n_poll_delay, const int n_bus_ready_retry, + const int n_data_ready_retry, const int n_read_data_retry, + const int n_write_data_retry); + +int nthw_iic_read_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + void *p_void); +int nthw_iic_readbyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + uint8_t *p_byte); +int nthw_iic_write_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + void *p_void); +int nthw_iic_writebyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + uint8_t *p_byte); +bool nthw_iic_bus_ready(nthw_iic_t *p); +bool nthw_iic_data_ready(nthw_iic_t *p); + +int nthw_iic_scan(nthw_iic_t *p); +int nthw_iic_scan_dev_addr(nthw_iic_t *p, int n_dev_addr, int n_reg_addr); + +#endif /* __NTHW_IIC_H__ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h b/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h new file mode 100644 index 0000000000..846c09b1b9 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_pcie3.h @@ -0,0 +1,96 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_PCIE3_H__ +#define __NTHW_PCIE3_H__ + +struct nthw_pcie3 { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_pcie3; + int mn_instance; + + nthw_register_t *mp_reg_stat_ctrl; + nthw_field_t *mp_fld_stat_ctrl_req; + nthw_field_t *mp_fld_stat_ctrl_ena; + + nthw_register_t *mp_reg_stat_rx; + nthw_field_t *mp_fld_stat_rx_counter; + + nthw_register_t *mp_reg_stat_tx; + nthw_field_t *mp_fld_stat_tx_counter; + + nthw_register_t *mp_reg_stat_rq_rdy; + nthw_field_t *mp_fld_stat_rq_rdy_counter; + + nthw_register_t *mp_reg_stat_rq_vld; + nthw_field_t *mp_fld_stat_rq_vld_counter; + + nthw_register_t *mp_reg_status0; + nthw_field_t *mp_fld_status0_tags_in_use; + + nthw_register_t *mp_reg_stat_ref_clk; + nthw_field_t *mp_fld_stat_ref_clk_ref_clk; + + nthw_register_t *mp_reg_rp_to_ep_err; + nthw_field_t *mp_fld_rp_to_ep_err_cor; + nthw_field_t *mp_fld_rp_to_ep_err_non_fatal; + nthw_field_t *mp_fld_rp_to_ep_err_fatal; + + nthw_register_t *mp_reg_ep_to_rp_err; + nthw_field_t *mp_fld_ep_to_rp_err_cor; + nthw_field_t *mp_fld_ep_to_rp_err_non_fatal; + nthw_field_t *mp_fld_ep_to_rp_err_fatal; + + nthw_register_t *mp_reg_sample_time; + nthw_field_t *mp_fld_sample_time; + + nthw_register_t *mp_reg_pci_end_point; + nthw_field_t *mp_fld_pci_end_point_if_id; + nthw_field_t *mp_fld_pci_end_point_send_msg; + nthw_field_t *mp_fld_pci_end_point_get_msg; + nthw_field_t *mp_fld_pci_end_point_dmaep0_allow_mask; + nthw_field_t *mp_fld_pci_end_point_dmaep1_allow_mask; + + nthw_register_t *mp_reg_pci_e3_mark_adr_lsb; + nthw_field_t *mp_fld_pci_e3_mark_adr_lsb_adr; + + nthw_register_t *mp_reg_pci_e3_mark_adr_msb; + nthw_field_t *mp_fld_pci_e3_mark_adr_msb_adr; + + nthw_register_t *mp_reg_pci_test0; + nthw_field_t *mp_fld_pci_test0; + + nthw_register_t *mp_reg_pci_test1; + nthw_field_t *mp_fld_pci_test1; + + nthw_register_t *mp_reg_pci_test2; + nthw_field_t *mp_fld_pci_test2; + + nthw_register_t *mp_reg_pci_test3; + nthw_field_t *mp_fld_pci_test3; +}; + +typedef struct nthw_pcie3 nthw_pcie3_t; + +nthw_pcie3_t *nthw_pcie3_new(void); +void nthw_pcie3_delete(nthw_pcie3_t *p); +int nthw_pcie3_init(nthw_pcie3_t *p, nthw_fpga_t *p_fpga, int n_instance); + +int nthw_pcie3_trigger_sample_time(nthw_pcie3_t *p); + +int nthw_pcie3_stat_req_enable(nthw_pcie3_t *p); +int nthw_pcie3_stat_req_disable(nthw_pcie3_t *p); + +int nthw_pcie3_get_stat(nthw_pcie3_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt, + uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq, + uint32_t *p_tag_use_cnt, uint32_t *p_rq_rdy_cnt, uint32_t *p_rq_vld_cnt); +int nthw_pcie3_get_stat_rate(nthw_pcie3_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate, + uint64_t *p_ref_clk_cnt, uint64_t *p_tag_use_cnt, + uint64_t *p_pci_nt_bus_util, uint64_t *p_pci_xil_bus_util); + +int nthw_pcie3_end_point_counters_sample_post(nthw_pcie3_t *p, + struct nthw_hif_end_point_counters *epc); + +#endif /* __NTHW_PCIE3_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_hif.c b/drivers/net/ntnic/nthw/core/nthw_hif.c new file mode 100644 index 0000000000..f05e1a0c51 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_hif.c @@ -0,0 +1,312 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_hif.h" + +nthw_hif_t *nthw_hif_new(void) +{ + nthw_hif_t *p = malloc(sizeof(nthw_hif_t)); + + if (p) + memset(p, 0, sizeof(nthw_hif_t)); + + return p; +} + +void nthw_hif_delete(nthw_hif_t *p) +{ + if (p) { + memset(p, 0, sizeof(nthw_hif_t)); + free(p); + } +} + +int nthw_hif_init(nthw_hif_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + (void)p_adapter_id_str; + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_HIF, n_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: HIF %d: no such instance\n", + p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_hif = mod; + + /* default for (Xilinx-based) products until august 2022: (1e6/4000 = 250 MHz) */ + p->mn_fpga_param_hif_per_ps = nthw_fpga_get_product_param(p->mp_fpga, NT_HIF_PER_PS, 4000); + p->mn_fpga_hif_ref_clk_freq = + (uint32_t)(1000000000000ULL / (unsigned int)p->mn_fpga_param_hif_per_ps); + + p->mp_reg_prod_id_lsb = nthw_module_get_register(p->mp_mod_hif, HIF_PROD_ID_LSB); + p->mp_fld_prod_id_lsb_rev_id = + nthw_register_get_field(p->mp_reg_prod_id_lsb, HIF_PROD_ID_LSB_REV_ID); + p->mp_fld_prod_id_lsb_ver_id = + nthw_register_get_field(p->mp_reg_prod_id_lsb, HIF_PROD_ID_LSB_VER_ID); + p->mp_fld_prod_id_lsb_group_id = + nthw_register_get_field(p->mp_reg_prod_id_lsb, HIF_PROD_ID_LSB_GROUP_ID); + + p->mp_reg_prod_id_msb = nthw_module_get_register(p->mp_mod_hif, HIF_PROD_ID_MSB); + p->mp_fld_prod_id_msb_type_id = + nthw_register_get_field(p->mp_reg_prod_id_msb, HIF_PROD_ID_MSB_TYPE_ID); + p->mp_fld_prod_id_msb_build_no = + nthw_register_get_field(p->mp_reg_prod_id_msb, HIF_PROD_ID_MSB_BUILD_NO); + + p->mp_reg_build_time = nthw_module_get_register(p->mp_mod_hif, HIF_BUILD_TIME); + p->mp_fld_build_time = nthw_register_get_field(p->mp_reg_build_time, HIF_BUILD_TIME_TIME); + + p->mn_fpga_id_prod = nthw_field_get_updated(p->mp_fld_prod_id_lsb_group_id); + p->mn_fpga_id_ver = nthw_field_get_updated(p->mp_fld_prod_id_lsb_ver_id); + p->mn_fpga_id_rev = nthw_field_get_updated(p->mp_fld_prod_id_lsb_rev_id); + p->mn_fpga_id_build_no = nthw_field_get_updated(p->mp_fld_prod_id_msb_build_no); + p->mn_fpga_id_item = nthw_field_get_updated(p->mp_fld_prod_id_msb_type_id); + + NT_LOG(DBG, NTHW, "%s: HIF %d: %d-%d-%d-%d-%d\n", p_adapter_id_str, p->mn_instance, + p->mn_fpga_id_item, p->mn_fpga_id_prod, p->mn_fpga_id_ver, + p->mn_fpga_id_rev, p->mn_fpga_id_build_no); + NT_LOG(DBG, NTHW, "%s: HIF %d: HIF ref clock: %d Hz (%d ticks/ps)\n", p_adapter_id_str, + p->mn_instance, p->mn_fpga_hif_ref_clk_freq, p->mn_fpga_param_hif_per_ps); + + p->mp_reg_build_seed = NULL; /* Reg/Fld not present on HIF */ + + if (p->mp_reg_build_seed) + p->mp_fld_build_seed = NULL; /* Reg/Fld not present on HIF */ + else + p->mp_fld_build_seed = NULL; + + p->mp_reg_core_speed = NULL; /* Reg/Fld not present on HIF */ + + if (p->mp_reg_core_speed) { + p->mp_fld_core_speed = NULL; /* Reg/Fld not present on HIF */ + p->mp_fld_ddr3_speed = NULL; /* Reg/Fld not present on HIF */ + + } else { + p->mp_reg_core_speed = NULL; + p->mp_fld_core_speed = NULL; + p->mp_fld_ddr3_speed = NULL; + } + + /* Optional registers since: 2018-04-25 */ + p->mp_reg_int_mask = NULL; /* Reg/Fld not present on HIF */ + p->mp_reg_int_clr = NULL; /* Reg/Fld not present on HIF */ + p->mp_reg_int_force = NULL; /* Reg/Fld not present on HIF */ + + p->mp_fld_int_mask_timer = NULL; + p->mp_fld_int_clr_timer = NULL; + p->mp_fld_int_force_timer = NULL; + + p->mp_fld_int_mask_port = NULL; + p->mp_fld_int_clr_port = NULL; + p->mp_fld_int_force_port = NULL; + + p->mp_fld_int_mask_pps = NULL; + p->mp_fld_int_clr_pps = NULL; + p->mp_fld_int_force_pps = NULL; + + p->mp_reg_ctrl = nthw_module_get_register(p->mp_mod_hif, HIF_CONTROL); + p->mp_fld_ctrl_fsr = nthw_register_query_field(p->mp_reg_ctrl, HIF_CONTROL_FSR); + + p->mp_reg_stat_ctrl = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_CTRL); + p->mp_fld_stat_ctrl_ena = + nthw_register_get_field(p->mp_reg_stat_ctrl, HIF_STAT_CTRL_STAT_ENA); + p->mp_fld_stat_ctrl_req = + nthw_register_get_field(p->mp_reg_stat_ctrl, HIF_STAT_CTRL_STAT_REQ); + + p->mp_reg_stat_rx = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_RX); + p->mp_fld_stat_rx_counter = + nthw_register_get_field(p->mp_reg_stat_rx, HIF_STAT_RX_COUNTER); + + p->mp_reg_stat_tx = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_TX); + p->mp_fld_stat_tx_counter = + nthw_register_get_field(p->mp_reg_stat_tx, HIF_STAT_TX_COUNTER); + + p->mp_reg_stat_ref_clk = nthw_module_get_register(p->mp_mod_hif, HIF_STAT_REFCLK); + p->mp_fld_stat_ref_clk_ref_clk = + nthw_register_get_field(p->mp_reg_stat_ref_clk, HIF_STAT_REFCLK_REFCLK250); + + p->mp_reg_status = nthw_module_query_register(p->mp_mod_hif, HIF_STATUS); + + if (p->mp_reg_status) { + p->mp_fld_status_tags_in_use = + nthw_register_query_field(p->mp_reg_status, HIF_STATUS_TAGS_IN_USE); + p->mp_fld_status_wr_err = + nthw_register_query_field(p->mp_reg_status, HIF_STATUS_WR_ERR); + p->mp_fld_status_rd_err = + nthw_register_query_field(p->mp_reg_status, HIF_STATUS_RD_ERR); + + } else { + p->mp_reg_status = nthw_module_query_register(p->mp_mod_hif, HIF_STATUS); + p->mp_fld_status_tags_in_use = + nthw_register_query_field(p->mp_reg_status, HIF_STATUS_TAGS_IN_USE); + p->mp_fld_status_wr_err = NULL; + p->mp_fld_status_rd_err = NULL; + } + + p->mp_reg_pci_test0 = nthw_module_get_register(p->mp_mod_hif, HIF_TEST0); + p->mp_fld_pci_test0 = nthw_register_get_field(p->mp_reg_pci_test0, HIF_TEST0_DATA); + + p->mp_reg_pci_test1 = nthw_module_get_register(p->mp_mod_hif, HIF_TEST1); + p->mp_fld_pci_test1 = nthw_register_get_field(p->mp_reg_pci_test1, HIF_TEST1_DATA); + + /* Module::Version({2, 0})+ */ + p->mp_reg_pci_test2 = nthw_module_query_register(p->mp_mod_hif, HIF_TEST2); + + if (p->mp_reg_pci_test2) + p->mp_fld_pci_test2 = nthw_register_get_field(p->mp_reg_pci_test2, HIF_TEST2_DATA); + + else + p->mp_fld_pci_test2 = NULL; + + /* Module::Version({1, 2})+ */ + p->mp_reg_pci_test3 = nthw_module_query_register(p->mp_mod_hif, HIF_TEST3); + + if (p->mp_reg_pci_test3) + p->mp_fld_pci_test3 = nthw_register_get_field(p->mp_reg_pci_test3, HIF_TEST3_DATA); + + else + p->mp_fld_pci_test3 = NULL; + + /* Required to run TSM */ + p->mp_reg_sample_time = nthw_module_get_register(p->mp_mod_hif, HIF_SAMPLE_TIME); + + if (p->mp_reg_sample_time) { + p->mp_fld_sample_time = nthw_register_get_field(p->mp_reg_sample_time, + HIF_SAMPLE_TIME_SAMPLE_TIME); + + } else { + p->mp_fld_sample_time = NULL; + } + + /* We need to optimize PCIe3 TLP-size read-request and extended tag usage */ + { + p->mp_reg_config = nthw_module_query_register(p->mp_mod_hif, HIF_CONFIG); + + if (p->mp_reg_config) { + p->mp_fld_max_tlp = + nthw_register_get_field(p->mp_reg_config, HIF_CONFIG_MAX_TLP); + p->mp_fld_max_read = + nthw_register_get_field(p->mp_reg_config, HIF_CONFIG_MAX_READ); + p->mp_fld_ext_tag = + nthw_register_get_field(p->mp_reg_config, HIF_CONFIG_EXT_TAG); + + } else { + p->mp_fld_max_tlp = NULL; + p->mp_fld_max_read = NULL; + p->mp_fld_ext_tag = NULL; + } + } + + return 0; +} + +int nthw_hif_trigger_sample_time(nthw_hif_t *p) +{ + nthw_field_set_val_flush32(p->mp_fld_sample_time, 0xfee1dead); + + return 0; +} + +int nthw_hif_get_stat(nthw_hif_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt, + uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq, + uint64_t *p_tags_in_use, uint64_t *p_rd_err, uint64_t *p_wr_err) +{ + *p_rx_cnt = nthw_field_get_updated(p->mp_fld_stat_rx_counter); + *p_tx_cnt = nthw_field_get_updated(p->mp_fld_stat_tx_counter); + + *p_ref_clk_cnt = nthw_field_get_updated(p->mp_fld_stat_ref_clk_ref_clk); + + *p_tg_unit_size = NTHW_TG_CNT_SIZE; + *p_tg_ref_freq = p->mn_fpga_hif_ref_clk_freq; + + *p_tags_in_use = (p->mp_fld_status_tags_in_use + ? nthw_field_get_updated(p->mp_fld_status_tags_in_use) + : 0); + + *p_rd_err = + (p->mp_fld_status_rd_err ? nthw_field_get_updated(p->mp_fld_status_rd_err) : 0); + *p_wr_err = + (p->mp_fld_status_wr_err ? nthw_field_get_updated(p->mp_fld_status_wr_err) : 0); + + return 0; +} + +int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate, + uint64_t *p_ref_clk_cnt, uint64_t *p_tags_in_use, + uint64_t *p_rd_err_cnt, uint64_t *p_wr_err_cnt) +{ + uint32_t rx_cnt, tx_cnt, ref_clk_cnt, tg_unit_size, tg_ref_freq; + uint64_t n_tags_in_use, n_rd_err, n_wr_err; + + nthw_hif_get_stat(p, &rx_cnt, &tx_cnt, &ref_clk_cnt, &tg_unit_size, &tg_ref_freq, + &n_tags_in_use, &n_rd_err, &n_wr_err); + + *p_tags_in_use = n_tags_in_use; + + if (n_rd_err) + (*p_rd_err_cnt)++; + + if (n_wr_err) + (*p_wr_err_cnt)++; + + if (ref_clk_cnt) { + uint64_t rx_rate; + uint64_t tx_rate; + + *p_ref_clk_cnt = ref_clk_cnt; + + rx_rate = ((uint64_t)rx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt; + *p_pci_rx_rate = rx_rate; + + tx_rate = ((uint64_t)tx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt; + *p_pci_tx_rate = tx_rate; + + } else { + *p_pci_rx_rate = 0; + *p_pci_tx_rate = 0; + *p_ref_clk_cnt = 0; + } + + return 0; +} + +int nthw_hif_stat_req_enable(nthw_hif_t *p) +{ + nthw_field_set_all(p->mp_fld_stat_ctrl_ena); + nthw_field_set_all(p->mp_fld_stat_ctrl_req); + nthw_field_flush_register(p->mp_fld_stat_ctrl_req); + return 0; +} + +int nthw_hif_stat_req_disable(nthw_hif_t *p) +{ + nthw_field_clr_all(p->mp_fld_stat_ctrl_ena); + nthw_field_set_all(p->mp_fld_stat_ctrl_req); + nthw_field_flush_register(p->mp_fld_stat_ctrl_req); + return 0; +} + +int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct nthw_hif_end_point_counters *epc) +{ + assert(epc); + + /* Get stat rate and maintain rx/tx min/max */ + nthw_hif_get_stat_rate(p, &epc->cur_tx, &epc->cur_rx, &epc->n_ref_clk_cnt, + &epc->n_tags_in_use, &epc->n_rd_err, &epc->n_wr_err); + + return 0; +} diff --git a/drivers/net/ntnic/nthw/core/nthw_iic.c b/drivers/net/ntnic/nthw/core/nthw_iic.c new file mode 100644 index 0000000000..7f324dec78 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_iic.c @@ -0,0 +1,527 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_iic.h" + +#define I2C_TRANSMIT_WR (0x00) +#define I2C_TRANSMIT_RD (0x01) + +#define I2C_WAIT_US(x) nt_os_wait_usec(x) + +/* + * Minimum timing values for I2C for a Marvel 88E11111 Phy. + * This Phy is used in many Trispeed NIMs. + * In order to access this Phy, the I2C clock speed is needed to be set to 100KHz. + */ +static const uint32_t SUSTA = 4700; /* ns */ +static const uint32_t SUSTO = 4000; /* ns */ +static const uint32_t HDSTA = 4000; /* ns */ +static const uint32_t SUDAT = 250; /* ns */ +static const uint32_t BUF = 4700; /* ns */ +static const uint32_t HIGH = 4000; /* ns */ +static const uint32_t LOW = 4700; /* ns */ +static const uint32_t HDDAT = 300; /* ns */ + +static int nthw_iic_reg_control_txfifo_reset(nthw_iic_t *p) +{ + nthw_field_update_register(p->mp_fld_cr_txfifo_reset); + + nthw_field_set_all(p->mp_fld_cr_txfifo_reset); + nthw_field_flush_register(p->mp_fld_cr_txfifo_reset); + + nthw_field_clr_all(p->mp_fld_cr_txfifo_reset); + nthw_field_flush_register(p->mp_fld_cr_txfifo_reset); + + return 0; +} + +static int nthw_iic_reg_tx_fifo_write(nthw_iic_t *p, uint32_t data, bool start, bool stop) +{ + if (start) + nthw_field_set_all(p->mp_fld_tx_fifo_start); + + else + nthw_field_clr_all(p->mp_fld_tx_fifo_start); + + if (stop) + nthw_field_set_all(p->mp_fld_tx_fifo_stop); + + else + nthw_field_clr_all(p->mp_fld_tx_fifo_stop); + + nthw_field_set_val32(p->mp_fld_tx_fifo_txdata, data); + + nthw_register_flush(p->mp_reg_tx_fifo, 1); + + return 0; +} + +static int nthw_iic_reg_read_i2c_rx_fifo(nthw_iic_t *p, uint8_t *p_data) +{ + assert(p_data); + + *p_data = (uint8_t)nthw_field_get_updated(p->mp_fld_rx_fifo_rxdata); + + return 0; +} + +static int nthw_iic_reg_softr(nthw_iic_t *p) +{ + nthw_field_update_register(p->mp_fld_cr_en); + nthw_field_set_val_flush32(p->mp_fld_softr_rkey, 0x0A); + + return 0; +} + +static int nthw_iic_reg_enable(nthw_iic_t *p) +{ + nthw_field_update_register(p->mp_fld_cr_en); + nthw_field_set_flush(p->mp_fld_cr_en); + + return 0; +} + +static int nthw_iic_reg_busbusy(nthw_iic_t *p, bool *pb_flag) +{ + assert(pb_flag); + + *pb_flag = nthw_field_get_updated(p->mp_fld_sr_bb) ? true : false; + + return 0; +} + +static int nthw_iic_reg_rxfifo_empty(nthw_iic_t *p, bool *pb_flag) +{ + assert(pb_flag); + + *pb_flag = nthw_field_get_updated(p->mp_fld_sr_rxfifo_empty) ? true : false; + + return 0; +} + +/* + * n_iic_cycle_time is the I2C clock cycle time in ns ie 125MHz = 8ns + */ +static int nthw_iic_reg_set_timing(nthw_iic_t *p, uint32_t n_iic_cycle_time) +{ + uint32_t val; + + val = SUSTA / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_tsusta, &val, 1); + + val = SUSTO / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_tsusto, &val, 1); + + val = HDSTA / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_thdsta, &val, 1); + + val = SUDAT / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_tsudat, &val, 1); + + val = BUF / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_tbuf, &val, 1); + + val = HIGH / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_thigh, &val, 1); + + val = LOW / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_tlow, &val, 1); + + val = HDDAT / n_iic_cycle_time; + nthw_field_set_val_flush(p->mp_fld_thddat, &val, 1); + + return 0; +} + +nthw_iic_t *nthw_iic_new(void) +{ + nthw_iic_t *p = malloc(sizeof(nthw_iic_t)); + + if (p) + memset(p, 0, sizeof(nthw_iic_t)); + + return p; +} + +int nthw_iic_init(nthw_iic_t *p, nthw_fpga_t *p_fpga, int n_iic_instance, + uint32_t n_iic_cycle_time) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_IIC, n_iic_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: I2C %d: no such instance\n", p_adapter_id_str, + n_iic_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_iic_instance = n_iic_instance; + + p->mn_iic_cycle_time = n_iic_cycle_time; + + nthw_iic_set_retry_params(p, -1, -1, -1, -1, -1); + + p->mp_mod_iic = mod; + + /* I2C is a primary communication channel - turn off debug by default */ + nthw_module_set_debug_mode(p->mp_mod_iic, 0x00); + + p->mp_reg_tsusta = nthw_module_get_register(p->mp_mod_iic, IIC_TSUSTA); + p->mp_fld_tsusta = nthw_register_get_field(p->mp_reg_tsusta, IIC_TSUSTA_TSUSTA_VAL); + + p->mp_reg_tsusto = nthw_module_get_register(p->mp_mod_iic, IIC_TSUSTO); + p->mp_fld_tsusto = nthw_register_get_field(p->mp_reg_tsusto, IIC_TSUSTO_TSUSTO_VAL); + + p->mp_reg_thdsta = nthw_module_get_register(p->mp_mod_iic, IIC_THDSTA); + p->mp_fld_thdsta = nthw_register_get_field(p->mp_reg_thdsta, IIC_THDSTA_THDSTA_VAL); + + p->mp_reg_tsudat = nthw_module_get_register(p->mp_mod_iic, IIC_TSUDAT); + p->mp_fld_tsudat = nthw_register_get_field(p->mp_reg_tsudat, IIC_TSUDAT_TSUDAT_VAL); + + p->mp_reg_tbuf = nthw_module_get_register(p->mp_mod_iic, IIC_TBUF); + p->mp_fld_tbuf = nthw_register_get_field(p->mp_reg_tbuf, IIC_TBUF_TBUF_VAL); + + p->mp_reg_thigh = nthw_module_get_register(p->mp_mod_iic, IIC_THIGH); + p->mp_fld_thigh = nthw_register_get_field(p->mp_reg_thigh, IIC_THIGH_THIGH_VAL); + + p->mp_reg_tlow = nthw_module_get_register(p->mp_mod_iic, IIC_TLOW); + p->mp_fld_tlow = nthw_register_get_field(p->mp_reg_tlow, IIC_TLOW_TLOW_VAL); + + p->mp_reg_thddat = nthw_module_get_register(p->mp_mod_iic, IIC_THDDAT); + p->mp_fld_thddat = nthw_register_get_field(p->mp_reg_thddat, IIC_THDDAT_THDDAT_VAL); + + p->mp_reg_cr = nthw_module_get_register(p->mp_mod_iic, IIC_CR); + p->mp_fld_cr_en = nthw_register_get_field(p->mp_reg_cr, IIC_CR_EN); + p->mp_fld_cr_msms = nthw_register_get_field(p->mp_reg_cr, IIC_CR_MSMS); + p->mp_fld_cr_txfifo_reset = nthw_register_get_field(p->mp_reg_cr, IIC_CR_TXFIFO_RESET); + p->mp_fld_cr_txak = nthw_register_get_field(p->mp_reg_cr, IIC_CR_TXAK); + + p->mp_reg_sr = nthw_module_get_register(p->mp_mod_iic, IIC_SR); + p->mp_fld_sr_bb = nthw_register_get_field(p->mp_reg_sr, IIC_SR_BB); + p->mp_fld_sr_rxfifo_full = nthw_register_get_field(p->mp_reg_sr, IIC_SR_RXFIFO_FULL); + p->mp_fld_sr_rxfifo_empty = nthw_register_get_field(p->mp_reg_sr, IIC_SR_RXFIFO_EMPTY); + p->mp_fld_sr_txfifo_full = nthw_register_get_field(p->mp_reg_sr, IIC_SR_TXFIFO_FULL); + p->mp_fld_sr_txfifo_empty = nthw_register_get_field(p->mp_reg_sr, IIC_SR_TXFIFO_EMPTY); + + p->mp_reg_tx_fifo = nthw_module_get_register(p->mp_mod_iic, IIC_TX_FIFO); + p->mp_fld_tx_fifo_txdata = nthw_register_get_field(p->mp_reg_tx_fifo, IIC_TX_FIFO_TXDATA); + p->mp_fld_tx_fifo_start = nthw_register_get_field(p->mp_reg_tx_fifo, IIC_TX_FIFO_START); + p->mp_fld_tx_fifo_stop = nthw_register_get_field(p->mp_reg_tx_fifo, IIC_TX_FIFO_STOP); + + p->mp_reg_rx_fifo_pirq = nthw_module_get_register(p->mp_mod_iic, IIC_RX_FIFO_PIRQ); + p->mp_fld_rx_fifo_pirq_cmp_val = + nthw_register_get_field(p->mp_reg_rx_fifo_pirq, IIC_RX_FIFO_PIRQ_CMP_VAL); + + p->mp_reg_rx_fifo = nthw_module_get_register(p->mp_mod_iic, IIC_RX_FIFO); + p->mp_fld_rx_fifo_rxdata = nthw_register_get_field(p->mp_reg_rx_fifo, IIC_RX_FIFO_RXDATA); + + p->mp_reg_softr = nthw_module_get_register(p->mp_mod_iic, IIC_SOFTR); + p->mp_fld_softr_rkey = nthw_register_get_field(p->mp_reg_softr, IIC_SOFTR_RKEY); + + /* + * Initialize I2C controller by applying soft reset and enable the controller + */ + nthw_iic_reg_softr(p); + /* Enable the controller */ + nthw_iic_reg_enable(p); + + /* Setup controller timing */ + if (p->mn_iic_cycle_time) { + NT_LOG(DBG, NTHW, "%s: I2C%d: cycletime=%d\n", p_adapter_id_str, + p->mn_iic_instance, p->mn_iic_cycle_time); + nthw_iic_reg_set_timing(p, p->mn_iic_cycle_time); + } + + /* Reset TX fifo - must be after enable */ + nthw_iic_reg_control_txfifo_reset(p); + nthw_iic_reg_tx_fifo_write(p, 0, 0, 0); + + return 0; +} + +void nthw_iic_delete(nthw_iic_t *p) +{ + if (p) { + memset(p, 0, sizeof(nthw_iic_t)); + free(p); + } +} + +int nthw_iic_set_retry_params(nthw_iic_t *p, const int n_poll_delay, const int n_bus_ready_retry, + const int n_data_ready_retry, const int n_read_data_retry, + const int n_write_data_retry) +{ + p->mn_poll_delay = n_poll_delay >= 0 ? n_poll_delay : 10; + + p->mn_bus_ready_retry = n_bus_ready_retry >= 0 ? n_bus_ready_retry : 1000; + p->mn_data_ready_retry = n_data_ready_retry >= 0 ? n_data_ready_retry : 1000; + + p->mn_read_data_retry = n_read_data_retry >= 0 ? n_read_data_retry : 10; + p->mn_write_data_retry = n_write_data_retry >= 0 ? n_write_data_retry : 10; + + return 0; +} + +int nthw_iic_read_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + void *p_void) +{ + const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str; + const int n_debug_mode = nthw_module_get_debug_mode(p->mp_mod_iic); + + uint8_t *pb = (uint8_t *)p_void; + int retry = (p->mn_read_data_retry >= 0 ? p->mn_read_data_retry : 10); + + if (n_debug_mode == 0xff) { + NT_LOG(DBG, NTHW, "%s: adr=0x%2.2x, reg=%d, len=%d\n", p_adapter_id_str, dev_addr, + a_reg_addr, data_len); + } + + while (nthw_iic_readbyte(p, dev_addr, a_reg_addr, data_len, pb) != 0) { + retry--; + + if (retry <= 0) { + NT_LOG(ERR, NTHW, + "%s: I2C%d: Read retry exhausted (dev_addr=%d a_reg_addr=%d)\n", + p_adapter_id_str, p->mn_iic_instance, dev_addr, a_reg_addr); + return -1; + + } else { + NT_LOG(DBG, NTHW, "%s: I2C%d: Read retry=%d (dev_addr=%d a_reg_addr=%d)\n", + p_adapter_id_str, p->mn_iic_instance, retry, dev_addr, a_reg_addr); + } + } + + if (n_debug_mode == 0xff) { + NT_LOG(DBG, NTHW, "%s: adr=0x%2.2x, reg=%d, len=%d, retries remaining: %d\n", + p_adapter_id_str, dev_addr, a_reg_addr, data_len, retry); + } + + return 0; +} + +int nthw_iic_readbyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + uint8_t *p_byte) +{ + const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str; + + uint32_t value; + uint32_t i; + + if (nthw_iic_bus_ready(p)) { + /* Reset TX fifo */ + nthw_iic_reg_control_txfifo_reset(p); + + /* Write device address to TX_FIFO and set start bit!! */ + value = (dev_addr << 1) | I2C_TRANSMIT_WR; + nthw_iic_reg_tx_fifo_write(p, value, 1, 0); + + /* Write a_reg_addr to TX FIFO */ + nthw_iic_reg_tx_fifo_write(p, a_reg_addr, 0, 1); + + if (!nthw_iic_bus_ready(p)) { + NT_LOG_DBGX(ERR, NTHW, "%s: error:\n", p_adapter_id_str); + return -1; + } + + /* Write device address + RD bit to TX_FIFO and set start bit!! */ + value = (dev_addr << 1) | I2C_TRANSMIT_RD; + nthw_iic_reg_tx_fifo_write(p, value, 1, 0); + + /* Write data_len to TX_FIFO and set stop bit!! */ + nthw_iic_reg_tx_fifo_write(p, data_len, 0, 1); + + for (i = 0; i < data_len; i++) { + /* Wait for RX FIFO not empty */ + if (!nthw_iic_data_ready(p)) + return -1; + + /* Read data_len bytes from RX_FIFO */ + nthw_iic_reg_read_i2c_rx_fifo(p, p_byte); + p_byte++; + } + + return 0; + + } else { + NT_LOG_DBGX(ERR, NTHW, "%s: error\n", p_adapter_id_str); + return -1; + } + + return 0; +} + +int nthw_iic_write_data(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + void *p_void) +{ + const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str; + int retry = (p->mn_write_data_retry >= 0 ? p->mn_write_data_retry : 10); + uint8_t *pb = (uint8_t *)p_void; + + while (nthw_iic_writebyte(p, dev_addr, a_reg_addr, data_len, pb) != 0) { + retry--; + + if (retry <= 0) { + NT_LOG(ERR, NTHW, + "%s: I2C%d: Write retry exhausted (dev_addr=%d a_reg_addr=%d)\n", + p_adapter_id_str, p->mn_iic_instance, dev_addr, a_reg_addr); + return -1; + + } else { + NT_LOG(DBG, NTHW, + "%s: I2C%d: Write retry=%d (dev_addr=%d a_reg_addr=%d)\n", + p_adapter_id_str, p->mn_iic_instance, retry, dev_addr, a_reg_addr); + } + } + + return 0; +} + +int nthw_iic_writebyte(nthw_iic_t *p, uint8_t dev_addr, uint8_t a_reg_addr, uint8_t data_len, + uint8_t *p_byte) +{ + const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str; + uint32_t value; + int count; + int i; + + if (data_len == 0) + return -1; + + count = data_len - 1; + + if (nthw_iic_bus_ready(p)) { + /* Reset TX fifo */ + nthw_iic_reg_control_txfifo_reset(p); + + /* Write device address to TX_FIFO and set start bit!! */ + value = (dev_addr << 1) | I2C_TRANSMIT_WR; + nthw_iic_reg_tx_fifo_write(p, value, 1, 0); + + /* Write a_reg_addr to TX FIFO */ + nthw_iic_reg_tx_fifo_write(p, a_reg_addr, 0, 0); + + for (i = 0; i < count; i++) { + /* Write data byte to TX fifo and set stop bit */ + nthw_iic_reg_tx_fifo_write(p, *p_byte, 0, 0); + p_byte++; + } + + /* Write data byte to TX fifo and set stop bit */ + nthw_iic_reg_tx_fifo_write(p, *p_byte, 0, 1); + + if (!nthw_iic_bus_ready(p)) { + NT_LOG_DBGX(WARNING, NTHW, "%s: warn: !busReady\n", p_adapter_id_str); + + while (true) + if (nthw_iic_bus_ready(p)) { + NT_LOG_DBGX(DEBUG, NTHW, "%s: info: busReady\n", + p_adapter_id_str); + break; + } + } + + return 0; + + } else { + NT_LOG_DBGX(WARNING, NTHW, "%s\n", p_adapter_id_str); + return -1; + } +} + +/* + * Support function for read/write functions below. Waits for bus ready. + */ +bool nthw_iic_bus_ready(nthw_iic_t *p) +{ + int count = (p->mn_bus_ready_retry >= 0 ? p->mn_bus_ready_retry : 1000); + bool b_bus_busy = true; + + while (true) { + nthw_iic_reg_busbusy(p, &b_bus_busy); + + if (!b_bus_busy) + break; + + count--; + + if (count <= 0) /* Test for timeout */ + break; + + if (p->mn_poll_delay != 0) + I2C_WAIT_US(p->mn_poll_delay); + } + + if (count == 0) + return false; + + return true; +} + +/* + * Support function for read function. Waits for data ready. + */ +bool nthw_iic_data_ready(nthw_iic_t *p) +{ + int count = (p->mn_data_ready_retry >= 0 ? p->mn_data_ready_retry : 1000); + bool b_rx_fifo_empty = true; + + while (true) { + nthw_iic_reg_rxfifo_empty(p, &b_rx_fifo_empty); + + if (!b_rx_fifo_empty) + break; + + count--; + + if (count <= 0) /* Test for timeout */ + break; + + if (p->mn_poll_delay != 0) + I2C_WAIT_US(p->mn_poll_delay); + } + + if (count == 0) + return false; + + return true; +} + +int nthw_iic_scan_dev_addr(nthw_iic_t *p, int n_dev_addr, int n_reg_addr) +{ + const char *const p_adapter_id_str = p->mp_fpga->p_fpga_info->mp_adapter_id_str; + (void)p_adapter_id_str; + int res; + uint8_t data_val = -1; + res = nthw_iic_readbyte(p, (uint8_t)n_dev_addr, (uint8_t)n_reg_addr, 1, &data_val); + + if (res == 0) { + NT_LOG(DBG, NTHW, + "%s: I2C%d: devaddr=0x%02X (%03d) regaddr=%02X val=%02X (%03d) res=%d\n", + p_adapter_id_str, p->mn_iic_instance, n_dev_addr, n_dev_addr, n_reg_addr, + data_val, data_val, res); + } + + return res; +} + +int nthw_iic_scan(nthw_iic_t *p) +{ + int i; + + for (i = 0; i < 128; i++) + (void)nthw_iic_scan_dev_addr(p, i, 0x00); + + return 0; +} diff --git a/drivers/net/ntnic/nthw/core/nthw_pcie3.c b/drivers/net/ntnic/nthw/core/nthw_pcie3.c new file mode 100644 index 0000000000..c6cb3ce8de --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_pcie3.c @@ -0,0 +1,259 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_pcie3.h" + +#define NTHW_TG_REF_FREQ (250000000ULL) + +nthw_pcie3_t *nthw_pcie3_new(void) +{ + nthw_pcie3_t *p = malloc(sizeof(nthw_pcie3_t)); + + if (p) + memset(p, 0, sizeof(nthw_pcie3_t)); + + return p; +} + +void nthw_pcie3_delete(nthw_pcie3_t *p) +{ + if (p) { + memset(p, 0, sizeof(nthw_pcie3_t)); + free(p); + } +} + +int nthw_pcie3_init(nthw_pcie3_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_PCIE3, n_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: PCIE3 %d: no such instance\n", + p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_pcie3 = mod; + + /* PCIe3 */ + p->mp_reg_stat_ctrl = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_CTRL); + p->mp_fld_stat_ctrl_ena = + nthw_register_get_field(p->mp_reg_stat_ctrl, PCIE3_STAT_CTRL_STAT_ENA); + p->mp_fld_stat_ctrl_req = + nthw_register_get_field(p->mp_reg_stat_ctrl, PCIE3_STAT_CTRL_STAT_REQ); + + p->mp_reg_stat_rx = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_RX); + p->mp_fld_stat_rx_counter = + nthw_register_get_field(p->mp_reg_stat_rx, PCIE3_STAT_RX_COUNTER); + + p->mp_reg_stat_tx = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_TX); + p->mp_fld_stat_tx_counter = + nthw_register_get_field(p->mp_reg_stat_tx, PCIE3_STAT_TX_COUNTER); + + p->mp_reg_stat_ref_clk = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_REFCLK); + p->mp_fld_stat_ref_clk_ref_clk = + nthw_register_get_field(p->mp_reg_stat_ref_clk, PCIE3_STAT_REFCLK_REFCLK250); + + p->mp_reg_stat_rq_rdy = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_RQ_RDY); + p->mp_fld_stat_rq_rdy_counter = + nthw_register_get_field(p->mp_reg_stat_rq_rdy, PCIE3_STAT_RQ_RDY_COUNTER); + + p->mp_reg_stat_rq_vld = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STAT_RQ_VLD); + p->mp_fld_stat_rq_vld_counter = + nthw_register_get_field(p->mp_reg_stat_rq_vld, PCIE3_STAT_RQ_VLD_COUNTER); + + p->mp_reg_status0 = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_STATUS0); + p->mp_fld_status0_tags_in_use = + nthw_register_get_field(p->mp_reg_status0, PCIE3_STATUS0_TAGS_IN_USE); + + p->mp_reg_rp_to_ep_err = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_RP_TO_EP_ERR); + p->mp_fld_rp_to_ep_err_cor = + nthw_register_get_field(p->mp_reg_rp_to_ep_err, PCIE3_RP_TO_EP_ERR_ERR_COR); + p->mp_fld_rp_to_ep_err_non_fatal = + nthw_register_get_field(p->mp_reg_rp_to_ep_err, PCIE3_RP_TO_EP_ERR_ERR_NONFATAL); + p->mp_fld_rp_to_ep_err_fatal = + nthw_register_get_field(p->mp_reg_rp_to_ep_err, PCIE3_RP_TO_EP_ERR_ERR_FATAL); + + p->mp_reg_ep_to_rp_err = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_EP_TO_RP_ERR); + p->mp_fld_ep_to_rp_err_cor = + nthw_register_get_field(p->mp_reg_ep_to_rp_err, PCIE3_EP_TO_RP_ERR_ERR_COR); + p->mp_fld_ep_to_rp_err_non_fatal = + nthw_register_get_field(p->mp_reg_ep_to_rp_err, PCIE3_EP_TO_RP_ERR_ERR_NONFATAL); + p->mp_fld_ep_to_rp_err_fatal = + nthw_register_get_field(p->mp_reg_ep_to_rp_err, PCIE3_EP_TO_RP_ERR_ERR_FATAL); + + p->mp_reg_sample_time = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_SAMPLE_TIME); + p->mp_fld_sample_time = + nthw_register_get_field(p->mp_reg_sample_time, PCIE3_SAMPLE_TIME_SAMPLE_TIME); + + p->mp_reg_pci_end_point = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_PCI_ENDPOINT); + p->mp_fld_pci_end_point_if_id = + nthw_register_get_field(p->mp_reg_pci_end_point, PCIE3_PCI_ENDPOINT_IF_ID); + p->mp_fld_pci_end_point_send_msg = + nthw_register_get_field(p->mp_reg_pci_end_point, PCIE3_PCI_ENDPOINT_SEND_MSG); + p->mp_fld_pci_end_point_get_msg = + nthw_register_get_field(p->mp_reg_pci_end_point, PCIE3_PCI_ENDPOINT_GET_MSG); + p->mp_fld_pci_end_point_dmaep0_allow_mask = + nthw_register_get_field(p->mp_reg_pci_end_point, + PCIE3_PCI_ENDPOINT_DMA_EP0_ALLOW_MASK); + p->mp_fld_pci_end_point_dmaep1_allow_mask = + nthw_register_get_field(p->mp_reg_pci_end_point, + PCIE3_PCI_ENDPOINT_DMA_EP1_ALLOW_MASK); + + if (p->mp_reg_pci_end_point) + nthw_register_update(p->mp_reg_pci_end_point); + + p->mp_reg_pci_test0 = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_PCI_TEST0); + p->mp_fld_pci_test0 = nthw_register_get_field(p->mp_reg_pci_test0, PCIE3_PCI_TEST0_DATA); + + if (p->mp_reg_pci_test0) + nthw_register_update(p->mp_reg_pci_test0); + + p->mp_reg_pci_test1 = nthw_module_get_register(p->mp_mod_pcie3, PCIE3_PCI_TEST1); + p->mp_fld_pci_test1 = nthw_register_get_field(p->mp_reg_pci_test1, PCIE3_PCI_TEST1_DATA); + + if (p->mp_reg_pci_test1) + nthw_register_update(p->mp_reg_pci_test1); + + p->mp_reg_pci_e3_mark_adr_lsb = + nthw_module_get_register(p->mp_mod_pcie3, PCIE3_MARKADR_LSB); + p->mp_fld_pci_e3_mark_adr_lsb_adr = + nthw_register_get_field(p->mp_reg_pci_e3_mark_adr_lsb, PCIE3_MARKADR_LSB_ADR); + + if (p->mp_reg_pci_e3_mark_adr_lsb) + nthw_register_update(p->mp_reg_pci_e3_mark_adr_lsb); + + p->mp_reg_pci_e3_mark_adr_msb = + nthw_module_get_register(p->mp_mod_pcie3, PCIE3_MARKADR_MSB); + p->mp_fld_pci_e3_mark_adr_msb_adr = + nthw_register_get_field(p->mp_reg_pci_e3_mark_adr_msb, PCIE3_MARKADR_MSB_ADR); + + if (p->mp_reg_pci_e3_mark_adr_msb) + nthw_register_update(p->mp_reg_pci_e3_mark_adr_msb); + + /* Initial setup - disable markerscheme and bifurcation */ + if (p->mp_fld_pci_end_point_dmaep0_allow_mask) + nthw_field_clr_flush(p->mp_fld_pci_end_point_dmaep0_allow_mask); + + if (p->mp_fld_pci_end_point_dmaep1_allow_mask) + nthw_field_clr_flush(p->mp_fld_pci_end_point_dmaep1_allow_mask); + + if (p->mp_fld_pci_e3_mark_adr_lsb_adr) + nthw_field_set_val_flush32(p->mp_fld_pci_e3_mark_adr_lsb_adr, 0UL); + + if (p->mp_fld_pci_e3_mark_adr_msb_adr) + nthw_field_set_val_flush32(p->mp_fld_pci_e3_mark_adr_msb_adr, 0UL); + + if (p->mp_fld_pci_end_point_dmaep0_allow_mask) + nthw_field_set_flush(p->mp_fld_pci_end_point_dmaep0_allow_mask); + + if (p->mp_fld_pci_end_point_dmaep1_allow_mask) + nthw_field_clr_flush(p->mp_fld_pci_end_point_dmaep1_allow_mask); + + return 0; +}; + +int nthw_pcie3_trigger_sample_time(nthw_pcie3_t *p) +{ + nthw_field_set_val_flush32(p->mp_fld_sample_time, 0xfee1dead); + + return 0; +} + +int nthw_pcie3_stat_req_enable(nthw_pcie3_t *p) +{ + nthw_field_set_all(p->mp_fld_stat_ctrl_ena); + nthw_field_set_all(p->mp_fld_stat_ctrl_req); + nthw_field_flush_register(p->mp_fld_stat_ctrl_req); + return 0; +} + +int nthw_pcie3_stat_req_disable(nthw_pcie3_t *p) +{ + nthw_field_clr_all(p->mp_fld_stat_ctrl_ena); + nthw_field_set_all(p->mp_fld_stat_ctrl_req); + nthw_field_flush_register(p->mp_fld_stat_ctrl_req); + return 0; +} + +int nthw_pcie3_get_stat(nthw_pcie3_t *p, uint32_t *p_rx_cnt, uint32_t *p_tx_cnt, + uint32_t *p_ref_clk_cnt, uint32_t *p_tg_unit_size, uint32_t *p_tg_ref_freq, + uint32_t *p_tag_use_cnt, uint32_t *p_rq_rdy_cnt, uint32_t *p_rq_vld_cnt) +{ + *p_rx_cnt = nthw_field_get_updated(p->mp_fld_stat_rx_counter); + *p_tx_cnt = nthw_field_get_updated(p->mp_fld_stat_tx_counter); + + *p_ref_clk_cnt = nthw_field_get_updated(p->mp_fld_stat_ref_clk_ref_clk); + + *p_tg_unit_size = NTHW_TG_CNT_SIZE; + *p_tg_ref_freq = NTHW_TG_REF_FREQ; + + *p_tag_use_cnt = nthw_field_get_updated(p->mp_fld_status0_tags_in_use); + + *p_rq_rdy_cnt = nthw_field_get_updated(p->mp_fld_stat_rq_rdy_counter); + *p_rq_vld_cnt = nthw_field_get_updated(p->mp_fld_stat_rq_vld_counter); + + return 0; +} + +int nthw_pcie3_get_stat_rate(nthw_pcie3_t *p, uint64_t *p_pci_rx_rate, uint64_t *p_pci_tx_rate, + uint64_t *p_ref_clk_cnt, uint64_t *p_tag_use_cnt, + uint64_t *p_pci_nt_bus_util, uint64_t *p_pci_xil_bus_util) +{ + uint32_t rx_cnt, tx_cnt, ref_clk_cnt; + uint32_t tg_unit_size, tg_ref_freq; + uint32_t tag_use_cnt, rq_rdy_cnt, rq_vld_cnt; + + nthw_pcie3_get_stat(p, &rx_cnt, &tx_cnt, &ref_clk_cnt, &tg_unit_size, &tg_ref_freq, + &tag_use_cnt, &rq_rdy_cnt, &rq_vld_cnt); + + if (ref_clk_cnt) { + uint64_t nt_bus_util, xil_bus_util; + uint64_t rx_rate, tx_rate; + + rx_rate = ((uint64_t)rx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt; + *p_pci_rx_rate = rx_rate; + + tx_rate = ((uint64_t)tx_cnt * tg_unit_size * tg_ref_freq) / (uint64_t)ref_clk_cnt; + *p_pci_tx_rate = tx_rate; + + *p_ref_clk_cnt = ref_clk_cnt; + + *p_tag_use_cnt = tag_use_cnt; + + nt_bus_util = ((uint64_t)rq_vld_cnt * 1000000ULL) / (uint64_t)ref_clk_cnt; + *p_pci_nt_bus_util = nt_bus_util; + xil_bus_util = ((uint64_t)rq_rdy_cnt * 1000000ULL) / (uint64_t)ref_clk_cnt; + *p_pci_xil_bus_util = xil_bus_util; + + } else { + *p_ref_clk_cnt = 0; + *p_pci_nt_bus_util = 0; + *p_pci_xil_bus_util = 0; + } + + return 0; +} + +int nthw_pcie3_end_point_counters_sample_post(nthw_pcie3_t *p, + struct nthw_hif_end_point_counters *epc) +{ + NT_LOG_DBGX(DEBUG, NTHW); + assert(epc); + nthw_pcie3_get_stat_rate(p, &epc->cur_tx, &epc->cur_rx, &epc->n_ref_clk_cnt, + &epc->n_tags_in_use, &epc->cur_pci_nt_util, + &epc->cur_pci_xil_util); + return 0; +} diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h index 0b89a5c5a0..d7cd64bb1d 100644 --- a/drivers/net/ntnic/nthw/nthw_drv.h +++ b/drivers/net/ntnic/nthw/nthw_drv.h @@ -6,8 +6,7 @@ #ifndef __NTHW_DRV_H__ #define __NTHW_DRV_H__ -#include -#include "nthw_platform_drv.h" +#include "nthw_core.h" typedef enum nt_meta_port_type_e { PORT_TYPE_PHYSICAL, diff --git a/drivers/net/ntnic/nthw/nthw_rac.c b/drivers/net/ntnic/nthw/nthw_rac.c new file mode 100644 index 0000000000..2aef0c148f --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_rac.c @@ -0,0 +1,784 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" +#include "nthw_rac.h" + +#include + + +#define RAB_READ (0x01) +#define RAB_WRITE (0x02) +#define RAB_ECHO (0x08) +#define RAB_COMPLETION (0x0F) + +#define RAB_OPR_LO (28) + +#define RAB_CNT_LO (20) +#define RAB_CNT_BW (8) + +#define RAB_BUSID_LO (16) +#define RAB_BUSID_BW (4) + +#define RAB_ADDR_BW (16) + +nthw_rac_t *nthw_rac_new(void) +{ + nthw_rac_t *p = malloc(sizeof(nthw_rac_t)); + memset(p, 0, sizeof(nthw_rac_t)); + return p; +} + +int nthw_rac_init(nthw_rac_t *p, nthw_fpga_t *p_fpga, struct fpga_info_s *p_fpga_info) +{ + assert(p_fpga_info); + + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_RAC, 0); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: RAC %d: no such instance\n", p_adapter_id_str, 0); + return -1; + } + + p->mp_fpga = p_fpga; + p->mp_mod_rac = p_mod; + + p->mn_param_rac_rab_interfaces = + nthw_fpga_get_product_param(p->mp_fpga, NT_RAC_RAB_INTERFACES, 3); + NT_LOG(DBG, NTHW, "%s: NT_RAC_RAB_INTERFACES=%d\n", p_adapter_id_str, + p->mn_param_rac_rab_interfaces); + + p->mn_param_rac_rab_ob_update = + nthw_fpga_get_product_param(p->mp_fpga, NT_RAC_RAB_OB_UPDATE, 0); + NT_LOG(DBG, NTHW, "%s: NT_RAC_RAB_OB_UPDATE=%d\n", p_adapter_id_str, + p->mn_param_rac_rab_ob_update); + + /* Optional dummy test registers */ + p->mp_reg_dummy0 = nthw_module_query_register(p->mp_mod_rac, RAC_DUMMY0); + p->mp_reg_dummy1 = nthw_module_query_register(p->mp_mod_rac, RAC_DUMMY1); + p->mp_reg_dummy2 = nthw_module_query_register(p->mp_mod_rac, RAC_DUMMY2); + + p->mp_reg_rab_init = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_INIT); + p->mp_fld_rab_init = nthw_register_get_field(p->mp_reg_rab_init, RAC_RAB_INIT_RAB); + p->mn_fld_rab_init_bw = nthw_field_get_bit_width(p->mp_fld_rab_init); + p->mn_fld_rab_init_mask = nthw_field_get_mask(p->mp_fld_rab_init); + + /* RAC_RAB_INIT_RAB reg/field sanity checks: */ + assert(p->mn_fld_rab_init_mask == ((1UL << p->mn_fld_rab_init_bw) - 1)); + assert(p->mn_fld_rab_init_bw == p->mn_param_rac_rab_interfaces); + + p->mp_reg_dbg_ctrl = nthw_module_query_register(p->mp_mod_rac, RAC_DBG_CTRL); + + if (p->mp_reg_dbg_ctrl) + p->mp_fld_dbg_ctrl = nthw_register_query_field(p->mp_reg_dbg_ctrl, RAC_DBG_CTRL_C); + + else + p->mp_fld_dbg_ctrl = NULL; + + p->mp_reg_dbg_data = nthw_module_query_register(p->mp_mod_rac, RAC_DBG_DATA); + + if (p->mp_reg_dbg_data) + p->mp_fld_dbg_data = nthw_register_query_field(p->mp_reg_dbg_data, RAC_DBG_DATA_D); + + else + p->mp_reg_dbg_data = NULL; + + p->mp_reg_rab_ib_data = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_IB_DATA); + p->mp_fld_rab_ib_data = nthw_register_get_field(p->mp_reg_rab_ib_data, RAC_RAB_IB_DATA_D); + + p->mp_reg_rab_ob_data = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_OB_DATA); + p->mp_fld_rab_ob_data = nthw_register_get_field(p->mp_reg_rab_ob_data, RAC_RAB_OB_DATA_D); + + p->mp_reg_rab_buf_free = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_BUF_FREE); + p->mp_fld_rab_buf_free_ib_free = + nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_IB_FREE); + p->mp_fld_rab_buf_free_ib_ovf = + nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_IB_OVF); + p->mp_fld_rab_buf_free_ob_free = + nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_OB_FREE); + p->mp_fld_rab_buf_free_ob_ovf = + nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_OB_OVF); + p->mp_fld_rab_buf_free_timeout = + nthw_register_get_field(p->mp_reg_rab_buf_free, RAC_RAB_BUF_FREE_TIMEOUT); + + p->mp_reg_rab_buf_used = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_BUF_USED); + p->mp_fld_rab_buf_used_ib_used = + nthw_register_get_field(p->mp_reg_rab_buf_used, RAC_RAB_BUF_USED_IB_USED); + p->mp_fld_rab_buf_used_ob_used = + nthw_register_get_field(p->mp_reg_rab_buf_used, RAC_RAB_BUF_USED_OB_USED); + p->mp_fld_rab_buf_used_flush = + nthw_register_get_field(p->mp_reg_rab_buf_used, RAC_RAB_BUF_USED_FLUSH); + + /* + * RAC_RAB_DMA regs are optional - only found in real + * NT4GA - not found in 9231/9232 and earlier + */ + p->mp_reg_rab_dma_ib_lo = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_LO); + p->mp_fld_rab_dma_ib_lo_phy_addr = + nthw_register_get_field(p->mp_reg_rab_dma_ib_lo, RAC_RAB_DMA_IB_LO_PHYADDR); + + p->mp_reg_rab_dma_ib_hi = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_HI); + p->mp_fld_rab_dma_ib_hi_phy_addr = + nthw_register_get_field(p->mp_reg_rab_dma_ib_hi, RAC_RAB_DMA_IB_HI_PHYADDR); + + p->mp_reg_rab_dma_ob_lo = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_OB_LO); + p->mp_fld_rab_dma_ob_lo_phy_addr = + nthw_register_get_field(p->mp_reg_rab_dma_ob_lo, RAC_RAB_DMA_OB_LO_PHYADDR); + + p->mp_reg_rab_dma_ob_hi = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_OB_HI); + p->mp_fld_rab_dma_ob_hi_phy_addr = + nthw_register_get_field(p->mp_reg_rab_dma_ob_hi, RAC_RAB_DMA_OB_HI_PHYADDR); + + p->mp_reg_rab_dma_ib_wr = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_WR); + p->mp_fld_rab_dma_ib_wr_ptr = + nthw_register_get_field(p->mp_reg_rab_dma_ib_wr, RAC_RAB_DMA_IB_WR_PTR); + + p->mp_reg_rab_dma_ib_rd = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_IB_RD); + p->mp_fld_rab_dma_ib_rd_ptr = + nthw_register_get_field(p->mp_reg_rab_dma_ib_rd, RAC_RAB_DMA_IB_RD_PTR); + + p->mp_reg_rab_dma_ob_wr = nthw_module_get_register(p->mp_mod_rac, RAC_RAB_DMA_OB_WR); + p->mp_fld_rab_dma_ob_wr_ptr = + nthw_register_get_field(p->mp_reg_rab_dma_ob_wr, RAC_RAB_DMA_OB_WR_PTR); + + p->RAC_RAB_INIT_ADDR = nthw_register_get_address(p->mp_reg_rab_init); + p->RAC_RAB_IB_DATA_ADDR = nthw_register_get_address(p->mp_reg_rab_ib_data); + p->RAC_RAB_OB_DATA_ADDR = nthw_register_get_address(p->mp_reg_rab_ob_data); + p->RAC_RAB_BUF_FREE_ADDR = nthw_register_get_address(p->mp_reg_rab_buf_free); + p->RAC_RAB_BUF_USED_ADDR = nthw_register_get_address(p->mp_reg_rab_buf_used); + + /* + * RAC_RAB_DMA regs are optional - only found in real NT4GA - not found in 9231/9232 and + * earlier + */ + + p->RAC_RAB_DMA_IB_LO_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_lo); + p->RAC_RAB_DMA_IB_HI_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_hi); + p->RAC_RAB_DMA_OB_LO_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ob_lo); + p->RAC_RAB_DMA_OB_HI_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ob_hi); + p->RAC_RAB_DMA_IB_RD_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_rd); + p->RAC_RAB_DMA_OB_WR_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ob_wr); + p->RAC_RAB_DMA_IB_WR_ADDR = nthw_register_get_address(p->mp_reg_rab_dma_ib_wr); + + p->RAC_RAB_BUF_FREE_IB_FREE_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_free_ib_free); + p->RAC_RAB_BUF_FREE_OB_FREE_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_free_ob_free); + p->RAC_RAB_BUF_USED_IB_USED_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_used_ib_used); + p->RAC_RAB_BUF_USED_OB_USED_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_used_ob_used); + + p->RAC_RAB_BUF_USED_FLUSH_MASK = nthw_field_get_mask(p->mp_fld_rab_buf_used_flush); + + p->RAC_RAB_BUF_USED_OB_USED_LOW = + nthw_field_get_bit_pos_low(p->mp_fld_rab_buf_used_ob_used); + + p->mp_reg_rab_nmb_rd = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_RD_ADR); + + if (p->mp_reg_rab_nmb_rd) + p->RAC_NMB_RD_ADR_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_rd); + + p->mp_reg_rab_nmb_data = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_DATA); + + if (p->mp_reg_rab_nmb_data) + p->RAC_NMB_DATA_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_data); + + p->mp_reg_rab_nmb_wr = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_WR_ADR); + + if (p->mp_reg_rab_nmb_wr) + p->RAC_NMB_WR_ADR_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_wr); + + p->mp_reg_rab_nmb_status = nthw_module_query_register(p->mp_mod_rac, RAC_NMB_STATUS); + + if (p->mp_reg_rab_nmb_status) + p->RAC_NMB_STATUS_ADDR = nthw_register_get_address(p->mp_reg_rab_nmb_status); + + p->m_dma = NULL; + + { + /* + * RAC is a primary communication channel - debug will be messy + * turn off debug by default - except for rac_rab_init + * NOTE: currently debug will not work - due to optimizations + */ + const int n_debug_mode = nthw_module_get_debug_mode(p->mp_mod_rac); + + if (n_debug_mode && n_debug_mode <= 0xff) { + nthw_module_set_debug_mode(p->mp_mod_rac, 0); + nthw_register_set_debug_mode(p->mp_reg_rab_init, n_debug_mode); + } + } + + pthread_mutex_init(&p->m_mutex, NULL); + + return 0; +} + +static int nthw_rac_get_rab_interface_count(const nthw_rac_t *p) +{ + return p->mn_param_rac_rab_interfaces; +} + +/* private function for internal RAC operations - + * improves log flexibility and prevents log flooding + */ +static void nthw_rac_reg_read32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr, + uint32_t *p_data) +{ + *p_data = *(volatile uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr); +} + +/* private function for internal RAC operations - + * improves log flexibility and prevents log flooding + */ +static void nthw_rac_reg_write32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr, + uint32_t n_data) +{ + *(volatile uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr) = n_data; +} + +static inline int _nthw_rac_wait_for_rab_done(const nthw_rac_t *p, uint32_t address, + uint32_t word_cnt) +{ + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + uint32_t used = 0; + uint32_t retry; + + for (retry = 0; retry < 100000; retry++) { + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &used); + used = (used & p->RAC_RAB_BUF_USED_OB_USED_MASK) >> + p->RAC_RAB_BUF_USED_OB_USED_LOW; + + if (used >= word_cnt) + break; + } + + if (used < word_cnt) { + NT_LOG(ERR, NTHW, "%s: Fail rab bus r/w addr=0x%08X used=%x wordcount=%d\n", + p_adapter_id_str, address, used, word_cnt); + return -1; + } + + return 0; +} + +/* + * NT_PCI_REG_P9xyz_RAC_RAB_INIT + * + * Initializes (resets) the programmable registers on the Register Access Buses (RAB). + * This initialization must be performed by software as part of the driver load procedure. + * + * Bit n of this field initializes the programmable registers on RAB interface n. + * Software must write one to the bit and then clear the bit again. + * + * All RAB module registers will be reset to their defaults. + * This includes the product specific RESET module (eg RST9xyz) + * As a consequence of this behavior the official reset sequence + * must be excersised - as all RAB modules will be held in reset. + */ +int nthw_rac_rab_init(nthw_rac_t *p, uint32_t n_rab_intf_mask) +{ + /* + * Write rac_rab_init + * Perform operation twice - first to get trace of operation - + * second to get things done... + */ + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + nthw_field_set_val_flush32(p->mp_fld_rab_init, n_rab_intf_mask); + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_INIT_ADDR, n_rab_intf_mask); + return 0; +} + +int nthw_rac_rab_reset(nthw_rac_t *p) +{ + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + (void)p_adapter_id_str; + + /* RAC RAB bus "flip/flip" reset */ + const int n_rac_rab_bus_count = nthw_rac_get_rab_interface_count(p); + const int n_rac_rab_bus_mask = (1 << n_rac_rab_bus_count) - 1; + + NT_LOG(DBG, NTHW, "%s: NT_RAC_RAB_INTERFACES=%d (0x%02X)\n", p_adapter_id_str, + n_rac_rab_bus_count, n_rac_rab_bus_mask); + assert(n_rac_rab_bus_count); + assert(n_rac_rab_bus_mask); + + /* RAC RAB bus "flip/flip" reset first stage - new impl (ref RMT#37020) */ + nthw_rac_rab_init(p, 0); + nthw_rac_rab_init(p, n_rac_rab_bus_mask); + nthw_rac_rab_init(p, n_rac_rab_bus_mask & ~0x01); + + return 0; +} + +int nthw_rac_rab_setup(nthw_rac_t *p) +{ + int rc = 0; + + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + uint32_t n_dma_buf_size = 2L * RAB_DMA_BUF_CNT * sizeof(uint32_t); + const size_t align_size = nt_util_align_size(n_dma_buf_size); + int numa_node = p_fpga_info->numa_node; + uint64_t dma_addr; + uint32_t buf; + + if (!p->m_dma) { + struct nt_dma_s *vfio_dma; + /* FPGA needs Page alignment (4K) */ + vfio_dma = nt_dma_alloc(align_size, 0x1000, numa_node); + + if (vfio_dma == NULL) { + NT_LOG(ERR, NTNIC, "nt_dma_alloc failed\n"); + return -1; + } + + p->m_dma_in_buf = (uint32_t *)vfio_dma->addr; + p->m_dma_out_buf = p->m_dma_in_buf + RAB_DMA_BUF_CNT; + p->m_dma = vfio_dma; + } + + /* Setup DMA on the adapter */ + dma_addr = p->m_dma->iova; + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_IB_LO_ADDR, dma_addr & 0xffffffff); + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_IB_HI_ADDR, + (uint32_t)(dma_addr >> 32) & 0xffffffff); + dma_addr += RAB_DMA_BUF_CNT * sizeof(uint32_t); + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_OB_LO_ADDR, dma_addr & 0xffffffff); + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_DMA_OB_HI_ADDR, + (uint32_t)(dma_addr >> 32) & 0xffffffff); + + /* Set initial value of internal pointers */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_DMA_IB_RD_ADDR, &buf); + p->m_dma_in_ptr_wr = (uint16_t)(buf / sizeof(uint32_t)); + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_DMA_OB_WR_ADDR, &buf); + p->m_dma_out_ptr_rd = (uint16_t)(buf / sizeof(uint32_t)); + p->m_in_free = RAB_DMA_BUF_CNT; + + return rc; +} + +void nthw_rac_bar0_read32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr, + uint32_t word_cnt, uint32_t *p_data) +{ + volatile const uint32_t *const src_addr = + (uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr); + + for (uint32_t i = 0; i < word_cnt; i++) + p_data[i] = src_addr[i]; +} + +void nthw_rac_bar0_write32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr, + uint32_t word_cnt, const uint32_t *p_data) +{ + volatile uint32_t *const dst_addr = + (uint32_t *)((uint8_t *)p_fpga_info->bar0_addr + reg_addr); + + for (uint32_t i = 0; i < word_cnt; i++) + dst_addr[i] = p_data[i]; +} + +int nthw_rac_rab_write32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address, + uint32_t word_cnt, const uint32_t *p_data) +{ + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + uint32_t buf_used; + uint32_t buf_free; + uint32_t in_buf_free; + uint32_t out_buf_free; + int res = 0; + + if (address > (1 << RAB_ADDR_BW)) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal address: value too large %d - max %d\n", + p_adapter_id_str, address, (1 << RAB_ADDR_BW)); + return -1; + } + + if (bus_id > (1 << RAB_BUSID_BW)) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal bus id: value too large %d - max %d\n", + p_adapter_id_str, bus_id, (1 << RAB_BUSID_BW)); + return -1; + } + + if (word_cnt == 0) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value is zero (%d)\n", + p_adapter_id_str, word_cnt); + return -1; + } + + if (word_cnt > (1 << RAB_CNT_BW)) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value too large %d - max %d\n", + p_adapter_id_str, word_cnt, (1 << RAB_CNT_BW)); + return -1; + } + + pthread_mutex_lock(&p->m_mutex); + + if (p->m_dma_active) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal operation: DMA enabled\n", p_adapter_id_str); + res = -1; + goto exit_unlock_res; + } + + /* Read buffer free register */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free); + + in_buf_free = buf_free & p->RAC_RAB_BUF_FREE_IB_FREE_MASK; + out_buf_free = (buf_free & p->RAC_RAB_BUF_FREE_OB_FREE_MASK) >> 16; + + /* Read buffer used register */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &buf_used); + + buf_used = + buf_used & (p->RAC_RAB_BUF_USED_IB_USED_MASK | p->RAC_RAB_BUF_USED_OB_USED_MASK); + + /* + * Verify that output buffer can hold one completion word, + * input buffer can hold the number of words to be written + + * one write and one completion command + * and that the input and output "used" buffer is 0 + */ + if (out_buf_free >= 1 && in_buf_free >= word_cnt + 2 && buf_used == 0) { + const uint32_t rab_oper_cmpl = (RAB_COMPLETION << RAB_OPR_LO); + uint32_t rab_echo_oper_cmpl; + uint32_t word_cnt_expected = 1; + uint32_t rab_oper_wr; + uint32_t i; + + rab_oper_wr = (RAB_WRITE << RAB_OPR_LO) | + ((word_cnt & ((1 << RAB_CNT_BW) - 1)) << RAB_CNT_LO) | + (bus_id << RAB_BUSID_LO) | address; + + if (trc) { + rab_oper_wr |= (RAB_ECHO << RAB_OPR_LO); + word_cnt_expected += word_cnt + 1; + } + + /* Write command */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_wr); + + /* Write data to input buffer */ + for (i = 0; i < word_cnt; i++) + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, p_data[i]); + + /* Write completion command */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_cmpl); + + /* Wait until done */ + if (_nthw_rac_wait_for_rab_done(p, address, word_cnt_expected)) { + res = -1; + goto exit_unlock_res; + } + + if (trc) { + uint32_t rab_echo_oper_wr; + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, + &rab_echo_oper_wr); + + if (p->mn_param_rac_rab_ob_update) + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0); + + if (rab_oper_wr != rab_echo_oper_wr) { + NT_LOG(ERR, NTHW, + "%s: expected rab read echo oper (0x%08X) - read (0x%08X)\n", + p_adapter_id_str, rab_oper_wr, rab_echo_oper_wr); + } + } + + { + /* Read data from output buffer */ + uint32_t data; + char *tmp_string; + + if (trc) { + tmp_string = ntlog_helper_str_alloc("Register::write"); + ntlog_helper_str_add(tmp_string, + "(Dev: NA, Bus: RAB%u, Addr: 0x%08X, Cnt: %d, Data:", + bus_id, address, word_cnt); + } + + for (i = 0; i < word_cnt; i++) { + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, &data); + + if (p->mn_param_rac_rab_ob_update) { + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, + 0); + } + + if (trc) + ntlog_helper_str_add(tmp_string, " 0x%08X", data); + } + + if (trc) { + ntlog_helper_str_add(tmp_string, ")"); + NT_LOG(DBG, NTHW, "%s", tmp_string); + ntlog_helper_str_free(tmp_string); + } + } + + /* Read completion from out buffer */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, &rab_echo_oper_cmpl); + + if (p->mn_param_rac_rab_ob_update) + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0); + + if (rab_echo_oper_cmpl != rab_oper_cmpl) { + NT_LOG(ERR, NTHW, + "%s: RAB: Unexpected value of completion (0x%08X)- inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n", + p_adapter_id_str, rab_echo_oper_cmpl, in_buf_free, out_buf_free, + buf_used); + res = -1; + goto exit_unlock_res; + } + + /* Read buffer free register */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free); + + if (buf_free & 0x80000000) { + /* Clear Timeout and overflow bits */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, 0x0); + NT_LOG(ERR, NTHW, + "%s: RAB: timeout - Access outside register - bus: %d addr: 0x%08X - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n", + p_adapter_id_str, bus_id, address, in_buf_free, out_buf_free, + buf_used); + res = -1; + goto exit_unlock_res; + } + + res = 0; + goto exit_unlock_res; + + } else { + NT_LOG(ERR, NTHW, + "%s: RAB: Fail rab bus buffer check - bus: %d addr: 0x%08X wordcount: %d - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n", + p_adapter_id_str, bus_id, address, word_cnt, in_buf_free, out_buf_free, + buf_used); + res = -1; + goto exit_unlock_res; + } + +exit_unlock_res: + pthread_mutex_unlock(&p->m_mutex); + return res; +} + +int nthw_rac_rab_read32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address, + uint32_t word_cnt, uint32_t *p_data) +{ + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + uint32_t buf_used; + uint32_t buf_free; + uint32_t in_buf_free; + uint32_t out_buf_free; + int res = 0; + + pthread_mutex_lock(&p->m_mutex); + + if (address > (1 << RAB_ADDR_BW)) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal address: value too large %d - max %d\n", + p_adapter_id_str, address, (1 << RAB_ADDR_BW)); + res = -1; + goto exit_unlock_res; + } + + if (bus_id > (1 << RAB_BUSID_BW)) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal bus id: value too large %d - max %d\n", + p_adapter_id_str, bus_id, (1 << RAB_BUSID_BW)); + res = -1; + goto exit_unlock_res; + } + + if (word_cnt == 0) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value is zero (%d)\n", + p_adapter_id_str, word_cnt); + res = -1; + goto exit_unlock_res; + } + + if (word_cnt > (1 << RAB_CNT_BW)) { + NT_LOG(ERR, NTHW, "%s: RAB: Illegal word count: value too large %d - max %d\n", + p_adapter_id_str, word_cnt, (1 << RAB_CNT_BW)); + res = -1; + goto exit_unlock_res; + } + + /* Read buffer free register */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free); + + in_buf_free = buf_free & p->RAC_RAB_BUF_FREE_IB_FREE_MASK; + out_buf_free = (buf_free & p->RAC_RAB_BUF_FREE_OB_FREE_MASK) >> 16; + + /* Read buffer used register */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &buf_used); + + buf_used = + buf_used & (p->RAC_RAB_BUF_USED_IB_USED_MASK | p->RAC_RAB_BUF_USED_OB_USED_MASK); + + /* + * Verify that output buffer can hold the number of words to be read, + * input buffer can hold one read command + * and that the input and output "used" buffer is 0 + */ + if (out_buf_free >= word_cnt && in_buf_free >= 1 && buf_used == 0) { + const uint32_t rab_oper_cmpl = (RAB_COMPLETION << RAB_OPR_LO); + uint32_t rab_read_oper_cmpl; + uint32_t word_cnt_expected = word_cnt + 1; + uint32_t rab_oper_rd; + + rab_oper_rd = (RAB_READ << RAB_OPR_LO) | + ((word_cnt & ((1 << RAB_CNT_BW) - 1)) << RAB_CNT_LO) | + (bus_id << RAB_BUSID_LO) | address; + + if (trc) { + rab_oper_rd |= (RAB_ECHO << RAB_OPR_LO); + word_cnt_expected++; + } + + /* Write command */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_rd); + + /* Write completion command */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_IB_DATA_ADDR, rab_oper_cmpl); + + /* Wait until done */ + if (_nthw_rac_wait_for_rab_done(p, address, word_cnt_expected)) { + res = -1; + goto exit_unlock_res; + } + + if (trc) { + uint32_t rab_echo_oper_rd; + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, + &rab_echo_oper_rd); + + if (p->mn_param_rac_rab_ob_update) + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0); + + if (rab_oper_rd != rab_echo_oper_rd) { + NT_LOG(ERR, NTHW, + "%s: RAB: expected rab read echo oper (0x%08X) - read (0x%08X)\n", + p_adapter_id_str, rab_oper_rd, rab_echo_oper_rd); + } + } + + { + /* Read data from output buffer */ + uint32_t i; + + for (i = 0; i < word_cnt; i++) { + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, + &p_data[i]); + + if (p->mn_param_rac_rab_ob_update) { + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, + 0); + } + } + + if (trc) { + char *tmp_string = ntlog_helper_str_alloc("Register::read"); + ntlog_helper_str_add(tmp_string, + "(Dev: NA, Bus: RAB%u, Addr: 0x%08X, Cnt: %d, Data:", + bus_id, address, word_cnt); + + for (i = 0; i < word_cnt; i++) + ntlog_helper_str_add(tmp_string, " 0x%08X", p_data[i]); + + ntlog_helper_str_add(tmp_string, ")"); + NT_LOG(DBG, NTHW, "%s", tmp_string); + ntlog_helper_str_free(tmp_string); + } + } + + /* Read completion from out buffer */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, &rab_read_oper_cmpl); + + if (p->mn_param_rac_rab_ob_update) + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_OB_DATA_ADDR, 0); + + if (rab_read_oper_cmpl != rab_oper_cmpl) { + NT_LOG(ERR, NTHW, + "%s: RAB: Unexpected value of completion (0x%08X)- inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n", + p_adapter_id_str, rab_read_oper_cmpl, in_buf_free, out_buf_free, + buf_used); + res = -1; + goto exit_unlock_res; + } + + /* Read buffer free register */ + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, &buf_free); + + if (buf_free & 0x80000000) { + /* Clear Timeout and overflow bits */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, 0x0); + NT_LOG(ERR, NTHW, + "%s: RAB: timeout - Access outside register - bus: %d addr: 0x%08X - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n", + p_adapter_id_str, bus_id, address, in_buf_free, out_buf_free, + buf_used); + res = -1; + goto exit_unlock_res; + } + + res = 0; + goto exit_unlock_res; + + } else { + NT_LOG(ERR, NTHW, + "%s: RAB: Fail rab bus buffer check - bus: %d addr: 0x%08X wordcount: %d - inBufFree: 0x%08X, outBufFree: 0x%08X, bufUsed: 0x%08X\n", + p_adapter_id_str, bus_id, address, word_cnt, in_buf_free, out_buf_free, + buf_used); + res = -1; + goto exit_unlock_res; + } + +exit_unlock_res: + pthread_mutex_unlock(&p->m_mutex); + return res; +} + +int nthw_rac_rab_flush(nthw_rac_t *p) +{ + const struct fpga_info_s *const p_fpga_info = p->mp_fpga->p_fpga_info; + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + uint32_t data = 0; + uint32_t retry; + int res = 0; + + pthread_mutex_lock(&p->m_mutex); + + /* Set the flush bit */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, + p->RAC_RAB_BUF_USED_FLUSH_MASK); + + /* Reset BUF FREE register */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_FREE_ADDR, 0x0); + + /* Wait until OB_USED and IB_USED are 0 */ + for (retry = 0; retry < 100000; retry++) { + nthw_rac_reg_read32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, &data); + + if ((data & 0xFFFFFFFF) == p->RAC_RAB_BUF_USED_FLUSH_MASK) + break; + } + + if (data != p->RAC_RAB_BUF_USED_FLUSH_MASK) { + NT_LOG(ERR, NTHW, "%s: RAB: Rab bus flush error.\n", p_adapter_id_str); + res = -1; + } + + /* Clear flush bit when done */ + nthw_rac_reg_write32(p_fpga_info, p->RAC_RAB_BUF_USED_ADDR, 0x0); + + pthread_mutex_unlock(&p->m_mutex); + return res; +} diff --git a/drivers/net/ntnic/nthw/nthw_rac.h b/drivers/net/ntnic/nthw/nthw_rac.h new file mode 100644 index 0000000000..c16ff77189 --- /dev/null +++ b/drivers/net/ntnic/nthw/nthw_rac.h @@ -0,0 +1,153 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_RAC_H__ +#define __NTHW_RAC_H__ + +#include "nt_util.h" + +#define RAB_DMA_BUF_CNT (0x4000) + +typedef uint8_t nthw_rab_bus_id_t; + +struct nthw_rac { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_rac; + + pthread_mutex_t m_mutex; + + int mn_param_rac_rab_interfaces; + int mn_param_rac_rab_ob_update; + + nthw_register_t *mp_reg_dummy0; + nthw_register_t *mp_reg_dummy1; + nthw_register_t *mp_reg_dummy2; + + nthw_register_t *mp_reg_rab_init; + nthw_field_t *mp_fld_rab_init; + + int mn_fld_rab_init_bw; + uint32_t mn_fld_rab_init_mask; + + nthw_register_t *mp_reg_dbg_ctrl; + nthw_field_t *mp_fld_dbg_ctrl; + + nthw_register_t *mp_reg_dbg_data; + nthw_field_t *mp_fld_dbg_data; + + nthw_register_t *mp_reg_rab_ib_data; + nthw_field_t *mp_fld_rab_ib_data; + + nthw_register_t *mp_reg_rab_ob_data; + nthw_field_t *mp_fld_rab_ob_data; + + nthw_register_t *mp_reg_rab_buf_free; + nthw_field_t *mp_fld_rab_buf_free_ib_free; + nthw_field_t *mp_fld_rab_buf_free_ib_ovf; + nthw_field_t *mp_fld_rab_buf_free_ob_free; + nthw_field_t *mp_fld_rab_buf_free_ob_ovf; + nthw_field_t *mp_fld_rab_buf_free_timeout; + + nthw_register_t *mp_reg_rab_buf_used; + nthw_field_t *mp_fld_rab_buf_used_ib_used; + nthw_field_t *mp_fld_rab_buf_used_ob_used; + nthw_field_t *mp_fld_rab_buf_used_flush; + + nthw_register_t *mp_reg_rab_dma_ib_lo; + nthw_field_t *mp_fld_rab_dma_ib_lo_phy_addr; + + nthw_register_t *mp_reg_rab_dma_ib_hi; + nthw_field_t *mp_fld_rab_dma_ib_hi_phy_addr; + + nthw_register_t *mp_reg_rab_dma_ob_hi; + nthw_field_t *mp_fld_rab_dma_ob_hi_phy_addr; + + nthw_register_t *mp_reg_rab_dma_ob_lo; + nthw_field_t *mp_fld_rab_dma_ob_lo_phy_addr; + + nthw_register_t *mp_reg_rab_dma_ib_wr; + nthw_field_t *mp_fld_rab_dma_ib_wr_ptr; + + nthw_register_t *mp_reg_rab_dma_ib_rd; + nthw_field_t *mp_fld_rab_dma_ib_rd_ptr; + + nthw_register_t *mp_reg_rab_dma_ob_wr; + nthw_field_t *mp_fld_rab_dma_ob_wr_ptr; + + nthw_register_t *mp_reg_rab_nmb_rd; + nthw_register_t *mp_reg_rab_nmb_data; + nthw_register_t *mp_reg_rab_nmb_wr; + nthw_register_t *mp_reg_rab_nmb_status; + + uint32_t RAC_RAB_INIT_ADDR; + uint32_t RAC_RAB_IB_DATA_ADDR; + uint32_t RAC_RAB_OB_DATA_ADDR; + uint32_t RAC_RAB_BUF_FREE_ADDR; + uint32_t RAC_RAB_BUF_USED_ADDR; + + uint32_t RAC_RAB_DMA_IB_LO_ADDR; + uint32_t RAC_RAB_DMA_IB_HI_ADDR; + uint32_t RAC_RAB_DMA_OB_LO_ADDR; + uint32_t RAC_RAB_DMA_OB_HI_ADDR; + uint32_t RAC_RAB_DMA_IB_RD_ADDR; + uint32_t RAC_RAB_DMA_OB_WR_ADDR; + uint32_t RAC_RAB_DMA_IB_WR_ADDR; + + uint32_t RAC_RAB_BUF_FREE_IB_FREE_MASK; + uint32_t RAC_RAB_BUF_FREE_OB_FREE_MASK; + uint32_t RAC_RAB_BUF_USED_IB_USED_MASK; + uint32_t RAC_RAB_BUF_USED_OB_USED_MASK; + uint32_t RAC_RAB_BUF_USED_FLUSH_MASK; + + uint32_t RAC_RAB_BUF_USED_OB_USED_LOW; + + uint32_t RAC_NMB_RD_ADR_ADDR; + uint32_t RAC_NMB_DATA_ADDR; + uint32_t RAC_NMB_WR_ADR_ADDR; + uint32_t RAC_NMB_STATUS_ADDR; + + bool m_dma_active; + + struct nt_dma_s *m_dma; + + volatile uint32_t *m_dma_in_buf; + volatile uint32_t *m_dma_out_buf; + + uint16_t m_dma_out_ptr_rd; + uint16_t m_dma_in_ptr_wr; + uint32_t m_in_free; +}; + +typedef struct nthw_rac nthw_rac_t; +typedef struct nthw_rac nthw_rac; + +struct dma_buf_ptr { + uint32_t size; + uint32_t index; + volatile uint32_t *base; +}; + +nthw_rac_t *nthw_rac_new(void); +int nthw_rac_init(nthw_rac_t *p, nthw_fpga_t *p_fpga, struct fpga_info_s *p_fpga_info); + +int nthw_rac_rab_init(nthw_rac_t *p, uint32_t n_rab_intf_mask); + +int nthw_rac_rab_setup(nthw_rac_t *p); + +int nthw_rac_rab_reset(nthw_rac_t *p); + +int nthw_rac_rab_write32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address, + uint32_t word_cnt, const uint32_t *p_data); +int nthw_rac_rab_read32(nthw_rac_t *p, bool trc, nthw_rab_bus_id_t bus_id, uint32_t address, + uint32_t word_cnt, uint32_t *p_data); + +int nthw_rac_rab_flush(nthw_rac_t *p); + +void nthw_rac_bar0_read32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr, + uint32_t word_cnt, uint32_t *p_data); +void nthw_rac_bar0_write32(const struct fpga_info_s *p_fpga_info, uint32_t reg_addr, + uint32_t word_cnt, const uint32_t *p_data); + +#endif /* __NTHW_RAC_H__ */ From patchwork Wed Jul 17 13:32:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142473 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9B1C45635; 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Signed-off-by: Serhii Iliushyk --- v5 * Fix Typo/Spelling v7 * Add FW update feature to documentation - INI and RST files v10 * Use 8 spaces as indentation in meson --- doc/guides/nics/features/ntnic.ini | 1 + doc/guides/nics/ntnic.rst | 5 + drivers/net/ntnic/adapter/nt4ga_adapter.c | 49 +++- drivers/net/ntnic/meson.build | 7 + .../net/ntnic/nthw/core/include/nthw_core.h | 4 + .../net/ntnic/nthw/core/include/nthw_fpga.h | 22 ++ drivers/net/ntnic/nthw/core/nthw_fpga.c | 222 ++++++++++++++++++ drivers/net/ntnic/nthw/nthw_drv.h | 1 + drivers/net/ntnic/nthw/nthw_register.h | 1 + drivers/net/ntnic/ntnic_ethdev.c | 41 +++- drivers/net/ntnic/ntnic_mod_reg.h | 1 + 11 files changed, 352 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_fpga.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_fpga.c diff --git a/doc/guides/nics/features/ntnic.ini b/doc/guides/nics/features/ntnic.ini index 9ceb75a03b..03f4d5aac8 100644 --- a/doc/guides/nics/features/ntnic.ini +++ b/doc/guides/nics/features/ntnic.ini @@ -4,5 +4,6 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +FW version = Y Linux = Y x86-64 = Y diff --git a/doc/guides/nics/ntnic.rst b/doc/guides/nics/ntnic.rst index b150fe1481..db168e1686 100644 --- a/doc/guides/nics/ntnic.rst +++ b/doc/guides/nics/ntnic.rst @@ -29,6 +29,11 @@ Supported NICs All information about NT200A02 can be found by link below: https://www.napatech.com/products/nt200a02-smartnic-inline/ +Features +-------- + +- FW version + Limitations ~~~~~~~~~~~ diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c index 42b3a98d21..381884349b 100644 --- a/drivers/net/ntnic/adapter/nt4ga_adapter.c +++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c @@ -6,7 +6,7 @@ #include #include "ntlog.h" -#include "nt_util.h" +#include "nthw_fpga.h" #include "ntnic_mod_reg.h" static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *pfh) @@ -15,6 +15,7 @@ static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE * const char *const p_adapter_id_str = p_adapter_info->mp_adapter_id_str; fpga_info_t *p_fpga_info = &p_adapter_info->fpga_info; hw_info_t *p_hw_info = &p_adapter_info->hw_info; + mcu_info_t *mcu_info = &p_adapter_info->fpga_info.mcu_info; char a_pci_ident_str[32]; snprintf(a_pci_ident_str, sizeof(a_pci_ident_str), PCIIDENT_PRINT_STR, @@ -37,6 +38,8 @@ static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE * fprintf(pfh, "%s: Hw=0x%02X_rev%d: %s\n", p_adapter_id_str, p_hw_info->hw_platform_id, p_fpga_info->nthw_hw_info.hw_id, p_fpga_info->nthw_hw_info.hw_plat_id_str); fprintf(pfh, "%s: MCU Details:\n", p_adapter_id_str); + fprintf(pfh, "%s: HasMcu=%d McuType=%d McuDramSize=%d\n", p_adapter_id_str, + mcu_info->mb_has_mcu, mcu_info->mn_mcu_type, mcu_info->mn_mcu_dram_size); return 0; } @@ -48,6 +51,13 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) fpga_info_t *fpga_info = &p_adapter_info->fpga_info; hw_info_t *p_hw_info = &p_adapter_info->hw_info; + /* + * IMPORTANT: Most variables cannot be determined before nthw fpga model is instantiated + * (nthw_fpga_init()) + */ + int n_phy_ports = -1; + int res = -1; + nthw_fpga_t *p_fpga = NULL; p_hw_info->n_nthw_adapter_id = nthw_platform_get_nthw_adapter_id(p_hw_info->pci_device_id); @@ -99,6 +109,39 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) } } + res = nthw_fpga_init(&p_adapter_info->fpga_info); + + if (res) { + NT_LOG_DBGX(ERR, NTNIC, "%s: %s: FPGA=%04d res=x%08X\n", p_adapter_id_str, + p_dev_name, fpga_info->n_fpga_prod_id, res); + return res; + } + + assert(fpga_info); + p_fpga = fpga_info->mp_fpga; + assert(p_fpga); + n_phy_ports = fpga_info->n_phy_ports; + assert(n_phy_ports >= 1); + + { + assert(fpga_info->n_fpga_prod_id > 0); + + switch (fpga_info->n_fpga_prod_id) { + default: + NT_LOG(ERR, NTNIC, "Unsupported FPGA product: %04d\n", + fpga_info->n_fpga_prod_id); + res = -1; + break; + } + + if (res) { + NT_LOG_DBGX(ERR, NTNIC, "%s: %s: FPGA=%04d res=x%08X\n", + p_adapter_id_str, p_dev_name, + fpga_info->n_fpga_prod_id, res); + return res; + } + } + return 0; } @@ -108,6 +151,10 @@ static int nt4ga_adapter_deinit(struct adapter_info_s *p_adapter_info) int i; int res = -1; + nthw_fpga_shutdown(&p_adapter_info->fpga_info); + + /* Rac rab reset flip flop */ + res = nthw_rac_rab_reset(fpga_info->mp_nthw_rac); /* Free adapter port ident strings */ for (i = 0; i < fpga_info->n_phy_ports; i++) { diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index a3522ca20b..74d4f12425 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -16,6 +16,7 @@ includes = [ include_directories('nthw/core/include'), include_directories('nthw'), include_directories('nthw/supported'), + include_directories('nthw/model'), ] # all sources @@ -24,7 +25,13 @@ sources = files( 'nthw/supported/nthw_fpga_9563_055_039_0000.c', 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', + 'nthw/core/nthw_fpga.c', + 'nthw/core/nthw_hif.c', + 'nthw/core/nthw_iic.c', + 'nthw/core/nthw_pcie3.c', + 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', + 'nthw/nthw_rac.c', 'ntlog/ntlog.c', 'ntutil/nt_util.c', 'ntnic_mod_reg.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index c2602e396f..69af113816 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -11,6 +11,10 @@ #include #include "nthw_platform_drv.h" +#include "nthw_fpga_model.h" +#include "nthw_hif.h" +#include "nthw_pcie3.h" +#include "nthw_iic.h" #endif /* __NTHW_CORE_H__ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h new file mode 100644 index 0000000000..1943f6e225 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h @@ -0,0 +1,22 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_FPGA_H__ +#define __NTHW_FPGA_H__ + +#include "nthw_drv.h" + +#include "nthw_fpga_model.h" + +#include "nthw_rac.h" +#include "nthw_iic.h" + +int nthw_fpga_init(struct fpga_info_s *p_fpga_info); +int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info); + +int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga); + + +#endif /* __NTHW_FPGA_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c new file mode 100644 index 0000000000..df238ec4ef --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c @@ -0,0 +1,222 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_fpga.h" + +#include "nthw_fpga_instances.h" +#include "nthw_fpga_mod_str_map.h" + +#include + +int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga) +{ + mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info; + + const int n_phy_ports = nthw_fpga_get_product_param(p_fpga, NT_PHY_PORTS, -1); + const int n_phy_quads = nthw_fpga_get_product_param(p_fpga, NT_PHY_QUADS, -1); + const int n_rx_ports = nthw_fpga_get_product_param(p_fpga, NT_RX_PORTS, -1); + const int n_tx_ports = nthw_fpga_get_product_param(p_fpga, NT_TX_PORTS, -1); + const int n_vf_offset = nthw_fpga_get_product_param(p_fpga, NT_HIF_VF_OFFSET, 4); + + p_fpga_info->n_phy_ports = n_phy_ports; + p_fpga_info->n_phy_quads = n_phy_quads; + p_fpga_info->n_rx_ports = n_rx_ports; + p_fpga_info->n_tx_ports = n_tx_ports; + p_fpga_info->n_vf_offset = n_vf_offset; + p_fpga_info->profile = FPGA_INFO_PROFILE_UNKNOWN; + + /* Check for MCU */ + if (nthw_fpga_get_product_param(p_fpga, NT_MCU_PRESENT, 0) != 0) { + p_mcu_info->mb_has_mcu = true; + /* Check MCU Type */ + p_mcu_info->mn_mcu_type = nthw_fpga_get_product_param(p_fpga, NT_MCU_TYPE, -1); + /* MCU DRAM size */ + p_mcu_info->mn_mcu_dram_size = + nthw_fpga_get_product_param(p_fpga, NT_MCU_DRAM_SIZE, -1); + + } else { + p_mcu_info->mb_has_mcu = false; + p_mcu_info->mn_mcu_type = -1; + p_mcu_info->mn_mcu_dram_size = -1; + } + + /* Check for VSWITCH FPGA */ + if (nthw_fpga_get_product_param(p_fpga, NT_NFV_OVS_PRODUCT, 0) != 0) { + p_fpga_info->profile = FPGA_INFO_PROFILE_VSWITCH; + + } else if (nthw_fpga_get_product_param(p_fpga, NT_IOA_PRESENT, 0) != 0) { + /* Check for VSWITCH FPGA - legacy */ + p_fpga_info->profile = FPGA_INFO_PROFILE_VSWITCH; + + } else if (nthw_fpga_get_product_param(p_fpga, NT_QM_PRESENT, 0) != 0) { + p_fpga_info->profile = FPGA_INFO_PROFILE_CAPTURE; + + } else { + p_fpga_info->profile = FPGA_INFO_PROFILE_INLINE; + } + + return 0; +} + +int nthw_fpga_init(struct fpga_info_s *p_fpga_info) +{ + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + + nthw_hif_t *p_nthw_hif = NULL; + nthw_pcie3_t *p_nthw_pcie3 = NULL; + nthw_rac_t *p_nthw_rac = NULL; + + mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info; + uint64_t n_fpga_ident = 0; + nthw_fpga_mgr_t *p_fpga_mgr = NULL; + nthw_fpga_t *p_fpga = NULL; + + char s_fpga_prod_ver_rev_str[32] = { 0 }; + + int res = 0; + + assert(p_fpga_info); + + { + const uint64_t n_fpga_ident = nthw_fpga_read_ident(p_fpga_info); + const uint32_t n_fpga_build_time = nthw_fpga_read_buildtime(p_fpga_info); + const int n_fpga_type_id = nthw_fpga_extract_type_id(n_fpga_ident); + const int n_fpga_prod_id = nthw_fpga_extract_prod_id(n_fpga_ident); + const int n_fpga_ver_id = nthw_fpga_extract_ver_id(n_fpga_ident); + const int n_fpga_rev_id = nthw_fpga_extract_rev_id(n_fpga_ident); + + p_fpga_info->n_fpga_ident = n_fpga_ident; + p_fpga_info->n_fpga_type_id = n_fpga_type_id; + p_fpga_info->n_fpga_prod_id = n_fpga_prod_id; + p_fpga_info->n_fpga_ver_id = n_fpga_ver_id; + p_fpga_info->n_fpga_rev_id = n_fpga_rev_id; + p_fpga_info->n_fpga_build_time = n_fpga_build_time; + + snprintf(s_fpga_prod_ver_rev_str, sizeof(s_fpga_prod_ver_rev_str), + "%04d-%04d-%02d-%02d", n_fpga_type_id, n_fpga_prod_id, n_fpga_ver_id, + n_fpga_rev_id); + + NT_LOG(INF, NTHW, "%s: FPGA %s (%" PRIX64 ") [%08X]\n", p_adapter_id_str, + s_fpga_prod_ver_rev_str, n_fpga_ident, n_fpga_build_time); + } + + n_fpga_ident = p_fpga_info->n_fpga_ident; + + p_fpga_mgr = nthw_fpga_mgr_new(); + nthw_fpga_mgr_init(p_fpga_mgr, nthw_fpga_instances, + (const void *)sa_nthw_fpga_mod_str_map); + nthw_fpga_mgr_log_dump(p_fpga_mgr); + p_fpga = nthw_fpga_mgr_query_fpga(p_fpga_mgr, n_fpga_ident, p_fpga_info); + p_fpga_info->mp_fpga = p_fpga; + + if (p_fpga == NULL) { + NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: %s (%08X)\n", p_adapter_id_str, + s_fpga_prod_ver_rev_str, p_fpga_info->n_fpga_build_time); + return -1; + } + + if (p_fpga_mgr) { + nthw_fpga_mgr_delete(p_fpga_mgr); + p_fpga_mgr = NULL; + } + + /* Read Fpga param info */ + nthw_fpga_get_param_info(p_fpga_info, p_fpga); + + /* debug: report params */ + NT_LOG(DBG, NTHW, "%s: NT_PHY_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_ports); + NT_LOG(DBG, NTHW, "%s: NT_PHY_QUADS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_quads); + NT_LOG(DBG, NTHW, "%s: NT_RX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_rx_ports); + NT_LOG(DBG, NTHW, "%s: NT_TX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_tx_ports); + NT_LOG(DBG, NTHW, "%s: nProfile=%d\n", p_adapter_id_str, (int)p_fpga_info->profile); + NT_LOG(DBG, NTHW, "%s: bHasMcu=%d\n", p_adapter_id_str, p_mcu_info->mb_has_mcu); + NT_LOG(DBG, NTHW, "%s: McuType=%d\n", p_adapter_id_str, p_mcu_info->mn_mcu_type); + NT_LOG(DBG, NTHW, "%s: McuDramSize=%d\n", p_adapter_id_str, p_mcu_info->mn_mcu_dram_size); + + p_nthw_rac = nthw_rac_new(); + + if (p_nthw_rac == NULL) { + NT_LOG(ERR, NTHW, "%s: Unsupported FPGA: RAC is not found: %s (%08X)\n", + p_adapter_id_str, s_fpga_prod_ver_rev_str, p_fpga_info->n_fpga_build_time); + return -1; + } + + nthw_rac_init(p_nthw_rac, p_fpga, p_fpga_info); + nthw_rac_rab_flush(p_nthw_rac); + p_fpga_info->mp_nthw_rac = p_nthw_rac; + + switch (p_fpga_info->n_nthw_adapter_id) { + default: + NT_LOG(ERR, NTHW, "%s: Unsupported HW product id: %d\n", p_adapter_id_str, + p_fpga_info->n_nthw_adapter_id); + res = -1; + break; + } + + if (res) { + NT_LOG(ERR, NTHW, "%s: status: 0x%08X\n", p_adapter_id_str, res); + return res; + } + + res = nthw_pcie3_init(NULL, p_fpga, 0); /* Probe for module */ + + if (res == 0) { + p_nthw_pcie3 = nthw_pcie3_new(); + + if (p_nthw_pcie3) { + res = nthw_pcie3_init(p_nthw_pcie3, p_fpga, 0); + + if (res == 0) { + NT_LOG(DBG, NTHW, "%s: Pcie3 module found\n", p_adapter_id_str); + nthw_pcie3_trigger_sample_time(p_nthw_pcie3); + + } else { + nthw_pcie3_delete(p_nthw_pcie3); + p_nthw_pcie3 = NULL; + } + } + + p_fpga_info->mp_nthw_pcie3 = p_nthw_pcie3; + } + + if (p_nthw_pcie3 == NULL) { + p_nthw_hif = nthw_hif_new(); + + if (p_nthw_hif) { + res = nthw_hif_init(p_nthw_hif, p_fpga, 0); + + if (res == 0) { + NT_LOG(DBG, NTHW, "%s: Hif module found\n", p_adapter_id_str); + nthw_hif_trigger_sample_time(p_nthw_hif); + + } else { + nthw_hif_delete(p_nthw_hif); + p_nthw_hif = NULL; + } + } + } + + p_fpga_info->mp_nthw_hif = p_nthw_hif; + + + return res; +} + +int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info) +{ + int res = -1; + + if (p_fpga_info) { + if (p_fpga_info && p_fpga_info->mp_nthw_rac) + res = nthw_rac_rab_reset(p_fpga_info->mp_nthw_rac); + } + + return res; +} diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h index d7cd64bb1d..071618eb6e 100644 --- a/drivers/net/ntnic/nthw/nthw_drv.h +++ b/drivers/net/ntnic/nthw/nthw_drv.h @@ -22,6 +22,7 @@ enum fpga_info_profile { }; typedef struct mcu_info_s { + bool mb_has_mcu; int mn_mcu_type; int mn_mcu_dram_size; } mcu_info_t; diff --git a/drivers/net/ntnic/nthw/nthw_register.h b/drivers/net/ntnic/nthw/nthw_register.h index db006fcf72..ecc661a656 100644 --- a/drivers/net/ntnic/nthw/nthw_register.h +++ b/drivers/net/ntnic/nthw/nthw_register.h @@ -11,6 +11,7 @@ #include #include +#include "nthw_fpga_model.h" #include "fpga_model.h" diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 5d154c8e38..b68fcba25b 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -175,12 +175,33 @@ eth_dev_close(struct rte_eth_dev *eth_dev) return 0; } +static int +eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size) +{ + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + + fpga_info_t *fpga_info = &internals->p_drv->ntdrv.adapter_info.fpga_info; + const int length = snprintf(fw_version, fw_size, "%03d-%04d-%02d-%02d", + fpga_info->n_fpga_type_id, fpga_info->n_fpga_prod_id, + fpga_info->n_fpga_ver_id, fpga_info->n_fpga_rev_id); + + if ((size_t)length < fw_size) { + /* We have space for the version string */ + return 0; + + } else { + /* We do not have space for the version string -return the needed space */ + return length + 1; + } +} + static const struct eth_dev_ops nthw_eth_dev_ops = { .dev_configure = eth_dev_configure, .dev_start = eth_dev_start, .dev_stop = eth_dev_stop, .dev_close = eth_dev_close, .dev_infos_get = eth_dev_infos_get, + .fw_version_get = eth_fw_version_get, }; static int @@ -197,6 +218,8 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) struct drv_s *p_drv; ntdrv_4ga_t *p_nt_drv; + hw_info_t *p_hw_info; + fpga_info_t *fpga_info; uint32_t n_port_mask = -1; /* All ports enabled by default */ uint32_t nb_rx_queues = 1; uint32_t nb_tx_queues = 1; @@ -228,6 +251,8 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) /* context */ p_nt_drv = &p_drv->ntdrv; + p_hw_info = &p_nt_drv->adapter_info.hw_info; + fpga_info = &p_nt_drv->adapter_info.fpga_info; p_drv->p_dev = pci_dev; @@ -237,6 +262,11 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) p_nt_drv->adapter_info.n_rx_host_buffers = nb_rx_queues; p_nt_drv->adapter_info.n_tx_host_buffers = nb_tx_queues; + fpga_info->bar0_addr = (void *)pci_dev->mem_resource[0].addr; + fpga_info->bar0_size = pci_dev->mem_resource[0].len; + fpga_info->numa_node = pci_dev->device.numa_node; + fpga_info->pciident = p_nt_drv->pciident; + fpga_info->adapter_no = p_drv->adapter_no; p_nt_drv->adapter_info.hw_info.pci_class_id = pci_dev->id.class_id; p_nt_drv->adapter_info.hw_info.pci_vendor_id = pci_dev->id.vendor_id; @@ -273,6 +303,15 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) /* mp_adapter_id_str is initialized after nt4ga_adapter_init(p_nt_drv) */ const char *const p_adapter_id_str = p_nt_drv->adapter_info.mp_adapter_id_str; (void)p_adapter_id_str; + NT_LOG(DBG, NTNIC, + "%s: %s: AdapterPCI=" PCIIDENT_PRINT_STR " Hw=0x%02X_rev%d PhyPorts=%d\n", + (pci_dev->name[0] ? pci_dev->name : "NA"), p_adapter_id_str, + PCIIDENT_TO_DOMAIN(p_nt_drv->adapter_info.fpga_info.pciident), + PCIIDENT_TO_BUSNR(p_nt_drv->adapter_info.fpga_info.pciident), + PCIIDENT_TO_DEVNR(p_nt_drv->adapter_info.fpga_info.pciident), + PCIIDENT_TO_FUNCNR(p_nt_drv->adapter_info.fpga_info.pciident), + p_hw_info->hw_platform_id, fpga_info->nthw_hw_info.hw_id, + fpga_info->n_phy_ports); } else { NT_LOG_DBGX(ERR, NTNIC, "%s: error=%d\n", @@ -280,7 +319,7 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) return -1; } - n_phy_ports = 0; + n_phy_ports = fpga_info->n_phy_ports; for (int n_intf_no = 0; n_intf_no < n_phy_ports; n_intf_no++) { const char *const p_port_id_str = p_nt_drv->adapter_info.mp_port_id_str[n_intf_no]; diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index 48a9f8f7b9..96fc829399 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -7,6 +7,7 @@ #define __NTNIC_MOD_REG_H__ #include +#include "nthw_fpga_model.h" #include "nthw_platform_drv.h" #include "nthw_drv.h" #include "nt4ga_adapter.h" From patchwork Wed Jul 17 13:32:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142466 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C40445635; 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Received-SPF: Fail (protection.outlook.com: domain of napatech.com does not designate 178.72.21.4 as permitted sender) receiver=protection.outlook.com; client-ip=178.72.21.4; helo=localhost.localdomain; Received: from localhost.localdomain (178.72.21.4) by AM3PEPF0000A799.mail.protection.outlook.com (10.167.16.104) with Microsoft SMTP Server id 15.20.7784.11 via Frontend Transport; Wed, 17 Jul 2024 13:33:24 +0000 From: Serhii Iliushyk To: dev@dpdk.org Cc: mko-plv@napatech.com, sil-plv@napatech.com, ckm@napatech.com, andrew.rybchenko@oktetlabs.ru, ferruh.yigit@amd.com Subject: [PATCH v10 12/21] net/ntnic: add support of the NT200A0X smartNIC Date: Wed, 17 Jul 2024 15:32:59 +0200 Message-ID: <20240717133313.3104239-12-sil-plv@napatech.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240717133313.3104239-1-sil-plv@napatech.com> References: <20240530144929.4127931-1-sil-plv@napatech.com> <20240717133313.3104239-1-sil-plv@napatech.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM3PEPF0000A799:EE_|DB8P190MB0700:EE_ X-MS-Office365-Filtering-Correlation-Id: 63214352-9d14-458e-f59d-08dca6650855 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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switch (fpga_info->n_fpga_prod_id) { + /* NT200A01: 2x100G (Xilinx) */ + case 9563: /* NT200A02 (Cap) */ + NT_LOG(ERR, NTNIC, "NT200A02 100G link module uninitialized\n"); + res = -1; + break; + default: NT_LOG(ERR, NTNIC, "Unsupported FPGA product: %04d\n", fpga_info->n_fpga_prod_id); diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 74d4f12425..e6e930f09b 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -25,6 +25,7 @@ sources = files( 'nthw/supported/nthw_fpga_9563_055_039_0000.c', 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', + 'nthw/core/nt200a0x/nthw_fpga_nt200a0x.c', 'nthw/core/nthw_fpga.c', 'nthw/core/nthw_hif.c', 'nthw/core/nthw_iic.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h index 1943f6e225..ba86b4d8d2 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h @@ -18,5 +18,12 @@ int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info); int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga); +struct nt200a0x_ops { + int (*nthw_fpga_nt200a0x_init)(struct fpga_info_s *p_fpga_info); +}; + +void register_nt200a0x_ops(struct nt200a0x_ops *ops); +struct nt200a0x_ops *get_nt200a0x_ops(void); +void nt200a0x_ops_init(void); #endif /* __NTHW_FPGA_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c new file mode 100644 index 0000000000..7db6a03d88 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c @@ -0,0 +1,54 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_fpga.h" +#include "ntnic_mod_reg.h" + +static int nthw_fpga_nt200a0x_init(struct fpga_info_s *p_fpga_info) +{ + assert(p_fpga_info); + + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + int res = -1; + + bool included = true; + + /* reset specific */ + switch (p_fpga_info->n_fpga_prod_id) { + case 9563: + included = false; + break; + + default: + NT_LOG(ERR, NTHW, "%s: Unsupported FPGA product: %04d\n", p_adapter_id_str, + p_fpga_info->n_fpga_prod_id); + res = -1; + break; + } + + if (!included) { + NT_LOG(ERR, NTHW, "%s: NOT INCLUDED FPGA product: %04d\n", p_adapter_id_str, + p_fpga_info->n_fpga_prod_id); + res = -1; + } + + if (res) { + NT_LOG_DBGX(ERR, NTHW, "%s: FPGA=%04d res=%d\n", p_adapter_id_str, + p_fpga_info->n_fpga_prod_id, res); + return res; + } + + return res; +} + +static struct nt200a0x_ops nt200a0x_ops = { .nthw_fpga_nt200a0x_init = nthw_fpga_nt200a0x_init }; + +void nt200a0x_ops_init(void) +{ + NT_LOG(INF, NTHW, "NT200A0X OPS INIT\n"); + register_nt200a0x_ops(&nt200a0x_ops); +} diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c index df238ec4ef..98d29744cb 100644 --- a/drivers/net/ntnic/nthw/core/nthw_fpga.c +++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c @@ -152,7 +152,18 @@ int nthw_fpga_init(struct fpga_info_s *p_fpga_info) nthw_rac_rab_flush(p_nthw_rac); p_fpga_info->mp_nthw_rac = p_nthw_rac; + bool included = true; + struct nt200a0x_ops *nt200a0x_ops = get_nt200a0x_ops(); + switch (p_fpga_info->n_nthw_adapter_id) { + case NT_HW_ADAPTER_ID_NT200A02: + if (nt200a0x_ops != NULL) + res = nt200a0x_ops->nthw_fpga_nt200a0x_init(p_fpga_info); + + else + included = false; + + break; default: NT_LOG(ERR, NTHW, "%s: Unsupported HW product id: %d\n", p_adapter_id_str, p_fpga_info->n_nthw_adapter_id); @@ -160,6 +171,12 @@ int nthw_fpga_init(struct fpga_info_s *p_fpga_info) break; } + if (!included) { + NT_LOG(ERR, NTHW, "%s: NOT INCLUDED HW product: %d\n", p_adapter_id_str, + p_fpga_info->n_nthw_adapter_id); + res = -1; + } + if (res) { NT_LOG(ERR, NTHW, "%s: status: 0x%08X\n", p_adapter_id_str, res); return res; @@ -220,3 +237,17 @@ int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info) return res; } + +static struct nt200a0x_ops *nt200a0x_ops; + +void register_nt200a0x_ops(struct nt200a0x_ops *ops) +{ + nt200a0x_ops = ops; +} + +struct nt200a0x_ops *get_nt200a0x_ops(void) +{ + if (nt200a0x_ops == NULL) + nt200a0x_ops_init(); + return nt200a0x_ops; +} diff --git a/drivers/net/ntnic/nthw/nthw_platform.c b/drivers/net/ntnic/nthw/nthw_platform.c index 181330dd37..33e18e549f 100644 --- a/drivers/net/ntnic/nthw/nthw_platform.c +++ b/drivers/net/ntnic/nthw/nthw_platform.c @@ -8,6 +8,9 @@ nthw_adapter_id_t nthw_platform_get_nthw_adapter_id(const uint16_t n_pci_device_id) { switch (n_pci_device_id) { + case NT_HW_PCI_DEVICE_ID_NT200A02: + return NT_HW_ADAPTER_ID_NT200A02; + default: return NT_HW_ADAPTER_ID_UNKNOWN; } diff --git a/drivers/net/ntnic/nthw/nthw_platform_drv.h b/drivers/net/ntnic/nthw/nthw_platform_drv.h index ab26d8149a..42eb0b8b05 100644 --- a/drivers/net/ntnic/nthw/nthw_platform_drv.h +++ b/drivers/net/ntnic/nthw/nthw_platform_drv.h @@ -9,9 +9,11 @@ #include #define NT_HW_PCI_VENDOR_ID (0x18f4) +#define NT_HW_PCI_DEVICE_ID_NT200A02 (0x1C5) enum nthw_adapter_id_e { NT_HW_ADAPTER_ID_UNKNOWN = 0, + NT_HW_ADAPTER_ID_NT200A02, }; typedef enum nthw_adapter_id_e nthw_adapter_id_t; diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index b68fcba25b..5d3da88c58 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -25,6 +25,7 @@ #define EXCEPTION_PATH_HID 0 static const struct rte_pci_id nthw_pci_id_map[] = { + { RTE_PCI_DEVICE(NT_HW_PCI_VENDOR_ID, NT_HW_PCI_DEVICE_ID_NT200A02) }, { .vendor_id = 0, }, /* sentinel */ @@ -475,9 +476,11 @@ nthw_pci_remove(struct rte_pci_device *pci_dev) static struct rte_pci_driver rte_nthw_pmd = { .id_table = nthw_pci_id_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, .probe = nthw_pci_probe, .remove = nthw_pci_remove, }; RTE_PMD_REGISTER_PCI(net_ntnic, rte_nthw_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_ntnic, nthw_pci_id_map); RTE_PMD_REGISTER_KMOD_DEP(net_ntnic, "* vfio-pci"); From patchwork Wed Jul 17 13:33:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142469 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08CD545635; Wed, 17 Jul 2024 15:34:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3FB4D42D68; Wed, 17 Jul 2024 15:33:39 +0200 (CEST) Received: from egress-ip11b.ess.de.barracuda.com (egress-ip11b.ess.de.barracuda.com [18.185.115.215]) by mails.dpdk.org (Postfix) with ESMTP id 03742410F2 for ; Wed, 17 Jul 2024 15:33:30 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05lp2113.outbound.protection.outlook.com [104.47.18.113]) by mx-outbound23-33.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); 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Also adds SDRAM Controller (SDC) module, as it is part of the startup and reset sequence. Signed-off-by: Serhii Iliushyk --- v5 * Fix Typo/Spelling v10 * Use 8 spaces as indentation in meson --- .../include/ntnic_nthw_fpga_rst_nt200a0x.h | 81 +++ drivers/net/ntnic/meson.build | 3 + .../net/ntnic/nthw/core/include/nthw_core.h | 2 + .../net/ntnic/nthw/core/include/nthw_fpga.h | 6 + .../net/ntnic/nthw/core/include/nthw_sdc.h | 42 ++ .../nthw/core/nt200a0x/nthw_fpga_nt200a0x.c | 24 +- .../core/nt200a0x/reset/nthw_fpga_rst9563.c | 216 +++++++ .../nt200a0x/reset/nthw_fpga_rst_nt200a0x.c | 570 ++++++++++++++++++ drivers/net/ntnic/nthw/core/nthw_fpga.c | 82 +++ drivers/net/ntnic/nthw/core/nthw_sdc.c | 176 ++++++ drivers/net/ntnic/ntnic_mod_reg.c | 28 + drivers/net/ntnic/ntnic_mod_reg.h | 20 + 12 files changed, 1249 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_sdc.h create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c create mode 100644 drivers/net/ntnic/nthw/core/nthw_sdc.c diff --git a/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h new file mode 100644 index 0000000000..8a0b3fae50 --- /dev/null +++ b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h @@ -0,0 +1,81 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTNIC_NTHW_FPGA_RST_NT200A0X_H__ +#define __NTNIC_NTHW_FPGA_RST_NT200A0X_H__ + +#include "nthw_drv.h" +#include "nthw_fpga_model.h" + +struct nthw_fpga_rst_nt200a0x { + int mn_fpga_product_id; + int mn_fpga_version; + int mn_fpga_revision; + + int mn_hw_id; + + int mn_si_labs_clock_synth_model; + + nthw_field_t *mp_fld_rst_sys; + nthw_field_t *mp_fld_rst_sys_mmcm; + nthw_field_t *mp_fld_rst_core_mmcm; + nthw_field_t *mp_fld_rst_rpp; + nthw_field_t *mp_fld_rst_ddr4; + nthw_field_t *mp_fld_rst_sdc; + nthw_field_t *mp_fld_rst_phy; + nthw_field_t *mp_fld_rst_serdes_rx; + nthw_field_t *mp_fld_rst_serdes_tx; + nthw_field_t *mp_fld_rst_serdes_rx_datapath; + nthw_field_t *mp_fld_rst_pcs_rx; + nthw_field_t *mp_fld_rst_mac_rx; + nthw_field_t *mp_fld_rst_mac_tx; + nthw_field_t *mp_fld_rst_ptp; + nthw_field_t *mp_fld_rst_ts; + nthw_field_t *mp_fld_rst_ptp_mmcm; + nthw_field_t *mp_fld_rst_ts_mmcm; + nthw_field_t *mp_fld_rst_periph; + nthw_field_t *mp_fld_rst_tsm_ref_mmcm; + nthw_field_t *mp_fld_rst_tmc; + + /* CTRL register field pointers */ + nthw_field_t *mp_fld_ctrl_ts_clk_sel_override; + nthw_field_t *mp_fld_ctrl_ts_clk_sel; + nthw_field_t *mp_fld_ctrl_ts_clk_sel_ref; + nthw_field_t *mp_fld_ctrl_ptp_mmcm_clk_sel; + + /* STAT register field pointers */ + nthw_field_t *mp_fld_stat_ddr4_mmcm_locked; + nthw_field_t *mp_fld_stat_sys_mmcm_locked; + nthw_field_t *mp_fld_stat_core_mmcm_locked; + nthw_field_t *mp_fld_stat_ddr4_pll_locked; + nthw_field_t *mp_fld_stat_ptp_mmcm_locked; + nthw_field_t *mp_fld_stat_ts_mmcm_locked; + nthw_field_t *mp_fld_stat_tsm_ref_mmcm_locked; + + /* STICKY register field pointers */ + nthw_field_t *mp_fld_sticky_ptp_mmcm_unlocked; + nthw_field_t *mp_fld_sticky_ts_mmcm_unlocked; + nthw_field_t *mp_fld_sticky_ddr4_mmcm_unlocked; + nthw_field_t *mp_fld_sticky_ddr4_pll_unlocked; + nthw_field_t *mp_fld_sticky_core_mmcm_unlocked; + nthw_field_t *mp_fld_sticky_pci_sys_mmcm_unlocked; + nthw_field_t *mp_fld_sticky_tsm_ref_mmcm_unlocked; + + /* POWER register field pointers */ + nthw_field_t *mp_fld_power_pu_phy; + nthw_field_t *mp_fld_power_pu_nseb; + + void (*reset_serdes_rx)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, uint32_t rst); + void (*pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, uint32_t rst); + void (*get_serdes_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, + uint32_t *p_set); + void (*get_pcs_rx_rst)(struct nthw_fpga_rst_nt200a0x *p, uint32_t intf_no, + uint32_t *p_set); + bool (*is_rst_serdes_rx_datapath_implemented)(struct nthw_fpga_rst_nt200a0x *p); +}; + +typedef struct nthw_fpga_rst_nt200a0x nthw_fpga_rst_nt200a0x_t; + +#endif /* __NTHW_FPGA_RST_NT200A0X_H__ */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index e6e930f09b..085719becb 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -26,10 +26,13 @@ sources = files( 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', 'nthw/core/nt200a0x/nthw_fpga_nt200a0x.c', + 'nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c', + 'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c', 'nthw/core/nthw_fpga.c', 'nthw/core/nthw_hif.c', 'nthw/core/nthw_iic.c', 'nthw/core/nthw_pcie3.c', + 'nthw/core/nthw_sdc.c', 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', 'nthw/nthw_rac.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index 69af113816..8bdf7ee01d 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -16,5 +16,7 @@ #include "nthw_pcie3.h" #include "nthw_iic.h" +#include "nthw_sdc.h" + #endif /* __NTHW_CORE_H__ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h index ba86b4d8d2..1df1480109 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h @@ -18,6 +18,12 @@ int nthw_fpga_shutdown(struct fpga_info_s *p_fpga_info); int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpga); +int nthw_fpga_iic_scan(nthw_fpga_t *p_fpga, const int n_instance_no_begin, + const int n_instance_no_end); + +int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const int n_dev_addr, + const int n_page_reg_addr); + struct nt200a0x_ops { int (*nthw_fpga_nt200a0x_init)(struct fpga_info_s *p_fpga_info); }; diff --git a/drivers/net/ntnic/nthw/core/include/nthw_sdc.h b/drivers/net/ntnic/nthw/core/include/nthw_sdc.h new file mode 100644 index 0000000000..58247d67f0 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_sdc.h @@ -0,0 +1,42 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_SDC_H__ +#define __NTHW_SDC_H__ + +struct nthw_sdc { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_sdc; + int mn_instance; + + nthw_field_t *mp_fld_ctrl_init; + nthw_field_t *mp_fld_ctrl_run_test; + nthw_field_t *mp_fld_ctrl_stop_client; + nthw_field_t *mp_fld_ctrl_test_enable; + + nthw_field_t *mp_fld_stat_calib; + nthw_field_t *mp_fld_stat_cell_cnt_stopped; + nthw_field_t *mp_fld_stat_err_found; + nthw_field_t *mp_fld_stat_init_done; + nthw_field_t *mp_fld_stat_mmcm_lock; + nthw_field_t *mp_fld_stat_pll_lock; + nthw_field_t *mp_fld_stat_resetting; + + nthw_field_t *mp_fld_cell_cnt; + nthw_field_t *mp_fld_cell_cnt_period; + nthw_field_t *mp_fld_fill_level; + nthw_field_t *mp_fld_max_fill_level; +}; + +typedef struct nthw_sdc nthw_sdc_t; + +nthw_sdc_t *nthw_sdc_new(void); +int nthw_sdc_init(nthw_sdc_t *p, nthw_fpga_t *p_fpga, int n_instance); +void nthw_sdc_delete(nthw_sdc_t *p); + +int nthw_sdc_wait_states(nthw_sdc_t *p, const int n_poll_iterations, const int n_poll_interval); +int nthw_sdc_get_states(nthw_sdc_t *p, uint64_t *pn_result_mask); + +#endif /* __NTHW_SDC_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c index 7db6a03d88..3009e30670 100644 --- a/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c +++ b/drivers/net/ntnic/nthw/core/nt200a0x/nthw_fpga_nt200a0x.c @@ -13,14 +13,36 @@ static int nthw_fpga_nt200a0x_init(struct fpga_info_s *p_fpga_info) assert(p_fpga_info); const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + struct nthw_fpga_rst_nt200a0x rst; int res = -1; + const struct rst_nt200a0x_ops *rst_nt200a0x_ops = get_rst_nt200a0x_ops(); + + if (rst_nt200a0x_ops == NULL) { + NT_LOG(ERR, NTHW, "RST NT200A0X NOT INCLUDED\n"); + return -1; + } + + /* reset common */ + res = rst_nt200a0x_ops->nthw_fpga_rst_nt200a0x_init(p_fpga_info, &rst); + + if (res) { + NT_LOG_DBGX(ERR, NTHW, "%s: FPGA=%04d res=%d\n", p_adapter_id_str, + p_fpga_info->n_fpga_prod_id, res); + return res; + } bool included = true; + struct rst9563_ops *rst9563_ops = get_rst9563_ops(); /* reset specific */ switch (p_fpga_info->n_fpga_prod_id) { case 9563: - included = false; + if (rst9563_ops != NULL) + res = rst9563_ops->nthw_fpga_rst9563_init(p_fpga_info, &rst); + + else + included = false; + break; default: diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c new file mode 100644 index 0000000000..a3b6511b06 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c @@ -0,0 +1,216 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" +#include "nthw_fpga.h" + +#include "ntnic_mod_reg.h" + +static int nthw_fpga_rst9563_setup(nthw_fpga_t *p_fpga, struct nthw_fpga_rst_nt200a0x *const p) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + const int n_fpga_product_id = p_fpga->mn_product_id; + const int n_fpga_version = p_fpga->mn_fpga_version; + const int n_fpga_revision = p_fpga->mn_fpga_revision; + + nthw_module_t *p_mod_rst; + nthw_register_t *p_curr_reg; + + assert(p); + p->mn_fpga_product_id = n_fpga_product_id; + p->mn_fpga_version = n_fpga_version; + p->mn_fpga_revision = n_fpga_revision; + + NT_LOG_DBGX(DEBUG, NTHW, "%s: FPGA reset setup: FPGA %04d-%02d-%02d\n", p_adapter_id_str, + n_fpga_product_id, n_fpga_version, n_fpga_revision); + + p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9563, 0); + + if (p_mod_rst == NULL) { + NT_LOG(ERR, NTHW, "%s: RST %d: no such instance\n", p_adapter_id_str, 0); + return -1; + } + + p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9563, 0); + + if (p_mod_rst == NULL) { + NT_LOG(ERR, NTHW, "%s: RST %d: no such instance\n", p_adapter_id_str, 0); + return -1; + } + + /* RST register field pointers */ + p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_RST); + p->mp_fld_rst_sys = nthw_register_get_field(p_curr_reg, RST9563_RST_SYS); + p->mp_fld_rst_sys_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_SYS_MMCM); + p->mp_fld_rst_core_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_CORE_MMCM); + p->mp_fld_rst_rpp = nthw_register_get_field(p_curr_reg, RST9563_RST_RPP); + p->mp_fld_rst_ddr4 = nthw_register_get_field(p_curr_reg, RST9563_RST_DDR4); + p->mp_fld_rst_sdc = nthw_register_get_field(p_curr_reg, RST9563_RST_SDC); + p->mp_fld_rst_phy = nthw_register_get_field(p_curr_reg, RST9563_RST_PHY); + p->mp_fld_rst_serdes_rx = NULL; /* Field not present on 9563 */ + p->mp_fld_rst_serdes_tx = NULL; /* Field not present on 9563 */ + p->mp_fld_rst_serdes_rx_datapath = NULL;/* Field not present on 9563 */ + p->mp_fld_rst_pcs_rx = NULL; /* Field not present on 9563 */ + p->mp_fld_rst_mac_rx = nthw_register_get_field(p_curr_reg, RST9563_RST_MAC_RX); + p->mp_fld_rst_mac_tx = NULL; + p->mp_fld_rst_ptp = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP); + p->mp_fld_rst_ptp = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP); + p->mp_fld_rst_ts = nthw_register_get_field(p_curr_reg, RST9563_RST_TS); + p->mp_fld_rst_ptp_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_PTP_MMCM); + p->mp_fld_rst_ts_mmcm = nthw_register_get_field(p_curr_reg, RST9563_RST_TS_MMCM); + /* referenced in separate function */ + p->mp_fld_rst_periph = nthw_register_get_field(p_curr_reg, RST9563_RST_PERIPH); + p->mp_fld_rst_tsm_ref_mmcm = + nthw_register_query_field(p_curr_reg, RST9563_RST_TSM_REF_MMCM); + p->mp_fld_rst_tmc = nthw_register_query_field(p_curr_reg, RST9563_RST_TMC); + + if (!p->mp_fld_rst_tsm_ref_mmcm) + NT_LOG(DBG, NTHW, "%s: No RST9563_RST_TSM_REF_MMCM found\n", p_adapter_id_str); + + if (!p->mp_fld_rst_tmc) + NT_LOG(DBG, NTHW, "%s: No RST9563_RST_TMC found\n", p_adapter_id_str); + + nthw_register_update(p_curr_reg); + + /* CTRL register field pointers */ + p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_CTRL); + p->mp_fld_ctrl_ts_clk_sel_override = + nthw_register_get_field(p_curr_reg, RST9563_CTRL_TS_CLKSEL_OVERRIDE); + /* Field not present on 9563 */ + p->mp_fld_ctrl_ts_clk_sel = nthw_register_get_field(p_curr_reg, RST9563_CTRL_TS_CLKSEL); + p->mp_fld_ctrl_ts_clk_sel_ref = NULL; /* Field not present on 9563 */ + p->mp_fld_ctrl_ptp_mmcm_clk_sel = + nthw_register_get_field(p_curr_reg, RST9563_CTRL_PTP_MMCM_CLKSEL); + nthw_register_update(p_curr_reg); + + /* STAT register field pointers */ + p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_STAT); + p->mp_fld_stat_ddr4_mmcm_locked = + nthw_register_get_field(p_curr_reg, RST9563_STAT_DDR4_MMCM_LOCKED); + p->mp_fld_stat_sys_mmcm_locked = + nthw_register_get_field(p_curr_reg, RST9563_STAT_SYS_MMCM_LOCKED); + p->mp_fld_stat_core_mmcm_locked = + nthw_register_get_field(p_curr_reg, RST9563_STAT_CORE_MMCM_LOCKED); + p->mp_fld_stat_ddr4_pll_locked = + nthw_register_get_field(p_curr_reg, RST9563_STAT_DDR4_PLL_LOCKED); + p->mp_fld_stat_ptp_mmcm_locked = + nthw_register_get_field(p_curr_reg, RST9563_STAT_PTP_MMCM_LOCKED); + p->mp_fld_stat_ts_mmcm_locked = + nthw_register_get_field(p_curr_reg, RST9563_STAT_TS_MMCM_LOCKED); + p->mp_fld_stat_tsm_ref_mmcm_locked = NULL; /* Field not present on 9563 */ + + if (!p->mp_fld_stat_tsm_ref_mmcm_locked) { + NT_LOG(DBG, NTHW, "%s: No RST9563_STAT_TSM_REF_MMCM_LOCKED found\n", + p_adapter_id_str); + } + + nthw_register_update(p_curr_reg); + + /* STICKY register field pointers */ + p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_STICKY); + p->mp_fld_sticky_ptp_mmcm_unlocked = + nthw_register_get_field(p_curr_reg, RST9563_STICKY_PTP_MMCM_UNLOCKED); + p->mp_fld_sticky_ts_mmcm_unlocked = + nthw_register_get_field(p_curr_reg, RST9563_STICKY_TS_MMCM_UNLOCKED); + p->mp_fld_sticky_ddr4_mmcm_unlocked = + nthw_register_get_field(p_curr_reg, RST9563_STICKY_DDR4_MMCM_UNLOCKED); + p->mp_fld_sticky_ddr4_pll_unlocked = + nthw_register_get_field(p_curr_reg, RST9563_STICKY_DDR4_PLL_UNLOCKED); + p->mp_fld_sticky_core_mmcm_unlocked = + nthw_register_get_field(p_curr_reg, RST9563_STICKY_CORE_MMCM_UNLOCKED); + p->mp_fld_sticky_pci_sys_mmcm_unlocked = NULL; /* Field not present on 9563 */ + p->mp_fld_sticky_tsm_ref_mmcm_unlocked = NULL; /* Field not present on 9563 */ + + if (!p->mp_fld_sticky_tsm_ref_mmcm_unlocked) { + NT_LOG(DBG, NTHW, "%s: No RST9563_STICKY_TSM_REF_MMCM_UNLOCKED found\n", + p_adapter_id_str); + } + + nthw_register_update(p_curr_reg); + + /* POWER register field pointers */ + p_curr_reg = nthw_module_get_register(p_mod_rst, RST9563_POWER); + p->mp_fld_power_pu_phy = nthw_register_get_field(p_curr_reg, RST9563_POWER_PU_PHY); + p->mp_fld_power_pu_nseb = nthw_register_get_field(p_curr_reg, RST9563_POWER_PU_NSEB); + nthw_register_update(p_curr_reg); + + return 0; +} + +static int nthw_fpga_rst9563_periph_reset(nthw_fpga_t *p_fpga) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + (void)p_adapter_id_str; + nthw_module_t *p_mod_rst = nthw_fpga_query_module(p_fpga, MOD_RST9563, 0); + + if (p_mod_rst) { + nthw_register_t *p_reg_rst; + nthw_field_t *p_fld_rst_periph; + NT_LOG(DBG, NTHW, "%s: PERIPH RST\n", p_adapter_id_str); + p_reg_rst = nthw_module_get_register(p_mod_rst, RST9563_RST); + p_fld_rst_periph = nthw_register_get_field(p_reg_rst, RST9563_RST_PERIPH); + nthw_field_set_flush(p_fld_rst_periph); + nthw_field_clr_flush(p_fld_rst_periph); + + } else { + return -1; + } + + return 0; +} + +static int nthw_fpga_rst9563_init(struct fpga_info_s *p_fpga_info, + struct nthw_fpga_rst_nt200a0x *p_rst) +{ + assert(p_fpga_info); + assert(p_rst); + + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + (void)p_adapter_id_str; + int res = -1; + nthw_fpga_t *p_fpga = NULL; + + p_fpga = p_fpga_info->mp_fpga; + + res = nthw_fpga_rst9563_periph_reset(p_fpga); + + if (res) { + NT_LOG_DBGX(DEBUG, NTHW, "%s: ERROR: res=%d\n", p_adapter_id_str, res); + return res; + } + + if (res) { + NT_LOG_DBGX(DEBUG, NTHW, "%s: ERROR: res=%d\n", p_adapter_id_str, res); + return res; + } + + res = nthw_fpga_rst9563_setup(p_fpga, p_rst); + + if (res) { + NT_LOG_DBGX(DEBUG, NTHW, "%s: ERROR: res=%d\n", p_adapter_id_str, res); + return res; + } + + const struct rst_nt200a0x_ops *rst_ops = get_rst_nt200a0x_ops(); + res = rst_ops != NULL ? rst_ops->nthw_fpga_rst_nt200a0x_reset(p_fpga, p_rst) : -1; + + if (res) { + NT_LOG_DBGX(DEBUG, NTHW, "%s: ERROR: res=%d\n", p_adapter_id_str, res); + return res; + } + + return res; +} + +static struct rst9563_ops rst9563_ops = { .nthw_fpga_rst9563_init = nthw_fpga_rst9563_init }; + +void rst9563_ops_init(void) +{ + NT_LOG(INF, NTHW, "RST9563 OPS INIT\n"); + register_rst9563_ops(&rst9563_ops); +} diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c new file mode 100644 index 0000000000..84f13e8371 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c @@ -0,0 +1,570 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" +#include "nthw_fpga.h" + +#include "ntnic_mod_reg.h" + +static const uint8_t si5338_u23_i2c_addr_7bit = 0x70; +static const uint8_t si5340_u23_i2c_addr_7bit = 0x74; + +/* + * Wait until DDR4 PLL LOCKED + */ +static int nthw_fpga_rst_nt200a0x_wait_ddr4_pll_locked(nthw_fpga_t *p_fpga, + const struct nthw_fpga_rst_nt200a0x *p) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + uint32_t locked; + uint32_t retrycount = 5; + uint32_t timeout = 50000; /* initial timeout must be set to 5 sec. */ + /* 14: wait until DDR4 PLL LOCKED */ + NT_LOG(DBG, NTHW, "%s: Waiting for DDR4 PLL to lock\n", p_adapter_id_str); + + /* + * The following retry count gives a total timeout of 1 * 5 + 5 * 8 = 45sec + * It has been observed that at least 21sec can be necessary + */ + while (true) { + int locked = + nthw_field_wait_set_any32(p->mp_fld_stat_ddr4_pll_locked, timeout, 100); + + if (locked == 0) { + break; + + } else { + NT_LOG(DBG, NTHW, "%s: Waiting for DDR4 PLL to lock - timeout\n", + p_adapter_id_str); + + if (retrycount <= 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for DDR4 PLL to lock failed (%d)\n", + p_adapter_id_str, locked); + break; + } + + nthw_field_set_flush(p->mp_fld_rst_ddr4); /* Reset DDR PLL */ + nthw_field_clr_flush(p->mp_fld_rst_ddr4); /* Reset DDR PLL */ + retrycount--; + timeout = 80000;/* Increase timeout for second attempt to 8 sec. */ + } + } + + NT_LOG(DBG, NTHW, "%s: Waiting for DDR4 MMCM to lock\n", p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_ddr4_mmcm_locked, -1, -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for DDR4 MMCM to lock failed (%d)\n", + p_adapter_id_str, locked); + return -1; + } + + if (true && p->mp_fld_stat_tsm_ref_mmcm_locked) { + NT_LOG(DBG, NTHW, "%s: Waiting for TSM REF MMCM to lock\n", p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_tsm_ref_mmcm_locked, -1, -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for TSM REF MMCM to lock failed (%d)\n", + p_adapter_id_str, locked); + return -1; + } + } + + /* 10: Clear all MMCM/PLL lock sticky bits before testing them */ + NT_LOG(DBG, NTHW, "%s: Clear sticky MMCM unlock bits\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_sticky_ptp_mmcm_unlocked); + /* Clear all sticky bits */ + nthw_field_set_flush(p->mp_fld_sticky_ptp_mmcm_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_ts_mmcm_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_ddr4_mmcm_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_ddr4_pll_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_core_mmcm_unlocked); + + if (p->mp_fld_sticky_tsm_ref_mmcm_unlocked) + nthw_field_set_flush(p->mp_fld_sticky_tsm_ref_mmcm_unlocked); + + if (p->mp_fld_sticky_pci_sys_mmcm_unlocked) + nthw_field_set_flush(p->mp_fld_sticky_pci_sys_mmcm_unlocked); + + /* 11: Ensure sticky bits are not unlocked except PTP MMCM and TS MMCM */ + if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_mmcm_unlocked() returned true\n", + p_adapter_id_str); + } + + if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_pll_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_pll_unlocked() returned true\n", + p_adapter_id_str); + } + + return 0; +} + +/* + * Wait for SDRAM controller has been calibrated - On some adapters we have seen + * calibration time of 2.3 seconds + */ +static int nthw_fpga_rst_nt200a0x_wait_sdc_calibrated(nthw_fpga_t *p_fpga, + const struct nthw_fpga_rst_nt200a0x *p) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_sdc_t *p_nthw_sdc = NULL; + const int n_retry_cnt_max = 5; + int n_retry_cnt; + int res; + + res = nthw_sdc_init(NULL, p_fpga, 0); /* probe for module */ + + if (res == 0) { + p_nthw_sdc = nthw_sdc_new(); + + if (p_nthw_sdc) { + res = nthw_sdc_init(p_nthw_sdc, p_fpga, 0); + + if (res) { + NT_LOG_DBGX(ERR, NTHW, "%s: SDC init failed: res=%d\n", + p_adapter_id_str, res); + nthw_sdc_delete(p_nthw_sdc); + p_nthw_sdc = NULL; + return -1; + } + + } else { + nthw_sdc_delete(p_nthw_sdc); + p_nthw_sdc = NULL; + } + + } else { + NT_LOG(DBG, NTHW, "%s: No SDC found\n", p_adapter_id_str); + } + + n_retry_cnt = 0; + res = -1; + + while ((res != 0) && (n_retry_cnt <= n_retry_cnt_max)) { + /* wait until DDR4 PLL LOCKED */ + res = nthw_fpga_rst_nt200a0x_wait_ddr4_pll_locked(p_fpga, p); + + if (res == 0) { + if (p_nthw_sdc) { + /* + * Wait for SDRAM controller has been calibrated + * On some adapters we have seen calibration time of 2.3 seconds + */ + NT_LOG(DBG, NTHW, "%s: Waiting for SDRAM to calibrate\n", + p_adapter_id_str); + res = nthw_sdc_wait_states(p_nthw_sdc, 10000, 1000); + { + uint64_t n_result_mask; + int n_state_code = + nthw_sdc_get_states(p_nthw_sdc, &n_result_mask); + (void)n_state_code; + NT_LOG(DBG, NTHW, + "%s: SDRAM state=0x%08lX state_code=%d retry=%d code=%d\n", + p_adapter_id_str, n_result_mask, n_state_code, + n_retry_cnt, res); + } + + if (res == 0) + break; + } + + if (n_retry_cnt >= n_retry_cnt_max) { + uint64_t n_result_mask; + int n_state_code = nthw_sdc_get_states(p_nthw_sdc, &n_result_mask); + (void)n_state_code; + + NT_LOG(DBG, NTHW, + "%s: SDRAM state=0x%08lX state_code=%d retry=%d code=%d\n", + p_adapter_id_str, n_result_mask, n_state_code, n_retry_cnt, + res); + + if (res != 0) { + NT_LOG(ERR, NTHW, + "%s: Timeout waiting for SDRAM controller calibration\n", + p_adapter_id_str); + } + } + } + + /* + * SDRAM controller is not calibrated with DDR4 ram blocks: + * reset DDR and perform calibration retry + */ + nthw_field_set_flush(p->mp_fld_rst_ddr4); /* Reset DDR PLL */ + nt_os_wait_usec(100); + nthw_field_clr_flush(p->mp_fld_rst_ddr4); + + n_retry_cnt++; + } + + nthw_sdc_delete(p_nthw_sdc); + + return res; +} + +static int nthw_fpga_rst_nt200a0x_reset(nthw_fpga_t *p_fpga, + const struct nthw_fpga_rst_nt200a0x *p) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + const fpga_info_t *const p_fpga_info = p_fpga->p_fpga_info; + + const int n_fpga_product_id = p->mn_fpga_product_id; + const int n_fpga_version = p->mn_fpga_version; + const int n_fpga_revision = p->mn_fpga_revision; + const int n_hw_id = p_fpga_info->nthw_hw_info.hw_id; + int locked; + int res = -1; + + NT_LOG_DBGX(DEBUG, NTHW, "%s: FPGA reset sequence: FPGA %04d-%02d-%02d @ HWId%d\n", + p_adapter_id_str, n_fpga_product_id, n_fpga_version, n_fpga_revision, + n_hw_id); + assert(n_fpga_product_id == p_fpga->mn_product_id); + + /* + * Reset all domains / modules except peripherals + * Set default reset values to ensure that all modules are reset correctly + * no matter if nic has been powercycled or ntservice has been reloaded + */ + + /* + * reset to defaults + * 1: Reset all domains + */ + NT_LOG(DBG, NTHW, "%s: RST defaults\n", p_adapter_id_str); + + nthw_field_update_register(p->mp_fld_rst_sys); + nthw_field_set_flush(p->mp_fld_rst_sys); + + if (p->mp_fld_rst_tmc) + nthw_field_set_flush(p->mp_fld_rst_tmc); + + nthw_field_set_flush(p->mp_fld_rst_rpp); + nthw_field_set_flush(p->mp_fld_rst_ddr4); /* 0x07 3 banks */ + nthw_field_set_flush(p->mp_fld_rst_sdc); + + /* Reset port 0 and 1 in the following registers: */ + nthw_field_set_flush(p->mp_fld_rst_phy);/* 0x03 2 ports */ + + if (p->mp_fld_rst_mac_rx) + nthw_field_set_flush(p->mp_fld_rst_mac_rx); /* 0x03 2 ports */ + + if (p->mp_fld_rst_mac_tx) + nthw_field_set_flush(p->mp_fld_rst_mac_tx); /* 0x03 2 ports */ + + if (p->mp_fld_rst_pcs_rx) + nthw_field_set_flush(p->mp_fld_rst_pcs_rx); /* 0x03 2 ports */ + + if (p->mp_fld_rst_serdes_rx) + nthw_field_set_flush(p->mp_fld_rst_serdes_rx); /* 0x03 2 ports */ + + if (p->mp_fld_rst_serdes_rx_datapath) { + nthw_field_set_flush(p->mp_fld_rst_serdes_rx_datapath); + nthw_field_clr_flush(p->mp_fld_rst_serdes_rx); + } + + if (p->mp_fld_rst_serdes_tx) + nthw_field_set_flush(p->mp_fld_rst_serdes_tx); + + nthw_field_set_flush(p->mp_fld_rst_ptp); + nthw_field_set_flush(p->mp_fld_rst_ts); + nthw_field_set_flush(p->mp_fld_rst_sys_mmcm); + nthw_field_set_flush(p->mp_fld_rst_core_mmcm); + nthw_field_set_flush(p->mp_fld_rst_ptp_mmcm); + nthw_field_set_flush(p->mp_fld_rst_ts_mmcm); + + if (true && p->mp_fld_rst_tsm_ref_mmcm) + nthw_field_set_flush(p->mp_fld_rst_tsm_ref_mmcm); + + /* Write all changes to register */ + nthw_field_flush_register(p->mp_fld_rst_sys); + + /* + * 2: Force use of 50 MHz reference clock for timesync; + * NOTE: From 9508-05-18 this is a 20 MHz clock + */ + NT_LOG(DBG, NTHW, "%s: Setting TS CLK SEL OVERRIDE\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_ctrl_ts_clk_sel_override); + nthw_field_set_flush(p->mp_fld_ctrl_ts_clk_sel_override); + + NT_LOG(DBG, NTHW, "%s: Setting TS CLK SEL\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_ctrl_ts_clk_sel); + nthw_field_set_flush(p->mp_fld_ctrl_ts_clk_sel); + + /* 4: De-assert sys reset, CORE and SYS MMCM resets */ + NT_LOG(DBG, NTHW, "%s: De-asserting SYS, CORE and SYS MMCM resets\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_rst_sys); + nthw_field_clr_flush(p->mp_fld_rst_sys); + nthw_field_clr_flush(p->mp_fld_rst_sys_mmcm); + nthw_field_clr_flush(p->mp_fld_rst_core_mmcm); + + /* 5: wait until CORE MMCM and SYS MMCM are LOCKED */ + NT_LOG(DBG, NTHW, "%s: Waiting for SYS MMCM to lock\n", p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_sys_mmcm_locked, -1, -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for SYS MMCM to lock failed (%d)\n", + p_adapter_id_str, locked); + } + + NT_LOG(DBG, NTHW, "%s: Waiting for CORE MMCM to lock\n", p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_core_mmcm_locked, -1, -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for CORE MMCM to lock failed (%d)\n", + p_adapter_id_str, locked); + } + + /* + * RAC RAB bus "flip/flip" reset second stage - new impl (ref RMT#37020) + * RAC/RAB init - SYS/CORE MMCM is locked - pull the remaining RAB buses out of reset + */ + { + nthw_rac_t *p_nthw_rac = p_fpga_info->mp_nthw_rac; + NT_LOG(DBG, NTHW, "%s: De-asserting remaining RAB buses\n", p_adapter_id_str); + nthw_rac_rab_init(p_nthw_rac, 0); + } + + if (true && p->mp_fld_rst_tsm_ref_mmcm) { + NT_LOG(DBG, NTHW, "%s: De-asserting TSM REF MMCM\n", p_adapter_id_str); + nthw_field_clr_flush(p->mp_fld_rst_tsm_ref_mmcm); + + if (p->mp_fld_stat_tsm_ref_mmcm_locked) { + NT_LOG(DBG, NTHW, "%s: Waiting for TSM REF MMCM to lock\n", + p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_tsm_ref_mmcm_locked, -1, + -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, + "%s: Waiting for TSM REF MMCM to lock failed (%d)\n", + p_adapter_id_str, locked); + } + } + } + + NT_LOG(DBG, NTHW, "%s: De-asserting all PHY resets\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_rst_phy); + nthw_field_clr_flush(p->mp_fld_rst_phy); + + /* + * 8: De-assert reset for remaining domains/modules resets except + * TS, PTP, PTP_MMCM and TS_MMCM + */ + NT_LOG(DBG, NTHW, "%s: De-asserting TMC RST\n", p_adapter_id_str); + + if (p->mp_fld_rst_tmc) { + nthw_field_update_register(p->mp_fld_rst_tmc); + nthw_field_clr_flush(p->mp_fld_rst_tmc); + } + + NT_LOG(DBG, NTHW, "%s: De-asserting RPP RST\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_rst_rpp); + nthw_field_clr_flush(p->mp_fld_rst_rpp); + + NT_LOG(DBG, NTHW, "%s: De-asserting DDR4 RST\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_rst_ddr4); + nthw_field_clr_flush(p->mp_fld_rst_ddr4); + + NT_LOG(DBG, NTHW, "%s: De-asserting SDC RST\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_rst_sdc); + nthw_field_clr_flush(p->mp_fld_rst_sdc); + + /* NOTE: 9522 implements PHY10G_QPLL reset and lock at this stage in mac_rx_rst() */ + NT_LOG(DBG, NTHW, "%s: De-asserting MAC RX RST\n", p_adapter_id_str); + + if (p->mp_fld_rst_mac_rx) { + nthw_field_update_register(p->mp_fld_rst_mac_rx); + nthw_field_clr_flush(p->mp_fld_rst_mac_rx); + } + + /* await until DDR4 PLL LOCKED and SDRAM controller has been calibrated */ + res = nthw_fpga_rst_nt200a0x_wait_sdc_calibrated(p_fpga, p); + + if (res) { + NT_LOG(ERR, NTHW, + "%s: nthw_fpga_rst_nt200a0x_wait_sdc_calibrated() returned true\n", + p_adapter_id_str); + return -1; + } + + if (nthw_field_get_updated(p->mp_fld_sticky_core_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_core_mmcm_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + if (p->mp_fld_sticky_pci_sys_mmcm_unlocked && + nthw_field_get_updated(p->mp_fld_sticky_pci_sys_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_pci_sys_mmcm_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + /* + * Timesync/PTP reset sequence + * De-assert TS_MMCM reset + */ + NT_LOG(DBG, NTHW, "%s: De-asserting TS MMCM RST\n", p_adapter_id_str); + nthw_field_clr_flush(p->mp_fld_rst_ts_mmcm); + + /* Wait until TS_MMCM LOCKED (NT_RAB0_REG_P9508_RST9508_STAT_TS_MMCM_LOCKED=1); */ + NT_LOG(DBG, NTHW, "%s: Waiting for TS MMCM to lock\n", p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_ts_mmcm_locked, -1, -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for TS MMCM to lock failed (%d)\n", + p_adapter_id_str, locked); + } + + NT_LOG(DBG, NTHW, "%s: Calling clear_sticky_mmcm_unlock_bits()\n", p_adapter_id_str); + nthw_field_update_register(p->mp_fld_sticky_ptp_mmcm_unlocked); + /* Clear all sticky bits */ + nthw_field_set_flush(p->mp_fld_sticky_ptp_mmcm_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_ts_mmcm_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_ddr4_mmcm_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_ddr4_pll_unlocked); + nthw_field_set_flush(p->mp_fld_sticky_core_mmcm_unlocked); + + if (p->mp_fld_sticky_tsm_ref_mmcm_unlocked) + nthw_field_set_flush(p->mp_fld_sticky_tsm_ref_mmcm_unlocked); + + if (p->mp_fld_sticky_pci_sys_mmcm_unlocked) + nthw_field_set_flush(p->mp_fld_sticky_pci_sys_mmcm_unlocked); + + /* De-assert TS reset bit */ + NT_LOG(DBG, NTHW, "%s: De-asserting TS RST\n", p_adapter_id_str); + nthw_field_clr_flush(p->mp_fld_rst_ts); + + if (nthw_field_get_updated(p->mp_fld_sticky_ts_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_ts_mmcm_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_mmcm_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + if (nthw_field_get_updated(p->mp_fld_sticky_ddr4_pll_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_ddr4_pll_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + if (nthw_field_get_updated(p->mp_fld_sticky_core_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_core_mmcm_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + if (p->mp_fld_sticky_pci_sys_mmcm_unlocked && + nthw_field_get_updated(p->mp_fld_sticky_pci_sys_mmcm_unlocked)) { + NT_LOG(ERR, NTHW, "%s: get_sticky_pci_sys_mmcm_unlocked() returned true\n", + p_adapter_id_str); + return -1; + } + + + if (false) { + /* Deassert PTP_MMCM */ + NT_LOG(DBG, NTHW, "%s: De-asserting PTP MMCM RST\n", p_adapter_id_str); + nthw_field_clr_flush(p->mp_fld_rst_ptp_mmcm); + + /* Switch PTP MMCM sel to use ptp clk */ + NT_LOG(DBG, NTHW, "%s: Setting PTP MMCM CLK SEL\n", p_adapter_id_str); + nthw_field_set_flush(p->mp_fld_ctrl_ptp_mmcm_clk_sel); + + /* Wait until TS_MMCM LOCKED (NT_RAB0_REG_P9508_RST9508_STAT_TS_MMCM_LOCKED=1); */ + NT_LOG(DBG, NTHW, "%s: Waiting for TS MMCM to re-lock\n", p_adapter_id_str); + locked = nthw_field_wait_set_any32(p->mp_fld_stat_ts_mmcm_locked, -1, -1); + + if (locked != 0) { + NT_LOG(ERR, NTHW, "%s: Waiting for TS MMCM to re-lock failed (%d)\n", + p_adapter_id_str, locked); + } + } + + NT_LOG(DBG, NTHW, "%s: De-asserting PTP RST\n", p_adapter_id_str); + nthw_field_clr_flush(p->mp_fld_rst_ptp); + + /* POWER staging introduced in 9508-05-09 and always for 9512 */ + if (n_fpga_product_id == 9508 && n_fpga_version <= 5 && n_fpga_revision <= 8) { + NT_LOG(DBG, NTHW, "%s: No power staging\n", p_adapter_id_str); + + } else { + NT_LOG(DBG, NTHW, "%s: Staging power\n", p_adapter_id_str); + nthw_field_set_flush(p->mp_fld_power_pu_phy); /* PHY power up */ + nthw_field_clr_flush(p->mp_fld_power_pu_nseb); /* NSEB power down */ + } + + NT_LOG_DBGX(DEBUG, NTHW, "%s END\n", p_adapter_id_str); + + return 0; +} + +static int nthw_fpga_rst_nt200a0x_init(struct fpga_info_s *p_fpga_info, + struct nthw_fpga_rst_nt200a0x *p_rst) +{ + assert(p_fpga_info); + + const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; + int res = -1; + int n_si_labs_clock_synth_model = -1; + uint8_t n_si_labs_clock_synth_i2c_addr = 0; + nthw_fpga_t *p_fpga = NULL; + + p_fpga = p_fpga_info->mp_fpga; + + NT_LOG_DBGX(DEBUG, NTHW, "%s: RAB init/reset\n", p_adapter_id_str); + nthw_rac_rab_reset(p_fpga_info->mp_nthw_rac); + nthw_rac_rab_setup(p_fpga_info->mp_nthw_rac); + + res = nthw_fpga_iic_scan(p_fpga, 0, 0); + res = nthw_fpga_iic_scan(p_fpga, 2, 3); + + /* + * Detect clock synth model + * check for NT200A02/NT200A01 HW-build2 - most commonly seen + */ + n_si_labs_clock_synth_i2c_addr = si5340_u23_i2c_addr_7bit; + n_si_labs_clock_synth_model = + nthw_fpga_silabs_detect(p_fpga, 0, n_si_labs_clock_synth_i2c_addr, 1); + + if (n_si_labs_clock_synth_model == -1) { + /* check for old NT200A01 HW-build1 */ + n_si_labs_clock_synth_i2c_addr = si5338_u23_i2c_addr_7bit; + n_si_labs_clock_synth_model = + nthw_fpga_silabs_detect(p_fpga, 0, n_si_labs_clock_synth_i2c_addr, 255); + + if (n_si_labs_clock_synth_model == -1) { + NT_LOG(ERR, NTHW, "%s: Failed to detect clock synth model (%d)\n", + p_adapter_id_str, n_si_labs_clock_synth_model); + return -1; + } + } + + p_rst->mn_si_labs_clock_synth_model = n_si_labs_clock_synth_model; + p_rst->mn_hw_id = p_fpga_info->nthw_hw_info.hw_id; + + return res; +} + +static struct rst_nt200a0x_ops rst_nt200a0x_ops = { .nthw_fpga_rst_nt200a0x_init = + nthw_fpga_rst_nt200a0x_init, + .nthw_fpga_rst_nt200a0x_reset = + nthw_fpga_rst_nt200a0x_reset +}; + +void rst_nt200a0x_ops_init(void) +{ + NT_LOG(INF, NTHW, "RST NT200A0X OPS INIT\n"); + register_rst_nt200a0x_ops(&rst_nt200a0x_ops); +} diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c index 98d29744cb..1650bb8a5c 100644 --- a/drivers/net/ntnic/nthw/core/nthw_fpga.c +++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c @@ -65,6 +65,88 @@ int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpg return 0; } +int nthw_fpga_iic_scan(nthw_fpga_t *p_fpga, const int n_instance_no_begin, + const int n_instance_no_end) +{ + int i; + + assert(n_instance_no_begin <= n_instance_no_end); + + for (i = n_instance_no_begin; i <= n_instance_no_end; i++) { + nthw_iic_t *p_nthw_iic = nthw_iic_new(); + + if (p_nthw_iic) { + const int rc = nthw_iic_init(p_nthw_iic, p_fpga, i, 8); + + if (rc == 0) { + nthw_iic_set_retry_params(p_nthw_iic, -1, 100, 100, 3, 3); + nthw_iic_scan(p_nthw_iic); + } + + nthw_iic_delete(p_nthw_iic); + p_nthw_iic = NULL; + } + } + + return 0; +} + +int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const int n_dev_addr, + const int n_page_reg_addr) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + (void)p_adapter_id_str; + uint64_t ident = -1; + int res = -1; + + nthw_iic_t *p_nthw_iic = nthw_iic_new(); + + if (p_nthw_iic) { + uint8_t data; + uint8_t a_silabs_ident[8]; + nthw_iic_init(p_nthw_iic, p_fpga, n_instance_no, 8); + + data = 0; + /* switch to page 0 */ + nthw_iic_write_data(p_nthw_iic, (uint8_t)n_dev_addr, (uint8_t)n_page_reg_addr, 1, + &data); + res = nthw_iic_read_data(p_nthw_iic, (uint8_t)n_dev_addr, 0x00, + sizeof(a_silabs_ident), a_silabs_ident); + + if (res == 0) { + int i; + + for (i = 0; i < (int)sizeof(a_silabs_ident); i++) { + ident <<= 8; + ident |= a_silabs_ident[i]; + } + } + + nthw_iic_delete(p_nthw_iic); + p_nthw_iic = NULL; + + /* Conclude SiLabs part */ + if (res == 0) { + if (a_silabs_ident[3] == 0x53) { + if (a_silabs_ident[2] == 0x40) + res = 5340; + + else if (a_silabs_ident[2] == 0x41) + res = 5341; + + } else if (a_silabs_ident[2] == 38) { + res = 5338; + + } else { + res = -1; + } + } + } + + NT_LOG(DBG, NTHW, "%s: %016" PRIX64 ": %d\n", p_adapter_id_str, ident, res); + return res; +} + int nthw_fpga_init(struct fpga_info_s *p_fpga_info) { const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; diff --git a/drivers/net/ntnic/nthw/core/nthw_sdc.c b/drivers/net/ntnic/nthw/core/nthw_sdc.c new file mode 100644 index 0000000000..7666af7e5a --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_sdc.c @@ -0,0 +1,176 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_sdc.h" + +nthw_sdc_t *nthw_sdc_new(void) +{ + nthw_sdc_t *p = malloc(sizeof(nthw_sdc_t)); + + if (p) + memset(p, 0, sizeof(nthw_sdc_t)); + + return p; +} + +void nthw_sdc_delete(nthw_sdc_t *p) +{ + if (p) { + memset(p, 0, sizeof(nthw_sdc_t)); + free(p); + } +} + +int nthw_sdc_init(nthw_sdc_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_SDC, n_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: SDC %d: no such instance\n", p_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_sdc = mod; + + { + nthw_register_t *p_reg; + + p_reg = nthw_module_get_register(p->mp_mod_sdc, SDC_CTRL); + p->mp_fld_ctrl_init = nthw_register_get_field(p_reg, SDC_CTRL_INIT); + p->mp_fld_ctrl_run_test = nthw_register_get_field(p_reg, SDC_CTRL_RUN_TEST); + p->mp_fld_ctrl_stop_client = nthw_register_get_field(p_reg, SDC_CTRL_STOP_CLIENT); + p->mp_fld_ctrl_test_enable = nthw_register_get_field(p_reg, SDC_CTRL_TEST_EN); + + p_reg = nthw_module_get_register(p->mp_mod_sdc, SDC_STAT); + p->mp_fld_stat_calib = nthw_register_get_field(p_reg, SDC_STAT_CALIB); + p->mp_fld_stat_cell_cnt_stopped = + nthw_register_get_field(p_reg, SDC_STAT_CELL_CNT_STOPPED); + p->mp_fld_stat_err_found = nthw_register_get_field(p_reg, SDC_STAT_ERR_FOUND); + p->mp_fld_stat_init_done = nthw_register_get_field(p_reg, SDC_STAT_INIT_DONE); + p->mp_fld_stat_mmcm_lock = nthw_register_get_field(p_reg, SDC_STAT_MMCM_LOCK); + p->mp_fld_stat_pll_lock = nthw_register_get_field(p_reg, SDC_STAT_PLL_LOCK); + p->mp_fld_stat_resetting = nthw_register_get_field(p_reg, SDC_STAT_RESETTING); + + p_reg = nthw_module_get_register(p->mp_mod_sdc, SDC_CELL_CNT); + p->mp_fld_cell_cnt = nthw_register_get_field(p_reg, SDC_CELL_CNT_CELL_CNT); + + p_reg = nthw_module_get_register(p->mp_mod_sdc, SDC_CELL_CNT_PERIOD); + p->mp_fld_cell_cnt_period = + nthw_register_get_field(p_reg, SDC_CELL_CNT_PERIOD_CELL_CNT_PERIOD); + + p_reg = nthw_module_get_register(p->mp_mod_sdc, SDC_FILL_LVL); + p->mp_fld_fill_level = nthw_register_get_field(p_reg, SDC_FILL_LVL_FILL_LVL); + + p_reg = nthw_module_get_register(p->mp_mod_sdc, SDC_MAX_FILL_LVL); + p->mp_fld_max_fill_level = + nthw_register_get_field(p_reg, SDC_MAX_FILL_LVL_MAX_FILL_LVL); + } + return 0; +} + +int nthw_sdc_get_states(nthw_sdc_t *p, uint64_t *pn_result_mask) +{ + int n_err_cnt = 0; + uint64_t n_mask = 0; + uint32_t val; + uint32_t val_mask; + int n_val_width; + + if (!p || !pn_result_mask) + return -1; + + val = nthw_field_get_updated(p->mp_fld_stat_calib); + n_val_width = nthw_field_get_bit_width(p->mp_fld_stat_calib); + val_mask = ((1 << n_val_width) - 1); + n_mask = (n_mask << n_val_width) | (val & val_mask); + + if (val != val_mask) + n_err_cnt++; + + val = nthw_field_get_updated(p->mp_fld_stat_init_done); + n_val_width = nthw_field_get_bit_width(p->mp_fld_stat_init_done); + val_mask = ((1 << n_val_width) - 1); + n_mask = (n_mask << n_val_width) | (val & val_mask); + + if (val != val_mask) + n_err_cnt++; + + val = nthw_field_get_updated(p->mp_fld_stat_mmcm_lock); + n_val_width = nthw_field_get_bit_width(p->mp_fld_stat_mmcm_lock); + val_mask = ((1 << n_val_width) - 1); + n_mask = (n_mask << n_val_width) | (val & val_mask); + + if (val != val_mask) + n_err_cnt++; + + val = nthw_field_get_updated(p->mp_fld_stat_pll_lock); + n_val_width = nthw_field_get_bit_width(p->mp_fld_stat_pll_lock); + val_mask = ((1 << n_val_width) - 1); + n_mask = (n_mask << n_val_width) | (val & val_mask); + + if (val != val_mask) + n_err_cnt++; + + val = nthw_field_get_updated(p->mp_fld_stat_resetting); + n_val_width = nthw_field_get_bit_width(p->mp_fld_stat_resetting); + val_mask = ((1 << n_val_width) - 1); + n_mask = (n_mask << n_val_width) | (val & val_mask); + + if (val != 0) + n_err_cnt++; + + if (pn_result_mask) + *pn_result_mask = n_mask; + + return n_err_cnt; /* 0 = all ok */ +} + +int nthw_sdc_wait_states(nthw_sdc_t *p, const int n_poll_iterations, const int n_poll_interval) +{ + int res; + int n_err_cnt = 0; + + res = nthw_field_wait_set_all32(p->mp_fld_stat_calib, n_poll_iterations, n_poll_interval); + + if (res) + n_err_cnt++; + + res = nthw_field_wait_set_all32(p->mp_fld_stat_init_done, n_poll_iterations, + n_poll_interval); + + if (res) + n_err_cnt++; + + res = nthw_field_wait_set_all32(p->mp_fld_stat_mmcm_lock, n_poll_iterations, + n_poll_interval); + + if (res) + n_err_cnt++; + + res = nthw_field_wait_set_all32(p->mp_fld_stat_pll_lock, n_poll_iterations, + n_poll_interval); + + if (res) + n_err_cnt++; + + res = nthw_field_wait_clr_all32(p->mp_fld_stat_resetting, n_poll_iterations, + n_poll_interval); + + if (res) + n_err_cnt++; + + return n_err_cnt; /* 0 = all ok */ +} diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c index 006221bbe3..bd0a966be2 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.c +++ b/drivers/net/ntnic/ntnic_mod_reg.c @@ -18,3 +18,31 @@ const struct adapter_ops *get_adapter_ops(void) adapter_init(); return adapter_ops; } + +static struct rst_nt200a0x_ops *rst_nt200a0x_ops; + +void register_rst_nt200a0x_ops(struct rst_nt200a0x_ops *ops) +{ + rst_nt200a0x_ops = ops; +} + +struct rst_nt200a0x_ops *get_rst_nt200a0x_ops(void) +{ + if (rst_nt200a0x_ops == NULL) + rst_nt200a0x_ops_init(); + return rst_nt200a0x_ops; +} + +static struct rst9563_ops *rst9563_ops; + +void register_rst9563_ops(struct rst9563_ops *ops) +{ + rst9563_ops = ops; +} + +struct rst9563_ops *get_rst9563_ops(void) +{ + if (rst9563_ops == NULL) + rst9563_ops_init(); + return rst9563_ops; +} diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index 96fc829399..df8a8b9aca 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -11,6 +11,7 @@ #include "nthw_platform_drv.h" #include "nthw_drv.h" #include "nt4ga_adapter.h" +#include "ntnic_nthw_fpga_rst_nt200a0x.h" #include "ntos_drv.h" struct adapter_ops { @@ -24,5 +25,24 @@ void register_adapter_ops(const struct adapter_ops *ops); const struct adapter_ops *get_adapter_ops(void); void adapter_init(void); +struct rst_nt200a0x_ops { + int (*nthw_fpga_rst_nt200a0x_init)(struct fpga_info_s *p_fpga_info, + struct nthw_fpga_rst_nt200a0x *p_rst); + int (*nthw_fpga_rst_nt200a0x_reset)(nthw_fpga_t *p_fpga, + const struct nthw_fpga_rst_nt200a0x *p); +}; + +void register_rst_nt200a0x_ops(struct rst_nt200a0x_ops *ops); +struct rst_nt200a0x_ops *get_rst_nt200a0x_ops(void); +void rst_nt200a0x_ops_init(void); + +struct rst9563_ops { + int (*nthw_fpga_rst9563_init)(struct fpga_info_s *p_fpga_info, + struct nthw_fpga_rst_nt200a0x *const p); +}; + +void register_rst9563_ops(struct rst9563_ops *ops); +struct rst9563_ops *get_rst9563_ops(void); +void rst9563_ops_init(void); #endif /* __NTNIC_MOD_REG_H__ */ From patchwork Wed Jul 17 13:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142471 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A9BE145635; Wed, 17 Jul 2024 15:35:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C0AE42D83; Wed, 17 Jul 2024 15:33:42 +0200 (CEST) Received: from egress-ip11a.ess.de.barracuda.com (egress-ip11a.ess.de.barracuda.com [18.184.203.234]) by mails.dpdk.org (Postfix) with ESMTP id 578EB40E5E for ; Wed, 17 Jul 2024 15:33:31 +0200 (CEST) Received: from EUR02-VI1-obe.outbound.protection.outlook.com (mail-vi1eur02lp2040.outbound.protection.outlook.com [104.47.11.40]) by mx-outbound40-186.eu-central-1c.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); 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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: FRZP190MB2182 X-BESS-ID: 1721223208-310426-12659-14779-1 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.11.40 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKViZmQABkZgBFLVINDIyTLI0TE8 3MUwwNDZJMUo1NDUxMUw0SU43NUkyUamMBDR6tDUIAAAA= X-BESS-Outbound-Spam-Score: 0.70 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan21-11.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.20 PR0N_SUBJECT META: Subject has letters around special characters (pr0n) X-BESS-Outbound-Spam-Status: SCORE=0.70 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND, PR0N_SUBJECT X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Because the ntnic hardware supports multiple different FPGAs with different pipelines and port speeds, the clock profile is not hardcoded into the product, and need to be initialized from software. The clock profile itself is an array of integers that was generated by Silicon Labs ClockBuilder. Signed-off-by: Serhii Iliushyk --- v6 * EOF comment was removed v10 * Remove "#ifdef __cplusplus" and "#endif" around static_assert * Use 8 spaces as indentation in meson --- .../ntnic/include/clock_profiles_structs.h | 33 + .../include/ntnic_nthw_fpga_rst_nt200a0x.h | 1 + drivers/net/ntnic/meson.build | 2 + .../net/ntnic/nthw/core/include/nthw_core.h | 2 + .../net/ntnic/nthw/core/include/nthw_fpga.h | 4 + .../net/ntnic/nthw/core/include/nthw_si5340.h | 33 + .../NT200A02_U23_Si5340_adr0_v5-Registers.h | 753 ++++++++++++++++++ .../clock_profiles/nthw_fpga_clk9563.c | 45 ++ .../core/nt200a0x/reset/nthw_fpga_rst9563.c | 35 + .../nt200a0x/reset/nthw_fpga_rst_nt200a0x.c | 3 + drivers/net/ntnic/nthw/core/nthw_fpga.c | 23 + drivers/net/ntnic/nthw/core/nthw_si5340.c | 198 +++++ drivers/net/ntnic/ntnic_mod_reg.c | 14 + drivers/net/ntnic/ntnic_mod_reg.h | 9 + 14 files changed, 1155 insertions(+) create mode 100644 drivers/net/ntnic/include/clock_profiles_structs.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_si5340.h create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/NT200A02_U23_Si5340_adr0_v5-Registers.h create mode 100644 drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c create mode 100644 drivers/net/ntnic/nthw/core/nthw_si5340.c diff --git a/drivers/net/ntnic/include/clock_profiles_structs.h b/drivers/net/ntnic/include/clock_profiles_structs.h new file mode 100644 index 0000000000..28a582a5e7 --- /dev/null +++ b/drivers/net/ntnic/include/clock_profiles_structs.h @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NT_CLOCK_PROFILES_STRUCTS_H_ +#define _NT_CLOCK_PROFILES_STRUCTS_H_ + +#include + +#define clk_profile_size_error_msg "Size test failed" + +struct clk_profile_data_fmt1_s { + uint16_t reg_addr; + uint8_t reg_val; +}; + +struct clk_profile_data_fmt2_s { + unsigned int reg_addr; + unsigned char reg_val; +}; + +typedef struct clk_profile_data_fmt1_s clk_profile_data_fmt1_t; +typedef struct clk_profile_data_fmt2_s clk_profile_data_fmt2_t; + +enum clk_profile_data_fmt_e { + clk_profile_data_fmt_1, + clk_profile_data_fmt_2, +}; + +typedef enum clk_profile_data_fmt_e clk_profile_data_fmt_t; + +#endif /* _NT_CLOCK_PROFILES_STRUCTS_H_ */ diff --git a/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h index 8a0b3fae50..a1ee618c26 100644 --- a/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h +++ b/drivers/net/ntnic/include/ntnic_nthw_fpga_rst_nt200a0x.h @@ -17,6 +17,7 @@ struct nthw_fpga_rst_nt200a0x { int mn_hw_id; int mn_si_labs_clock_synth_model; + uint8_t mn_si_labs_clock_synth_i2c_addr; nthw_field_t *mp_fld_rst_sys; nthw_field_t *mp_fld_rst_sys_mmcm; diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 085719becb..b197315e2d 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -25,6 +25,7 @@ sources = files( 'nthw/supported/nthw_fpga_9563_055_039_0000.c', 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', + 'nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c', 'nthw/core/nt200a0x/nthw_fpga_nt200a0x.c', 'nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c', 'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c', @@ -33,6 +34,7 @@ sources = files( 'nthw/core/nthw_iic.c', 'nthw/core/nthw_pcie3.c', 'nthw/core/nthw_sdc.c', + 'nthw/core/nthw_si5340.c', 'nthw/model/nthw_fpga_model.c', 'nthw/nthw_platform.c', 'nthw/nthw_rac.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index 8bdf7ee01d..5648bd8983 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -18,5 +18,7 @@ #include "nthw_sdc.h" +#include "nthw_si5340.h" + #endif /* __NTHW_CORE_H__ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h index 1df1480109..cee1d23090 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_fpga.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_fpga.h @@ -24,6 +24,10 @@ int nthw_fpga_iic_scan(nthw_fpga_t *p_fpga, const int n_instance_no_begin, int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const int n_dev_addr, const int n_page_reg_addr); +int nthw_fpga_si5340_clock_synth_init_fmt2(nthw_fpga_t *p_fpga, const uint8_t n_iic_addr, + const clk_profile_data_fmt2_t *p_clk_profile, + const int n_clk_profile_rec_cnt); + struct nt200a0x_ops { int (*nthw_fpga_nt200a0x_init)(struct fpga_info_s *p_fpga_info); }; diff --git a/drivers/net/ntnic/nthw/core/include/nthw_si5340.h b/drivers/net/ntnic/nthw/core/include/nthw_si5340.h new file mode 100644 index 0000000000..f56883d99a --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_si5340.h @@ -0,0 +1,33 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_SI5340_H__ +#define __NTHW_SI5340_H__ + +#include "clock_profiles_structs.h" + +#define SI5340_SUCCESS (0) +#define SI5340_FAILED (999) +#define SI5340_TIMEOUT (666) + +struct nthw_si5340 { + uint8_t mn_iic_addr; + nthw_iic_t *mp_nthw_iic; + int mn_clk_cfg; + uint8_t m_si5340_page; +}; + +typedef struct nthw_si5340 nthw_si5340_t; + +nthw_si5340_t *nthw_si5340_new(void); +int nthw_si5340_init(nthw_si5340_t *p, nthw_iic_t *p_nthw_iic, uint8_t n_iic_addr); +void nthw_si5340_delete(nthw_si5340_t *p); + +int nthw_si5340_config(nthw_si5340_t *p, const void *p_data, int data_cnt, + clk_profile_data_fmt_t data_format); +int nthw_si5340_config_fmt2(nthw_si5340_t *p, const clk_profile_data_fmt2_t *p_data, + const int data_cnt); + +#endif /* __NTHW_SI5338_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/NT200A02_U23_Si5340_adr0_v5-Registers.h b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/NT200A02_U23_Si5340_adr0_v5-Registers.h new file mode 100644 index 0000000000..956d725b7f --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/NT200A02_U23_Si5340_adr0_v5-Registers.h @@ -0,0 +1,753 @@ + +/* + * Si5340 Rev D Configuration Register Export Header File + * + * This file represents a series of Silicon Labs Si5340 Rev D + * register writes that can be performed to load a single configuration + * on a device. It was created by a Silicon Labs ClockBuilder Pro + * export tool. + * + * Part: Si5340 Rev D + * Design ID: 05 + * Includes Pre/Post Download Control Register Writes: Yes + * Created By: ClockBuilder Pro v2.28.1 [2018-09-24] + * Timestamp: 2018-11-14 16:20:29 GMT+01:00 + * + * A complete design report corresponding to this export is included at the end + * of this header file. + * + */ + +#ifndef SI5340_REVD_REG_CONFIG_HEADER +#define SI5340_REVD_REG_CONFIG_HEADER + +#define SI5340_REVD_REG_CONFIG_NUM_REGS 326 + +typedef struct { + unsigned int address; /* 16-bit register address */ + unsigned char value; /* 8-bit register data */ + +} si5340_revd_register_t; + +static const si5340_revd_register_t si5340_revd_registers[SI5340_REVD_REG_CONFIG_NUM_REGS] = { + /* Start configuration preamble */ + { 0x0B24, 0xC0 }, + { 0x0B25, 0x00 }, + /* Rev D stuck divider fix */ + { 0x0502, 0x01 }, + { 0x0505, 0x03 }, + { 0x0957, 0x17 }, + { 0x0B4E, 0x1A }, + /* End configuration preamble */ + + /* Delay 300 msec */ + /* Delay is worst case time for device to complete any calibration */ + /* that is running due to device state change previous to this script */ + /* being processed. */ + + /* Start configuration registers */ + { 0x0006, 0x00 }, + { 0x0007, 0x00 }, + { 0x0008, 0x00 }, + { 0x000B, 0x74 }, + { 0x0017, 0xF0 }, + { 0x0018, 0xFF }, + { 0x0021, 0x0F }, + { 0x0022, 0x00 }, + { 0x002B, 0x0A }, + { 0x002C, 0x20 }, + { 0x002D, 0x00 }, + { 0x002E, 0x00 }, + { 0x002F, 0x00 }, + { 0x0030, 0x00 }, + { 0x0031, 0x00 }, + { 0x0032, 0x00 }, + { 0x0033, 0x00 }, + { 0x0034, 0x00 }, + { 0x0035, 0x00 }, + { 0x0036, 0x00 }, + { 0x0037, 0x00 }, + { 0x0038, 0x00 }, + { 0x0039, 0x00 }, + { 0x003A, 0x00 }, + { 0x003B, 0x00 }, + { 0x003C, 0x00 }, + { 0x003D, 0x00 }, + { 0x0041, 0x00 }, + { 0x0042, 0x00 }, + { 0x0043, 0x00 }, + { 0x0044, 0x00 }, + { 0x009E, 0x00 }, + { 0x0102, 0x01 }, + { 0x0112, 0x02 }, + { 0x0113, 0x09 }, + { 0x0114, 0x3E }, + { 0x0115, 0x19 }, + { 0x0117, 0x06 }, + { 0x0118, 0x09 }, + { 0x0119, 0x3E }, + { 0x011A, 0x18 }, + { 0x0126, 0x06 }, + { 0x0127, 0x09 }, + { 0x0128, 0x3E }, + { 0x0129, 0x18 }, + { 0x012B, 0x06 }, + { 0x012C, 0x09 }, + { 0x012D, 0x3E }, + { 0x012E, 0x1A }, + { 0x013F, 0x00 }, + { 0x0140, 0x00 }, + { 0x0141, 0x40 }, + { 0x0206, 0x00 }, + { 0x0208, 0x00 }, + { 0x0209, 0x00 }, + { 0x020A, 0x00 }, + { 0x020B, 0x00 }, + { 0x020C, 0x00 }, + { 0x020D, 0x00 }, + { 0x020E, 0x00 }, + { 0x020F, 0x00 }, + { 0x0210, 0x00 }, + { 0x0211, 0x00 }, + { 0x0212, 0x00 }, + { 0x0213, 0x00 }, + { 0x0214, 0x00 }, + { 0x0215, 0x00 }, + { 0x0216, 0x00 }, + { 0x0217, 0x00 }, + { 0x0218, 0x00 }, + { 0x0219, 0x00 }, + { 0x021A, 0x00 }, + { 0x021B, 0x00 }, + { 0x021C, 0x00 }, + { 0x021D, 0x00 }, + { 0x021E, 0x00 }, + { 0x021F, 0x00 }, + { 0x0220, 0x00 }, + { 0x0221, 0x00 }, + { 0x0222, 0x00 }, + { 0x0223, 0x00 }, + { 0x0224, 0x00 }, + { 0x0225, 0x00 }, + { 0x0226, 0x00 }, + { 0x0227, 0x00 }, + { 0x0228, 0x00 }, + { 0x0229, 0x00 }, + { 0x022A, 0x00 }, + { 0x022B, 0x00 }, + { 0x022C, 0x00 }, + { 0x022D, 0x00 }, + { 0x022E, 0x00 }, + { 0x022F, 0x00 }, + { 0x0235, 0x00 }, + { 0x0236, 0x00 }, + { 0x0237, 0x00 }, + { 0x0238, 0xA6 }, + { 0x0239, 0x8B }, + { 0x023A, 0x00 }, + { 0x023B, 0x00 }, + { 0x023C, 0x00 }, + { 0x023D, 0x00 }, + { 0x023E, 0x80 }, + { 0x0250, 0x03 }, + { 0x0251, 0x00 }, + { 0x0252, 0x00 }, + { 0x0253, 0x00 }, + { 0x0254, 0x00 }, + { 0x0255, 0x00 }, + { 0x025C, 0x00 }, + { 0x025D, 0x00 }, + { 0x025E, 0x00 }, + { 0x025F, 0x00 }, + { 0x0260, 0x00 }, + { 0x0261, 0x00 }, + { 0x026B, 0x30 }, + { 0x026C, 0x35 }, + { 0x026D, 0x00 }, + { 0x026E, 0x00 }, + { 0x026F, 0x00 }, + { 0x0270, 0x00 }, + { 0x0271, 0x00 }, + { 0x0272, 0x00 }, + { 0x0302, 0x00 }, + { 0x0303, 0x00 }, + { 0x0304, 0x00 }, + { 0x0305, 0x00 }, + { 0x0306, 0x0D }, + { 0x0307, 0x00 }, + { 0x0308, 0x00 }, + { 0x0309, 0x00 }, + { 0x030A, 0x00 }, + { 0x030B, 0x80 }, + { 0x030C, 0x00 }, + { 0x030D, 0x00 }, + { 0x030E, 0x00 }, + { 0x030F, 0x00 }, + { 0x0310, 0x61 }, + { 0x0311, 0x08 }, + { 0x0312, 0x00 }, + { 0x0313, 0x00 }, + { 0x0314, 0x00 }, + { 0x0315, 0x00 }, + { 0x0316, 0x80 }, + { 0x0317, 0x00 }, + { 0x0318, 0x00 }, + { 0x0319, 0x00 }, + { 0x031A, 0x00 }, + { 0x031B, 0xD0 }, + { 0x031C, 0x1A }, + { 0x031D, 0x00 }, + { 0x031E, 0x00 }, + { 0x031F, 0x00 }, + { 0x0320, 0x00 }, + { 0x0321, 0xA0 }, + { 0x0322, 0x00 }, + { 0x0323, 0x00 }, + { 0x0324, 0x00 }, + { 0x0325, 0x00 }, + { 0x0326, 0x00 }, + { 0x0327, 0x00 }, + { 0x0328, 0x00 }, + { 0x0329, 0x00 }, + { 0x032A, 0x00 }, + { 0x032B, 0x00 }, + { 0x032C, 0x00 }, + { 0x032D, 0x00 }, + { 0x0338, 0x00 }, + { 0x0339, 0x1F }, + { 0x033B, 0x00 }, + { 0x033C, 0x00 }, + { 0x033D, 0x00 }, + { 0x033E, 0x00 }, + { 0x033F, 0x00 }, + { 0x0340, 0x00 }, + { 0x0341, 0x00 }, + { 0x0342, 0x00 }, + { 0x0343, 0x00 }, + { 0x0344, 0x00 }, + { 0x0345, 0x00 }, + { 0x0346, 0x00 }, + { 0x0347, 0x00 }, + { 0x0348, 0x00 }, + { 0x0349, 0x00 }, + { 0x034A, 0x00 }, + { 0x034B, 0x00 }, + { 0x034C, 0x00 }, + { 0x034D, 0x00 }, + { 0x034E, 0x00 }, + { 0x034F, 0x00 }, + { 0x0350, 0x00 }, + { 0x0351, 0x00 }, + { 0x0352, 0x00 }, + { 0x0359, 0x00 }, + { 0x035A, 0x00 }, + { 0x035B, 0x00 }, + { 0x035C, 0x00 }, + { 0x035D, 0x00 }, + { 0x035E, 0x00 }, + { 0x035F, 0x00 }, + { 0x0360, 0x00 }, + { 0x0802, 0x00 }, + { 0x0803, 0x00 }, + { 0x0804, 0x00 }, + { 0x0805, 0x00 }, + { 0x0806, 0x00 }, + { 0x0807, 0x00 }, + { 0x0808, 0x00 }, + { 0x0809, 0x00 }, + { 0x080A, 0x00 }, + { 0x080B, 0x00 }, + { 0x080C, 0x00 }, + { 0x080D, 0x00 }, + { 0x080E, 0x00 }, + { 0x080F, 0x00 }, + { 0x0810, 0x00 }, + { 0x0811, 0x00 }, + { 0x0812, 0x00 }, + { 0x0813, 0x00 }, + { 0x0814, 0x00 }, + { 0x0815, 0x00 }, + { 0x0816, 0x00 }, + { 0x0817, 0x00 }, + { 0x0818, 0x00 }, + { 0x0819, 0x00 }, + { 0x081A, 0x00 }, + { 0x081B, 0x00 }, + { 0x081C, 0x00 }, + { 0x081D, 0x00 }, + { 0x081E, 0x00 }, + { 0x081F, 0x00 }, + { 0x0820, 0x00 }, + { 0x0821, 0x00 }, + { 0x0822, 0x00 }, + { 0x0823, 0x00 }, + { 0x0824, 0x00 }, + { 0x0825, 0x00 }, + { 0x0826, 0x00 }, + { 0x0827, 0x00 }, + { 0x0828, 0x00 }, + { 0x0829, 0x00 }, + { 0x082A, 0x00 }, + { 0x082B, 0x00 }, + { 0x082C, 0x00 }, + { 0x082D, 0x00 }, + { 0x082E, 0x00 }, + { 0x082F, 0x00 }, + { 0x0830, 0x00 }, + { 0x0831, 0x00 }, + { 0x0832, 0x00 }, + { 0x0833, 0x00 }, + { 0x0834, 0x00 }, + { 0x0835, 0x00 }, + { 0x0836, 0x00 }, + { 0x0837, 0x00 }, + { 0x0838, 0x00 }, + { 0x0839, 0x00 }, + { 0x083A, 0x00 }, + { 0x083B, 0x00 }, + { 0x083C, 0x00 }, + { 0x083D, 0x00 }, + { 0x083E, 0x00 }, + { 0x083F, 0x00 }, + { 0x0840, 0x00 }, + { 0x0841, 0x00 }, + { 0x0842, 0x00 }, + { 0x0843, 0x00 }, + { 0x0844, 0x00 }, + { 0x0845, 0x00 }, + { 0x0846, 0x00 }, + { 0x0847, 0x00 }, + { 0x0848, 0x00 }, + { 0x0849, 0x00 }, + { 0x084A, 0x00 }, + { 0x084B, 0x00 }, + { 0x084C, 0x00 }, + { 0x084D, 0x00 }, + { 0x084E, 0x00 }, + { 0x084F, 0x00 }, + { 0x0850, 0x00 }, + { 0x0851, 0x00 }, + { 0x0852, 0x00 }, + { 0x0853, 0x00 }, + { 0x0854, 0x00 }, + { 0x0855, 0x00 }, + { 0x0856, 0x00 }, + { 0x0857, 0x00 }, + { 0x0858, 0x00 }, + { 0x0859, 0x00 }, + { 0x085A, 0x00 }, + { 0x085B, 0x00 }, + { 0x085C, 0x00 }, + { 0x085D, 0x00 }, + { 0x085E, 0x00 }, + { 0x085F, 0x00 }, + { 0x0860, 0x00 }, + { 0x0861, 0x00 }, + { 0x090E, 0x02 }, + { 0x091C, 0x04 }, + { 0x0943, 0x00 }, + { 0x0949, 0x00 }, + { 0x094A, 0x00 }, + { 0x094E, 0x49 }, + { 0x094F, 0x02 }, + { 0x095E, 0x00 }, + { 0x0A02, 0x00 }, + { 0x0A03, 0x07 }, + { 0x0A04, 0x01 }, + { 0x0A05, 0x07 }, + { 0x0A14, 0x00 }, + { 0x0A1A, 0x00 }, + { 0x0A20, 0x00 }, + { 0x0A26, 0x00 }, + { 0x0B44, 0x0F }, + { 0x0B4A, 0x08 }, + { 0x0B57, 0x0E }, + { 0x0B58, 0x01 }, + /* End configuration registers */ + + /* Start configuration postamble */ + { 0x001C, 0x01 }, + { 0x0B24, 0xC3 }, + { 0x0B25, 0x02 }, + /* End configuration postamble */ +}; + +/* + * Design Report + * + * Overview + * ======== + * Part: Si5340AB Rev D + * Project File: P:\Hardware\NT + * Adapters\NT200A02\design\Clock_syn_design\NT200A02_U23_Si5340_adr0_v5.slabtimeproj Design ID: 05 + * Created By: ClockBuilder Pro v2.28.1 [2018-09-24] + * Timestamp: 2018-11-14 16:20:29 GMT+01:00 + * + * Design Rule Check + * ================= + * Errors: + * - No errors + * + * Warnings: + * - No warnings + * + * Device Grade + * ============ + * Maximum Output Frequency: 257.8125 MHz + * Frequency Synthesis Mode: Fractional + * Frequency Plan Grade: B + * Minimum Base OPN: Si5340B* + * + * Base Output Clock Supported Frequency Synthesis Modes + * OPN Grade Frequency Range (Typical Jitter) + * --------- ------------------- -------------------------------------------- + * Si5340A 100 Hz to 1.028 GHz Integer (< 100 fs) and fractional (< 150 fs) + * Si5340B* 100 Hz to 350 MHz " + * Si5340C 100 Hz to 1.028 GHz Integer only (< 100 fs) + * Si5340D 100 Hz to 350 MHz " + * + * * Based on your calculated frequency plan, a Si5340B grade device is + * sufficient for your design. For more in-system configuration flexibility + * (higher frequencies and/or to enable fractional synthesis), consider + * selecting device grade Si5340A when specifying an ordering part number (OPN) + * for your application. See the datasheet Ordering Guide for more information. + * + * Design + * ====== + * Host Interface: + * I/O Power Supply: VDD (Core) + * SPI Mode: 3-Wire + * I2C Address Range: 116d to 119d / 0x74 to 0x77 (selected via A0/A1 pins) + * + * Inputs: + * XAXB: 48 MHz + * Crystal Mode + * IN0: Unused + * IN1: Unused + * IN2: Unused + * FB_IN: Unused + * + * Outputs: + * OUT0: 100 MHz + * Enabled, LVDS 1.8 V + * OUT1: 257.8125 MHz [ 257 + 13/16 MHz ] + * Enabled, LVDS 1.8 V + * OUT2: 257.8125 MHz [ 257 + 13/16 MHz ] + * Enabled, LVDS 1.8 V + * OUT3: 156.25 MHz [ 156 + 1/4 MHz ] + * Enabled, LVDS 1.8 V + * + * Frequency Plan + * ============== + * Priority: OUT1 is lowest jitter output + * + * Fpfd = 48 MHz + * Fvco = 13.40625 GHz [ 13 + 13/32 GHz ] + * Fms0 = 515.625 MHz [ 515 + 5/8 MHz ] + * Fms1 = 800 MHz + * Fms2 = 312.5 MHz [ 312 + 1/2 MHz ] + * + * P dividers: + * P0 = Unused + * P1 = Unused + * P2 = Unused + * P3 = Unused + * Pxaxb = 1 + * + * M = 279.296875 [ 279 + 19/64 ] + * N dividers: + * N0: + * Value: 26 + * Skew: 0.000 s + * OUT1: 257.8125 MHz [ 257 + 13/16 MHz ] + * OUT2: 257.8125 MHz [ 257 + 13/16 MHz ] + * N1: + * Value: 16.7578125 [ 16 + 97/128 ] + * Skew: 0.000 s + * OUT0: 100 MHz + * N2: + * Value: 42.9 [ 42 + 9/10 ] + * Skew: 0.000 s + * OUT3: 156.25 MHz [ 156 + 1/4 MHz ] + * N3: + * Unused + * + * R dividers: + * R0 = 8 + * R1 = 2 + * R2 = 2 + * R3 = 2 + * + * Dividers listed above show effective values. These values are translated to register settings by + * ClockBuilder Pro. For the actual register values, see below. Refer to the Family Reference + * Manual for information on registers related to frequency plan. + * + * Digitally Controlled Oscillator (DCO) + * ===================================== + * Mode: FINC/FDEC + * + * N0: DCO Disabled + * + * N1: DCO Disabled + * + * N2: DCO Disabled + * + * N3: DCO Disabled + * + * Estimated Power & Junction Temperature + * ====================================== + * Assumptions: + * + * Revision: D + * VDD: 1.8 V + * Ta: 70 °C + * Airflow: None + * + * Total Power: 767 mW, On Chip Power: 743 mW, Tj: 87 °C + * + * Frequency Format Voltage Current Power + * ------------ ------ -------- -------- -------- + * VDD 1.8 V 146.3 mA 263 mW + * VDDA 3.3 V 117.4 mA 387 mW + * VDDO0 100 MHz LVDS 1.8 V 15.6 mA 28 mW + * VDDO1 257.8125 MHz LVDS 1.8 V 16.6 mA 30 mW + * VDDO2 257.8125 MHz LVDS 1.8 V 16.6 mA 30 mW + * VDDO3 156.25 MHz LVDS 1.8 V 15.9 mA 29 mW + * -------- -------- + * Total 328.4 mA 767 mW + * + * Note: + * + * -Total power includes on- and off-chip power. This is a typical value and estimate only. + * -Use an EVB for a more exact power measurement + * -On-chip power excludes power dissipated in external terminations. + * -Tj is junction temperature. Tj must be less than 125 °C (on Si5340 Revision D) for device to + * comply with datasheet specifications. + * + * Settings + * ======== + * + * Location Setting Name Decimal Value Hex Value + * ------------ ------------------- ----------------- ----------------- + * 0x0006[23:0] TOOL_VERSION 0 0x000000 + * 0x000B[6:0] I2C_ADDR 116 0x74 + * 0x0017[0] SYSINCAL_INTR_MSK 0 0x0 + * 0x0017[1] LOSXAXB_INTR_MSK 0 0x0 + * 0x0017[2] LOSREF_INTR_MSK 0 0x0 + * 0x0017[3] LOL_INTR_MSK 0 0x0 + * 0x0017[5] SMB_TMOUT_INTR_MSK 1 0x1 + * 0x0018[3:0] LOSIN_INTR_MSK 15 0xF + * 0x0021[0] IN_SEL_REGCTRL 1 0x1 + * 0x0021[2:1] IN_SEL 3 0x3 + * 0x0022[1] OE 0 0x0 + * 0x002B[3] SPI_3WIRE 1 0x1 + * 0x002B[5] AUTO_NDIV_UPDATE 0 0x0 + * 0x002C[3:0] LOS_EN 0 0x0 + * 0x002C[4] LOSXAXB_DIS 0 0x0 + * 0x002D[1:0] LOS0_VAL_TIME 0 0x0 + * 0x002D[3:2] LOS1_VAL_TIME 0 0x0 + * 0x002D[5:4] LOS2_VAL_TIME 0 0x0 + * 0x002D[7:6] LOS3_VAL_TIME 0 0x0 + * 0x002E[15:0] LOS0_TRG_THR 0 0x0000 + * 0x0030[15:0] LOS1_TRG_THR 0 0x0000 + * 0x0032[15:0] LOS2_TRG_THR 0 0x0000 + * 0x0034[15:0] LOS3_TRG_THR 0 0x0000 + * 0x0036[15:0] LOS0_CLR_THR 0 0x0000 + * 0x0038[15:0] LOS1_CLR_THR 0 0x0000 + * 0x003A[15:0] LOS2_CLR_THR 0 0x0000 + * 0x003C[15:0] LOS3_CLR_THR 0 0x0000 + * 0x0041[4:0] LOS0_DIV_SEL 0 0x00 + * 0x0042[4:0] LOS1_DIV_SEL 0 0x00 + * 0x0043[4:0] LOS2_DIV_SEL 0 0x00 + * 0x0044[4:0] LOS3_DIV_SEL 0 0x00 + * 0x009E[7:4] LOL_SET_THR 0 0x0 + * 0x0102[0] OUTALL_DISABLE_LOW 1 0x1 + * 0x0112[0] OUT0_PDN 0 0x0 + * 0x0112[1] OUT0_OE 1 0x1 + * 0x0112[2] OUT0_RDIV_FORCE2 0 0x0 + * 0x0113[2:0] OUT0_FORMAT 1 0x1 + * 0x0113[3] OUT0_SYNC_EN 1 0x1 + * 0x0113[5:4] OUT0_DIS_STATE 0 0x0 + * 0x0113[7:6] OUT0_CMOS_DRV 0 0x0 + * 0x0114[3:0] OUT0_CM 14 0xE + * 0x0114[6:4] OUT0_AMPL 3 0x3 + * 0x0115[2:0] OUT0_MUX_SEL 1 0x1 + * 0x0115[5:4] OUT0_VDD_SEL 1 0x1 + * 0x0115[3] OUT0_VDD_SEL_EN 1 0x1 + * 0x0115[7:6] OUT0_INV 0 0x0 + * 0x0117[0] OUT1_PDN 0 0x0 + * 0x0117[1] OUT1_OE 1 0x1 + * 0x0117[2] OUT1_RDIV_FORCE2 1 0x1 + * 0x0118[2:0] OUT1_FORMAT 1 0x1 + * 0x0118[3] OUT1_SYNC_EN 1 0x1 + * 0x0118[5:4] OUT1_DIS_STATE 0 0x0 + * 0x0118[7:6] OUT1_CMOS_DRV 0 0x0 + * 0x0119[3:0] OUT1_CM 14 0xE + * 0x0119[6:4] OUT1_AMPL 3 0x3 + * 0x011A[2:0] OUT1_MUX_SEL 0 0x0 + * 0x011A[5:4] OUT1_VDD_SEL 1 0x1 + * 0x011A[3] OUT1_VDD_SEL_EN 1 0x1 + * 0x011A[7:6] OUT1_INV 0 0x0 + * 0x0126[0] OUT2_PDN 0 0x0 + * 0x0126[1] OUT2_OE 1 0x1 + * 0x0126[2] OUT2_RDIV_FORCE2 1 0x1 + * 0x0127[2:0] OUT2_FORMAT 1 0x1 + * 0x0127[3] OUT2_SYNC_EN 1 0x1 + * 0x0127[5:4] OUT2_DIS_STATE 0 0x0 + * 0x0127[7:6] OUT2_CMOS_DRV 0 0x0 + * 0x0128[3:0] OUT2_CM 14 0xE + * 0x0128[6:4] OUT2_AMPL 3 0x3 + * 0x0129[2:0] OUT2_MUX_SEL 0 0x0 + * 0x0129[5:4] OUT2_VDD_SEL 1 0x1 + * 0x0129[3] OUT2_VDD_SEL_EN 1 0x1 + * 0x0129[7:6] OUT2_INV 0 0x0 + * 0x012B[0] OUT3_PDN 0 0x0 + * 0x012B[1] OUT3_OE 1 0x1 + * 0x012B[2] OUT3_RDIV_FORCE2 1 0x1 + * 0x012C[2:0] OUT3_FORMAT 1 0x1 + * 0x012C[3] OUT3_SYNC_EN 1 0x1 + * 0x012C[5:4] OUT3_DIS_STATE 0 0x0 + * 0x012C[7:6] OUT3_CMOS_DRV 0 0x0 + * 0x012D[3:0] OUT3_CM 14 0xE + * 0x012D[6:4] OUT3_AMPL 3 0x3 + * 0x012E[2:0] OUT3_MUX_SEL 2 0x2 + * 0x012E[5:4] OUT3_VDD_SEL 1 0x1 + * 0x012E[3] OUT3_VDD_SEL_EN 1 0x1 + * 0x012E[7:6] OUT3_INV 0 0x0 + * 0x013F[11:0] OUTX_ALWAYS_ON 0 0x000 + * 0x0141[5] OUT_DIS_LOL_MSK 0 0x0 + * 0x0141[7] OUT_DIS_MSK_LOS_PFD 0 0x0 + * 0x0206[1:0] PXAXB 0 0x0 + * 0x0208[47:0] P0 0 0x000000000000 + * 0x020E[31:0] P0_SET 0 0x00000000 + * 0x0212[47:0] P1 0 0x000000000000 + * 0x0218[31:0] P1_SET 0 0x00000000 + * 0x021C[47:0] P2 0 0x000000000000 + * 0x0222[31:0] P2_SET 0 0x00000000 + * 0x0226[47:0] P3 0 0x000000000000 + * 0x022C[31:0] P3_SET 0 0x00000000 + * 0x0235[43:0] M_NUM 599785472000 0x08BA6000000 + * 0x023B[31:0] M_DEN 2147483648 0x80000000 + * 0x0250[23:0] R0_REG 3 0x000003 + * 0x0253[23:0] R1_REG 0 0x000000 + * 0x025C[23:0] R2_REG 0 0x000000 + * 0x025F[23:0] R3_REG 0 0x000000 + * 0x026B[7:0] DESIGN_ID0 48 0x30 + * 0x026C[7:0] DESIGN_ID1 53 0x35 + * 0x026D[7:0] DESIGN_ID2 0 0x00 + * 0x026E[7:0] DESIGN_ID3 0 0x00 + * 0x026F[7:0] DESIGN_ID4 0 0x00 + * 0x0270[7:0] DESIGN_ID5 0 0x00 + * 0x0271[7:0] DESIGN_ID6 0 0x00 + * 0x0272[7:0] DESIGN_ID7 0 0x00 + * 0x0302[43:0] N0_NUM 55834574848 0x00D00000000 + * 0x0308[31:0] N0_DEN 2147483648 0x80000000 + * 0x030C[0] N0_UPDATE 0 0x0 + * 0x030D[43:0] N1_NUM 35987128320 0x00861000000 + * 0x0313[31:0] N1_DEN 2147483648 0x80000000 + * 0x0317[0] N1_UPDATE 0 0x0 + * 0x0318[43:0] N2_NUM 115158810624 0x01AD0000000 + * 0x031E[31:0] N2_DEN 2684354560 0xA0000000 + * 0x0322[0] N2_UPDATE 0 0x0 + * 0x0323[43:0] N3_NUM 0 0x00000000000 + * 0x0329[31:0] N3_DEN 0 0x00000000 + * 0x032D[0] N3_UPDATE 0 0x0 + * 0x0338[1] N_UPDATE 0 0x0 + * 0x0339[4:0] N_FSTEP_MSK 31 0x1F + * 0x033B[43:0] N0_FSTEPW 0 0x00000000000 + * 0x0341[43:0] N1_FSTEPW 0 0x00000000000 + * 0x0347[43:0] N2_FSTEPW 0 0x00000000000 + * 0x034D[43:0] N3_FSTEPW 0 0x00000000000 + * 0x0359[15:0] N0_DELAY 0 0x0000 + * 0x035B[15:0] N1_DELAY 0 0x0000 + * 0x035D[15:0] N2_DELAY 0 0x0000 + * 0x035F[15:0] N3_DELAY 0 0x0000 + * 0x0802[15:0] FIXREGSA0 0 0x0000 + * 0x0804[7:0] FIXREGSD0 0 0x00 + * 0x0805[15:0] FIXREGSA1 0 0x0000 + * 0x0807[7:0] FIXREGSD1 0 0x00 + * 0x0808[15:0] FIXREGSA2 0 0x0000 + * 0x080A[7:0] FIXREGSD2 0 0x00 + * 0x080B[15:0] FIXREGSA3 0 0x0000 + * 0x080D[7:0] FIXREGSD3 0 0x00 + * 0x080E[15:0] FIXREGSA4 0 0x0000 + * 0x0810[7:0] FIXREGSD4 0 0x00 + * 0x0811[15:0] FIXREGSA5 0 0x0000 + * 0x0813[7:0] FIXREGSD5 0 0x00 + * 0x0814[15:0] FIXREGSA6 0 0x0000 + * 0x0816[7:0] FIXREGSD6 0 0x00 + * 0x0817[15:0] FIXREGSA7 0 0x0000 + * 0x0819[7:0] FIXREGSD7 0 0x00 + * 0x081A[15:0] FIXREGSA8 0 0x0000 + * 0x081C[7:0] FIXREGSD8 0 0x00 + * 0x081D[15:0] FIXREGSA9 0 0x0000 + * 0x081F[7:0] FIXREGSD9 0 0x00 + * 0x0820[15:0] FIXREGSA10 0 0x0000 + * 0x0822[7:0] FIXREGSD10 0 0x00 + * 0x0823[15:0] FIXREGSA11 0 0x0000 + * 0x0825[7:0] FIXREGSD11 0 0x00 + * 0x0826[15:0] FIXREGSA12 0 0x0000 + * 0x0828[7:0] FIXREGSD12 0 0x00 + * 0x0829[15:0] FIXREGSA13 0 0x0000 + * 0x082B[7:0] FIXREGSD13 0 0x00 + * 0x082C[15:0] FIXREGSA14 0 0x0000 + * 0x082E[7:0] FIXREGSD14 0 0x00 + * 0x082F[15:0] FIXREGSA15 0 0x0000 + * 0x0831[7:0] FIXREGSD15 0 0x00 + * 0x0832[15:0] FIXREGSA16 0 0x0000 + * 0x0834[7:0] FIXREGSD16 0 0x00 + * 0x0835[15:0] FIXREGSA17 0 0x0000 + * 0x0837[7:0] FIXREGSD17 0 0x00 + * 0x0838[15:0] FIXREGSA18 0 0x0000 + * 0x083A[7:0] FIXREGSD18 0 0x00 + * 0x083B[15:0] FIXREGSA19 0 0x0000 + * 0x083D[7:0] FIXREGSD19 0 0x00 + * 0x083E[15:0] FIXREGSA20 0 0x0000 + * 0x0840[7:0] FIXREGSD20 0 0x00 + * 0x0841[15:0] FIXREGSA21 0 0x0000 + * 0x0843[7:0] FIXREGSD21 0 0x00 + * 0x0844[15:0] FIXREGSA22 0 0x0000 + * 0x0846[7:0] FIXREGSD22 0 0x00 + * 0x0847[15:0] FIXREGSA23 0 0x0000 + * 0x0849[7:0] FIXREGSD23 0 0x00 + * 0x084A[15:0] FIXREGSA24 0 0x0000 + * 0x084C[7:0] FIXREGSD24 0 0x00 + * 0x084D[15:0] FIXREGSA25 0 0x0000 + * 0x084F[7:0] FIXREGSD25 0 0x00 + * 0x0850[15:0] FIXREGSA26 0 0x0000 + * 0x0852[7:0] FIXREGSD26 0 0x00 + * 0x0853[15:0] FIXREGSA27 0 0x0000 + * 0x0855[7:0] FIXREGSD27 0 0x00 + * 0x0856[15:0] FIXREGSA28 0 0x0000 + * 0x0858[7:0] FIXREGSD28 0 0x00 + * 0x0859[15:0] FIXREGSA29 0 0x0000 + * 0x085B[7:0] FIXREGSD29 0 0x00 + * 0x085C[15:0] FIXREGSA30 0 0x0000 + * 0x085E[7:0] FIXREGSD30 0 0x00 + * 0x085F[15:0] FIXREGSA31 0 0x0000 + * 0x0861[7:0] FIXREGSD31 0 0x00 + * 0x090E[0] XAXB_EXTCLK_EN 0 0x0 + * 0x090E[1] XAXB_PDNB 1 0x1 + * 0x091C[2:0] ZDM_EN 4 0x4 + * 0x0943[0] IO_VDD_SEL 0 0x0 + * 0x0949[3:0] IN_EN 0 0x0 + * 0x0949[7:4] IN_PULSED_CMOS_EN 0 0x0 + * 0x094A[7:4] INX_TO_PFD_EN 0 0x0 + * 0x094E[11:0] REFCLK_HYS_SEL 585 0x249 + * 0x095E[0] M_INTEGER 0 0x0 + * 0x0A02[4:0] N_ADD_0P5 0 0x00 + * 0x0A03[4:0] N_CLK_TO_OUTX_EN 7 0x07 + * 0x0A04[4:0] N_PIBYP 1 0x01 + * 0x0A05[4:0] N_PDNB 7 0x07 + * 0x0A14[3] N0_HIGH_FREQ 0 0x0 + * 0x0A1A[3] N1_HIGH_FREQ 0 0x0 + * 0x0A20[3] N2_HIGH_FREQ 0 0x0 + * 0x0A26[3] N3_HIGH_FREQ 0 0x0 + * 0x0B44[3:0] PDIV_ENB 15 0xF + * 0x0B4A[4:0] N_CLK_DIS 8 0x08 + * 0x0B57[11:0] VCO_RESET_CALCODE 270 0x10E + * + * + */ + +#endif diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c new file mode 100644 index 0000000000..dc8015ccab --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nt200a0x/clock_profiles/nthw_fpga_clk9563.c @@ -0,0 +1,45 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntnic_mod_reg.h" + +/* + * Clock profile for NT200A02 FPGA 9563 + */ +#define si5340_revd_register_t type_9563_si5340_nt200a02_u23_v5 +#define si5340_revd_registers data_9563_si5340_nt200a02_u23_v5 +#include "NT200A02_U23_Si5340_adr0_v5-Registers.h" +static_assert(sizeof(type_9563_si5340_nt200a02_u23_v5) == sizeof(clk_profile_data_fmt2_t), + clk_profile_size_error_msg); +static const int n_data_9563_si5340_nt200a02_u23_v5 = SI5340_REVD_REG_CONFIG_NUM_REGS; +static const clk_profile_data_fmt2_t *p_data_9563_si5340_nt200a02_u23_v5 = + (const clk_profile_data_fmt2_t *)&data_9563_si5340_nt200a02_u23_v5[0]; + +static const int *get_n_data_9563_si5340_nt200a02_u23_v5(void) +{ + return &n_data_9563_si5340_nt200a02_u23_v5; +} + +static const clk_profile_data_fmt2_t *get_p_data_9563_si5340_nt200a02_u23_v5(void) +{ + return p_data_9563_si5340_nt200a02_u23_v5; +} + +static struct clk9563_ops ops = { .get_n_data_9563_si5340_nt200a02_u23_v5 = + get_n_data_9563_si5340_nt200a02_u23_v5, + .get_p_data_9563_si5340_nt200a02_u23_v5 = + get_p_data_9563_si5340_nt200a02_u23_v5 +}; + +void clk9563_ops_init(void) +{ + register_clk9563_ops(&ops); +} + +#undef si5340_revd_registers +#undef si5340_revd_register_t +#undef SI5340_REVD_REG_CONFIG_HEADER /* Disable the include once protection */ + +#undef code diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c index a3b6511b06..380f877096 100644 --- a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c +++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c @@ -164,6 +164,34 @@ static int nthw_fpga_rst9563_periph_reset(nthw_fpga_t *p_fpga) return 0; } +static int nthw_fpga_rst9563_clock_synth_init(nthw_fpga_t *p_fpga, + const int n_si_labs_clock_synth_model, + const uint8_t n_si_labs_clock_synth_i2c_addr) +{ + const char *const p_adapter_id_str = p_fpga->p_fpga_info->mp_adapter_id_str; + const int n_fpga_product_id = p_fpga->mn_product_id; + int res; + const struct clk9563_ops *clk9563_ops = get_clk9563_ops(); + + if (clk9563_ops == NULL) { + NT_LOG(INF, NTNIC, "CLK9563 module not included\n"); + return -1; + } + + if (n_si_labs_clock_synth_model == 5340) { + res = nthw_fpga_si5340_clock_synth_init_fmt2(p_fpga, n_si_labs_clock_synth_i2c_addr, + clk9563_ops->get_p_data_9563_si5340_nt200a02_u23_v5(), + *clk9563_ops->get_n_data_9563_si5340_nt200a02_u23_v5()); + + } else { + NT_LOG(ERR, NTHW, "%s: Fpga %d: Unsupported clock synth model (%d)\n", + p_adapter_id_str, n_fpga_product_id, n_si_labs_clock_synth_model); + res = -1; + } + + return res; +} + static int nthw_fpga_rst9563_init(struct fpga_info_s *p_fpga_info, struct nthw_fpga_rst_nt200a0x *p_rst) { @@ -173,9 +201,13 @@ static int nthw_fpga_rst9563_init(struct fpga_info_s *p_fpga_info, const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; (void)p_adapter_id_str; int res = -1; + int n_si_labs_clock_synth_model; + uint8_t n_si_labs_clock_synth_i2c_addr; nthw_fpga_t *p_fpga = NULL; p_fpga = p_fpga_info->mp_fpga; + n_si_labs_clock_synth_model = p_rst->mn_si_labs_clock_synth_model; + n_si_labs_clock_synth_i2c_addr = p_rst->mn_si_labs_clock_synth_i2c_addr; res = nthw_fpga_rst9563_periph_reset(p_fpga); @@ -184,6 +216,9 @@ static int nthw_fpga_rst9563_init(struct fpga_info_s *p_fpga_info, return res; } + res = nthw_fpga_rst9563_clock_synth_init(p_fpga, n_si_labs_clock_synth_model, + n_si_labs_clock_synth_i2c_addr); + if (res) { NT_LOG_DBGX(DEBUG, NTHW, "%s: ERROR: res=%d\n", p_adapter_id_str, res); return res; diff --git a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c index 84f13e8371..ea0276a90c 100644 --- a/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c +++ b/drivers/net/ntnic/nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c @@ -552,7 +552,10 @@ static int nthw_fpga_rst_nt200a0x_init(struct fpga_info_s *p_fpga_info, } p_rst->mn_si_labs_clock_synth_model = n_si_labs_clock_synth_model; + p_rst->mn_si_labs_clock_synth_i2c_addr = n_si_labs_clock_synth_i2c_addr; p_rst->mn_hw_id = p_fpga_info->nthw_hw_info.hw_id; + NT_LOG_DBGX(DEBUG, NTHW, "%s: Si%04d @ 0x%02x\n", p_adapter_id_str, + p_rst->mn_si_labs_clock_synth_model, p_rst->mn_si_labs_clock_synth_i2c_addr); return res; } diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c index 1650bb8a5c..38169176a5 100644 --- a/drivers/net/ntnic/nthw/core/nthw_fpga.c +++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c @@ -147,6 +147,29 @@ int nthw_fpga_silabs_detect(nthw_fpga_t *p_fpga, const int n_instance_no, const return res; } +/* + * NT200A02, NT200A01-HWbuild2 + */ +int nthw_fpga_si5340_clock_synth_init_fmt2(nthw_fpga_t *p_fpga, const uint8_t n_iic_addr, + const clk_profile_data_fmt2_t *p_clk_profile, + const int n_clk_profile_rec_cnt) +{ + int res; + nthw_iic_t *p_nthw_iic = nthw_iic_new(); + nthw_si5340_t *p_nthw_si5340 = nthw_si5340_new(); + + assert(p_nthw_iic); + assert(p_nthw_si5340); + nthw_iic_init(p_nthw_iic, p_fpga, 0, 8);/* I2C cycle time 125Mhz ~ 8ns */ + + nthw_si5340_init(p_nthw_si5340, p_nthw_iic, n_iic_addr);/* si5340_u23_i2c_addr_7bit */ + res = nthw_si5340_config_fmt2(p_nthw_si5340, p_clk_profile, n_clk_profile_rec_cnt); + nthw_si5340_delete(p_nthw_si5340); + p_nthw_si5340 = NULL; + + return res; +} + int nthw_fpga_init(struct fpga_info_s *p_fpga_info) { const char *const p_adapter_id_str = p_fpga_info->mp_adapter_id_str; diff --git a/drivers/net/ntnic/nthw/core/nthw_si5340.c b/drivers/net/ntnic/nthw/core/nthw_si5340.c new file mode 100644 index 0000000000..10bd4d8105 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_si5340.c @@ -0,0 +1,198 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + * + * This file implements Si5340 clock synthesizer support. + * The implementation is generic and must be tailored to a specific use by the + * correct initialization data. + */ + +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_si5340.h" + +#define SI5340_PAGE_REG_ADDR (0x01) + +nthw_si5340_t *nthw_si5340_new(void) +{ + nthw_si5340_t *p = malloc(sizeof(nthw_si5340_t)); + + if (p) + memset(p, 0, sizeof(nthw_si5340_t)); + + return p; +} + +int nthw_si5340_init(nthw_si5340_t *p, nthw_iic_t *p_nthw_iic, uint8_t n_iic_addr) +{ + uint8_t data; + + p->mp_nthw_iic = p_nthw_iic; + p->mn_iic_addr = n_iic_addr; + p->mn_clk_cfg = -1; + + p->m_si5340_page = 0; + data = p->m_si5340_page; + nthw_iic_write_data(p->mp_nthw_iic, p->mn_iic_addr, SI5340_PAGE_REG_ADDR, 1, &data); + + return 0; +} + +void nthw_si5340_delete(nthw_si5340_t *p) +{ + if (p) { + memset(p, 0, sizeof(nthw_si5340_t)); + free(p); + } +} + +/* + * Read access (via I2C) to the clock synthesizer IC. The IC is located at I2C + * 7bit address 0x74 + */ +static uint8_t nthw_si5340_read(nthw_si5340_t *p, uint16_t reg_addr) +{ + const uint8_t offset_adr = (uint8_t)(reg_addr & 0xff); + uint8_t page = (uint8_t)((reg_addr >> 8) & 0xff); + uint8_t data; + + /* check if we are on the right page */ + if (page != p->m_si5340_page) { + nthw_iic_write_data(p->mp_nthw_iic, p->mn_iic_addr, SI5340_PAGE_REG_ADDR, 1, + &page); + p->m_si5340_page = page; + } + + nthw_iic_read_data(p->mp_nthw_iic, p->mn_iic_addr, offset_adr, 1, &data); + return data; +} + +/* + * Write access (via I2C) to the clock synthesizer IC. The IC is located at I2C + * 7 bit address 0x74 + */ +static int nthw_si5340_write(nthw_si5340_t *p, uint16_t reg_addr, uint8_t data) +{ + const uint8_t offset_adr = (uint8_t)(reg_addr & 0xff); + uint8_t page = (uint8_t)((reg_addr >> 8) & 0xff); + + /* check if we are on the right page */ + if (page != p->m_si5340_page) { + nthw_iic_write_data(p->mp_nthw_iic, p->mn_iic_addr, SI5340_PAGE_REG_ADDR, 1, + &page); + p->m_si5340_page = page; + } + + nthw_iic_write_data(p->mp_nthw_iic, p->mn_iic_addr, offset_adr, 1, &data); + + return 0; +} + +static int nthw_si5340_cfg(nthw_si5340_t *p, const void *p_data, int data_cnt, + clk_profile_data_fmt_t data_format) +{ + const char *const p_adapter_id_str = + p->mp_nthw_iic->mp_fpga->p_fpga_info->mp_adapter_id_str; + int i; + uint16_t addr; + uint8_t value; + uint8_t ctrl_value; + + NT_LOG(DBG, NTHW, "%s: data_cnt = %d, data_format = %d\n", p_adapter_id_str, + data_cnt, data_format); + + for (i = 0; i < data_cnt; i++) { + if (data_format == clk_profile_data_fmt_1) { + addr = ((const clk_profile_data_fmt1_t *)p_data)->reg_addr; + value = ((const clk_profile_data_fmt1_t *)p_data)->reg_val; + p_data = ((const clk_profile_data_fmt1_t *)p_data) + 1; + + } else if (data_format == clk_profile_data_fmt_2) { + addr = (uint16_t)(((const clk_profile_data_fmt2_t *)p_data)->reg_addr); + value = ((const clk_profile_data_fmt2_t *)p_data)->reg_val; + p_data = ((const clk_profile_data_fmt2_t *)p_data) + 1; + + } else { + NT_LOG(ERR, NTHW, "%s: Unhandled Si5340 data format (%d)\n", + p_adapter_id_str, data_format); + return -1; + } + + if (addr == 0x0006) { + /* Wait 300ms before continuing. See NT200E3-2-PTP_U23_Si5340_adr0_v2.h */ + nt_os_wait_usec(300000); + } + + nthw_si5340_write(p, addr, value); + + if (addr == 0x001C) { + /* skip readback for "soft reset" register */ + continue; + } + + ctrl_value = nthw_si5340_read(p, addr); + + if (ctrl_value != value) { + NT_LOG(ERR, NTHW, + "%s: Si5340 configuration readback check failed. (Addr = 0x%04X, Write = 0x%02X, Read = 0x%02X)\n", + p_adapter_id_str, addr, value, ctrl_value); + return -1; + } + } + + return 0; +} + +int nthw_si5340_config(nthw_si5340_t *p, const void *p_data, int data_cnt, + clk_profile_data_fmt_t data_format) +{ + const char *const p_adapter_id_str = + p->mp_nthw_iic->mp_fpga->p_fpga_info->mp_adapter_id_str; + int i; + bool success = false; + uint8_t status, sticky; + uint8_t design_id[9]; + + (void)nthw_si5340_cfg(p, p_data, data_cnt, data_format); + + /* Check if DPLL is locked and SYS is calibrated */ + for (i = 0; i < 5; i++) { + status = nthw_si5340_read(p, 0x0c); + sticky = nthw_si5340_read(p, 0x11); + nthw_si5340_write(p, 0x11, 0x00); + + if (((status & 0x09) == 0x00) && ((sticky & 0x09) == 0x00)) { + success = true; + break; + } + + nt_os_wait_usec(1000000); /* 1 sec */ + } + + if (!success) { + NT_LOG(ERR, NTHW, + "%s: Si5340 configuration failed. (Status = 0x%02X, Sticky = 0x%02X)\n", + p_adapter_id_str, status, sticky); + return -1; + } + + for (i = 0; i < (int)sizeof(design_id) - 1; i++) + design_id[i] = nthw_si5340_read(p, (uint16_t)(0x26B + i)); + + design_id[sizeof(design_id) - 1] = 0; + + (void)design_id;/* Only used in debug mode */ + NT_LOG(DBG, NTHW, "%s: Si5340.Design_id = %s\n", p_adapter_id_str, design_id); + + return 0; +} + +int nthw_si5340_config_fmt2(nthw_si5340_t *p, const clk_profile_data_fmt2_t *p_data, + const int data_cnt) +{ + return nthw_si5340_config(p, p_data, data_cnt, clk_profile_data_fmt_2); +} diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c index bd0a966be2..3f03299a83 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.c +++ b/drivers/net/ntnic/ntnic_mod_reg.c @@ -19,6 +19,20 @@ const struct adapter_ops *get_adapter_ops(void) return adapter_ops; } +static struct clk9563_ops *clk9563_ops; + +void register_clk9563_ops(struct clk9563_ops *ops) +{ + clk9563_ops = ops; +} + +struct clk9563_ops *get_clk9563_ops(void) +{ + if (clk9563_ops == NULL) + clk9563_ops_init(); + return clk9563_ops; +} + static struct rst_nt200a0x_ops *rst_nt200a0x_ops; void register_rst_nt200a0x_ops(struct rst_nt200a0x_ops *ops) diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index df8a8b9aca..45f5632981 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -25,6 +25,15 @@ void register_adapter_ops(const struct adapter_ops *ops); const struct adapter_ops *get_adapter_ops(void); void adapter_init(void); +struct clk9563_ops { + const int *(*get_n_data_9563_si5340_nt200a02_u23_v5)(void); + const clk_profile_data_fmt2_t *(*get_p_data_9563_si5340_nt200a02_u23_v5)(void); +}; + +void register_clk9563_ops(struct clk9563_ops *ops); +struct clk9563_ops *get_clk9563_ops(void); +void clk9563_ops_init(void); + struct rst_nt200a0x_ops { int (*nthw_fpga_rst_nt200a0x_init)(struct fpga_info_s *p_fpga_info, struct nthw_fpga_rst_nt200a0x *p_rst); From patchwork Wed Jul 17 13:33:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142470 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E77C45635; 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Note that must functions are not implemented yet. Adds the following eth_dev_ops: - dev_set_link_up - dev_set_link_down - link_update - mac_addr_add - mac_addr_set - set_mc_addr_list - promiscuous_enable Signed-off-by: Serhii Iliushyk --- v5 * Fix Typo/Spelling v6 * if_index was replaced with n_intf_no * MAC addr assignment approach was reworked v7 * Add relate features to documentation - INI and RST files v10 * Use 8 spaces as indentation in meson --- doc/guides/nics/features/ntnic.ini | 3 + doc/guides/nics/ntnic.rst | 5 + drivers/net/ntnic/adapter/nt4ga_adapter.c | 6 + drivers/net/ntnic/include/nt4ga_adapter.h | 5 +- drivers/net/ntnic/include/nt4ga_link.h | 84 +++++++ drivers/net/ntnic/include/ntos_drv.h | 10 + drivers/net/ntnic/link_mgmt/nt4ga_link.c | 176 ++++++++++++++ drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/ntnic_ethdev.c | 281 ++++++++++++++++++++++ drivers/net/ntnic/ntnic_mod_reg.c | 14 ++ drivers/net/ntnic/ntnic_mod_reg.h | 50 +++- drivers/net/ntnic/ntutil/nt_util.c | 131 ++++++++++ drivers/net/ntnic/ntutil/nt_util.h | 11 + 13 files changed, 775 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/include/nt4ga_link.h create mode 100644 drivers/net/ntnic/link_mgmt/nt4ga_link.c diff --git a/doc/guides/nics/features/ntnic.ini b/doc/guides/nics/features/ntnic.ini index 03f4d5aac8..0a74817fcf 100644 --- a/doc/guides/nics/features/ntnic.ini +++ b/doc/guides/nics/features/ntnic.ini @@ -5,5 +5,8 @@ ; [Features] FW version = Y +Speed capabilities = Y +Unicast MAC filter = Y +Multicast MAC filter = Y Linux = Y x86-64 = Y diff --git a/doc/guides/nics/ntnic.rst b/doc/guides/nics/ntnic.rst index db168e1686..d612da53ee 100644 --- a/doc/guides/nics/ntnic.rst +++ b/doc/guides/nics/ntnic.rst @@ -33,6 +33,11 @@ Features -------- - FW version +- Speed capabilities +- Link status (Link update only) +- Unicast MAC filter +- Multicast MAC filter +- Promiscuous mode (Enable only. The device always run promiscuous mode) Limitations ~~~~~~~~~~~ diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c index 1bdd11f227..be98938cc3 100644 --- a/drivers/net/ntnic/adapter/nt4ga_adapter.c +++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c @@ -124,8 +124,14 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) assert(n_phy_ports >= 1); { + int i; assert(fpga_info->n_fpga_prod_id > 0); + for (i = 0; i < NUM_ADAPTER_PORTS_MAX; i++) { + /* Disable all ports. Must be enabled later */ + p_adapter_info->nt4ga_link.port_action[i].port_disable = true; + } + switch (fpga_info->n_fpga_prod_id) { /* NT200A01: 2x100G (Xilinx) */ case 9563: /* NT200A02 (Cap) */ diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h index 2c72583caf..ed14936b38 100644 --- a/drivers/net/ntnic/include/nt4ga_adapter.h +++ b/drivers/net/ntnic/include/nt4ga_adapter.h @@ -6,7 +6,8 @@ #ifndef _NT4GA_ADAPTER_H_ #define _NT4GA_ADAPTER_H_ -#include "ntos_drv.h" +#include "nt4ga_link.h" + typedef struct hw_info_s { /* pciids */ uint16_t pci_vendor_id; @@ -23,6 +24,8 @@ typedef struct hw_info_s { } hw_info_t; typedef struct adapter_info_s { + struct nt4ga_link_s nt4ga_link; + struct hw_info_s hw_info; struct fpga_info_s fpga_info; diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h new file mode 100644 index 0000000000..849261ce3a --- /dev/null +++ b/drivers/net/ntnic/include/nt4ga_link.h @@ -0,0 +1,84 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NT4GA_LINK_H_ +#define NT4GA_LINK_H_ + +#include "ntos_drv.h" + +enum nt_link_state_e { + NT_LINK_STATE_UNKNOWN = 0, /* The link state has not been read yet */ + NT_LINK_STATE_DOWN = 1, /* The link state is DOWN */ + NT_LINK_STATE_UP = 2, /* The link state is UP */ + NT_LINK_STATE_ERROR = 3 /* The link state could not be read */ +}; + +typedef enum nt_link_state_e nt_link_state_t, *nt_link_state_p; + +enum nt_link_duplex_e { + NT_LINK_DUPLEX_UNKNOWN = 0, + NT_LINK_DUPLEX_HALF = 0x01, /* Half duplex */ + NT_LINK_DUPLEX_FULL = 0x02, /* Full duplex */ +}; + +typedef enum nt_link_duplex_e nt_link_duplex_t; + +enum nt_link_loopback_e { + NT_LINK_LOOPBACK_OFF = 0, + NT_LINK_LOOPBACK_HOST = 0x01, /* Host loopback mode */ + NT_LINK_LOOPBACK_LINE = 0x02, /* Line loopback mode */ +}; + +enum nt_link_auto_neg_e { + NT_LINK_AUTONEG_NA = 0, + NT_LINK_AUTONEG_MANUAL = 0x01, + NT_LINK_AUTONEG_OFF = NT_LINK_AUTONEG_MANUAL, /* Auto negotiation OFF */ + NT_LINK_AUTONEG_AUTO = 0x02, + NT_LINK_AUTONEG_ON = NT_LINK_AUTONEG_AUTO, /* Auto negotiation ON */ +}; + +typedef struct link_state_s { + bool link_disabled; + bool link_up; + enum nt_link_state_e link_state; + enum nt_link_state_e link_state_latched; +} link_state_t; + +enum nt_link_speed_e { + NT_LINK_SPEED_UNKNOWN = 0, + NT_LINK_SPEED_10M = 0x01, /* 10 Mbps */ + NT_LINK_SPEED_100M = 0x02, /* 100 Mbps */ + NT_LINK_SPEED_1G = 0x04,/* 1 Gbps (Autoneg only) */ + NT_LINK_SPEED_10G = 0x08, /* 10 Gbps (Autoneg only) */ + NT_LINK_SPEED_40G = 0x10, /* 40 Gbps (Autoneg only) */ + NT_LINK_SPEED_100G = 0x20, /* 100 Gbps (Autoneg only) */ + NT_LINK_SPEED_50G = 0x40, /* 50 Gbps (Autoneg only) */ + NT_LINK_SPEED_25G = 0x80, /* 25 Gbps (Autoneg only) */ + NT_LINK_SPEED_END /* always keep this entry as the last in enum */ +}; +typedef enum nt_link_speed_e nt_link_speed_t; + +typedef struct link_info_s { + enum nt_link_speed_e link_speed; + enum nt_link_duplex_e link_duplex; + enum nt_link_auto_neg_e link_auto_neg; +} link_info_t; + +typedef struct port_action_s { + bool port_disable; + enum nt_link_speed_e port_speed; + enum nt_link_duplex_e port_duplex; + uint32_t port_lpbk_mode; +} port_action_t; + +typedef struct nt4ga_link_s { + link_state_t link_state[NUM_ADAPTER_PORTS_MAX]; + link_info_t link_info[NUM_ADAPTER_PORTS_MAX]; + port_action_t port_action[NUM_ADAPTER_PORTS_MAX]; + uint32_t speed_capa; + bool variables_initialized; +} nt4ga_link_t; + +#endif /* NT4GA_LINK_H_ */ diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h index 3f621143d9..67baf9fe0c 100644 --- a/drivers/net/ntnic/include/ntos_drv.h +++ b/drivers/net/ntnic/include/ntos_drv.h @@ -25,7 +25,17 @@ struct pmd_internals { const struct rte_pci_device *pci_dev; char name[20]; int n_intf_no; + int lpbk_mode; + unsigned int nb_rx_queues; + unsigned int nb_tx_queues; + /* Offset of the VF from the PF */ + uint8_t vf_offset; + nt_meta_port_type_t type; struct drv_s *p_drv; + /* Ethernet (MAC) addresses. Element number zero denotes default address. */ + struct rte_ether_addr eth_addrs[NUM_MAC_ADDRS_PER_PORT]; + /* Multicast ethernet (MAC) addresses. */ + struct rte_ether_addr mc_addrs[NUM_MULTICAST_ADDRS_PER_PORT]; struct pmd_internals *next; }; diff --git a/drivers/net/ntnic/link_mgmt/nt4ga_link.c b/drivers/net/ntnic/link_mgmt/nt4ga_link.c new file mode 100644 index 0000000000..ad23046aae --- /dev/null +++ b/drivers/net/ntnic/link_mgmt/nt4ga_link.c @@ -0,0 +1,176 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include +#include +#include + +#include "ntlog.h" +#include "ntnic_mod_reg.h" + +#include "nt4ga_link.h" + +/* + * port: speed capabilities + * This is actually an adapter capability mapped onto every port + */ +static uint32_t nt4ga_port_get_link_speed_capabilities(struct adapter_info_s *p, int port) +{ + (void)p; + (void)port; + nt4ga_link_t *const p_link = &p->nt4ga_link; + const uint32_t nt_link_speed_capa = p_link->speed_capa; + return nt_link_speed_capa; +} + +/* + * port: link mode + */ +static void nt4ga_port_set_adm_state(struct adapter_info_s *p, int port, bool adm_state) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + p_link->port_action[port].port_disable = !adm_state; +} + +static bool nt4ga_port_get_adm_state(struct adapter_info_s *p, int port) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + const bool adm_state = !p_link->port_action[port].port_disable; + return adm_state; +} + +/* + * port: link status + */ +static void nt4ga_port_set_link_status(struct adapter_info_s *p, int port, bool link_status) +{ + /* Setting link state/status is (currently) the same as controlling the port adm state */ + nt4ga_port_set_adm_state(p, port, link_status); +} + +static bool nt4ga_port_get_link_status(struct adapter_info_s *p, int port) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + bool status = p_link->link_state[port].link_up; + return status; +} + +/* + * port: link speed + */ +static void nt4ga_port_set_link_speed(struct adapter_info_s *p, int port, nt_link_speed_t speed) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + p_link->port_action[port].port_speed = speed; + p_link->link_info[port].link_speed = speed; +} + +static nt_link_speed_t nt4ga_port_get_link_speed(struct adapter_info_s *p, int port) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + nt_link_speed_t speed = p_link->link_info[port].link_speed; + return speed; +} + +/* + * port: link autoneg + * Currently not fully supported by link code + */ +static void nt4ga_port_set_link_autoneg(struct adapter_info_s *p, int port, bool autoneg) +{ + (void)p; + (void)port; + (void)autoneg; + nt4ga_link_t *const p_link = &p->nt4ga_link; + (void)p_link; +} + +static bool nt4ga_port_get_link_autoneg(struct adapter_info_s *p, int port) +{ + (void)p; + (void)port; + nt4ga_link_t *const p_link = &p->nt4ga_link; + (void)p_link; + return true; +} + +/* + * port: link duplex + * Currently not fully supported by link code + */ +static void nt4ga_port_set_link_duplex(struct adapter_info_s *p, int port, nt_link_duplex_t duplex) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + p_link->port_action[port].port_duplex = duplex; +} + +static nt_link_duplex_t nt4ga_port_get_link_duplex(struct adapter_info_s *p, int port) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + nt_link_duplex_t duplex = p_link->link_info[port].link_duplex; + return duplex; +} + +/* + * port: loopback mode + */ +static void nt4ga_port_set_loopback_mode(struct adapter_info_s *p, int port, uint32_t mode) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + p_link->port_action[port].port_lpbk_mode = mode; +} + +static uint32_t nt4ga_port_get_loopback_mode(struct adapter_info_s *p, int port) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + return p_link->port_action[port].port_lpbk_mode; +} + + +static const struct port_ops ops = { + /* + * port:s link mode + */ + .set_adm_state = nt4ga_port_set_adm_state, + .get_adm_state = nt4ga_port_get_adm_state, + + /* + * port:s link status + */ + .set_link_status = nt4ga_port_set_link_status, + .get_link_status = nt4ga_port_get_link_status, + + /* + * port: link autoneg + */ + .set_link_autoneg = nt4ga_port_set_link_autoneg, + .get_link_autoneg = nt4ga_port_get_link_autoneg, + + /* + * port: link speed + */ + .set_link_speed = nt4ga_port_set_link_speed, + .get_link_speed = nt4ga_port_get_link_speed, + + /* + * port: link duplex + */ + .set_link_duplex = nt4ga_port_set_link_duplex, + .get_link_duplex = nt4ga_port_get_link_duplex, + + /* + * port: loopback mode + */ + .set_loopback_mode = nt4ga_port_set_loopback_mode, + .get_loopback_mode = nt4ga_port_get_loopback_mode, + + .get_link_speed_capabilities = nt4ga_port_get_link_speed_capabilities, +}; + +void port_init(void) +{ + register_port_ops(&ops); +} diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index b197315e2d..5619bbe0bd 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -22,6 +22,7 @@ includes = [ # all sources sources = files( 'adapter/nt4ga_adapter.c', + 'link_mgmt/nt4ga_link.c', 'nthw/supported/nthw_fpga_9563_055_039_0000.c', 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c index 5d3da88c58..cd7b1dc5c8 100644 --- a/drivers/net/ntnic/ntnic_ethdev.c +++ b/drivers/net/ntnic/ntnic_ethdev.c @@ -22,6 +22,9 @@ #include "ntnic_mod_reg.h" #include "nt_util.h" +#define HW_MAX_PKT_LEN (10000) +#define MAX_MTU (HW_MAX_PKT_LEN - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN) + #define EXCEPTION_PATH_HID 0 static const struct rte_pci_id nthw_pci_id_map[] = { @@ -89,12 +92,133 @@ get_pdrv_from_pci(struct rte_pci_addr addr) return p_drv; } +static int +eth_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete __rte_unused) +{ + const struct port_ops *port_ops = get_port_ops(); + + if (port_ops == NULL) { + NT_LOG(ERR, NTNIC, "Link management module uninitialized\n"); + return -1; + } + + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + + const int n_intf_no = internals->n_intf_no; + struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info; + + if (eth_dev->data->dev_started) { + const bool port_link_status = port_ops->get_link_status(p_adapter_info, n_intf_no); + eth_dev->data->dev_link.link_status = + port_link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN; + + nt_link_speed_t port_link_speed = + port_ops->get_link_speed(p_adapter_info, n_intf_no); + eth_dev->data->dev_link.link_speed = + nt_link_speed_to_eth_speed_num(port_link_speed); + + nt_link_duplex_t nt_link_duplex = + port_ops->get_link_duplex(p_adapter_info, n_intf_no); + eth_dev->data->dev_link.link_duplex = nt_link_duplex_to_eth_duplex(nt_link_duplex); + + } else { + eth_dev->data->dev_link.link_status = RTE_ETH_LINK_DOWN; + eth_dev->data->dev_link.link_speed = RTE_ETH_SPEED_NUM_NONE; + eth_dev->data->dev_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + } + + return 0; +} + static int eth_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *dev_info) { + const struct port_ops *port_ops = get_port_ops(); + + if (port_ops == NULL) { + NT_LOG(ERR, NTNIC, "Link management module uninitialized\n"); + return -1; + } + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + const int n_intf_no = internals->n_intf_no; + struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info; + dev_info->driver_name = internals->name; + dev_info->max_mac_addrs = NUM_MAC_ADDRS_PER_PORT; + dev_info->max_rx_pktlen = HW_MAX_PKT_LEN; + dev_info->max_mtu = MAX_MTU; + + if (internals->p_drv) { + dev_info->max_rx_queues = internals->nb_rx_queues; + dev_info->max_tx_queues = internals->nb_tx_queues; + + dev_info->min_rx_bufsize = 64; + + const uint32_t nt_port_speed_capa = + port_ops->get_link_speed_capabilities(p_adapter_info, n_intf_no); + dev_info->speed_capa = nt_link_speed_capa_to_eth_speed_capa(nt_port_speed_capa); + } + + return 0; +} + +static int +eth_mac_addr_add(struct rte_eth_dev *eth_dev, + struct rte_ether_addr *mac_addr, + uint32_t index, + uint32_t vmdq __rte_unused) +{ + struct rte_ether_addr *const eth_addrs = eth_dev->data->mac_addrs; + + assert(index < NUM_MAC_ADDRS_PER_PORT); + + if (index >= NUM_MAC_ADDRS_PER_PORT) { + const struct pmd_internals *const internals = + (struct pmd_internals *)eth_dev->data->dev_private; + NT_LOG_DBGX(DEBUG, NTNIC, "Port %i: illegal index %u (>= %u)\n", + internals->n_intf_no, index, NUM_MAC_ADDRS_PER_PORT); + return -1; + } + + eth_addrs[index] = *mac_addr; + + return 0; +} + +static int +eth_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) +{ + struct rte_ether_addr *const eth_addrs = dev->data->mac_addrs; + + eth_addrs[0U] = *mac_addr; + + return 0; +} + +static int +eth_set_mc_addr_list(struct rte_eth_dev *eth_dev, + struct rte_ether_addr *mc_addr_set, + uint32_t nb_mc_addr) +{ + struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private; + struct rte_ether_addr *const mc_addrs = internals->mc_addrs; + size_t i; + + if (nb_mc_addr >= NUM_MULTICAST_ADDRS_PER_PORT) { + NT_LOG_DBGX(DEBUG, NTNIC, + "Port %i: too many multicast addresses %u (>= %u)\n", + internals->n_intf_no, nb_mc_addr, NUM_MULTICAST_ADDRS_PER_PORT); + return -1; + } + + for (i = 0U; i < NUM_MULTICAST_ADDRS_PER_PORT; i++) + if (i < nb_mc_addr) + mc_addrs[i] = mc_addr_set[i]; + + else + (void)memset(&mc_addrs[i], 0, sizeof(mc_addrs[i])); return 0; } @@ -112,10 +236,59 @@ eth_dev_configure(struct rte_eth_dev *eth_dev) static int eth_dev_start(struct rte_eth_dev *eth_dev) { + const struct port_ops *port_ops = get_port_ops(); + + if (port_ops == NULL) { + NT_LOG(ERR, NTNIC, "Link management module uninitialized\n"); + return -1; + } + struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + const int n_intf_no = internals->n_intf_no; + struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info; + NT_LOG_DBGX(DEBUG, NTNIC, "Port %u\n", internals->n_intf_no); + if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) { + eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP; + + } else { + /* Enable the port */ + port_ops->set_adm_state(p_adapter_info, internals->n_intf_no, true); + + /* + * wait for link on port + * If application starts sending too soon before FPGA port is ready, garbage is + * produced + */ + int loop = 0; + + while (port_ops->get_link_status(p_adapter_info, n_intf_no) == RTE_ETH_LINK_DOWN) { + /* break out after 5 sec */ + if (++loop >= 50) { + NT_LOG_DBGX(DEBUG, NTNIC, + "TIMEOUT No link on port %i (5sec timeout)\n", + internals->n_intf_no); + break; + } + + nt_os_wait_usec(100 * 1000); + } + + if (internals->lpbk_mode) { + if (internals->lpbk_mode & 1 << 0) { + port_ops->set_loopback_mode(p_adapter_info, n_intf_no, + NT_LINK_LOOPBACK_HOST); + } + + if (internals->lpbk_mode & 1 << 1) { + port_ops->set_loopback_mode(p_adapter_info, n_intf_no, + NT_LINK_LOOPBACK_LINE); + } + } + } + return 0; } @@ -130,6 +303,58 @@ eth_dev_stop(struct rte_eth_dev *eth_dev) return 0; } +static int +eth_dev_set_link_up(struct rte_eth_dev *eth_dev) +{ + const struct port_ops *port_ops = get_port_ops(); + + if (port_ops == NULL) { + NT_LOG(ERR, NTNIC, "Link management module uninitialized\n"); + return -1; + } + + struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private; + + struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info; + const int port = internals->n_intf_no; + + if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) + return 0; + + assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); + assert(port == internals->n_intf_no); + + port_ops->set_adm_state(p_adapter_info, port, true); + + return 0; +} + +static int +eth_dev_set_link_down(struct rte_eth_dev *eth_dev) +{ + const struct port_ops *port_ops = get_port_ops(); + + if (port_ops == NULL) { + NT_LOG(ERR, NTNIC, "Link management module uninitialized\n"); + return -1; + } + + struct pmd_internals *const internals = (struct pmd_internals *)eth_dev->data->dev_private; + + struct adapter_info_s *p_adapter_info = &internals->p_drv->ntdrv.adapter_info; + const int port = internals->n_intf_no; + + if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) + return 0; + + assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); + assert(port == internals->n_intf_no); + + port_ops->set_link_status(p_adapter_info, port, false); + + return 0; +} + static void drv_deinit(struct drv_s *p_drv) { @@ -181,6 +406,9 @@ eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size { struct pmd_internals *internals = (struct pmd_internals *)eth_dev->data->dev_private; + if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) + return 0; + fpga_info_t *fpga_info = &internals->p_drv->ntdrv.adapter_info.fpga_info; const int length = snprintf(fw_version, fw_size, "%03d-%04d-%02d-%02d", fpga_info->n_fpga_type_id, fpga_info->n_fpga_prod_id, @@ -196,19 +424,39 @@ eth_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, size_t fw_size } } +static int +promiscuous_enable(struct rte_eth_dev __rte_unused(*dev)) +{ + NT_LOG(DBG, NTHW, "The device always run promiscuous mode."); + return 0; +} + static const struct eth_dev_ops nthw_eth_dev_ops = { .dev_configure = eth_dev_configure, .dev_start = eth_dev_start, .dev_stop = eth_dev_stop, + .dev_set_link_up = eth_dev_set_link_up, + .dev_set_link_down = eth_dev_set_link_down, .dev_close = eth_dev_close, + .link_update = eth_link_update, .dev_infos_get = eth_dev_infos_get, .fw_version_get = eth_fw_version_get, + .mac_addr_add = eth_mac_addr_add, + .mac_addr_set = eth_mac_addr_set, + .set_mc_addr_list = eth_set_mc_addr_list, + .promiscuous_enable = promiscuous_enable, }; static int nthw_pci_dev_init(struct rte_pci_device *pci_dev) { nt_vfio_init(); + const struct port_ops *port_ops = get_port_ops(); + + if (port_ops == NULL) { + NT_LOG(ERR, NTNIC, "Link management module uninitialized\n"); + return -1; + } const struct adapter_ops *adapter_ops = get_adapter_ops(); @@ -225,6 +473,8 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) uint32_t nb_rx_queues = 1; uint32_t nb_tx_queues = 1; int n_phy_ports; + struct port_link_speed pls_mbps[NUM_ADAPTER_PORTS_MAX] = { 0 }; + int num_port_speeds = 0; NT_LOG_DBGX(DEBUG, NTNIC, "Dev %s PF #%i Init : %02x:%02x:%i\n", pci_dev->name, pci_dev->addr.function, pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function); @@ -287,6 +537,12 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) p_nt_drv->b_shutdown = false; p_nt_drv->adapter_info.pb_shutdown = &p_nt_drv->b_shutdown; + for (int i = 0; i < num_port_speeds; ++i) { + struct adapter_info_s *p_adapter_info = &p_nt_drv->adapter_info; + nt_link_speed_t link_speed = convert_link_speed(pls_mbps[i].link_speed); + port_ops->set_link_speed(p_adapter_info, i, link_speed); + } + /* store context */ store_pdrv(p_drv); @@ -351,6 +607,10 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) internals->pci_dev = pci_dev; internals->n_intf_no = n_intf_no; + internals->type = PORT_TYPE_PHYSICAL; + internals->nb_rx_queues = nb_rx_queues; + internals->nb_tx_queues = nb_tx_queues; + /* Setup queue_ids */ if (nb_rx_queues > 1) { @@ -365,6 +625,18 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) internals->n_intf_no, nb_tx_queues); } + /* Set MAC address (but only if the MAC address is permitted) */ + if (n_intf_no < fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_count) { + const uint64_t mac = + fpga_info->nthw_hw_info.vpd_info.mn_mac_addr_value + n_intf_no; + internals->eth_addrs[0].addr_bytes[0] = (mac >> 40) & 0xFFu; + internals->eth_addrs[0].addr_bytes[1] = (mac >> 32) & 0xFFu; + internals->eth_addrs[0].addr_bytes[2] = (mac >> 24) & 0xFFu; + internals->eth_addrs[0].addr_bytes[3] = (mac >> 16) & 0xFFu; + internals->eth_addrs[0].addr_bytes[4] = (mac >> 8) & 0xFFu; + internals->eth_addrs[0].addr_bytes[5] = (mac >> 0) & 0xFFu; + } + eth_dev = rte_eth_dev_allocate(name); if (!eth_dev) { @@ -373,6 +645,15 @@ nthw_pci_dev_init(struct rte_pci_device *pci_dev) return -1; } + /* connect structs */ + internals->p_drv = p_drv; + eth_dev->data->dev_private = internals; + eth_dev->data->mac_addrs = rte_malloc(NULL, + NUM_MAC_ADDRS_PER_PORT * sizeof(struct rte_ether_addr), 0); + rte_memcpy(ð_dev->data->mac_addrs[0], + &internals->eth_addrs[0], RTE_ETHER_ADDR_LEN); + + struct rte_eth_link pmd_link; pmd_link.link_speed = RTE_ETH_SPEED_NUM_NONE; pmd_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c index 3f03299a83..b79929c696 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.c +++ b/drivers/net/ntnic/ntnic_mod_reg.c @@ -5,6 +5,20 @@ #include "ntnic_mod_reg.h" +static const struct port_ops *port_ops; + +void register_port_ops(const struct port_ops *ops) +{ + port_ops = ops; +} + +const struct port_ops *get_port_ops(void) +{ + if (port_ops == NULL) + port_init(); + return port_ops; +} + static const struct adapter_ops *adapter_ops; void register_adapter_ops(const struct adapter_ops *ops) diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index 45f5632981..8d1971a9c4 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -12,7 +12,55 @@ #include "nthw_drv.h" #include "nt4ga_adapter.h" #include "ntnic_nthw_fpga_rst_nt200a0x.h" -#include "ntos_drv.h" + +struct port_ops { + /* + * port:s link mode + */ + void (*set_adm_state)(struct adapter_info_s *p, int port, bool adm_state); + bool (*get_adm_state)(struct adapter_info_s *p, int port); + + /* + * port:s link status + */ + void (*set_link_status)(struct adapter_info_s *p, int port, bool status); + bool (*get_link_status)(struct adapter_info_s *p, int port); + + /* + * port: link autoneg + */ + void (*set_link_autoneg)(struct adapter_info_s *p, int port, bool autoneg); + bool (*get_link_autoneg)(struct adapter_info_s *p, int port); + + /* + * port: link speed + */ + void (*set_link_speed)(struct adapter_info_s *p, int port, nt_link_speed_t speed); + nt_link_speed_t (*get_link_speed)(struct adapter_info_s *p, int port); + + /* + * port: link duplex + */ + void (*set_link_duplex)(struct adapter_info_s *p, int port, nt_link_duplex_t duplex); + nt_link_duplex_t (*get_link_duplex)(struct adapter_info_s *p, int port); + + /* + * port: loopback mode + */ + void (*set_loopback_mode)(struct adapter_info_s *p, int port, uint32_t mode); + uint32_t (*get_loopback_mode)(struct adapter_info_s *p, int port); + + uint32_t (*get_link_speed_capabilities)(struct adapter_info_s *p, int port); + + /* + * port: tx power + */ + int (*tx_power)(struct adapter_info_s *p, int port, bool disable); +}; + +void register_port_ops(const struct port_ops *ops); +const struct port_ops *get_port_ops(void); +void port_init(void); struct adapter_ops { int (*init)(struct adapter_info_s *p_adapter_info); diff --git a/drivers/net/ntnic/ntutil/nt_util.c b/drivers/net/ntnic/ntutil/nt_util.c index 53c39ef112..9904e3df3b 100644 --- a/drivers/net/ntnic/ntutil/nt_util.c +++ b/drivers/net/ntnic/ntutil/nt_util.c @@ -96,3 +96,134 @@ void nt_dma_free(struct nt_dma_s *vfio_addr) rte_free((void *)(vfio_addr->addr)); rte_free(vfio_addr); } + +/* NOTE: please note the difference between RTE_ETH_SPEED_NUM_xxx and RTE_ETH_LINK_SPEED_xxx */ +int nt_link_speed_to_eth_speed_num(enum nt_link_speed_e nt_link_speed) +{ + int eth_speed_num = RTE_ETH_SPEED_NUM_NONE; + + switch (nt_link_speed) { + case NT_LINK_SPEED_10M: + eth_speed_num = RTE_ETH_SPEED_NUM_10M; + break; + + case NT_LINK_SPEED_100M: + eth_speed_num = RTE_ETH_SPEED_NUM_100M; + break; + + case NT_LINK_SPEED_1G: + eth_speed_num = RTE_ETH_SPEED_NUM_1G; + break; + + case NT_LINK_SPEED_10G: + eth_speed_num = RTE_ETH_SPEED_NUM_10G; + break; + + case NT_LINK_SPEED_25G: + eth_speed_num = RTE_ETH_SPEED_NUM_25G; + break; + + case NT_LINK_SPEED_40G: + eth_speed_num = RTE_ETH_SPEED_NUM_40G; + break; + + case NT_LINK_SPEED_50G: + eth_speed_num = RTE_ETH_SPEED_NUM_50G; + break; + + case NT_LINK_SPEED_100G: + eth_speed_num = RTE_ETH_SPEED_NUM_100G; + break; + + default: + eth_speed_num = RTE_ETH_SPEED_NUM_NONE; + break; + } + + return eth_speed_num; +} + +uint32_t nt_link_speed_capa_to_eth_speed_capa(int nt_link_speed_capa) +{ + uint32_t eth_speed_capa = 0; + + if (nt_link_speed_capa & NT_LINK_SPEED_10M) + eth_speed_capa |= RTE_ETH_LINK_SPEED_10M; + + if (nt_link_speed_capa & NT_LINK_SPEED_100M) + eth_speed_capa |= RTE_ETH_LINK_SPEED_100M; + + if (nt_link_speed_capa & NT_LINK_SPEED_1G) + eth_speed_capa |= RTE_ETH_LINK_SPEED_1G; + + if (nt_link_speed_capa & NT_LINK_SPEED_10G) + eth_speed_capa |= RTE_ETH_LINK_SPEED_10G; + + if (nt_link_speed_capa & NT_LINK_SPEED_25G) + eth_speed_capa |= RTE_ETH_LINK_SPEED_25G; + + if (nt_link_speed_capa & NT_LINK_SPEED_40G) + eth_speed_capa |= RTE_ETH_LINK_SPEED_40G; + + if (nt_link_speed_capa & NT_LINK_SPEED_50G) + eth_speed_capa |= RTE_ETH_LINK_SPEED_50G; + + if (nt_link_speed_capa & NT_LINK_SPEED_100G) + eth_speed_capa |= RTE_ETH_LINK_SPEED_100G; + + return eth_speed_capa; +} + +/* Converts link speed provided in Mbps to NT specific definitions.*/ +nt_link_speed_t convert_link_speed(int link_speed_mbps) +{ + switch (link_speed_mbps) { + case 10: + return NT_LINK_SPEED_10M; + + case 100: + return NT_LINK_SPEED_100M; + + case 1000: + return NT_LINK_SPEED_1G; + + case 10000: + return NT_LINK_SPEED_10G; + + case 40000: + return NT_LINK_SPEED_40G; + + case 100000: + return NT_LINK_SPEED_100G; + + case 50000: + return NT_LINK_SPEED_50G; + + case 25000: + return NT_LINK_SPEED_25G; + + default: + return NT_LINK_SPEED_UNKNOWN; + } +} + +int nt_link_duplex_to_eth_duplex(enum nt_link_duplex_e nt_link_duplex) +{ + int eth_link_duplex = 0; + + switch (nt_link_duplex) { + case NT_LINK_DUPLEX_FULL: + eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX; + break; + + case NT_LINK_DUPLEX_HALF: + eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX; + break; + + case NT_LINK_DUPLEX_UNKNOWN: /* fall-through */ + default: + break; + } + + return eth_link_duplex; +} diff --git a/drivers/net/ntnic/ntutil/nt_util.h b/drivers/net/ntnic/ntutil/nt_util.h index 6dfd7428e1..ea91181a06 100644 --- a/drivers/net/ntnic/ntutil/nt_util.h +++ b/drivers/net/ntnic/ntutil/nt_util.h @@ -7,6 +7,7 @@ #define NTOSS_SYSTEM_NT_UTIL_H #include +#include "nt4ga_link.h" #ifndef ARRAY_SIZE #define ARRAY_SIZE(arr) RTE_DIM(arr) @@ -30,6 +31,11 @@ struct nt_dma_s { uint64_t size; }; +struct port_link_speed { + int port_id; + int link_speed; +}; + struct nt_dma_s *nt_dma_alloc(uint64_t size, uint64_t align, int numa); void nt_dma_free(struct nt_dma_s *vfio_addr); @@ -40,4 +46,9 @@ struct nt_util_vfio_impl { void nt_util_vfio_init(struct nt_util_vfio_impl *impl); +int nt_link_speed_to_eth_speed_num(enum nt_link_speed_e nt_link_speed); +uint32_t nt_link_speed_capa_to_eth_speed_capa(int nt_link_speed_capa); +nt_link_speed_t convert_link_speed(int link_speed_mbps); +int nt_link_duplex_to_eth_duplex(enum nt_link_duplex_e nt_link_duplex); + #endif /* NTOSS_SYSTEM_NT_UTIL_H */ From patchwork Wed Jul 17 13:33:03 2024 Content-Type: text/plain; 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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4P190MB1213 X-BESS-ID: 1721223208-305921-12777-14959-1 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.11.40 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVibmhkZAVgZQ0Mgw2cDA1DTVMM 0ixTg52cLA0sLSKCXZKMnYzDTVODFNqTYWAHLUZjBBAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan16-115.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org As the ntnic can support different speeds, an abstraction layer for 100G speed is needed. Signed-off-by: Serhii Iliushyk --- v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/adapter/nt4ga_adapter.c | 12 ++++- .../link_mgmt/link_100g/nt4ga_link_100g.c | 49 +++++++++++++++++++ drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/ntnic_mod_reg.c | 14 ++++++ drivers/net/ntnic/ntnic_mod_reg.h | 8 +++ 5 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c index be98938cc3..43bb566e33 100644 --- a/drivers/net/ntnic/adapter/nt4ga_adapter.c +++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c @@ -125,6 +125,7 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) { int i; + const struct link_ops_s *link_ops = NULL; assert(fpga_info->n_fpga_prod_id > 0); for (i = 0; i < NUM_ADAPTER_PORTS_MAX; i++) { @@ -135,8 +136,15 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) switch (fpga_info->n_fpga_prod_id) { /* NT200A01: 2x100G (Xilinx) */ case 9563: /* NT200A02 (Cap) */ - NT_LOG(ERR, NTNIC, "NT200A02 100G link module uninitialized\n"); - res = -1; + link_ops = get_100g_link_ops(); + + if (link_ops == NULL) { + NT_LOG(ERR, NTNIC, "NT200A02 100G link module uninitialized\n"); + res = -1; + break; + } + + res = link_ops->link_init(p_adapter_info, p_fpga); break; default: diff --git a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c new file mode 100644 index 0000000000..36c4bf031f --- /dev/null +++ b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c @@ -0,0 +1,49 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include /* memcmp, memset */ + +#include "nt_util.h" +#include "ntlog.h" +#include "ntnic_mod_reg.h" + +/* + * Initialize all ports + * The driver calls this function during initialization (of the driver). + */ +static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nthw_fpga_t *fpga) +{ + (void)fpga; + const int adapter_no = p_adapter_info->adapter_no; + int res = 0; + + NT_LOG(DBG, NTNIC, "%s: Initializing ports\n", p_adapter_info->mp_adapter_id_str); + + /* + * Initialize global variables + */ + assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); + + if (res == 0 && !p_adapter_info->nt4ga_link.variables_initialized) { + if (res == 0) { + p_adapter_info->nt4ga_link.speed_capa = NT_LINK_SPEED_100G; + p_adapter_info->nt4ga_link.variables_initialized = true; + } + } + + return res; +} + +/* + * Init 100G link ops variables + */ +static struct link_ops_s link_100g_ops = { + .link_init = nt4ga_link_100g_ports_init, +}; + +void link_100g_init(void) +{ + register_100g_link_ops(&link_100g_ops); +} diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 5619bbe0bd..18eab54a5b 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -22,6 +22,7 @@ includes = [ # all sources sources = files( 'adapter/nt4ga_adapter.c', + 'link_mgmt/link_100g/nt4ga_link_100g.c', 'link_mgmt/nt4ga_link.c', 'nthw/supported/nthw_fpga_9563_055_039_0000.c', 'nthw/supported/nthw_fpga_instances.c', diff --git a/drivers/net/ntnic/ntnic_mod_reg.c b/drivers/net/ntnic/ntnic_mod_reg.c index b79929c696..40e22c60fa 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.c +++ b/drivers/net/ntnic/ntnic_mod_reg.c @@ -5,6 +5,20 @@ #include "ntnic_mod_reg.h" +static struct link_ops_s *link_100g_ops; + +void register_100g_link_ops(struct link_ops_s *ops) +{ + link_100g_ops = ops; +} + +const struct link_ops_s *get_100g_link_ops(void) +{ + if (link_100g_ops == NULL) + link_100g_init(); + return link_100g_ops; +} + static const struct port_ops *port_ops; void register_port_ops(const struct port_ops *ops) diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index 8d1971a9c4..68629412b7 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -13,6 +13,14 @@ #include "nt4ga_adapter.h" #include "ntnic_nthw_fpga_rst_nt200a0x.h" +struct link_ops_s { + int (*link_init)(struct adapter_info_s *p_adapter_info, nthw_fpga_t *p_fpga); +}; + +void register_100g_link_ops(struct link_ops_s *ops); +const struct link_ops_s *get_100g_link_ops(void); +void link_100g_init(void); + struct port_ops { /* * port:s link mode From patchwork Wed Jul 17 13:33:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142474 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F05845635; 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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P190MB1153 X-BESS-ID: 1721223209-310426-12657-15020-1 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.51.169 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVsamRhZmQGYGUDQlzdIozdAg0d DYPDkVSCWaJyabJ5oaG5mkpRoZGyUr1cYCAA6Di8ZCAAAA X-BESS-Outbound-Spam-Score: 0.60 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan23-102.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.60 MARKETING_SUBJECT META: Subject contains popular marketing words X-BESS-Outbound-Spam-Status: SCORE=0.60 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND, MARKETING_SUBJECT X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org As the ntnic can support different port speeds, it also needs to support different NIMs (Network Interface Module). This commit add the generic NIM support for ntnic, such that the specific modules, such as QSFP28 can be added later. The communication with NIMs is in the form of I2C, so support for such a module is added as well. Additionally a thread is added to control the NIM stat machines. Signed-off-by: Serhii Iliushyk --- v6 * Remove unnecessary comments v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/adapter/nt4ga_adapter.c | 34 +++ drivers/net/ntnic/include/nt4ga_adapter.h | 3 + drivers/net/ntnic/include/nt4ga_link.h | 13 + drivers/net/ntnic/include/ntnic_nim.h | 61 +++++ .../link_mgmt/link_100g/nt4ga_link_100g.c | 214 ++++++++++++++++- drivers/net/ntnic/link_mgmt/nt4ga_link.c | 13 + drivers/net/ntnic/meson.build | 3 + drivers/net/ntnic/nim/i2c_nim.c | 224 ++++++++++++++++++ drivers/net/ntnic/nim/i2c_nim.h | 24 ++ drivers/net/ntnic/nim/nim_defines.h | 29 +++ .../net/ntnic/nthw/core/include/nthw_core.h | 1 + .../net/ntnic/nthw/core/include/nthw_i2cm.h | 50 ++++ drivers/net/ntnic/nthw/core/nthw_fpga.c | 3 + drivers/net/ntnic/nthw/core/nthw_i2cm.c | 192 +++++++++++++++ drivers/net/ntnic/nthw/nthw_drv.h | 1 + drivers/net/ntnic/ntnic_mod_reg.h | 7 + 16 files changed, 871 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ntnic/include/ntnic_nim.h create mode 100644 drivers/net/ntnic/nim/i2c_nim.c create mode 100644 drivers/net/ntnic/nim/i2c_nim.h create mode 100644 drivers/net/ntnic/nim/nim_defines.h create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_i2cm.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_i2cm.c diff --git a/drivers/net/ntnic/adapter/nt4ga_adapter.c b/drivers/net/ntnic/adapter/nt4ga_adapter.c index 43bb566e33..b704a256c6 100644 --- a/drivers/net/ntnic/adapter/nt4ga_adapter.c +++ b/drivers/net/ntnic/adapter/nt4ga_adapter.c @@ -9,6 +9,32 @@ #include "nthw_fpga.h" #include "ntnic_mod_reg.h" +/* + * Global variables shared by NT adapter types + */ +rte_thread_t monitor_tasks[NUM_ADAPTER_MAX]; +volatile int monitor_task_is_running[NUM_ADAPTER_MAX]; + +/* + * Signal-handler to stop all monitor threads + */ +static void stop_monitor_tasks(int signum) +{ + const size_t N = ARRAY_SIZE(monitor_task_is_running); + size_t i; + + /* Stop all monitor tasks */ + for (i = 0; i < N; i++) { + const int is_running = monitor_task_is_running[i]; + monitor_task_is_running[i] = 0; + + if (signum == -1 && is_running != 0) { + rte_thread_join(monitor_tasks[i], NULL); + memset(&monitor_tasks[i], 0, sizeof(monitor_tasks[0])); + } + } +} + static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE *pfh) { const char *const p_dev_name = p_adapter_info->p_dev_name; @@ -35,6 +61,9 @@ static int nt4ga_adapter_show_info(struct adapter_info_s *p_adapter_info, FILE * p_fpga_info->n_fpga_ver_id, p_fpga_info->n_fpga_rev_id, p_fpga_info->n_fpga_ident, p_fpga_info->n_fpga_build_time); fprintf(pfh, "%s: FpgaDebugMode=0x%x\n", p_adapter_id_str, p_fpga_info->n_fpga_debug_mode); + fprintf(pfh, "%s: Nims=%d PhyPorts=%d PhyQuads=%d RxPorts=%d TxPorts=%d\n", + p_adapter_id_str, p_fpga_info->n_nims, p_fpga_info->n_phy_ports, + p_fpga_info->n_phy_quads, p_fpga_info->n_rx_ports, p_fpga_info->n_tx_ports); fprintf(pfh, "%s: Hw=0x%02X_rev%d: %s\n", p_adapter_id_str, p_hw_info->hw_platform_id, p_fpga_info->nthw_hw_info.hw_id, p_fpga_info->nthw_hw_info.hw_plat_id_str); fprintf(pfh, "%s: MCU Details:\n", p_adapter_id_str); @@ -56,6 +85,7 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) * (nthw_fpga_init()) */ int n_phy_ports = -1; + int n_nim_ports = -1; int res = -1; nthw_fpga_t *p_fpga = NULL; @@ -122,6 +152,8 @@ static int nt4ga_adapter_init(struct adapter_info_s *p_adapter_info) assert(p_fpga); n_phy_ports = fpga_info->n_phy_ports; assert(n_phy_ports >= 1); + n_nim_ports = fpga_info->n_nims; + assert(n_nim_ports >= 1); { int i; @@ -171,6 +203,8 @@ static int nt4ga_adapter_deinit(struct adapter_info_s *p_adapter_info) int i; int res = -1; + stop_monitor_tasks(-1); + nthw_fpga_shutdown(&p_adapter_info->fpga_info); /* Rac rab reset flip flop */ diff --git a/drivers/net/ntnic/include/nt4ga_adapter.h b/drivers/net/ntnic/include/nt4ga_adapter.h index ed14936b38..4b204742a2 100644 --- a/drivers/net/ntnic/include/nt4ga_adapter.h +++ b/drivers/net/ntnic/include/nt4ga_adapter.h @@ -39,5 +39,8 @@ typedef struct adapter_info_s { int n_tx_host_buffers; } adapter_info_t; +extern rte_thread_t monitor_tasks[NUM_ADAPTER_MAX]; +extern volatile int monitor_task_is_running[NUM_ADAPTER_MAX]; + #endif /* _NT4GA_ADAPTER_H_ */ diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h index 849261ce3a..0851057f81 100644 --- a/drivers/net/ntnic/include/nt4ga_link.h +++ b/drivers/net/ntnic/include/nt4ga_link.h @@ -7,6 +7,7 @@ #define NT4GA_LINK_H_ #include "ntos_drv.h" +#include "ntnic_nim.h" enum nt_link_state_e { NT_LINK_STATE_UNKNOWN = 0, /* The link state has not been read yet */ @@ -41,6 +42,8 @@ enum nt_link_auto_neg_e { typedef struct link_state_s { bool link_disabled; + bool nim_present; + bool lh_nim_absent; bool link_up; enum nt_link_state_e link_state; enum nt_link_state_e link_state_latched; @@ -73,12 +76,22 @@ typedef struct port_action_s { uint32_t port_lpbk_mode; } port_action_t; +typedef struct adapter_100g_s { + nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX]; /* Should be the first field */ +} adapter_100g_t; + +typedef union adapter_var_s { + nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX]; /* First field in all the adapters type */ + adapter_100g_t var100g; +} adapter_var_u; + typedef struct nt4ga_link_s { link_state_t link_state[NUM_ADAPTER_PORTS_MAX]; link_info_t link_info[NUM_ADAPTER_PORTS_MAX]; port_action_t port_action[NUM_ADAPTER_PORTS_MAX]; uint32_t speed_capa; bool variables_initialized; + adapter_var_u u; } nt4ga_link_t; #endif /* NT4GA_LINK_H_ */ diff --git a/drivers/net/ntnic/include/ntnic_nim.h b/drivers/net/ntnic/include/ntnic_nim.h new file mode 100644 index 0000000000..fd4a915811 --- /dev/null +++ b/drivers/net/ntnic/include/ntnic_nim.h @@ -0,0 +1,61 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _NTNIC_NIM_H_ +#define _NTNIC_NIM_H_ + +#include + +typedef enum i2c_type { + I2C_HWIIC, +} i2c_type_e; + +enum nt_port_type_e { + NT_PORT_TYPE_NOT_AVAILABLE = 0, /* The NIM/port type is not available (unknown) */ + NT_PORT_TYPE_NOT_RECOGNISED, /* The NIM/port type not recognized */ +}; + +typedef enum nt_port_type_e nt_port_type_t, *nt_port_type_p; + +typedef struct nim_i2c_ctx { + union { + nthw_iic_t hwiic; /* depends on *Fpga_t, instance number, and cycle time */ + struct { + nthw_i2cm_t *p_nt_i2cm; + int mux_channel; + } hwagx; + }; + i2c_type_e type;/* 0 = hwiic (xilinx) - 1 = hwagx (agilex) */ + uint8_t instance; + uint8_t devaddr; + uint8_t regaddr; + uint8_t nim_id; + nt_port_type_t port_type; + + char vendor_name[17]; + char prod_no[17]; + char serial_no[17]; + char date[9]; + char rev[5]; + bool avg_pwr; + bool content_valid; + uint8_t pwr_level_req; + uint8_t pwr_level_cur; + uint16_t len_info[5]; + uint32_t speed_mask; /* Speeds supported by the NIM */ + int8_t lane_idx; + uint8_t lane_count; + uint32_t options; + bool tx_disable; + bool dmi_supp; + +} nim_i2c_ctx_t, *nim_i2c_ctx_p; + +struct nim_sensor_group { + struct nim_i2c_ctx *ctx; + struct nim_sensor_group *next; +}; + +#endif /* _NTNIC_NIM_H_ */ diff --git a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c index 36c4bf031f..4a8d28af9c 100644 --- a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c +++ b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c @@ -7,16 +7,202 @@ #include "nt_util.h" #include "ntlog.h" +#include "i2c_nim.h" #include "ntnic_mod_reg.h" +/* + * Initialize NIM, Code based on nt200e3_2_ptp.cpp: MyPort::createNim() + */ +static int _create_nim(adapter_info_t *drv, int port) +{ + int res = 0; + const uint8_t valid_nim_id = 17U; + nim_i2c_ctx_t *nim_ctx; + nt4ga_link_t *link_info = &drv->nt4ga_link; + + assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); + assert(link_info->variables_initialized); + + nim_ctx = &link_info->u.var100g.nim_ctx[port]; + + /* + * Wait a little after a module has been inserted before trying to access I2C + * data, otherwise the module will not respond correctly. + */ + nt_os_wait_usec(1000000); /* pause 1.0s */ + + res = construct_and_preinit_nim(nim_ctx); + + if (res) + return res; + + /* + * Does the driver support the NIM module type? + */ + if (nim_ctx->nim_id != valid_nim_id) { + NT_LOG(ERR, NTHW, "%s: The driver does not support the NIM module type %s\n", + drv->mp_port_id_str[port], nim_id_to_text(nim_ctx->nim_id)); + NT_LOG(DBG, NTHW, "%s: The driver supports the NIM module type %s\n", + drv->mp_port_id_str[port], nim_id_to_text(valid_nim_id)); + return -1; + } + + return res; +} + +/* + * Initialize one 100 Gbps port. + * The function shall not assume anything about the state of the adapter + * and/or port. + */ +static int _port_init(adapter_info_t *drv, int port) +{ + int res; + nt4ga_link_t *link_info = &drv->nt4ga_link; + + assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); + assert(link_info->variables_initialized); + + /* + * Phase 1. Pre-state machine (`port init` functions) + * 1.1) nt4ga_adapter::port_init() + */ + + /* No adapter set-up here, only state variables */ + + /* 1.2) MyPort::init() */ + link_info->link_info[port].link_speed = NT_LINK_SPEED_100G; + link_info->link_info[port].link_duplex = NT_LINK_DUPLEX_FULL; + link_info->link_info[port].link_auto_neg = NT_LINK_AUTONEG_OFF; + link_info->speed_capa |= NT_LINK_SPEED_100G; + + /* Phase 3. Link state machine steps */ + + /* 3.1) Create NIM, ::createNim() */ + res = _create_nim(drv, port); + + if (res) { + NT_LOG(WRN, NTNIC, "%s: NIM initialization failed\n", drv->mp_port_id_str[port]); + return res; + } + + NT_LOG(DBG, NTNIC, "%s: NIM initialized\n", drv->mp_port_id_str[port]); + + return res; +} + +/* + * State machine shared between kernel and userland + */ +static int _common_ptp_nim_state_machine(void *data) +{ + adapter_info_t *drv = (adapter_info_t *)data; + fpga_info_t *fpga_info = &drv->fpga_info; + nt4ga_link_t *link_info = &drv->nt4ga_link; + nthw_fpga_t *fpga = fpga_info->mp_fpga; + const int adapter_no = drv->adapter_no; + const int nb_ports = fpga_info->n_phy_ports; + uint32_t last_lpbk_mode[NUM_ADAPTER_PORTS_MAX]; + + link_state_t *link_state; + + if (!fpga) { + NT_LOG(ERR, NTNIC, "%s: fpga is NULL\n", drv->mp_adapter_id_str); + goto NT4GA_LINK_100G_MON_EXIT; + } + + assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); + link_state = link_info->link_state; + + monitor_task_is_running[adapter_no] = 1; + memset(last_lpbk_mode, 0, sizeof(last_lpbk_mode)); + + if (monitor_task_is_running[adapter_no]) + NT_LOG(DBG, NTNIC, "%s: link state machine running...\n", drv->mp_adapter_id_str); + + while (monitor_task_is_running[adapter_no]) { + int i; + + for (i = 0; i < nb_ports; i++) { + const bool is_port_disabled = link_info->port_action[i].port_disable; + const bool was_port_disabled = link_state[i].link_disabled; + const bool disable_port = is_port_disabled && !was_port_disabled; + const bool enable_port = !is_port_disabled && was_port_disabled; + + if (!monitor_task_is_running[adapter_no]) /* stop quickly */ + break; + + /* Has the administrative port state changed? */ + assert(!(disable_port && enable_port)); + + if (disable_port) { + memset(&link_state[i], 0, sizeof(link_state[i])); + link_info->link_info[i].link_speed = NT_LINK_SPEED_UNKNOWN; + link_state[i].link_disabled = true; + /* Turn off laser and LED, etc. */ + (void)_create_nim(drv, i); + NT_LOG(DBG, NTNIC, "%s: Port %i is disabled\n", + drv->mp_port_id_str[i], i); + continue; + } + + if (enable_port) { + link_state[i].link_disabled = false; + NT_LOG(DBG, NTNIC, "%s: Port %i is enabled\n", + drv->mp_port_id_str[i], i); + } + + if (is_port_disabled) + continue; + + if (link_info->port_action[i].port_lpbk_mode != last_lpbk_mode[i]) { + /* Loopback mode has changed. Do something */ + _port_init(drv, i); + + NT_LOG(INF, NTNIC, "%s: Loopback mode changed=%u\n", + drv->mp_port_id_str[i], + link_info->port_action[i].port_lpbk_mode); + + if (link_info->port_action[i].port_lpbk_mode == 1) + link_state[i].link_up = true; + + last_lpbk_mode[i] = link_info->port_action[i].port_lpbk_mode; + continue; + } + + } /* end-for */ + + if (monitor_task_is_running[adapter_no]) + nt_os_wait_usec(5 * 100000U); /* 5 x 0.1s = 0.5s */ + } + +NT4GA_LINK_100G_MON_EXIT: + + NT_LOG(DBG, NTNIC, "%s: Stopped NT4GA 100 Gbps link monitoring thread.\n", + drv->mp_adapter_id_str); + + return 0; +} + +/* + * Userland NIM state machine + */ +static uint32_t nt4ga_link_100g_mon(void *data) +{ + (void)_common_ptp_nim_state_machine(data); + + return 0; +} + /* * Initialize all ports * The driver calls this function during initialization (of the driver). */ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nthw_fpga_t *fpga) { - (void)fpga; + fpga_info_t *fpga_info = &p_adapter_info->fpga_info; const int adapter_no = p_adapter_info->adapter_no; + const int nb_ports = fpga_info->n_phy_ports; int res = 0; NT_LOG(DBG, NTNIC, "%s: Initializing ports\n", p_adapter_info->mp_adapter_id_str); @@ -27,12 +213,38 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); if (res == 0 && !p_adapter_info->nt4ga_link.variables_initialized) { + nim_i2c_ctx_t *nim_ctx = p_adapter_info->nt4ga_link.u.var100g.nim_ctx; + int i; + + for (i = 0; i < nb_ports; i++) { + /* 2 + adapter port number */ + const uint8_t instance = (uint8_t)(2U + i); + + res = nthw_iic_init(&nim_ctx[i].hwiic, fpga, instance, 8); + + if (res != 0) + break; + + nim_ctx[i].instance = instance; + nim_ctx[i].devaddr = 0x50; /* 0xA0 / 2 */ + nim_ctx[i].regaddr = 0U; + nim_ctx[i].type = I2C_HWIIC; + } + if (res == 0) { p_adapter_info->nt4ga_link.speed_capa = NT_LINK_SPEED_100G; p_adapter_info->nt4ga_link.variables_initialized = true; } } + /* Create state-machine thread */ + if (res == 0) { + if (!monitor_task_is_running[adapter_no]) { + res = rte_thread_create(&monitor_tasks[adapter_no], NULL, + nt4ga_link_100g_mon, p_adapter_info); + } + } + return res; } diff --git a/drivers/net/ntnic/link_mgmt/nt4ga_link.c b/drivers/net/ntnic/link_mgmt/nt4ga_link.c index ad23046aae..bc362776fc 100644 --- a/drivers/net/ntnic/link_mgmt/nt4ga_link.c +++ b/drivers/net/ntnic/link_mgmt/nt4ga_link.c @@ -12,6 +12,7 @@ #include "ntnic_mod_reg.h" #include "nt4ga_link.h" +#include "i2c_nim.h" /* * port: speed capabilities @@ -26,6 +27,16 @@ static uint32_t nt4ga_port_get_link_speed_capabilities(struct adapter_info_s *p, return nt_link_speed_capa; } +/* + * port: nim present + */ +static bool nt4ga_port_get_nim_present(struct adapter_info_s *p, int port) +{ + nt4ga_link_t *const p_link = &p->nt4ga_link; + const bool nim_present = p_link->link_state[port].nim_present; + return nim_present; +} + /* * port: link mode */ @@ -131,6 +142,8 @@ static uint32_t nt4ga_port_get_loopback_mode(struct adapter_info_s *p, int port) static const struct port_ops ops = { + .get_nim_present = nt4ga_port_get_nim_present, + /* * port:s link mode */ diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 18eab54a5b..5d044153e3 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -17,6 +17,7 @@ includes = [ include_directories('nthw'), include_directories('nthw/supported'), include_directories('nthw/model'), + include_directories('nim/'), ] # all sources @@ -24,6 +25,7 @@ sources = files( 'adapter/nt4ga_adapter.c', 'link_mgmt/link_100g/nt4ga_link_100g.c', 'link_mgmt/nt4ga_link.c', + 'nim/i2c_nim.c', 'nthw/supported/nthw_fpga_9563_055_039_0000.c', 'nthw/supported/nthw_fpga_instances.c', 'nthw/supported/nthw_fpga_mod_str_map.c', @@ -33,6 +35,7 @@ sources = files( 'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c', 'nthw/core/nthw_fpga.c', 'nthw/core/nthw_hif.c', + 'nthw/core/nthw_i2cm.c', 'nthw/core/nthw_iic.c', 'nthw/core/nthw_pcie3.c', 'nthw/core/nthw_sdc.c', diff --git a/drivers/net/ntnic/nim/i2c_nim.c b/drivers/net/ntnic/nim/i2c_nim.c new file mode 100644 index 0000000000..3281058822 --- /dev/null +++ b/drivers/net/ntnic/nim/i2c_nim.c @@ -0,0 +1,224 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include + +#include "nthw_drv.h" +#include "i2c_nim.h" +#include "ntlog.h" +#include "nt_util.h" +#include "ntnic_mod_reg.h" +#include "nim_defines.h" + +#define NIM_READ false +#define NIM_WRITE true +#define NIM_PAGE_SEL_REGISTER 127 +#define NIM_I2C_0XA0 0xA0 /* Basic I2C address */ + +static int nim_read_write_i2c_data(nim_i2c_ctx_p ctx, bool do_write, uint16_t lin_addr, + uint8_t i2c_addr, uint8_t a_reg_addr, uint8_t seq_cnt, + uint8_t *p_data) +{ + /* Divide i2c_addr by 2 because nthw_iic_read/writeData multiplies by 2 */ + const uint8_t i2c_devaddr = i2c_addr / 2U; + (void)lin_addr; /* Unused */ + + if (do_write) { + if (ctx->type == I2C_HWIIC) { + return nthw_iic_write_data(&ctx->hwiic, i2c_devaddr, a_reg_addr, seq_cnt, + p_data); + + } else { + return 0; + } + + } else if (ctx->type == I2C_HWIIC) { + return nthw_iic_read_data(&ctx->hwiic, i2c_devaddr, a_reg_addr, seq_cnt, p_data); + + } else { + return 0; + } +} + +/* + * ------------------------------------------------------------------------------ + * Selects a new page for page addressing. This is only relevant if the NIM + * supports this. Since page switching can take substantial time the current page + * select is read and subsequently only changed if necessary. + * Important: + * XFP Standard 8077, Ver 4.5, Page 61 states that: + * If the host attempts to write a table select value which is not supported in + * a particular module, the table select byte will revert to 01h. + * This can lead to some surprising result that some pages seems to be duplicated. + * ------------------------------------------------------------------------------ + */ + +static int nim_setup_page(nim_i2c_ctx_p ctx, uint8_t page_sel) +{ + uint8_t curr_page_sel; + + /* Read the current page select value */ + if (nim_read_write_i2c_data(ctx, NIM_READ, NIM_PAGE_SEL_REGISTER, NIM_I2C_0XA0, + NIM_PAGE_SEL_REGISTER, sizeof(curr_page_sel), + &curr_page_sel) != 0) { + return -1; + } + + /* Only write new page select value if necessary */ + if (page_sel != curr_page_sel) { + if (nim_read_write_i2c_data(ctx, NIM_WRITE, NIM_PAGE_SEL_REGISTER, NIM_I2C_0XA0, + NIM_PAGE_SEL_REGISTER, sizeof(page_sel), + &page_sel) != 0) { + return -1; + } + } + + return 0; +} + +static int nim_read_write_data_lin(nim_i2c_ctx_p ctx, bool m_page_addressing, uint16_t lin_addr, + uint16_t length, uint8_t *p_data, bool do_write) +{ + uint16_t i; + uint8_t a_reg_addr; /* The actual register address in I2C device */ + uint8_t i2c_addr; + int block_size = 128; /* Equal to size of MSA pages */ + int seq_cnt; + int max_seq_cnt = 1; + int multi_byte = 1; /* One byte per I2C register is default */ + + for (i = 0; i < length;) { + bool use_page_select = false; + + /* + * Find out how much can be read from the current block in case of + * single byte access + */ + if (multi_byte == 1) + max_seq_cnt = block_size - (lin_addr % block_size); + + if (m_page_addressing) { + if (lin_addr >= 128) { /* Only page setup above this address */ + use_page_select = true; + + /* Map to [128..255] of 0xA0 device */ + a_reg_addr = (uint8_t)(block_size + (lin_addr % block_size)); + + } else { + a_reg_addr = (uint8_t)lin_addr; + } + + i2c_addr = NIM_I2C_0XA0;/* Base I2C address */ + + } else if (lin_addr >= 256) { + /* Map to address [0..255] of 0xA2 device */ + a_reg_addr = (uint8_t)(lin_addr - 256); + i2c_addr = NIM_I2C_0XA2; + + } else { + a_reg_addr = (uint8_t)lin_addr; + i2c_addr = NIM_I2C_0XA0;/* Base I2C address */ + } + + /* Now actually do the reading/writing */ + seq_cnt = length - i; /* Number of remaining bytes */ + + if (seq_cnt > max_seq_cnt) + seq_cnt = max_seq_cnt; + + /* + * Read a number of bytes without explicitly specifying a new address. + * This can speed up I2C access since automatic incrementation of the + * I2C device internal address counter can be used. It also allows + * a HW implementation, that can deal with block access. + * Furthermore it also allows for access to data that must be accessed + * as 16bit words reading two bytes at each address eg PHYs. + */ + if (use_page_select) { + if (nim_setup_page(ctx, (uint8_t)((lin_addr / 128) - 1)) != 0) { + NT_LOG(ERR, NTNIC, + "Cannot set up page for linear address %u\n", lin_addr); + return -1; + } + } + + if (nim_read_write_i2c_data(ctx, do_write, lin_addr, i2c_addr, a_reg_addr, + (uint8_t)seq_cnt, p_data) != 0) { + NT_LOG(ERR, NTNIC, " Call to nim_read_write_i2c_data failed\n"); + return -1; + } + + p_data += seq_cnt; + i = (uint16_t)(i + seq_cnt); + lin_addr = (uint16_t)(lin_addr + (seq_cnt / multi_byte)); + } + + return 0; +} + +static int nim_read_id(nim_i2c_ctx_t *ctx) +{ + /* We are only reading the first byte so we don't care about pages here. */ + const bool USE_PAGE_ADDRESSING = false; + + if (nim_read_write_data_lin(ctx, USE_PAGE_ADDRESSING, NIM_IDENTIFIER_ADDR, + sizeof(ctx->nim_id), &ctx->nim_id, NIM_READ) != 0) { + return -1; + } + + return 0; +} + +static int i2c_nim_common_construct(nim_i2c_ctx_p ctx) +{ + ctx->nim_id = 0; + int res; + + if (ctx->type == I2C_HWIIC) + res = nim_read_id(ctx); + + else + res = -1; + + if (res) { + NT_LOG(ERR, PMD, "Can't read NIM id."); + return res; + } + + memset(ctx->vendor_name, 0, sizeof(ctx->vendor_name)); + memset(ctx->prod_no, 0, sizeof(ctx->prod_no)); + memset(ctx->serial_no, 0, sizeof(ctx->serial_no)); + memset(ctx->date, 0, sizeof(ctx->date)); + memset(ctx->rev, 0, sizeof(ctx->rev)); + + ctx->content_valid = false; + memset(ctx->len_info, 0, sizeof(ctx->len_info)); + ctx->pwr_level_req = 0; + ctx->pwr_level_cur = 0; + ctx->avg_pwr = false; + ctx->tx_disable = false; + ctx->lane_idx = -1; + ctx->lane_count = 1; + ctx->options = 0; + return 0; +} + +const char *nim_id_to_text(uint8_t nim_id) +{ + switch (nim_id) { + case 0x0: + return "UNKNOWN"; + + default: + return "ILLEGAL!"; + } +} + +int construct_and_preinit_nim(nim_i2c_ctx_p ctx) +{ + int res = i2c_nim_common_construct(ctx); + + return res; +} diff --git a/drivers/net/ntnic/nim/i2c_nim.h b/drivers/net/ntnic/nim/i2c_nim.h new file mode 100644 index 0000000000..e89ae47835 --- /dev/null +++ b/drivers/net/ntnic/nim/i2c_nim.h @@ -0,0 +1,24 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef I2C_NIM_H_ +#define I2C_NIM_H_ + +#include "ntnic_nim.h" + +/* + * Returns a type name such as "SFP/SFP+" for a given NIM type identifier, + * or the string "ILLEGAL!". + */ +const char *nim_id_to_text(uint8_t nim_id); + +/* + * This function tries to classify NIM based on it's ID and some register reads + * and collects information into ctx structure. The @extra parameter could contain + * the initialization argument for specific type of NIMS. + */ +int construct_and_preinit_nim(nim_i2c_ctx_p ctx); + +#endif /* I2C_NIM_H_ */ diff --git a/drivers/net/ntnic/nim/nim_defines.h b/drivers/net/ntnic/nim/nim_defines.h new file mode 100644 index 0000000000..9ba861bb4f --- /dev/null +++ b/drivers/net/ntnic/nim/nim_defines.h @@ -0,0 +1,29 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NIM_DEFINES_H_ +#define NIM_DEFINES_H_ + +#define NIM_IDENTIFIER_ADDR 0 /* 1 byte */ + +/* I2C addresses */ +#define NIM_I2C_0XA0 0xA0 /* Basic I2C address */ +#define NIM_I2C_0XA2 0xA2 /* Diagnostic monitoring */ + +typedef enum { + NIM_OPTION_TX_DISABLE, + /* Indicates that the module should be checked for the two next FEC types */ + NIM_OPTION_FEC, + NIM_OPTION_MEDIA_SIDE_FEC, + NIM_OPTION_HOST_SIDE_FEC, + NIM_OPTION_RX_ONLY +} nim_option_t; + +enum nt_nim_identifier_e { + NT_NIM_UNKNOWN = 0x00, /* Nim type is unknown */ +}; +typedef enum nt_nim_identifier_e nt_nim_identifier_t; + +#endif /* NIM_DEFINES_H_ */ diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index 5648bd8983..8d9d78b86d 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -15,6 +15,7 @@ #include "nthw_hif.h" #include "nthw_pcie3.h" #include "nthw_iic.h" +#include "nthw_i2cm.h" #include "nthw_sdc.h" diff --git a/drivers/net/ntnic/nthw/core/include/nthw_i2cm.h b/drivers/net/ntnic/nthw/core/include/nthw_i2cm.h new file mode 100644 index 0000000000..6e0ec4cf5e --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_i2cm.h @@ -0,0 +1,50 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef __NTHW_II2CM_H__ +#define __NTHW_II2CM_H__ + +#include "nthw_fpga_model.h" +#include "pthread.h" + +struct nt_i2cm { + nthw_fpga_t *mp_fpga; + + nthw_module_t *m_mod_i2cm; + + int mn_i2c_instance; + + nthw_register_t *mp_reg_prer_low; + nthw_field_t *mp_fld_prer_low_prer_low; + + nthw_register_t *mp_reg_prer_high; + nthw_field_t *mp_fld_prer_high_prer_high; + + nthw_register_t *mp_reg_ctrl; + nthw_field_t *mp_fld_ctrl_ien; + nthw_field_t *mp_fld_ctrl_en; + + nthw_register_t *mp_reg_data; + nthw_field_t *mp_fld_data_data; + + nthw_register_t *mp_reg_cmd_status; + nthw_field_t *mp_fld_cmd_status_cmd_status; + + nthw_register_t *mp_reg_select; + nthw_field_t *mp_fld_select_select; + + nthw_register_t *mp_reg_io_exp; + nthw_field_t *mp_fld_io_exp_rst; + nthw_field_t *mp_fld_io_exp_int_b; + + pthread_mutex_t i2cmmutex; +}; + +typedef struct nt_i2cm nthw_i2cm_t; + +int nthw_i2cm_read(nthw_i2cm_t *p, uint8_t dev_addr, uint8_t reg_addr, uint8_t *value); +int nthw_i2cm_write(nthw_i2cm_t *p, uint8_t dev_addr, uint8_t reg_addr, uint8_t value); + +#endif /* __NTHW_II2CM_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_fpga.c b/drivers/net/ntnic/nthw/core/nthw_fpga.c index 38169176a5..d70205e5e3 100644 --- a/drivers/net/ntnic/nthw/core/nthw_fpga.c +++ b/drivers/net/ntnic/nthw/core/nthw_fpga.c @@ -19,12 +19,14 @@ int nthw_fpga_get_param_info(struct fpga_info_s *p_fpga_info, nthw_fpga_t *p_fpg { mcu_info_t *p_mcu_info = &p_fpga_info->mcu_info; + const int n_nims = nthw_fpga_get_product_param(p_fpga, NT_NIMS, -1); const int n_phy_ports = nthw_fpga_get_product_param(p_fpga, NT_PHY_PORTS, -1); const int n_phy_quads = nthw_fpga_get_product_param(p_fpga, NT_PHY_QUADS, -1); const int n_rx_ports = nthw_fpga_get_product_param(p_fpga, NT_RX_PORTS, -1); const int n_tx_ports = nthw_fpga_get_product_param(p_fpga, NT_TX_PORTS, -1); const int n_vf_offset = nthw_fpga_get_product_param(p_fpga, NT_HIF_VF_OFFSET, 4); + p_fpga_info->n_nims = n_nims; p_fpga_info->n_phy_ports = n_phy_ports; p_fpga_info->n_phy_quads = n_phy_quads; p_fpga_info->n_rx_ports = n_rx_ports; @@ -236,6 +238,7 @@ int nthw_fpga_init(struct fpga_info_s *p_fpga_info) nthw_fpga_get_param_info(p_fpga_info, p_fpga); /* debug: report params */ + NT_LOG(DBG, NTHW, "%s: NT_NIMS=%d\n", p_adapter_id_str, p_fpga_info->n_nims); NT_LOG(DBG, NTHW, "%s: NT_PHY_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_ports); NT_LOG(DBG, NTHW, "%s: NT_PHY_QUADS=%d\n", p_adapter_id_str, p_fpga_info->n_phy_quads); NT_LOG(DBG, NTHW, "%s: NT_RX_PORTS=%d\n", p_adapter_id_str, p_fpga_info->n_rx_ports); diff --git a/drivers/net/ntnic/nthw/core/nthw_i2cm.c b/drivers/net/ntnic/nthw/core/nthw_i2cm.c new file mode 100644 index 0000000000..b5f8e299ff --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_i2cm.c @@ -0,0 +1,192 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_i2cm.h" + +#define NT_I2C_CMD_START 0x80 +#define NT_I2C_CMD_STOP 0x40 +#define NT_I2C_CMD_RD 0x20 +#define NT_I2C_CMD_WR 0x10 +#define NT_I2C_CMD_NACK 0x08 +#define NT_I2C_CMD_IRQ_ACK 0x01 + +#define NT_I2C_STATUS_NACK 0x80 +#define NT_I2C_STATUS_TIP 0x02 + +#define NT_I2C_TRANSMIT_WR 0x00 +#define NT_I2C_TRANSMIT_RD 0x01 + +#define NUM_RETRIES 50U +#define SLEEP_USECS 100U/* 0.1 ms */ + + +static bool nthw_i2cm_ready(nthw_i2cm_t *p, bool wait_for_ack) +{ + uint32_t flags = NT_I2C_STATUS_TIP | (wait_for_ack ? NT_I2C_STATUS_NACK : 0U); + + for (uint32_t i = 0U; i < NUM_RETRIES; i++) { + uint32_t status = nthw_field_get_updated(p->mp_fld_cmd_status_cmd_status); + uint32_t ready = (status & flags) == 0U; + /* MUST have a short break to avoid time-outs, even if ready == true */ + nt_os_wait_usec(SLEEP_USECS); + + if (ready) + return true; + } + + return false; +} + +static int nthw_i2cm_write_internal(nthw_i2cm_t *p, uint8_t value) +{ + /* Write data to data register */ + nthw_field_set_val_flush32(p->mp_fld_data_data, value); + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_WR | NT_I2C_CMD_IRQ_ACK); + + if (!nthw_i2cm_ready(p, true)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out writing data %u", __PRETTY_FUNCTION__, value); + return 1; + } + + /* Generate stop condition and clear interrupt */ + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + + if (!nthw_i2cm_ready(p, true)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out sending stop condition", __PRETTY_FUNCTION__); + return 1; + } + + return 0; +} + +static int nthw_i2cm_write_reg_addr_internal(nthw_i2cm_t *p, uint8_t dev_addr, uint8_t reg_addr, + bool send_stop) +{ + /* Write device address to data register */ + nthw_field_set_val_flush32(p->mp_fld_data_data, + (uint8_t)(dev_addr << 1 | NT_I2C_TRANSMIT_WR)); + + /* #Set start condition along with secondary I2C dev_addr */ + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_START | NT_I2C_CMD_WR | NT_I2C_CMD_IRQ_ACK); + + if (!nthw_i2cm_ready(p, true)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out writing device address %u, reg_addr=%u", + __PRETTY_FUNCTION__, dev_addr, reg_addr); + return 1; + } + + /* Writing I2C register address */ + nthw_field_set_val_flush32(p->mp_fld_data_data, reg_addr); + + if (send_stop) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_WR | NT_I2C_CMD_IRQ_ACK | NT_I2C_CMD_STOP); + + } else { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_WR | NT_I2C_CMD_IRQ_ACK); + } + + if (!nthw_i2cm_ready(p, true)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out writing register address %u", __PRETTY_FUNCTION__, + reg_addr); + return 1; + } + + return 0; +} + +static int nthw_i2cm_read_internal(nthw_i2cm_t *p, uint8_t dev_addr, uint8_t *value) +{ + /* Write I2C device address - with LSBit set to READ */ + + nthw_field_set_val_flush32(p->mp_fld_data_data, + (uint8_t)(dev_addr << 1 | NT_I2C_TRANSMIT_RD)); + /* #Send START condition along with secondary I2C dev_addr */ + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_START | NT_I2C_CMD_WR | NT_I2C_CMD_IRQ_ACK); + + if (!nthw_i2cm_ready(p, true)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out rewriting device address %u", __PRETTY_FUNCTION__, + dev_addr); + return 1; + } + + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_RD | NT_I2C_CMD_NACK | NT_I2C_CMD_IRQ_ACK); + + if (!nthw_i2cm_ready(p, false)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out during read operation", __PRETTY_FUNCTION__); + return 1; + } + + *value = (uint8_t)nthw_field_get_updated(p->mp_fld_data_data); + + /* Generate stop condition and clear interrupt */ + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + + if (!nthw_i2cm_ready(p, false)) { + nthw_field_set_val_flush32(p->mp_fld_cmd_status_cmd_status, + NT_I2C_CMD_STOP | NT_I2C_CMD_IRQ_ACK); + NT_LOG(ERR, NTHW, "%s: Time-out sending stop condition", __PRETTY_FUNCTION__); + return 1; + } + + return 0; +} + +int nthw_i2cm_read(nthw_i2cm_t *p, uint8_t dev_addr, uint8_t reg_addr, uint8_t *value) +{ + int status; + status = nthw_i2cm_write_reg_addr_internal(p, dev_addr, reg_addr, false); + + if (status != 0) + return status; + + status = nthw_i2cm_read_internal(p, dev_addr, value); + + if (status != 0) + return status; + + return 0; +} + +int nthw_i2cm_write(nthw_i2cm_t *p, uint8_t dev_addr, uint8_t reg_addr, uint8_t value) +{ + int status; + status = nthw_i2cm_write_reg_addr_internal(p, dev_addr, reg_addr, false); + + if (status != 0) + return status; + + status = nthw_i2cm_write_internal(p, value); + + if (status != 0) + return status; + + return 0; +} diff --git a/drivers/net/ntnic/nthw/nthw_drv.h b/drivers/net/ntnic/nthw/nthw_drv.h index 071618eb6e..de60ae171e 100644 --- a/drivers/net/ntnic/nthw/nthw_drv.h +++ b/drivers/net/ntnic/nthw/nthw_drv.h @@ -52,6 +52,7 @@ typedef struct fpga_info_s { int n_fpga_debug_mode; + int n_nims; int n_phy_ports; int n_phy_quads; int n_rx_ports; diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h index 68629412b7..3189b04f33 100644 --- a/drivers/net/ntnic/ntnic_mod_reg.h +++ b/drivers/net/ntnic/ntnic_mod_reg.h @@ -22,6 +22,8 @@ const struct link_ops_s *get_100g_link_ops(void); void link_100g_init(void); struct port_ops { + bool (*get_nim_present)(struct adapter_info_s *p, int port); + /* * port:s link mode */ @@ -60,6 +62,11 @@ struct port_ops { uint32_t (*get_link_speed_capabilities)(struct adapter_info_s *p, int port); + /* + * port: nim capabilities + */ + nim_i2c_ctx_t (*get_nim_capabilities)(struct adapter_info_s *p, int port); + /* * port: tx power */ From patchwork Wed Jul 17 13:33:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142475 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E0F745635; Wed, 17 Jul 2024 15:35:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B4CA042E44; Wed, 17 Jul 2024 15:33:49 +0200 (CEST) Received: from egress-ip11b.ess.de.barracuda.com (egress-ip11b.ess.de.barracuda.com [18.185.115.215]) by mails.dpdk.org (Postfix) with ESMTP id 9EAAE427C4 for ; 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Signed-off-by: Serhii Iliushyk --- drivers/net/ntnic/include/ntnic_nim.h | 10 + .../link_mgmt/link_100g/nt4ga_link_100g.c | 12 +- drivers/net/ntnic/nim/i2c_nim.c | 310 +++++++++++++++++- drivers/net/ntnic/nim/i2c_nim.h | 14 +- drivers/net/ntnic/nim/nim_defines.h | 3 + drivers/net/ntnic/nim/qsfp_registers.h | 43 +++ 6 files changed, 389 insertions(+), 3 deletions(-) create mode 100644 drivers/net/ntnic/nim/qsfp_registers.h diff --git a/drivers/net/ntnic/include/ntnic_nim.h b/drivers/net/ntnic/include/ntnic_nim.h index fd4a915811..216930af76 100644 --- a/drivers/net/ntnic/include/ntnic_nim.h +++ b/drivers/net/ntnic/include/ntnic_nim.h @@ -15,6 +15,8 @@ typedef enum i2c_type { enum nt_port_type_e { NT_PORT_TYPE_NOT_AVAILABLE = 0, /* The NIM/port type is not available (unknown) */ NT_PORT_TYPE_NOT_RECOGNISED, /* The NIM/port type not recognized */ + NT_PORT_TYPE_QSFP_PLUS_NOT_PRESENT, /* QSFP type but slot is empty */ + NT_PORT_TYPE_QSFP_PLUS, /* QSFP type */ }; typedef enum nt_port_type_e nt_port_type_t, *nt_port_type_p; @@ -51,6 +53,14 @@ typedef struct nim_i2c_ctx { bool tx_disable; bool dmi_supp; + union { + struct { + bool rx_only; + union { + } specific_u; + } qsfp; + + } specific_u; } nim_i2c_ctx_t, *nim_i2c_ctx_p; struct nim_sensor_group { diff --git a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c index 4a8d28af9c..69d0a5d24a 100644 --- a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c +++ b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c @@ -18,6 +18,7 @@ static int _create_nim(adapter_info_t *drv, int port) int res = 0; const uint8_t valid_nim_id = 17U; nim_i2c_ctx_t *nim_ctx; + sfp_nim_state_t nim; nt4ga_link_t *link_info = &drv->nt4ga_link; assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); @@ -31,11 +32,20 @@ static int _create_nim(adapter_info_t *drv, int port) */ nt_os_wait_usec(1000000); /* pause 1.0s */ - res = construct_and_preinit_nim(nim_ctx); + res = construct_and_preinit_nim(nim_ctx, NULL); if (res) return res; + res = nim_state_build(nim_ctx, &nim); + + if (res) + return res; + + NT_LOG(DBG, NTHW, "%s: NIM id = %u (%s), br = %u, vendor = '%s', pn = '%s', sn='%s'\n", + drv->mp_port_id_str[port], nim_ctx->nim_id, nim_id_to_text(nim_ctx->nim_id), nim.br, + nim_ctx->vendor_name, nim_ctx->prod_no, nim_ctx->serial_no); + /* * Does the driver support the NIM module type? */ diff --git a/drivers/net/ntnic/nim/i2c_nim.c b/drivers/net/ntnic/nim/i2c_nim.c index 3281058822..0071d452bb 100644 --- a/drivers/net/ntnic/nim/i2c_nim.c +++ b/drivers/net/ntnic/nim/i2c_nim.c @@ -10,6 +10,7 @@ #include "ntlog.h" #include "nt_util.h" #include "ntnic_mod_reg.h" +#include "qsfp_registers.h" #include "nim_defines.h" #define NIM_READ false @@ -17,6 +18,25 @@ #define NIM_PAGE_SEL_REGISTER 127 #define NIM_I2C_0XA0 0xA0 /* Basic I2C address */ + +static bool page_addressing(nt_nim_identifier_t id) +{ + switch (id) { + case NT_NIM_QSFP: + case NT_NIM_QSFP_PLUS: + return true; + + default: + NT_LOG(DBG, NTNIC, "Unknown NIM identifier %d\n", id); + return false; + } +} + +static nt_nim_identifier_t translate_nimid(const nim_i2c_ctx_t *ctx) +{ + return (nt_nim_identifier_t)ctx->nim_id; +} + static int nim_read_write_i2c_data(nim_i2c_ctx_p ctx, bool do_write, uint16_t lin_addr, uint8_t i2c_addr, uint8_t a_reg_addr, uint8_t seq_cnt, uint8_t *p_data) @@ -158,6 +178,13 @@ static int nim_read_write_data_lin(nim_i2c_ctx_p ctx, bool m_page_addressing, ui return 0; } +static int read_data_lin(nim_i2c_ctx_p ctx, uint16_t lin_addr, uint16_t length, void *data) +{ + /* Wrapper for using Mutex for QSFP TODO */ + return nim_read_write_data_lin(ctx, page_addressing(ctx->nim_id), lin_addr, length, data, + NIM_READ); +} + static int nim_read_id(nim_i2c_ctx_t *ctx) { /* We are only reading the first byte so we don't care about pages here. */ @@ -205,20 +232,301 @@ static int i2c_nim_common_construct(nim_i2c_ctx_p ctx) return 0; } +/* + * Read vendor information at a certain address. Any trailing whitespace is + * removed and a missing string termination in the NIM data is handled. + */ +static int nim_read_vendor_info(nim_i2c_ctx_p ctx, uint16_t addr, uint8_t max_len, char *p_data) +{ + const bool pg_addr = page_addressing(ctx->nim_id); + int i; + /* Subtract "1" from max_len that includes a terminating "0" */ + + if (nim_read_write_data_lin(ctx, pg_addr, addr, (uint8_t)(max_len - 1), (uint8_t *)p_data, + NIM_READ) != 0) { + return -1; + } + + /* Terminate at first found white space */ + for (i = 0; i < max_len - 1; i++) { + if (*p_data == ' ' || *p_data == '\n' || *p_data == '\t' || *p_data == '\v' || + *p_data == '\f' || *p_data == '\r') { + *p_data = '\0'; + return 0; + } + + p_data++; + } + + /* + * Add line termination as the very last character, if it was missing in the + * NIM data + */ + *p_data = '\0'; + return 0; +} + +static void qsfp_read_vendor_info(nim_i2c_ctx_t *ctx) +{ + nim_read_vendor_info(ctx, QSFP_VENDOR_NAME_LIN_ADDR, sizeof(ctx->vendor_name), + ctx->vendor_name); + nim_read_vendor_info(ctx, QSFP_VENDOR_PN_LIN_ADDR, sizeof(ctx->prod_no), ctx->prod_no); + nim_read_vendor_info(ctx, QSFP_VENDOR_SN_LIN_ADDR, sizeof(ctx->serial_no), ctx->serial_no); + nim_read_vendor_info(ctx, QSFP_VENDOR_DATE_LIN_ADDR, sizeof(ctx->date), ctx->date); + nim_read_vendor_info(ctx, QSFP_VENDOR_REV_LIN_ADDR, (uint8_t)(sizeof(ctx->rev) - 2), + ctx->rev); /*OBS Only two bytes*/ +} +static int qsfp_nim_state_build(nim_i2c_ctx_t *ctx, sfp_nim_state_t *state) +{ + int res = 0; /* unused due to no readings from HW */ + + assert(ctx && state); + assert(ctx->nim_id != NT_NIM_UNKNOWN && "Nim is not initialized"); + + (void)memset(state, 0, sizeof(*state)); + + switch (ctx->nim_id) { + case 12U: + state->br = 10U;/* QSFP: 4 x 1G = 4G */ + break; + + case 13U: + state->br = 103U; /* QSFP+: 4 x 10G = 40G */ + break; + + default: + NT_LOG(INF, NIM, "nim_id = %u is not an QSFP/QSFP+ module\n", ctx->nim_id); + res = -1; + } + + return res; +} + +int nim_state_build(nim_i2c_ctx_t *ctx, sfp_nim_state_t *state) +{ + return qsfp_nim_state_build(ctx, state); +} + const char *nim_id_to_text(uint8_t nim_id) { switch (nim_id) { case 0x0: return "UNKNOWN"; + case 0x0C: + return "QSFP"; + + case 0x0D: + return "QSFP+"; + default: return "ILLEGAL!"; } } -int construct_and_preinit_nim(nim_i2c_ctx_p ctx) +/* + * Disable laser for specific lane or all lanes + */ +int nim_qsfp_plus_nim_set_tx_laser_disable(nim_i2c_ctx_p ctx, bool disable, int lane_idx) +{ + uint8_t value; + uint8_t mask; + const bool pg_addr = page_addressing(ctx->nim_id); + + if (lane_idx < 0) /* If no lane is specified then all lanes */ + mask = QSFP_SOFT_TX_ALL_DISABLE_BITS; + + else + mask = (uint8_t)(1U << lane_idx); + + if (nim_read_write_data_lin(ctx, pg_addr, QSFP_CONTROL_STATUS_LIN_ADDR, sizeof(value), + &value, NIM_READ) != 0) { + return -1; + } + + if (disable) + value |= mask; + + else + value &= (uint8_t)(~mask); + + if (nim_read_write_data_lin(ctx, pg_addr, QSFP_CONTROL_STATUS_LIN_ADDR, sizeof(value), + &value, NIM_WRITE) != 0) { + return -1; + } + + return 0; +} + +/* + * Import length info in various units from NIM module data and convert to meters + */ +static void nim_import_len_info(nim_i2c_ctx_p ctx, uint8_t *p_nim_len_info, uint16_t *p_nim_units) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(ctx->len_info); i++) + if (*(p_nim_len_info + i) == 255) { + ctx->len_info[i] = 65535; + + } else { + uint32_t len = *(p_nim_len_info + i) * *(p_nim_units + i); + + if (len > 65535) + ctx->len_info[i] = 65535; + + else + ctx->len_info[i] = (uint16_t)len; + } +} + +static int qsfpplus_read_basic_data(nim_i2c_ctx_t *ctx) +{ + const bool pg_addr = page_addressing(ctx->nim_id); + uint8_t options; + uint8_t value; + uint8_t nim_len_info[5]; + uint16_t nim_units[5] = { 1000, 2, 1, 1, 1 }; /* QSFP MSA units in meters */ + const char *yes_no[2] = { "No", "Yes" }; + (void)yes_no; + NT_LOG(DBG, NTNIC, "Instance %d: NIM id: %s (%d)\n", ctx->instance, + nim_id_to_text(ctx->nim_id), ctx->nim_id); + + /* Read DMI options */ + if (nim_read_write_data_lin(ctx, pg_addr, QSFP_DMI_OPTION_LIN_ADDR, sizeof(options), + &options, NIM_READ) != 0) { + return -1; + } + + ctx->avg_pwr = options & QSFP_DMI_AVG_PWR_BIT; + NT_LOG(DBG, NTNIC, "Instance %d: NIM options: (DMI: Yes, AvgPwr: %s)\n", ctx->instance, + yes_no[ctx->avg_pwr]); + + qsfp_read_vendor_info(ctx); + NT_LOG(DBG, PMD, + "Instance %d: NIM info: (Vendor: %s, PN: %s, SN: %s, Date: %s, Rev: %s)\n", + ctx->instance, ctx->vendor_name, ctx->prod_no, ctx->serial_no, ctx->date, ctx->rev); + + if (nim_read_write_data_lin(ctx, pg_addr, QSFP_SUP_LEN_INFO_LIN_ADDR, sizeof(nim_len_info), + nim_len_info, NIM_READ) != 0) { + return -1; + } + + /* + * Returns supported length information in meters for various fibers as 5 indivi- + * dual values: [SM(9um), EBW(50um), MM(50um), MM(62.5um), Copper] + * If no length information is available for a certain entry, the returned value + * will be zero. This will be the case for SFP modules - EBW entry. + * If the MSBit is set the returned value in the lower 31 bits indicates that the + * supported length is greater than this. + */ + + nim_import_len_info(ctx, nim_len_info, nim_units); + + /* Read required power level */ + if (nim_read_write_data_lin(ctx, pg_addr, QSFP_EXTENDED_IDENTIFIER, sizeof(value), &value, + NIM_READ) != 0) { + return -1; + } + + /* + * Get power class according to SFF-8636 Rev 2.7, Table 6-16, Page 43: + * If power class >= 5 setHighPower must be called for the module to be fully + * functional + */ + if ((value & QSFP_POWER_CLASS_BITS_5_7) == 0) { + /* NIM in power class 1 - 4 */ + ctx->pwr_level_req = (uint8_t)(((value & QSFP_POWER_CLASS_BITS_1_4) >> 6) + 1); + + } else { + /* NIM in power class 5 - 7 */ + ctx->pwr_level_req = (uint8_t)((value & QSFP_POWER_CLASS_BITS_5_7) + 4); + } + + return 0; +} + +static void qsfpplus_find_port_params(nim_i2c_ctx_p ctx) +{ + uint8_t device_tech; + read_data_lin(ctx, QSFP_TRANSMITTER_TYPE_LIN_ADDR, sizeof(device_tech), &device_tech); + + switch (device_tech & 0xF0) { + case 0xA0: /* Copper cable unequalized */ + break; + + case 0xC0: /* Copper cable, near and far end limiting active equalizers */ + case 0xD0: /* Copper cable, far end limiting active equalizers */ + case 0xE0: /* Copper cable, near end limiting active equalizers */ + break; + + default:/* Optical */ + ctx->port_type = NT_PORT_TYPE_QSFP_PLUS; + break; + } +} + +static void qsfpplus_set_speed_mask(nim_i2c_ctx_p ctx) +{ + ctx->speed_mask = (ctx->lane_idx < 0) ? NT_LINK_SPEED_40G : (NT_LINK_SPEED_10G); +} + +static void qsfpplus_construct(nim_i2c_ctx_p ctx, int8_t lane_idx) +{ + assert(lane_idx < 4); + ctx->lane_idx = lane_idx; + ctx->lane_count = 4; +} + +static int qsfpplus_preinit(nim_i2c_ctx_p ctx, int8_t lane_idx) +{ + qsfpplus_construct(ctx, lane_idx); + int res = qsfpplus_read_basic_data(ctx); + + if (!res) { + qsfpplus_find_port_params(ctx); + + /* + * Read if TX_DISABLE has been implemented + * For passive optical modules this is required while it for copper and active + * optical modules is optional. Under all circumstances register 195.4 will + * indicate, if TX_DISABLE has been implemented in register 86.0-3 + */ + uint8_t value; + read_data_lin(ctx, QSFP_OPTION3_LIN_ADDR, sizeof(value), &value); + + ctx->tx_disable = (value & QSFP_OPTION3_TX_DISABLE_BIT) != 0; + + if (ctx->tx_disable) + ctx->options |= (1 << NIM_OPTION_TX_DISABLE); + + /* + * Previously - considering AFBR-89BRDZ - code tried to establish if a module was + * RxOnly by testing the state of the lasers after reset. Lasers were for this + * module default disabled. + * However that code did not work for GigaLight, GQS-MPO400-SR4C so it was + * decided that this option should not be detected automatically but from PN + */ + ctx->specific_u.qsfp.rx_only = (ctx->options & (1 << NIM_OPTION_RX_ONLY)) != 0; + qsfpplus_set_speed_mask(ctx); + } + + return res; +} + +int construct_and_preinit_nim(nim_i2c_ctx_p ctx, void *extra) { int res = i2c_nim_common_construct(ctx); + switch (translate_nimid(ctx)) { + case NT_NIM_QSFP_PLUS: + qsfpplus_preinit(ctx, extra ? *(int8_t *)extra : (int8_t)-1); + break; + + default: + res = 1; + NT_LOG(ERR, NTHW, "NIM type %s is not supported.\n", nim_id_to_text(ctx->nim_id)); + } + return res; } diff --git a/drivers/net/ntnic/nim/i2c_nim.h b/drivers/net/ntnic/nim/i2c_nim.h index e89ae47835..edb6dcf1b6 100644 --- a/drivers/net/ntnic/nim/i2c_nim.h +++ b/drivers/net/ntnic/nim/i2c_nim.h @@ -8,17 +8,29 @@ #include "ntnic_nim.h" +typedef struct sfp_nim_state { + uint8_t br; /* bit rate, units of 100 MBits/sec */ +} sfp_nim_state_t, *sfp_nim_state_p; + +/* + * Builds an nim state for the port implied by `ctx`, returns zero + * if successful, and non-zero otherwise. SFP and QSFP nims are supported + */ +int nim_state_build(nim_i2c_ctx_t *ctx, sfp_nim_state_t *state); + /* * Returns a type name such as "SFP/SFP+" for a given NIM type identifier, * or the string "ILLEGAL!". */ const char *nim_id_to_text(uint8_t nim_id); +int nim_qsfp_plus_nim_set_tx_laser_disable(nim_i2c_ctx_t *ctx, bool disable, int lane_idx); + /* * This function tries to classify NIM based on it's ID and some register reads * and collects information into ctx structure. The @extra parameter could contain * the initialization argument for specific type of NIMS. */ -int construct_and_preinit_nim(nim_i2c_ctx_p ctx); +int construct_and_preinit_nim(nim_i2c_ctx_p ctx, void *extra); #endif /* I2C_NIM_H_ */ diff --git a/drivers/net/ntnic/nim/nim_defines.h b/drivers/net/ntnic/nim/nim_defines.h index 9ba861bb4f..e5a033a3d4 100644 --- a/drivers/net/ntnic/nim/nim_defines.h +++ b/drivers/net/ntnic/nim/nim_defines.h @@ -7,6 +7,7 @@ #define NIM_DEFINES_H_ #define NIM_IDENTIFIER_ADDR 0 /* 1 byte */ +#define QSFP_EXTENDED_IDENTIFIER 129 /* I2C addresses */ #define NIM_I2C_0XA0 0xA0 /* Basic I2C address */ @@ -23,6 +24,8 @@ typedef enum { enum nt_nim_identifier_e { NT_NIM_UNKNOWN = 0x00, /* Nim type is unknown */ + NT_NIM_QSFP = 0x0C, /* Nim type = QSFP */ + NT_NIM_QSFP_PLUS = 0x0D,/* Nim type = QSFP+ */ }; typedef enum nt_nim_identifier_e nt_nim_identifier_t; diff --git a/drivers/net/ntnic/nim/qsfp_registers.h b/drivers/net/ntnic/nim/qsfp_registers.h new file mode 100644 index 0000000000..13172ce30b --- /dev/null +++ b/drivers/net/ntnic/nim/qsfp_registers.h @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef _QSFP_REGISTERS_H +#define _QSFP_REGISTERS_H + +/* + * QSFP Registers + */ +#define QSFP_INT_STATUS_RX_LOS_ADDR 3 +#define QSFP_TEMP_LIN_ADDR 22 +#define QSFP_VOLT_LIN_ADDR 26 +#define QSFP_RX_PWR_LIN_ADDR 34 /* uint16_t [0..3] */ +#define QSFP_TX_BIAS_LIN_ADDR 42/* uint16_t [0..3] */ +#define QSFP_TX_PWR_LIN_ADDR 50 /* uint16_t [0..3] */ + +#define QSFP_CONTROL_STATUS_LIN_ADDR 86 +#define QSFP_SOFT_TX_ALL_DISABLE_BITS 0x0F + +#define QSFP_POWER_CLASS_BITS_1_4 0xC0 +#define QSFP_POWER_CLASS_BITS_5_7 0x03 + +#define QSFP_SUP_LEN_INFO_LIN_ADDR 142 /* 5bytes */ +#define QSFP_TRANSMITTER_TYPE_LIN_ADDR 147 /* 1byte */ +#define QSFP_VENDOR_NAME_LIN_ADDR 148 /* 16bytes */ +#define QSFP_VENDOR_PN_LIN_ADDR 168 /* 16bytes */ +#define QSFP_VENDOR_SN_LIN_ADDR 196 /* 16bytes */ +#define QSFP_VENDOR_DATE_LIN_ADDR 212 /* 8bytes */ +#define QSFP_VENDOR_REV_LIN_ADDR 184 /* 2bytes */ + +#define QSFP_SPEC_COMPLIANCE_CODES_ADDR 131 /* 8 bytes */ +#define QSFP_EXT_SPEC_COMPLIANCE_CODES_ADDR 192 /* 1 byte */ + +#define QSFP_OPTION3_LIN_ADDR 195 +#define QSFP_OPTION3_TX_DISABLE_BIT (1 << 4) + +#define QSFP_DMI_OPTION_LIN_ADDR 220 +#define QSFP_DMI_AVG_PWR_BIT (1 << 3) + + +#endif /* _QSFP_REGISTERS_H */ From patchwork Wed Jul 17 13:33:06 2024 Content-Type: text/plain; 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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A799.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8P190MB2006 X-BESS-ID: 1721223210-310426-12657-15021-1 X-BESS-VER: 2019.1_20240716.1757 X-BESS-Apparent-Source-IP: 104.47.18.109 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVobGhubGQGYGUDQt2czE1NwkzT Il2SjN2NDQJMnS1CIlLdnA0MI0xTQpSak2FgBeleYvQgAAAA== X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.257687 [from cloudscan18-22.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Includes support for QSFP28 Signed-off-by: Serhii Iliushyk --- drivers/net/ntnic/include/ntnic_nim.h | 21 ++ drivers/net/ntnic/link_mgmt/nt4ga_link.c | 25 +++ drivers/net/ntnic/nim/i2c_nim.c | 267 ++++++++++++++++++++++- drivers/net/ntnic/nim/nim_defines.h | 1 + 4 files changed, 313 insertions(+), 1 deletion(-) diff --git a/drivers/net/ntnic/include/ntnic_nim.h b/drivers/net/ntnic/include/ntnic_nim.h index 216930af76..58daa8435f 100644 --- a/drivers/net/ntnic/include/ntnic_nim.h +++ b/drivers/net/ntnic/include/ntnic_nim.h @@ -17,6 +17,19 @@ enum nt_port_type_e { NT_PORT_TYPE_NOT_RECOGNISED, /* The NIM/port type not recognized */ NT_PORT_TYPE_QSFP_PLUS_NOT_PRESENT, /* QSFP type but slot is empty */ NT_PORT_TYPE_QSFP_PLUS, /* QSFP type */ + NT_PORT_TYPE_QSFP28_NOT_PRESENT,/* QSFP28 type but slot is empty */ + NT_PORT_TYPE_QSFP28, /* QSFP28 type */ + NT_PORT_TYPE_QSFP28_SR4,/* QSFP28-SR4 type */ + NT_PORT_TYPE_QSFP28_LR4,/* QSFP28-LR4 type */ + NT_PORT_TYPE_QSFP28_CR_CA_L, /* QSFP28-CR-CA-L type */ + NT_PORT_TYPE_QSFP28_CR_CA_S, /* QSFP28-CR-CA-S type */ + NT_PORT_TYPE_QSFP28_CR_CA_N, /* QSFP28-CR-CA-N type */ + /* QSFP28-FR type. Uses PAM4 modulation on one lane only */ + NT_PORT_TYPE_QSFP28_FR, + /* QSFP28-DR type. Uses PAM4 modulation on one lane only */ + NT_PORT_TYPE_QSFP28_DR, + /* QSFP28-LR type. Uses PAM4 modulation on one lane only */ + NT_PORT_TYPE_QSFP28_LR, }; typedef enum nt_port_type_e nt_port_type_t, *nt_port_type_p; @@ -56,7 +69,15 @@ typedef struct nim_i2c_ctx { union { struct { bool rx_only; + bool qsfp28; union { + struct { + uint8_t rev_compliance; + bool media_side_fec_ctrl; + bool host_side_fec_ctrl; + bool media_side_fec_ena; + bool host_side_fec_ena; + } qsfp28; } specific_u; } qsfp; diff --git a/drivers/net/ntnic/link_mgmt/nt4ga_link.c b/drivers/net/ntnic/link_mgmt/nt4ga_link.c index bc362776fc..4dc1c3d467 100644 --- a/drivers/net/ntnic/link_mgmt/nt4ga_link.c +++ b/drivers/net/ntnic/link_mgmt/nt4ga_link.c @@ -140,6 +140,26 @@ static uint32_t nt4ga_port_get_loopback_mode(struct adapter_info_s *p, int port) return p_link->port_action[port].port_lpbk_mode; } +/* + * port: tx power + */ +static int nt4ga_port_tx_power(struct adapter_info_s *p, int port, bool disable) +{ + nt4ga_link_t *link_info = &p->nt4ga_link; + + if (link_info->u.nim_ctx[port].port_type == NT_PORT_TYPE_QSFP28_SR4 || + link_info->u.nim_ctx[port].port_type == NT_PORT_TYPE_QSFP28 || + link_info->u.nim_ctx[port].port_type == NT_PORT_TYPE_QSFP28_LR4) { + nim_i2c_ctx_t *nim_ctx = &link_info->u.var100g.nim_ctx[port]; + + if (!nim_ctx->specific_u.qsfp.rx_only) { + if (nim_qsfp_plus_nim_set_tx_laser_disable(nim_ctx, disable, -1) != 0) + return 1; + } + } + + return 0; +} static const struct port_ops ops = { .get_nim_present = nt4ga_port_get_nim_present, @@ -181,6 +201,11 @@ static const struct port_ops ops = { .get_loopback_mode = nt4ga_port_get_loopback_mode, .get_link_speed_capabilities = nt4ga_port_get_link_speed_capabilities, + + /* + * port: tx power + */ + .tx_power = nt4ga_port_tx_power, }; void port_init(void) diff --git a/drivers/net/ntnic/nim/i2c_nim.c b/drivers/net/ntnic/nim/i2c_nim.c index 0071d452bb..e6e256b062 100644 --- a/drivers/net/ntnic/nim/i2c_nim.c +++ b/drivers/net/ntnic/nim/i2c_nim.c @@ -24,6 +24,7 @@ static bool page_addressing(nt_nim_identifier_t id) switch (id) { case NT_NIM_QSFP: case NT_NIM_QSFP_PLUS: + case NT_NIM_QSFP28: return true; default: @@ -185,6 +186,14 @@ static int read_data_lin(nim_i2c_ctx_p ctx, uint16_t lin_addr, uint16_t length, NIM_READ); } +/* Read and return a single byte */ +static uint8_t read_byte(nim_i2c_ctx_p ctx, uint16_t addr) +{ + uint8_t data; + read_data_lin(ctx, addr, sizeof(data), &data); + return data; +} + static int nim_read_id(nim_i2c_ctx_t *ctx) { /* We are only reading the first byte so we don't care about pages here. */ @@ -294,8 +303,12 @@ static int qsfp_nim_state_build(nim_i2c_ctx_t *ctx, sfp_nim_state_t *state) state->br = 103U; /* QSFP+: 4 x 10G = 40G */ break; + case 17U: + state->br = 255U; /* QSFP28: 4 x 25G = 100G */ + break; + default: - NT_LOG(INF, NIM, "nim_id = %u is not an QSFP/QSFP+ module\n", ctx->nim_id); + NT_LOG(INF, NIM, "nim_id = %u is not an QSFP/QSFP+/QSFP28 module\n", ctx->nim_id); res = -1; } @@ -319,6 +332,9 @@ const char *nim_id_to_text(uint8_t nim_id) case 0x0D: return "QSFP+"; + case 0x11: + return "QSFP28"; + default: return "ILLEGAL!"; } @@ -446,6 +462,132 @@ static int qsfpplus_read_basic_data(nim_i2c_ctx_t *ctx) return 0; } +static void qsfp28_find_port_params(nim_i2c_ctx_p ctx) +{ + uint8_t fiber_chan_speed; + + /* Table 6-17 SFF-8636 */ + read_data_lin(ctx, QSFP_SPEC_COMPLIANCE_CODES_ADDR, 1, &fiber_chan_speed); + + if (fiber_chan_speed & (1 << 7)) { + /* SFF-8024, Rev 4.7, Table 4-4 */ + uint8_t extended_specification_compliance_code = 0; + read_data_lin(ctx, QSFP_EXT_SPEC_COMPLIANCE_CODES_ADDR, 1, + &extended_specification_compliance_code); + + switch (extended_specification_compliance_code) { + case 0x02: + ctx->port_type = NT_PORT_TYPE_QSFP28_SR4; + break; + + case 0x03: + ctx->port_type = NT_PORT_TYPE_QSFP28_LR4; + break; + + case 0x0B: + ctx->port_type = NT_PORT_TYPE_QSFP28_CR_CA_L; + break; + + case 0x0C: + ctx->port_type = NT_PORT_TYPE_QSFP28_CR_CA_S; + break; + + case 0x0D: + ctx->port_type = NT_PORT_TYPE_QSFP28_CR_CA_N; + break; + + case 0x25: + ctx->port_type = NT_PORT_TYPE_QSFP28_DR; + break; + + case 0x26: + ctx->port_type = NT_PORT_TYPE_QSFP28_FR; + break; + + case 0x27: + ctx->port_type = NT_PORT_TYPE_QSFP28_LR; + break; + + default: + ctx->port_type = NT_PORT_TYPE_QSFP28; + } + + } else { + ctx->port_type = NT_PORT_TYPE_QSFP28; + } +} + +/* + * If true the user must actively select the desired rate. If false the module + * however can still support several rates without the user is required to select + * one of them. Supported rates must then be deduced from the product number. + * SFF-8636, Rev 2.10a: + * p40: 6.2.7 Rate Select + * p85: A.2 Rate Select + */ +static bool qsfp28_is_rate_selection_enabled(nim_i2c_ctx_p ctx) +{ + const uint8_t ext_rate_select_compl_reg_addr = 141; + const uint8_t options_reg_addr = 195; + const uint8_t enh_options_reg_addr = 221; + + uint8_t rate_select_ena = (read_byte(ctx, options_reg_addr) >> 5) & 0x01; /* bit: 5 */ + + if (rate_select_ena == 0) + return false; + + uint8_t rate_select_type = + (read_byte(ctx, enh_options_reg_addr) >> 2) & 0x03; /* bit 3..2 */ + + if (rate_select_type != 2) { + NT_LOG(DBG, PMD, "NIM has unhandled rate select type (%d)", rate_select_type); + return false; + } + + uint8_t ext_rate_select_ver = + read_byte(ctx, ext_rate_select_compl_reg_addr) & 0x03; /* bit 1..0 */ + + if (ext_rate_select_ver != 0x02) { + NT_LOG(DBG, PMD, "NIM has unhandled extended rate select version (%d)", + ext_rate_select_ver); + return false; + } + + return true; /* When true selectRate() can be used */ +} + +static void qsfp28_set_speed_mask(nim_i2c_ctx_p ctx) +{ + if (ctx->port_type == NT_PORT_TYPE_QSFP28_FR || ctx->port_type == NT_PORT_TYPE_QSFP28_DR || + ctx->port_type == NT_PORT_TYPE_QSFP28_LR) { + if (ctx->lane_idx < 0) + ctx->speed_mask = NT_LINK_SPEED_100G; + + else + /* PAM-4 modules can only run on all lanes together */ + ctx->speed_mask = 0; + + } else { + if (ctx->lane_idx < 0) + ctx->speed_mask = NT_LINK_SPEED_100G; + + else + ctx->speed_mask = NT_LINK_SPEED_25G; + + if (qsfp28_is_rate_selection_enabled(ctx)) { + /* + * It is assumed that if the module supports dual rates then the other rate + * is 10G per lane or 40G for all lanes. + */ + if (ctx->lane_idx < 0) + ctx->speed_mask |= NT_LINK_SPEED_40G; + + else + ctx->speed_mask = NT_LINK_SPEED_10G; + } + } +} + static void qsfpplus_find_port_params(nim_i2c_ctx_p ctx) { uint8_t device_tech; @@ -474,6 +616,7 @@ static void qsfpplus_set_speed_mask(nim_i2c_ctx_p ctx) static void qsfpplus_construct(nim_i2c_ctx_p ctx, int8_t lane_idx) { assert(lane_idx < 4); + ctx->specific_u.qsfp.qsfp28 = false; ctx->lane_idx = lane_idx; ctx->lane_count = 4; } @@ -514,6 +657,124 @@ static int qsfpplus_preinit(nim_i2c_ctx_p ctx, int8_t lane_idx) return res; } +static void qsfp28_wait_for_ready_after_reset(nim_i2c_ctx_p ctx) +{ + uint8_t data; + bool init_complete_flag_present = false; + + /* + * Revision compliance + * 7: SFF-8636 Rev 2.5, 2.6 and 2.7 + * 8: SFF-8636 Rev 2.8, 2.9 and 2.10 + */ + read_data_lin(ctx, 1, sizeof(ctx->specific_u.qsfp.specific_u.qsfp28.rev_compliance), + &ctx->specific_u.qsfp.specific_u.qsfp28.rev_compliance); + NT_LOG(DBG, NTHW, "NIM RevCompliance = %d", + ctx->specific_u.qsfp.specific_u.qsfp28.rev_compliance); + + /* Wait if lane_idx == -1 (all lanes are used) or lane_idx == 0 (the first lane) */ + if (ctx->lane_idx > 0) + return; + + if (ctx->specific_u.qsfp.specific_u.qsfp28.rev_compliance >= 7) { + /* Check if init complete flag is implemented */ + read_data_lin(ctx, 221, sizeof(data), &data); + init_complete_flag_present = (data & (1 << 4)) != 0; + } + + NT_LOG(DBG, NTHW, "NIM InitCompleteFlagPresent = %d", init_complete_flag_present); + + /* + * If the init complete flag is not present then wait 500ms that together with 500ms + * after reset (in the adapter code) should be enough to read data from upper pages + * that otherwise would not be ready. Especially BiDi modules AFBR-89BDDZ have been + * prone to this when trying to read sensor options using getQsfpOptionsFromData() + * Probably because access to the paged address space is required. + */ + if (!init_complete_flag_present) { + nt_os_wait_usec(500000); + return; + } + + /* Otherwise wait for the init complete flag to be set */ + int count = 0; + + while (true) { + if (count > 10) { /* 1 s timeout */ + NT_LOG(WRN, NTHW, "Timeout waiting for module ready"); + break; + } + + read_data_lin(ctx, 6, sizeof(data), &data); + + if (data & 0x01) { + NT_LOG(DBG, NTHW, "Module ready after %dms", count * 100); + break; + } + + nt_os_wait_usec(100000);/* 100 ms */ + count++; + } +} + +static void qsfp28_get_fec_options(nim_i2c_ctx_p ctx) +{ + const char *const nim_list[] = { + "AFBR-89BDDZ", /* Avago BiDi */ + "AFBR-89BRDZ", /* Avago BiDi, RxOnly */ + "FTLC4352RKPL", /* Finisar QSFP28-LR */ + "FTLC4352RHPL", /* Finisar QSFP28-DR */ + "FTLC4352RJPL", /* Finisar QSFP28-FR */ + "SFBR-89BDDZ-CS4", /* Foxconn, QSFP28 100G/40G BiDi */ + }; + + for (size_t i = 0; i < ARRAY_SIZE(nim_list); i++) { + if (ctx->prod_no == nim_list[i]) { + ctx->options |= (1 << NIM_OPTION_MEDIA_SIDE_FEC); + ctx->specific_u.qsfp.specific_u.qsfp28.media_side_fec_ena = true; + NT_LOG(DBG, NTHW, "Found FEC info via PN list"); + return; + } + } + + /* + * For modules not in the list find FEC info via registers + * Read if the module has controllable FEC + * SFF-8636, Rev 2.10a TABLE 6-28 Equalizer, Emphasis, Amplitude and Timing) + * (Page 03h, Bytes 224-229) + */ + uint8_t data; + uint16_t addr = 227 + 3 * 128; + read_data_lin(ctx, addr, sizeof(data), &data); + + /* Check if the module has FEC support that can be controlled */ + ctx->specific_u.qsfp.specific_u.qsfp28.media_side_fec_ctrl = (data & (1 << 6)) != 0; + ctx->specific_u.qsfp.specific_u.qsfp28.host_side_fec_ctrl = (data & (1 << 7)) != 0; + + if (ctx->specific_u.qsfp.specific_u.qsfp28.media_side_fec_ctrl) + ctx->options |= (1 << NIM_OPTION_MEDIA_SIDE_FEC); + + if (ctx->specific_u.qsfp.specific_u.qsfp28.host_side_fec_ctrl) + ctx->options |= (1 << NIM_OPTION_HOST_SIDE_FEC); +} + +static int qsfp28_preinit(nim_i2c_ctx_p ctx, int8_t lane_idx) +{ + int res = qsfpplus_preinit(ctx, lane_idx); + + if (!res) { + qsfp28_wait_for_ready_after_reset(ctx); + memset(&ctx->specific_u.qsfp.specific_u.qsfp28, 0, + sizeof(ctx->specific_u.qsfp.specific_u.qsfp28)); + ctx->specific_u.qsfp.qsfp28 = true; + qsfp28_find_port_params(ctx); + qsfp28_get_fec_options(ctx); + qsfp28_set_speed_mask(ctx); + } + + return res; +} + int construct_and_preinit_nim(nim_i2c_ctx_p ctx, void *extra) { int res = i2c_nim_common_construct(ctx); @@ -523,6 +784,10 @@ int construct_and_preinit_nim(nim_i2c_ctx_p ctx, void *extra) qsfpplus_preinit(ctx, extra ? *(int8_t *)extra : (int8_t)-1); break; + case NT_NIM_QSFP28: + qsfp28_preinit(ctx, extra ? *(int8_t *)extra : (int8_t)-1); + break; + default: res = 1; NT_LOG(ERR, NTHW, "NIM type %s is not supported.\n", nim_id_to_text(ctx->nim_id)); diff --git a/drivers/net/ntnic/nim/nim_defines.h b/drivers/net/ntnic/nim/nim_defines.h index e5a033a3d4..8e17b263c5 100644 --- a/drivers/net/ntnic/nim/nim_defines.h +++ b/drivers/net/ntnic/nim/nim_defines.h @@ -26,6 +26,7 @@ enum nt_nim_identifier_e { NT_NIM_UNKNOWN = 0x00, /* Nim type is unknown */ NT_NIM_QSFP = 0x0C, /* Nim type = QSFP */ NT_NIM_QSFP_PLUS = 0x0D,/* Nim type = QSFP+ */ + NT_NIM_QSFP28 = 0x11, /* Nim type = QSFP28 */ }; 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After this commit the NIMs supported by ntnic is able to start up and be controlled fully by the adapter. Signed-off-by: Serhii Iliushyk --- v5 * Fix Typo/Spelling v10 * Use 8 spaces as indentation in meson --- drivers/net/ntnic/include/nt4ga_link.h | 1 + .../link_mgmt/link_100g/nt4ga_link_100g.c | 71 ++++++++- drivers/net/ntnic/meson.build | 1 + .../net/ntnic/nthw/core/include/nthw_core.h | 1 + .../ntnic/nthw/core/include/nthw_gpio_phy.h | 48 ++++++ drivers/net/ntnic/nthw/core/nthw_gpio_phy.c | 145 ++++++++++++++++++ 6 files changed, 263 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_gpio_phy.c diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h index 0851057f81..5a16afea2a 100644 --- a/drivers/net/ntnic/include/nt4ga_link.h +++ b/drivers/net/ntnic/include/nt4ga_link.h @@ -78,6 +78,7 @@ typedef struct port_action_s { typedef struct adapter_100g_s { nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX]; /* Should be the first field */ + nthw_gpio_phy_t gpio_phy[NUM_ADAPTER_PORTS_MAX]; } adapter_100g_t; typedef union adapter_var_s { diff --git a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c index 69d0a5d24a..ed0b89d417 100644 --- a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c +++ b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c @@ -10,13 +10,24 @@ #include "i2c_nim.h" #include "ntnic_mod_reg.h" +/* + * Check whether a NIM module is present + */ +static bool _nim_is_present(nthw_gpio_phy_t *gpio_phy, uint8_t if_no) +{ + assert(if_no < NUM_ADAPTER_PORTS_MAX); + + return nthw_gpio_phy_is_module_present(gpio_phy, if_no); +} + /* * Initialize NIM, Code based on nt200e3_2_ptp.cpp: MyPort::createNim() */ -static int _create_nim(adapter_info_t *drv, int port) +static int _create_nim(adapter_info_t *drv, int port, bool enable) { int res = 0; const uint8_t valid_nim_id = 17U; + nthw_gpio_phy_t *gpio_phy; nim_i2c_ctx_t *nim_ctx; sfp_nim_state_t nim; nt4ga_link_t *link_info = &drv->nt4ga_link; @@ -24,14 +35,43 @@ static int _create_nim(adapter_info_t *drv, int port) assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); assert(link_info->variables_initialized); + gpio_phy = &link_info->u.var100g.gpio_phy[port]; nim_ctx = &link_info->u.var100g.nim_ctx[port]; + /* + * Check NIM is present before doing GPIO PHY reset. + */ + if (!_nim_is_present(gpio_phy, (uint8_t)port)) { + NT_LOG(INF, NTNIC, "%s: NIM module is absent\n", drv->mp_port_id_str[port]); + return 0; + } + + /* + * Perform PHY reset. + */ + NT_LOG(DBG, NTNIC, "%s: Performing NIM reset\n", drv->mp_port_id_str[port]); + nthw_gpio_phy_set_reset(gpio_phy, (uint8_t)port, true); + nt_os_wait_usec(100000);/* pause 0.1s */ + nthw_gpio_phy_set_reset(gpio_phy, (uint8_t)port, false); + /* * Wait a little after a module has been inserted before trying to access I2C * data, otherwise the module will not respond correctly. */ nt_os_wait_usec(1000000); /* pause 1.0s */ + if (!_nim_is_present(gpio_phy, (uint8_t)port)) { + NT_LOG(DBG, NTNIC, "%s: NIM module is no longer absent!\n", + drv->mp_port_id_str[port]); + return -1; + } + + if (!_nim_is_present(gpio_phy, (uint8_t)port)) { + NT_LOG(DBG, NTNIC, "%s: NIM module is no longer absent!\n", + drv->mp_port_id_str[port]); + return -1; + } + res = construct_and_preinit_nim(nim_ctx, NULL); if (res) @@ -57,6 +97,15 @@ static int _create_nim(adapter_info_t *drv, int port) return -1; } + if (enable) { + NT_LOG(DBG, NTNIC, "%s: De-asserting low power\n", drv->mp_port_id_str[port]); + nthw_gpio_phy_set_low_power(gpio_phy, (uint8_t)port, false); + + } else { + NT_LOG(DBG, NTNIC, "%s: Asserting low power\n", drv->mp_port_id_str[port]); + nthw_gpio_phy_set_low_power(gpio_phy, (uint8_t)port, true); + } + return res; } @@ -89,7 +138,7 @@ static int _port_init(adapter_info_t *drv, int port) /* Phase 3. Link state machine steps */ /* 3.1) Create NIM, ::createNim() */ - res = _create_nim(drv, port); + res = _create_nim(drv, port, true); if (res) { NT_LOG(WRN, NTNIC, "%s: NIM initialization failed\n", drv->mp_port_id_str[port]); @@ -115,6 +164,7 @@ static int _common_ptp_nim_state_machine(void *data) uint32_t last_lpbk_mode[NUM_ADAPTER_PORTS_MAX]; link_state_t *link_state; + nthw_gpio_phy_t *gpio_phy; if (!fpga) { NT_LOG(ERR, NTNIC, "%s: fpga is NULL\n", drv->mp_adapter_id_str); @@ -123,6 +173,7 @@ static int _common_ptp_nim_state_machine(void *data) assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); link_state = link_info->link_state; + gpio_phy = link_info->u.var100g.gpio_phy; monitor_task_is_running[adapter_no] = 1; memset(last_lpbk_mode, 0, sizeof(last_lpbk_mode)); @@ -150,7 +201,7 @@ static int _common_ptp_nim_state_machine(void *data) link_info->link_info[i].link_speed = NT_LINK_SPEED_UNKNOWN; link_state[i].link_disabled = true; /* Turn off laser and LED, etc. */ - (void)_create_nim(drv, i); + (void)_create_nim(drv, i, false); NT_LOG(DBG, NTNIC, "%s: Port %i is disabled\n", drv->mp_port_id_str[i], i); continue; @@ -167,7 +218,13 @@ static int _common_ptp_nim_state_machine(void *data) if (link_info->port_action[i].port_lpbk_mode != last_lpbk_mode[i]) { /* Loopback mode has changed. Do something */ - _port_init(drv, i); + if (!_nim_is_present(&gpio_phy[i], (uint8_t)i)) { + /* + * If there is no Nim present, we need to initialize the + * port anyway + */ + _port_init(drv, i); + } NT_LOG(INF, NTNIC, "%s: Loopback mode changed=%u\n", drv->mp_port_id_str[i], @@ -224,6 +281,7 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth if (res == 0 && !p_adapter_info->nt4ga_link.variables_initialized) { nim_i2c_ctx_t *nim_ctx = p_adapter_info->nt4ga_link.u.var100g.nim_ctx; + nthw_gpio_phy_t *gpio_phy = p_adapter_info->nt4ga_link.u.var100g.gpio_phy; int i; for (i = 0; i < nb_ports; i++) { @@ -239,6 +297,11 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth nim_ctx[i].devaddr = 0x50; /* 0xA0 / 2 */ nim_ctx[i].regaddr = 0U; nim_ctx[i].type = I2C_HWIIC; + + res = nthw_gpio_phy_init(&gpio_phy[i], fpga, 0 /* Only one instance */); + + if (res != 0) + break; } if (res == 0) { diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 5d044153e3..6dd972cf7d 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -34,6 +34,7 @@ sources = files( 'nthw/core/nt200a0x/reset/nthw_fpga_rst9563.c', 'nthw/core/nt200a0x/reset/nthw_fpga_rst_nt200a0x.c', 'nthw/core/nthw_fpga.c', + 'nthw/core/nthw_gpio_phy.c', 'nthw/core/nthw_hif.c', 'nthw/core/nthw_i2cm.c', 'nthw/core/nthw_iic.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index 8d9d78b86d..5cce56e13f 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -17,6 +17,7 @@ #include "nthw_iic.h" #include "nthw_i2cm.h" +#include "nthw_gpio_phy.h" #include "nthw_sdc.h" #include "nthw_si5340.h" diff --git a/drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h b/drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h new file mode 100644 index 0000000000..d4641cdb5d --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_gpio_phy.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTHW_GPIO_PHY_H_ +#define NTHW_GPIO_PHY_H_ + +#define GPIO_PHY_INTERFACES (2) + +typedef struct { + nthw_field_t *cfg_fld_lp_mode; /* Cfg Low Power Mode */ + nthw_field_t *cfg_int; /* Cfg Port Interrupt */ + nthw_field_t *cfg_reset;/* Cfg Reset */ + nthw_field_t *cfg_mod_prs; /* Cfg Module Present */ + nthw_field_t *cfg_pll_int; /* Cfg PLL Interrupt */ + nthw_field_t *cfg_port_rxlos; /* Emulate Cfg Port RXLOS */ + + nthw_field_t *gpio_fld_lp_mode; /* Gpio Low Power Mode */ + nthw_field_t *gpio_int; /* Gpio Port Interrupt */ + nthw_field_t *gpio_reset; /* Gpio Reset */ + nthw_field_t *gpio_mod_prs; /* Gpio Module Present */ + nthw_field_t *gpio_pll_int; /* Gpio PLL Interrupt */ + nthw_field_t *gpio_port_rxlos; /* Emulate Gpio Port RXLOS */ +} gpio_phy_fields_t; + +struct nthw_gpio_phy { + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_gpio_phy; + int mn_instance; + + /* Registers */ + nthw_register_t *mp_reg_config; + nthw_register_t *mp_reg_gpio; + + /* Fields */ + gpio_phy_fields_t mpa_fields[GPIO_PHY_INTERFACES]; +}; + +typedef struct nthw_gpio_phy nthw_gpio_phy_t; + +int nthw_gpio_phy_init(nthw_gpio_phy_t *p, nthw_fpga_t *p_fpga, int n_instance); + +bool nthw_gpio_phy_is_module_present(nthw_gpio_phy_t *p, uint8_t if_no); +void nthw_gpio_phy_set_low_power(nthw_gpio_phy_t *p, uint8_t if_no, bool enable); +void nthw_gpio_phy_set_reset(nthw_gpio_phy_t *p, uint8_t if_no, bool enable); + +#endif /* NTHW_GPIO_PHY_H_ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_gpio_phy.c b/drivers/net/ntnic/nthw/core/nthw_gpio_phy.c new file mode 100644 index 0000000000..754a8ca5a4 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_gpio_phy.c @@ -0,0 +1,145 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "ntlog.h" +#include "nt_util.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_gpio_phy.h" + +int nthw_gpio_phy_init(nthw_gpio_phy_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + nthw_module_t *p_mod = nthw_fpga_query_module(p_fpga, MOD_GPIO_PHY, n_instance); + + if (p == NULL) + return p_mod == NULL ? -1 : 0; + + if (p_mod == NULL) { + NT_LOG(ERR, NTHW, "%s: GPIO_PHY %d: no such instance\n", + p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_gpio_phy = p_mod; + + /* Registers */ + p->mp_reg_config = nthw_module_get_register(p->mp_mod_gpio_phy, GPIO_PHY_CFG); + p->mp_reg_gpio = nthw_module_get_register(p->mp_mod_gpio_phy, GPIO_PHY_GPIO); + + /* PORT-0, config fields */ + p->mpa_fields[0].cfg_fld_lp_mode = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_LPMODE); + p->mpa_fields[0].cfg_int = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_INT_B); + p->mpa_fields[0].cfg_reset = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_RESET_B); + p->mpa_fields[0].cfg_mod_prs = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_MODPRS_B); + + /* PORT-0, Non-mandatory fields (query_field) */ + p->mpa_fields[0].cfg_pll_int = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_PORT0_PLL_INTR); + p->mpa_fields[0].cfg_port_rxlos = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_E_PORT0_RXLOS); + + /* PORT-1, config fields */ + p->mpa_fields[1].cfg_fld_lp_mode = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_LPMODE); + p->mpa_fields[1].cfg_int = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_INT_B); + p->mpa_fields[1].cfg_reset = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_RESET_B); + p->mpa_fields[1].cfg_mod_prs = + nthw_register_get_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_MODPRS_B); + + /* PORT-1, Non-mandatory fields (query_field) */ + p->mpa_fields[1].cfg_pll_int = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_PORT1_PLL_INTR); + p->mpa_fields[1].cfg_port_rxlos = + nthw_register_query_field(p->mp_reg_config, GPIO_PHY_CFG_E_PORT1_RXLOS); + + /* PORT-0, gpio fields */ + p->mpa_fields[0].gpio_fld_lp_mode = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_LPMODE); + p->mpa_fields[0].gpio_int = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_INT_B); + p->mpa_fields[0].gpio_reset = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_RESET_B); + p->mpa_fields[0].gpio_mod_prs = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_MODPRS_B); + + /* PORT-0, Non-mandatory fields (query_field) */ + p->mpa_fields[0].gpio_pll_int = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT0_PLL_INTR); + p->mpa_fields[0].gpio_port_rxlos = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_E_PORT0_RXLOS); + + /* PORT-1, gpio fields */ + p->mpa_fields[1].gpio_fld_lp_mode = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_LPMODE); + p->mpa_fields[1].gpio_int = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_INT_B); + p->mpa_fields[1].gpio_reset = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_RESET_B); + p->mpa_fields[1].gpio_mod_prs = + nthw_register_get_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_MODPRS_B); + + /* PORT-1, Non-mandatory fields (query_field) */ + p->mpa_fields[1].gpio_pll_int = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_PORT1_PLL_INTR); + p->mpa_fields[1].gpio_port_rxlos = + nthw_register_query_field(p->mp_reg_gpio, GPIO_PHY_GPIO_E_PORT1_RXLOS); + + nthw_register_update(p->mp_reg_config); + + return 0; +} + +bool nthw_gpio_phy_is_module_present(nthw_gpio_phy_t *p, uint8_t if_no) +{ + if (if_no >= ARRAY_SIZE(p->mpa_fields)) { + assert(false); + return false; + } + + /* NOTE: This is a negated GPIO PIN "MODPRS_B" */ + return nthw_field_get_updated(p->mpa_fields[if_no].gpio_mod_prs) == 0U ? true : false; +} + +void nthw_gpio_phy_set_low_power(nthw_gpio_phy_t *p, uint8_t if_no, bool enable) +{ + if (if_no >= ARRAY_SIZE(p->mpa_fields)) { + assert(false); + return; + } + + if (enable) + nthw_field_set_flush(p->mpa_fields[if_no].gpio_fld_lp_mode); + + else + nthw_field_clr_flush(p->mpa_fields[if_no].gpio_fld_lp_mode); + + nthw_field_clr_flush(p->mpa_fields[if_no].cfg_fld_lp_mode); /* enable output */ +} + +void nthw_gpio_phy_set_reset(nthw_gpio_phy_t *p, uint8_t if_no, bool enable) +{ + if (if_no >= ARRAY_SIZE(p->mpa_fields)) { + assert(false); + return; + } + + if (enable) + nthw_field_clr_flush(p->mpa_fields[if_no].gpio_reset); + + else + nthw_field_set_flush(p->mpa_fields[if_no].gpio_reset); + + nthw_field_clr_flush(p->mpa_fields[if_no].cfg_reset); /* enable output */ +} From patchwork Wed Jul 17 13:33:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serhii Iliushyk X-Patchwork-Id: 142477 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2226445635; Wed, 17 Jul 2024 15:36:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4C5BC42E02; Wed, 17 Jul 2024 15:33:52 +0200 (CEST) Received: from egress-ip11b.ess.de.barracuda.com (egress-ip11b.ess.de.barracuda.com [18.185.115.215]) by mails.dpdk.org (Postfix) with ESMTP id CA8D1427E7 for ; Wed, 17 Jul 2024 15:33:37 +0200 (CEST) Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05lp2107.outbound.protection.outlook.com [104.47.18.107]) by mx-outbound23-33.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); 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This takes the form of the module MAC PCS (Media Access Control Physical Coding Sublayer). The functionality is used by the 100G link functionality to establish link. Signed-off-by: Serhii Iliushyk --- v10 * Remove GTY_RX_BUF_STAT initialization --- drivers/net/ntnic/include/nt4ga_link.h | 1 + .../link_mgmt/link_100g/nt4ga_link_100g.c | 393 +++++++- drivers/net/ntnic/meson.build | 1 + .../net/ntnic/nthw/core/include/nthw_core.h | 1 + .../ntnic/nthw/core/include/nthw_mac_pcs.h | 250 +++++ drivers/net/ntnic/nthw/core/nthw_mac_pcs.c | 864 ++++++++++++++++++ 6 files changed, 1508 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ntnic/nthw/core/include/nthw_mac_pcs.h create mode 100644 drivers/net/ntnic/nthw/core/nthw_mac_pcs.c diff --git a/drivers/net/ntnic/include/nt4ga_link.h b/drivers/net/ntnic/include/nt4ga_link.h index 5a16afea2a..8366484830 100644 --- a/drivers/net/ntnic/include/nt4ga_link.h +++ b/drivers/net/ntnic/include/nt4ga_link.h @@ -78,6 +78,7 @@ typedef struct port_action_s { typedef struct adapter_100g_s { nim_i2c_ctx_t nim_ctx[NUM_ADAPTER_PORTS_MAX]; /* Should be the first field */ + nthw_mac_pcs_t mac_pcs100g[NUM_ADAPTER_PORTS_MAX]; nthw_gpio_phy_t gpio_phy[NUM_ADAPTER_PORTS_MAX]; } adapter_100g_t; diff --git a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c index ed0b89d417..8f0afa1f60 100644 --- a/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c +++ b/drivers/net/ntnic/link_mgmt/link_100g/nt4ga_link_100g.c @@ -10,6 +10,168 @@ #include "i2c_nim.h" #include "ntnic_mod_reg.h" +/* + * Swap tx/rx polarity + */ +static int _swap_tx_rx_polarity(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs, int port, bool swap) +{ + const bool tx_polarity_swap[2][4] = { { true, true, false, false }, + { false, true, false, false } + }; + const bool rx_polarity_swap[2][4] = { { false, true, true, true }, + { false, true, true, false } + }; + uint8_t lane; + + (void)drv; + + for (lane = 0U; lane < 4U; lane++) { + if (swap) { + nthw_mac_pcs_swap_gty_tx_polarity(mac_pcs, lane, + tx_polarity_swap[port][lane]); + nthw_mac_pcs_swap_gty_rx_polarity(mac_pcs, lane, + rx_polarity_swap[port][lane]); + + } else { + nthw_mac_pcs_swap_gty_tx_polarity(mac_pcs, lane, false); + nthw_mac_pcs_swap_gty_rx_polarity(mac_pcs, lane, false); + } + } + + return 0; +} + +/* + * Reset RX + */ +static int _reset_rx(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs) +{ + (void)drv; + + nthw_mac_pcs_rx_path_rst(mac_pcs, true); + nt_os_wait_usec(10000); /* 10ms */ + nthw_mac_pcs_rx_path_rst(mac_pcs, false); + nt_os_wait_usec(10000); /* 10ms */ + + return 0; +} + +static void _set_loopback(struct adapter_info_s *p_adapter_info, + nthw_mac_pcs_t *mac_pcs, + int intf_no, + uint32_t mode, + uint32_t last_mode) +{ + bool swap_polerity = true; + + switch (mode) { + case 1: + NT_LOG(INF, NTNIC, "%s: Applying host loopback\n", + p_adapter_info->mp_port_id_str[intf_no]); + nthw_mac_pcs_set_fec(mac_pcs, true); + nthw_mac_pcs_set_host_loopback(mac_pcs, true); + swap_polerity = false; + break; + + case 2: + NT_LOG(INF, NTNIC, "%s: Applying line loopback\n", + p_adapter_info->mp_port_id_str[intf_no]); + nthw_mac_pcs_set_line_loopback(mac_pcs, true); + break; + + default: + switch (last_mode) { + case 1: + NT_LOG(INF, NTNIC, "%s: Removing host loopback\n", + p_adapter_info->mp_port_id_str[intf_no]); + nthw_mac_pcs_set_host_loopback(mac_pcs, false); + break; + + case 2: + NT_LOG(INF, NTNIC, "%s: Removing line loopback\n", + p_adapter_info->mp_port_id_str[intf_no]); + nthw_mac_pcs_set_line_loopback(mac_pcs, false); + break; + + default: + /* Do nothing */ + break; + } + + break; + } + + if (p_adapter_info->fpga_info.nthw_hw_info.hw_id == 2 || + p_adapter_info->hw_info.n_nthw_adapter_id == NT_HW_ADAPTER_ID_NT200A02) { + (void)_swap_tx_rx_polarity(p_adapter_info, mac_pcs, intf_no, swap_polerity); + } + + /* After changing the loopback the system must be properly reset */ + _reset_rx(p_adapter_info, mac_pcs); + + nt_os_wait_usec(10000); /* 10ms - arbitrary choice */ + + if (!nthw_mac_pcs_is_rx_path_rst(mac_pcs)) { + nthw_mac_pcs_reset_bip_counters(mac_pcs); + + if (!nthw_mac_pcs_get_fec_bypass(mac_pcs)) + nthw_mac_pcs_reset_fec_counters(mac_pcs); + } +} + +/* + * Function to retrieve the current state of a link (for one port) + */ +static int _link_state_build(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs, + nthw_gpio_phy_t *gpio_phy, int port, link_state_t *state, + bool is_port_disabled) +{ + uint32_t abs; + uint32_t phy_link_state; + uint32_t lh_abs; + uint32_t ll_phy_link_state; + uint32_t link_down_cnt; + uint32_t nim_interr; + uint32_t lh_local_fault; + uint32_t lh_remote_fault; + uint32_t lh_internal_local_fault; + uint32_t lh_received_local_fault; + + memset(state, 0, sizeof(*state)); + state->link_disabled = is_port_disabled; + nthw_mac_pcs_get_link_summary(mac_pcs, &abs, &phy_link_state, &lh_abs, &ll_phy_link_state, + &link_down_cnt, &nim_interr, &lh_local_fault, + &lh_remote_fault, &lh_internal_local_fault, + &lh_received_local_fault); + + assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); + state->nim_present = nthw_gpio_phy_is_module_present(gpio_phy, (uint8_t)port); + state->lh_nim_absent = !state->nim_present; + state->link_up = phy_link_state ? true : false; + + { + static char lsbuf[NUM_ADAPTER_MAX][NUM_ADAPTER_PORTS_MAX][256]; + char buf[255]; + const int adapter_no = drv->adapter_no; + snprintf(buf, sizeof(buf), + "%s: Port = %d: abs = %u, phy_link_state = %u, lh_abs = %u, " + "ll_phy_link_state = %u, " + "link_down_cnt = %u, nim_interr = %u, lh_local_fault = %u, lh_remote_fault = " + "%u, lh_internal_local_fault = %u, lh_received_local_fault = %u", + drv->mp_adapter_id_str, mac_pcs->mn_instance, abs, phy_link_state, lh_abs, + ll_phy_link_state, link_down_cnt, nim_interr, lh_local_fault, + lh_remote_fault, lh_internal_local_fault, lh_received_local_fault); + + if (strcmp(lsbuf[adapter_no][port], buf) != 0) { + snprintf(lsbuf[adapter_no][port], sizeof(lsbuf[adapter_no][port]), "%s", + buf); + lsbuf[adapter_no][port][sizeof(lsbuf[adapter_no][port]) - 1U] = '\0'; + NT_LOG(DBG, NTNIC, "%s\n", lsbuf[adapter_no][port]); + } + } + return 0; +} + /* * Check whether a NIM module is present */ @@ -20,6 +182,69 @@ static bool _nim_is_present(nthw_gpio_phy_t *gpio_phy, uint8_t if_no) return nthw_gpio_phy_is_module_present(gpio_phy, if_no); } +/* + * Enable RX + */ +static int _enable_rx(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs) +{ + (void)drv; /* unused */ + nthw_mac_pcs_set_rx_enable(mac_pcs, true); + return 0; +} + +/* + * Enable TX + */ +static int _enable_tx(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs) +{ + (void)drv; /* unused */ + nthw_mac_pcs_set_tx_enable(mac_pcs, true); + nthw_mac_pcs_set_tx_sel_host(mac_pcs, true); + return 0; +} + +/* + * Disable RX + */ +static int _disable_rx(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs) +{ + (void)drv; /* unused */ + nthw_mac_pcs_set_rx_enable(mac_pcs, false); + return 0; +} + +/* + * Disable TX + */ +static int _disable_tx(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs) +{ + (void)drv; /* unused */ + nthw_mac_pcs_set_tx_enable(mac_pcs, false); + nthw_mac_pcs_set_tx_sel_host(mac_pcs, false); + return 0; +} + +/* + * Check link once NIM is installed and link can be expected. + */ +static int check_link_state(adapter_info_t *drv, nthw_mac_pcs_t *mac_pcs) +{ + bool rst_required; + bool ber; + bool fec_all_locked; + + rst_required = nthw_mac_pcs_reset_required(mac_pcs); + + ber = nthw_mac_pcs_get_hi_ber(mac_pcs); + + fec_all_locked = nthw_mac_pcs_get_fec_stat_all_am_locked(mac_pcs); + + if (rst_required || ber || !fec_all_locked) + _reset_rx(drv, mac_pcs); + + return 0; +} + /* * Initialize NIM, Code based on nt200e3_2_ptp.cpp: MyPort::createNim() */ @@ -31,6 +256,7 @@ static int _create_nim(adapter_info_t *drv, int port, bool enable) nim_i2c_ctx_t *nim_ctx; sfp_nim_state_t nim; nt4ga_link_t *link_info = &drv->nt4ga_link; + nthw_mac_pcs_t *mac_pcs = &link_info->u.var100g.mac_pcs100g[port]; assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); assert(link_info->variables_initialized); @@ -46,6 +272,12 @@ static int _create_nim(adapter_info_t *drv, int port, bool enable) return 0; } + if (!enable) { + _disable_rx(drv, mac_pcs); + _disable_tx(drv, mac_pcs); + _reset_rx(drv, mac_pcs); + } + /* * Perform PHY reset. */ @@ -114,14 +346,29 @@ static int _create_nim(adapter_info_t *drv, int port, bool enable) * The function shall not assume anything about the state of the adapter * and/or port. */ -static int _port_init(adapter_info_t *drv, int port) +static int _port_init(adapter_info_t *drv, nthw_fpga_t *fpga, int port) { + int adapter_id; + int hw_id; int res; nt4ga_link_t *link_info = &drv->nt4ga_link; + nthw_mac_pcs_t *mac_pcs; + assert(port >= 0 && port < NUM_ADAPTER_PORTS_MAX); assert(link_info->variables_initialized); + if (fpga && fpga->p_fpga_info) { + adapter_id = fpga->p_fpga_info->n_nthw_adapter_id; + hw_id = fpga->p_fpga_info->nthw_hw_info.hw_id; + + } else { + adapter_id = -1; + hw_id = -1; + } + + mac_pcs = &link_info->u.var100g.mac_pcs100g[port]; + /* * Phase 1. Pre-state machine (`port init` functions) * 1.1) nt4ga_adapter::port_init() @@ -134,6 +381,28 @@ static int _port_init(adapter_info_t *drv, int port) link_info->link_info[port].link_duplex = NT_LINK_DUPLEX_FULL; link_info->link_info[port].link_auto_neg = NT_LINK_AUTONEG_OFF; link_info->speed_capa |= NT_LINK_SPEED_100G; + nthw_mac_pcs_set_led_mode(mac_pcs, NTHW_MAC_PCS_LED_AUTO); + nthw_mac_pcs_set_receiver_equalization_mode(mac_pcs, nthw_mac_pcs_receiver_mode_lpm); + + /* + * NT200A01 build 2 HW and NT200A02 that require GTY polarity swap + * if (adapter is `NT200A01 build 2 HW or NT200A02`) + */ + if (adapter_id == NT_HW_ADAPTER_ID_NT200A02 || hw_id == 2) + (void)_swap_tx_rx_polarity(drv, mac_pcs, port, true); + + nthw_mac_pcs_set_ts_eop(mac_pcs, true); /* end-of-frame timestamping */ + + /* Work in ABSOLUTE timing mode, don't set IFG mode. */ + + /* Phase 2. Pre-state machine (`setup` functions) */ + + /* 2.1) nt200a0x.cpp:Myport::setup() */ + NT_LOG(DBG, NTNIC, "%s: Setting up port %d\n", drv->mp_port_id_str[port], port); + + NT_LOG(DBG, NTNIC, "%s: Port %d: PHY TX enable\n", drv->mp_port_id_str[port], port); + _enable_tx(drv, mac_pcs); + _reset_rx(drv, mac_pcs); /* Phase 3. Link state machine steps */ @@ -147,6 +416,50 @@ static int _port_init(adapter_info_t *drv, int port) NT_LOG(DBG, NTNIC, "%s: NIM initialized\n", drv->mp_port_id_str[port]); + /* 3.2) MyPort::nimReady() */ + + /* 3.3) MyPort::nimReady100Gb() */ + + /* Setting FEC resets the lane counter in one half of the GMF */ + nthw_mac_pcs_set_fec(mac_pcs, true); + NT_LOG(DBG, NTNIC, "%s: Port %d: HOST FEC enabled\n", drv->mp_port_id_str[port], port); + + if (adapter_id == NT_HW_ADAPTER_ID_NT200A02 || hw_id == 2) { + const uint8_t pre = 5; + const uint8_t diff = 25; + const uint8_t post = 12; + + uint8_t lane = 0; + + for (lane = 0; lane < 4; lane++) + nthw_mac_pcs_set_gty_tx_tuning(mac_pcs, lane, pre, diff, post); + + } else { + NT_LOG(ERR, NTNIC, "Unhandled AdapterId/HwId: %02x_hwid%d\n", adapter_id, hw_id); + assert(0); + } + + _reset_rx(drv, mac_pcs); + + /* + * 3.4) MyPort::setLinkState() + * + * Compensation = 1640 - dly + * CMAC-core dly 188 ns + * FEC no correction 87 ns + * FEC active correction 211 + */ + if (nthw_mac_pcs_get_fec_valid(mac_pcs)) + nthw_mac_pcs_set_timestamp_comp_rx(mac_pcs, (1640 - 188 - 211)); + + else + nthw_mac_pcs_set_timestamp_comp_rx(mac_pcs, (1640 - 188 - 87)); + + /* 3.5) uint32_t MyPort::macConfig(nt_link_state_t link_state) */ + _enable_rx(drv, mac_pcs); + + nthw_mac_pcs_set_host_loopback(mac_pcs, false); + return res; } @@ -163,7 +476,9 @@ static int _common_ptp_nim_state_machine(void *data) const int nb_ports = fpga_info->n_phy_ports; uint32_t last_lpbk_mode[NUM_ADAPTER_PORTS_MAX]; + nim_i2c_ctx_t *nim_ctx; link_state_t *link_state; + nthw_mac_pcs_t *mac_pcs; nthw_gpio_phy_t *gpio_phy; if (!fpga) { @@ -172,7 +487,9 @@ static int _common_ptp_nim_state_machine(void *data) } assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); + nim_ctx = link_info->u.var100g.nim_ctx; link_state = link_info->link_state; + mac_pcs = link_info->u.var100g.mac_pcs100g; gpio_phy = link_info->u.var100g.gpio_phy; monitor_task_is_running[adapter_no] = 1; @@ -183,8 +500,10 @@ static int _common_ptp_nim_state_machine(void *data) while (monitor_task_is_running[adapter_no]) { int i; + static bool reported_link[NUM_ADAPTER_PORTS_MAX] = { false }; for (i = 0; i < nb_ports; i++) { + link_state_t new_link_state; const bool is_port_disabled = link_info->port_action[i].port_disable; const bool was_port_disabled = link_state[i].link_disabled; const bool disable_port = is_port_disabled && !was_port_disabled; @@ -200,6 +519,7 @@ static int _common_ptp_nim_state_machine(void *data) memset(&link_state[i], 0, sizeof(link_state[i])); link_info->link_info[i].link_speed = NT_LINK_SPEED_UNKNOWN; link_state[i].link_disabled = true; + reported_link[i] = false; /* Turn off laser and LED, etc. */ (void)_create_nim(drv, i, false); NT_LOG(DBG, NTNIC, "%s: Port %i is disabled\n", @@ -223,12 +543,17 @@ static int _common_ptp_nim_state_machine(void *data) * If there is no Nim present, we need to initialize the * port anyway */ - _port_init(drv, i); + _port_init(drv, fpga, i); } NT_LOG(INF, NTNIC, "%s: Loopback mode changed=%u\n", drv->mp_port_id_str[i], link_info->port_action[i].port_lpbk_mode); + _set_loopback(drv, + &mac_pcs[i], + i, + link_info->port_action[i].port_lpbk_mode, + last_lpbk_mode[i]); if (link_info->port_action[i].port_lpbk_mode == 1) link_state[i].link_up = true; @@ -237,6 +562,65 @@ static int _common_ptp_nim_state_machine(void *data) continue; } + (void)_link_state_build(drv, &mac_pcs[i], &gpio_phy[i], i, &new_link_state, + is_port_disabled); + + if (!new_link_state.nim_present) { + if (link_state[i].nim_present) { + NT_LOG(INF, NTNIC, "%s: NIM module removed\n", + drv->mp_port_id_str[i]); + } + + link_state[i] = new_link_state; + continue; + } + + /* NIM module is present */ + if (new_link_state.lh_nim_absent || !link_state[i].nim_present) { + sfp_nim_state_t new_state; + + NT_LOG(DBG, NTNIC, "%s: NIM module inserted\n", + drv->mp_port_id_str[i]); + + if (_port_init(drv, fpga, i)) { + NT_LOG(ERR, NTNIC, + "%s: Failed to initialize NIM module\n", + drv->mp_port_id_str[i]); + continue; + } + + if (nim_state_build(&nim_ctx[i], &new_state)) { + NT_LOG(ERR, NTNIC, "%s: Cannot read basic NIM data\n", + drv->mp_port_id_str[i]); + continue; + } + + assert(new_state.br); /* Cannot be zero if NIM is present */ + NT_LOG(DBG, NTNIC, + "%s: NIM id = %u (%s), br = %u, vendor = '%s', pn = '%s', sn='%s'\n", + drv->mp_port_id_str[i], nim_ctx->nim_id, + nim_id_to_text(nim_ctx->nim_id), (unsigned int)new_state.br, + nim_ctx->vendor_name, nim_ctx->prod_no, nim_ctx->serial_no); + + (void)_link_state_build(drv, &mac_pcs[i], &gpio_phy[i], i, + &link_state[i], is_port_disabled); + + NT_LOG(DBG, NTNIC, "%s: NIM module initialized\n", + drv->mp_port_id_str[i]); + continue; + } + + if (reported_link[i] != new_link_state.link_up) { + NT_LOG(INF, NTNIC, "%s: link is %s\n", drv->mp_port_id_str[i], + (new_link_state.link_up ? "up" : "down")); + link_info->link_info[i].link_speed = + (new_link_state.link_up ? NT_LINK_SPEED_100G + : NT_LINK_SPEED_UNKNOWN); + link_state[i].link_up = new_link_state.link_up; + reported_link[i] = new_link_state.link_up; + } + + check_link_state(drv, &mac_pcs[i]); } /* end-for */ if (monitor_task_is_running[adapter_no]) @@ -280,6 +664,7 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth assert(adapter_no >= 0 && adapter_no < NUM_ADAPTER_MAX); if (res == 0 && !p_adapter_info->nt4ga_link.variables_initialized) { + nthw_mac_pcs_t *mac_pcs = p_adapter_info->nt4ga_link.u.var100g.mac_pcs100g; nim_i2c_ctx_t *nim_ctx = p_adapter_info->nt4ga_link.u.var100g.nim_ctx; nthw_gpio_phy_t *gpio_phy = p_adapter_info->nt4ga_link.u.var100g.gpio_phy; int i; @@ -287,6 +672,10 @@ static int nt4ga_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nth for (i = 0; i < nb_ports; i++) { /* 2 + adapter port number */ const uint8_t instance = (uint8_t)(2U + i); + res = nthw_mac_pcs_init(&mac_pcs[i], fpga, i /* int n_instance */); + + if (res != 0) + break; res = nthw_iic_init(&nim_ctx[i].hwiic, fpga, instance, 8); diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 6dd972cf7d..9df2378f7c 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -38,6 +38,7 @@ sources = files( 'nthw/core/nthw_hif.c', 'nthw/core/nthw_i2cm.c', 'nthw/core/nthw_iic.c', + 'nthw/core/nthw_mac_pcs.c', 'nthw/core/nthw_pcie3.c', 'nthw/core/nthw_sdc.c', 'nthw/core/nthw_si5340.c', diff --git a/drivers/net/ntnic/nthw/core/include/nthw_core.h b/drivers/net/ntnic/nthw/core/include/nthw_core.h index 5cce56e13f..fe32891712 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_core.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_core.h @@ -18,6 +18,7 @@ #include "nthw_i2cm.h" #include "nthw_gpio_phy.h" +#include "nthw_mac_pcs.h" #include "nthw_sdc.h" #include "nthw_si5340.h" diff --git a/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs.h b/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs.h new file mode 100644 index 0000000000..8d0e81bd73 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/include/nthw_mac_pcs.h @@ -0,0 +1,250 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#ifndef NTHW_MAC_PCS_H_ +#define NTHW_MAC_PCS_H_ + +enum nthw_mac_pcs_led_mode_e { + NTHW_MAC_PCS_LED_AUTO = 0x00, + NTHW_MAC_PCS_LED_ON = 0x01, + NTHW_MAC_PCS_LED_OFF = 0x02, + NTHW_MAC_PCS_LED_PORTID = 0x03, +}; + +#define nthw_mac_pcs_receiver_mode_dfe (0) +#define nthw_mac_pcs_receiver_mode_lpm (1) + +struct nthw_mac_pcs { + uint8_t m_port_no; + + nthw_fpga_t *mp_fpga; + nthw_module_t *mp_mod_mac_pcs; + int mn_instance; + + /* Block lock status */ + nthw_field_t *mp_fld_block_lock_lock; + uint32_t m_fld_block_lock_lock_mask; + + /* Lane lock status */ + nthw_field_t *mp_fld_vl_demuxed_lock; + uint32_t m_fld_vl_demuxed_lock_mask; + + /* GTY_STAT */ + nthw_field_t *mp_fld_gty_stat_rx_rst_done0; + nthw_field_t *mp_fld_gty_stat_rx_rst_done1; + nthw_field_t *mp_fld_gty_stat_rx_rst_done2; + nthw_field_t *mp_fld_gty_stat_rx_rst_done3; + nthw_field_t *mp_fld_gty_stat_tx_rst_done0; + nthw_field_t *mp_fld_gty_stat_tx_rst_done1; + nthw_field_t *mp_fld_gty_stat_tx_rst_done2; + nthw_field_t *mp_fld_gty_stat_tx_rst_done3; + uint32_t m_fld_gty_stat_rx_rst_done_mask; + uint32_t m_fld_gty_stat_tx_rst_done_mask; + + /* GTY_LOOP */ + nthw_register_t *mp_reg_gty_loop; + nthw_field_t *mp_fld_gty_loop_gt_loop0; + nthw_field_t *mp_fld_gty_loop_gt_loop1; + nthw_field_t *mp_fld_gty_loop_gt_loop2; + nthw_field_t *mp_fld_gty_loop_gt_loop3; + + /* MAC_PCS_CONFIG */ + nthw_field_t *mp_fld_pcs_config_tx_path_rst; + nthw_field_t *mp_fld_pcs_config_rx_path_rst; + nthw_field_t *mp_fld_pcs_config_rx_enable; + nthw_field_t *mp_fld_pcs_config_rx_force_resync; + nthw_field_t *mp_fld_pcs_config_rx_test_pattern; + nthw_field_t *mp_fld_pcs_config_tx_enable; + nthw_field_t *mp_fld_pcs_config_tx_send_idle; + nthw_field_t *mp_fld_pcs_config_tx_send_rfi; + nthw_field_t *mp_fld_pcs_config_tx_test_pattern; + + /* STAT PCS */ + nthw_field_t *mp_fld_stat_pcs_rx_status; + nthw_field_t *mp_fld_stat_pcs_rx_aligned; + nthw_field_t *mp_fld_stat_pcs_rx_aligned_err; + nthw_field_t *mp_fld_stat_pcs_rx_misaligned; + nthw_field_t *mp_fld_stat_pcs_rx_internal_local_fault; + nthw_field_t *mp_fld_stat_pcs_rx_received_local_fault; + nthw_field_t *mp_fld_stat_pcs_rx_local_fault; + nthw_field_t *mp_fld_stat_pcs_rx_remote_fault; + nthw_field_t *mp_fld_stat_pcs_rx_hi_ber; + + /* STAT_PCS_RX_LATCH */ + nthw_field_t *mp_fld_stat_pcs_rx_latch_status; + + /* PHYMAC_MISC */ + nthw_field_t *mp_fld_phymac_misc_tx_sel_host; + nthw_field_t *mp_fld_phymac_misc_tx_sel_tfg; + nthw_field_t *mp_fld_phymac_misc_tx_sel_rx_loop; + nthw_field_t *mp_fld_phymac_misc_ts_eop; + + /* LINK_SUMMARY */ + nthw_register_t *mp_reg_link_summary; + nthw_field_t *mp_fld_link_summary_abs; + nthw_field_t *mp_fld_link_summary_nt_phy_link_state; + nthw_field_t *mp_fld_link_summary_lh_abs; + nthw_field_t *mp_fld_link_summary_ll_nt_phy_link_state; + nthw_field_t *mp_fld_link_summary_link_down_cnt; + nthw_field_t *mp_fld_link_summary_nim_interr; + nthw_field_t *mp_fld_link_summary_lh_local_fault; + nthw_field_t *mp_fld_link_summary_lh_remote_fault; + nthw_field_t *mp_fld_link_summary_local_fault; + nthw_field_t *mp_fld_link_summary_remote_fault; + + /* BIP_ERR */ + nthw_register_t *mp_reg_bip_err; + nthw_field_t *mp_fld_reg_bip_err_bip_err; + + /* FEC_CTRL */ + nthw_register_t *mp_reg_fec_ctrl; + nthw_field_t *mp_field_fec_ctrl_reg_rs_fec_ctrl_in; + + /* FEC_STAT */ + nthw_register_t *mp_reg_fec_stat; + nthw_field_t *mp_field_fec_stat_bypass; + nthw_field_t *mp_field_fec_stat_valid; + nthw_field_t *mp_field_fec_stat_am_lock0; + nthw_field_t *mp_field_fec_stat_am_lock1; + nthw_field_t *mp_field_fec_stat_am_lock2; + nthw_field_t *mp_field_fec_stat_am_lock3; + nthw_field_t *mp_field_fec_stat_fec_lane_algn; + + /* FEC Corrected code word count */ + nthw_register_t *mp_reg_fec_cw_cnt; + nthw_field_t *mp_field_fec_cw_cnt_cw_cnt; + + /* FEC Uncorrected code word count */ + nthw_register_t *mp_reg_fec_ucw_cnt; + nthw_field_t *mp_field_fec_ucw_cnt_ucw_cnt; + + /* GTY_RX_BUF_STAT */ + nthw_register_t *mp_reg_gty_rx_buf_stat; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat0; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat1; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat2; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat3; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat_changed0; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat_changed1; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat_changed2; + nthw_field_t *mp_field_gty_rx_buf_stat_rx_buf_stat_changed3; + + /* GTY_PRE_CURSOR */ + nthw_register_t *mp_reg_gty_pre_cursor; + nthw_field_t *mp_field_gty_pre_cursor_tx_pre_csr0; + nthw_field_t *mp_field_gty_pre_cursor_tx_pre_csr1; + nthw_field_t *mp_field_gty_pre_cursor_tx_pre_csr2; + nthw_field_t *mp_field_gty_pre_cursor_tx_pre_csr3; + + /* GTY_DIFF_CTL */ + nthw_register_t *mp_reg_gty_diff_ctl; + nthw_field_t *mp_field_gty_gty_diff_ctl_tx_diff_ctl0; + nthw_field_t *mp_field_gty_gty_diff_ctl_tx_diff_ctl1; + nthw_field_t *mp_field_gty_gty_diff_ctl_tx_diff_ctl2; + nthw_field_t *mp_field_gty_gty_diff_ctl_tx_diff_ctl3; + + /* GTY_POST_CURSOR */ + nthw_register_t *mp_reg_gty_post_cursor; + nthw_field_t *mp_field_gty_post_cursor_tx_post_csr0; + nthw_field_t *mp_field_gty_post_cursor_tx_post_csr1; + nthw_field_t *mp_field_gty_post_cursor_tx_post_csr2; + nthw_field_t *mp_field_gty_post_cursor_tx_post_csr3; + + /* GTY_CTL */ + nthw_register_t *mp_reg_gty_ctl; + nthw_register_t *mp_reg_gty_ctl_tx; + nthw_field_t *mp_field_gty_ctl_tx_pol0; + nthw_field_t *mp_field_gty_ctl_tx_pol1; + nthw_field_t *mp_field_gty_ctl_tx_pol2; + nthw_field_t *mp_field_gty_ctl_tx_pol3; + nthw_field_t *mp_field_gty_ctl_rx_pol0; + nthw_field_t *mp_field_gty_ctl_rx_pol1; + nthw_field_t *mp_field_gty_ctl_rx_pol2; + nthw_field_t *mp_field_gty_ctl_rx_pol3; + nthw_field_t *mp_field_gty_ctl_rx_lpm_en0; + nthw_field_t *mp_field_gty_ctl_rx_lpm_en1; + nthw_field_t *mp_field_gty_ctl_rx_lpm_en2; + nthw_field_t *mp_field_gty_ctl_rx_lpm_en3; + nthw_field_t *mp_field_gty_ctl_rx_equa_rst0; + nthw_field_t *mp_field_gty_ctl_rx_equa_rst1; + nthw_field_t *mp_field_gty_ctl_rx_equa_rst2; + nthw_field_t *mp_field_gty_ctl_rx_equa_rst3; + + /* DEBOUNCE_CTRL */ + nthw_register_t *mp_reg_debounce_ctrl; + nthw_field_t *mp_field_debounce_ctrl_nt_port_ctrl; + + /* TIMESTAMP_COMP */ + nthw_register_t *mp_reg_time_stamp_comp; + nthw_field_t *mp_field_time_stamp_comp_rx_dly; + nthw_field_t *mp_field_time_stamp_comp_tx_dly; + + /* STAT_PCS_RX */ + nthw_register_t *mp_reg_stat_pcs_rx; + + /* STAT_PCS_RX */ + nthw_register_t *mp_reg_stat_pcs_rx_latch; + + /* PHYMAC_MISC */ + nthw_register_t *mp_reg_phymac_misc; + + /* BLOCK_LOCK */ + nthw_register_t *mp_reg_block_lock; +}; + +typedef struct nthw_mac_pcs nthw_mac_pcs_t; + +int nthw_mac_pcs_init(nthw_mac_pcs_t *p, nthw_fpga_t *p_fpga, int n_instance); + +void nthw_mac_pcs_tx_path_rst(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_rx_path_rst(nthw_mac_pcs_t *p, bool enable); +bool nthw_mac_pcs_is_rx_path_rst(nthw_mac_pcs_t *p); +/* wrapper - for ease of use */ +void nthw_mac_pcs_set_rx_enable(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_set_tx_enable(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_set_tx_sel_host(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_set_tx_sel_tfg(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_set_ts_eop(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_set_host_loopback(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_set_line_loopback(nthw_mac_pcs_t *p, bool enable); +void nthw_mac_pcs_reset_bip_counters(nthw_mac_pcs_t *p); +bool nthw_mac_pcs_get_hi_ber(nthw_mac_pcs_t *p); + +void nthw_mac_pcs_get_link_summary(nthw_mac_pcs_t *p, + uint32_t *p_abs, + uint32_t *p_nt_phy_link_state, + uint32_t *p_lh_abs, + uint32_t *p_ll_nt_phy_link_state, + uint32_t *p_link_down_cnt, + uint32_t *p_nim_interr, + uint32_t *p_lh_local_fault, + uint32_t *p_lh_remote_fault, + uint32_t *p_local_fault, + uint32_t *p_remote_fault); + +bool nthw_mac_pcs_reset_required(nthw_mac_pcs_t *p); +void nthw_mac_pcs_set_fec(nthw_mac_pcs_t *p, bool enable); +bool nthw_mac_pcs_get_fec_bypass(nthw_mac_pcs_t *p); +bool nthw_mac_pcs_get_fec_valid(nthw_mac_pcs_t *p); +bool nthw_mac_pcs_get_fec_stat_all_am_locked(nthw_mac_pcs_t *p); +void nthw_mac_pcs_reset_fec_counters(nthw_mac_pcs_t *p); +void nthw_mac_pcs_set_gty_tx_tuning(nthw_mac_pcs_t *p, + uint8_t lane, + uint8_t tx_pre_csr, + uint8_t tx_diff_ctl, + uint8_t tx_post_csr); +void nthw_mac_pcs_swap_gty_tx_polarity(nthw_mac_pcs_t *p, uint8_t lane, bool swap); +void nthw_mac_pcs_swap_gty_rx_polarity(nthw_mac_pcs_t *p, uint8_t lane, bool swap); +void nthw_mac_pcs_set_receiver_equalization_mode(nthw_mac_pcs_t *p, uint8_t mode); +void nthw_mac_pcs_set_led_mode(nthw_mac_pcs_t *p, uint8_t mode); +void nthw_mac_pcs_set_timestamp_comp_rx(nthw_mac_pcs_t *p, uint16_t rx_dly); +void nthw_mac_pcs_set_port_no(nthw_mac_pcs_t *p, uint8_t port_no); + +uint32_t nthw_mac_pcs_get_fld_block_lock_lock(nthw_mac_pcs_t *p); +uint32_t nthw_mac_pcs_get_fld_block_lock_lock_mask(nthw_mac_pcs_t *p); +uint32_t nthw_mac_pcs_get_fld_lane_lock_lock(nthw_mac_pcs_t *p); +uint32_t nthw_mac_pcs_get_fld_lane_lock_lock_mask(nthw_mac_pcs_t *p); + +#endif /* NTHW_MAC_PCS_H_ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_mac_pcs.c b/drivers/net/ntnic/nthw/core/nthw_mac_pcs.c new file mode 100644 index 0000000000..398f4ffd15 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_mac_pcs.c @@ -0,0 +1,864 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_mac_pcs.h" + +#define NTHW_MAC_PCS_LANES (20) + +static const uint8_t c_pcs_lanes = NTHW_MAC_PCS_LANES; +static const uint8_t c_mac_pcs_receiver_mode_dfe; + +/* + * Parameters: + * p != NULL: init struct pointed to by p + * p == NULL: check fpga module(s) presence (but no struct to init) + * + * Return value: + * <0: if p == NULL then fpga module(s) is/are not present. + * if p != NULL then fpga module(s) is/are not present, struct undefined + * ==0: if p == NULL then fpga module(s) is/are present (no struct to init) + * : if p != NULL then fpga module(s) is/are present and struct initialized + */ +int nthw_mac_pcs_init(nthw_mac_pcs_t *p, nthw_fpga_t *p_fpga, int n_instance) +{ + nthw_module_t *mod = nthw_fpga_query_module(p_fpga, MOD_MAC_PCS, n_instance); + + if (p == NULL) + return mod == NULL ? -1 : 0; + + if (mod == NULL) { + NT_LOG(ERR, NTHW, "%s: MAC_PCS %d: no such instance\n", + p_fpga->p_fpga_info->mp_adapter_id_str, n_instance); + return -1; + } + + p->mp_fpga = p_fpga; + p->mn_instance = n_instance; + p->mp_mod_mac_pcs = mod; + + assert(n_instance >= 0 && n_instance <= 255); + nthw_mac_pcs_set_port_no(p, (uint8_t)n_instance); + + { + nthw_register_t *p_reg_block_lock, *p_reg_stat_pcs_rx, *p_reg_stat_pcs_rx_latch; + nthw_register_t *p_reg_vl_demuxed, *p_reg_gty_stat, *p_reg_pcs_config, + *p_reg_phymac_misc; + const int product_id = nthw_fpga_get_product_id(p_fpga); + + p_reg_block_lock = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_BLOCK_LOCK); + p->mp_reg_block_lock = p_reg_block_lock; + p->mp_fld_block_lock_lock = + nthw_register_get_field(p_reg_block_lock, MAC_PCS_BLOCK_LOCK_LOCK); + + p_reg_stat_pcs_rx = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_STAT_PCS_RX); + p->mp_reg_stat_pcs_rx = p_reg_stat_pcs_rx; + p->mp_fld_stat_pcs_rx_status = + nthw_register_get_field(p_reg_stat_pcs_rx, MAC_PCS_STAT_PCS_RX_STATUS); + p->mp_fld_stat_pcs_rx_aligned = + nthw_register_get_field(p_reg_stat_pcs_rx, MAC_PCS_STAT_PCS_RX_ALIGNED); + p->mp_fld_stat_pcs_rx_aligned_err = + nthw_register_get_field(p_reg_stat_pcs_rx, + MAC_PCS_STAT_PCS_RX_ALIGNED_ERR); + p->mp_fld_stat_pcs_rx_misaligned = + nthw_register_get_field(p_reg_stat_pcs_rx, MAC_PCS_STAT_PCS_RX_MISALIGNED); + p->mp_fld_stat_pcs_rx_internal_local_fault = + nthw_register_get_field(p_reg_stat_pcs_rx, + MAC_PCS_STAT_PCS_RX_INTERNAL_LOCAL_FAULT); + p->mp_fld_stat_pcs_rx_received_local_fault = + nthw_register_get_field(p_reg_stat_pcs_rx, + MAC_PCS_STAT_PCS_RX_RECEIVED_LOCAL_FAULT); + p->mp_fld_stat_pcs_rx_local_fault = + nthw_register_get_field(p_reg_stat_pcs_rx, + MAC_PCS_STAT_PCS_RX_LOCAL_FAULT); + p->mp_fld_stat_pcs_rx_remote_fault = + nthw_register_get_field(p_reg_stat_pcs_rx, + MAC_PCS_STAT_PCS_RX_REMOTE_FAULT); + p->mp_fld_stat_pcs_rx_hi_ber = + nthw_register_get_field(p_reg_stat_pcs_rx, MAC_PCS_STAT_PCS_RX_HI_BER); + + p_reg_stat_pcs_rx_latch = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_STAT_PCS_RX_LATCH); + p->mp_reg_stat_pcs_rx_latch = p_reg_stat_pcs_rx_latch; + p->mp_fld_stat_pcs_rx_latch_status = + nthw_register_get_field(p_reg_stat_pcs_rx_latch, + MAC_PCS_STAT_PCS_RX_LATCH_STATUS); + + p_reg_vl_demuxed = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_VL_DEMUXED); + p->mp_fld_vl_demuxed_lock = + nthw_register_get_field(p_reg_vl_demuxed, MAC_PCS_VL_DEMUXED_LOCK); + + p_reg_gty_stat = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_STAT); + p->mp_fld_gty_stat_tx_rst_done0 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_TX_RST_DONE_0); + p->mp_fld_gty_stat_tx_rst_done1 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_TX_RST_DONE_1); + p->mp_fld_gty_stat_tx_rst_done2 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_TX_RST_DONE_2); + p->mp_fld_gty_stat_tx_rst_done3 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_TX_RST_DONE_3); + p->mp_fld_gty_stat_rx_rst_done0 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_RX_RST_DONE_0); + p->mp_fld_gty_stat_rx_rst_done1 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_RX_RST_DONE_1); + p->mp_fld_gty_stat_rx_rst_done2 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_RX_RST_DONE_2); + p->mp_fld_gty_stat_rx_rst_done3 = + nthw_register_get_field(p_reg_gty_stat, MAC_PCS_GTY_STAT_RX_RST_DONE_3); + + p->m_fld_block_lock_lock_mask = 0; + p->m_fld_vl_demuxed_lock_mask = 0; + p->m_fld_gty_stat_tx_rst_done_mask = 0; + p->m_fld_gty_stat_rx_rst_done_mask = 0; + + if (product_id == 9563) { + /* NT200A01_2X100 implements 20 virtual lanes */ + p->m_fld_block_lock_lock_mask = (1 << 20) - 1; + /* NT200A01_2X100 implements 20 virtual lanes */ + p->m_fld_vl_demuxed_lock_mask = (1 << 20) - 1; + p->m_fld_gty_stat_tx_rst_done_mask = + 1; /* NT200A01_2X100 implements 4 GTY */ + p->m_fld_gty_stat_rx_rst_done_mask = + 1; /* NT200A01_2X100 implements 4 GTY */ + + } else { + /* Remember to add new product_ids */ + assert(0); + } + + p_reg_pcs_config = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_MAC_PCS_CONFIG); + p->mp_fld_pcs_config_tx_path_rst = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_TX_PATH_RST); + p->mp_fld_pcs_config_rx_path_rst = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_RX_PATH_RST); + p->mp_fld_pcs_config_rx_enable = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_RX_ENABLE); + p->mp_fld_pcs_config_rx_force_resync = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_RX_FORCE_RESYNC); + p->mp_fld_pcs_config_rx_test_pattern = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_RX_TEST_PATTERN); + p->mp_fld_pcs_config_tx_enable = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_TX_ENABLE); + p->mp_fld_pcs_config_tx_send_idle = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_TX_SEND_IDLE); + p->mp_fld_pcs_config_tx_send_rfi = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_TX_SEND_RFI); + p->mp_fld_pcs_config_tx_test_pattern = + nthw_register_get_field(p_reg_pcs_config, + MAC_PCS_MAC_PCS_CONFIG_TX_TEST_PATTERN); + + p->mp_reg_gty_loop = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_LOOP); + p->mp_fld_gty_loop_gt_loop0 = + nthw_register_get_field(p->mp_reg_gty_loop, MAC_PCS_GTY_LOOP_GT_LOOP_0); + p->mp_fld_gty_loop_gt_loop1 = + nthw_register_get_field(p->mp_reg_gty_loop, MAC_PCS_GTY_LOOP_GT_LOOP_1); + p->mp_fld_gty_loop_gt_loop2 = + nthw_register_get_field(p->mp_reg_gty_loop, MAC_PCS_GTY_LOOP_GT_LOOP_2); + p->mp_fld_gty_loop_gt_loop3 = + nthw_register_get_field(p->mp_reg_gty_loop, MAC_PCS_GTY_LOOP_GT_LOOP_3); + + p_reg_phymac_misc = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_PHYMAC_MISC); + p->mp_reg_phymac_misc = p_reg_phymac_misc; + p->mp_fld_phymac_misc_tx_sel_host = + nthw_register_get_field(p_reg_phymac_misc, + MAC_PCS_PHYMAC_MISC_TX_SEL_HOST); + p->mp_fld_phymac_misc_tx_sel_tfg = + nthw_register_get_field(p_reg_phymac_misc, MAC_PCS_PHYMAC_MISC_TX_SEL_TFG); + p->mp_fld_phymac_misc_tx_sel_rx_loop = + nthw_register_get_field(p_reg_phymac_misc, + MAC_PCS_PHYMAC_MISC_TX_SEL_RX_LOOP); + + /* SOP or EOP TIMESTAMP */ + p->mp_fld_phymac_misc_ts_eop = + nthw_register_query_field(p_reg_phymac_misc, MAC_PCS_PHYMAC_MISC_TS_EOP); + + p->mp_reg_link_summary = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_LINK_SUMMARY); + p->mp_fld_link_summary_abs = + nthw_register_get_field(p->mp_reg_link_summary, MAC_PCS_LINK_SUMMARY_ABS); + p->mp_fld_link_summary_nt_phy_link_state = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_NT_PHY_LINK_STATE); + p->mp_fld_link_summary_lh_abs = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_LH_ABS); + p->mp_fld_link_summary_ll_nt_phy_link_state = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_LL_PHY_LINK_STATE); + p->mp_fld_link_summary_link_down_cnt = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_LINK_DOWN_CNT); + p->mp_fld_link_summary_nim_interr = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_NIM_INTERR); + p->mp_fld_link_summary_lh_local_fault = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_LH_LOCAL_FAULT); + p->mp_fld_link_summary_lh_remote_fault = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_LH_REMOTE_FAULT); + p->mp_fld_link_summary_local_fault = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_LOCAL_FAULT); + p->mp_fld_link_summary_remote_fault = + nthw_register_get_field(p->mp_reg_link_summary, + MAC_PCS_LINK_SUMMARY_REMOTE_FAULT); + + p->mp_reg_bip_err = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_BIP_ERR); + p->mp_fld_reg_bip_err_bip_err = + nthw_register_get_field(p->mp_reg_bip_err, MAC_PCS_BIP_ERR_BIP_ERR); + + p->mp_reg_fec_ctrl = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_FEC_CTRL); + p->mp_field_fec_ctrl_reg_rs_fec_ctrl_in = + nthw_register_get_field(p->mp_reg_fec_ctrl, + MAC_PCS_FEC_CTRL_RS_FEC_CTRL_IN); + + p->mp_reg_fec_stat = nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_FEC_STAT); + p->mp_field_fec_stat_bypass = + nthw_register_get_field(p->mp_reg_fec_stat, MAC_PCS_FEC_STAT_BYPASS); + p->mp_field_fec_stat_valid = + nthw_register_get_field(p->mp_reg_fec_stat, MAC_PCS_FEC_STAT_VALID); + p->mp_field_fec_stat_am_lock0 = + nthw_register_get_field(p->mp_reg_fec_stat, MAC_PCS_FEC_STAT_AM_LOCK_0); + p->mp_field_fec_stat_am_lock1 = + nthw_register_get_field(p->mp_reg_fec_stat, MAC_PCS_FEC_STAT_AM_LOCK_1); + p->mp_field_fec_stat_am_lock2 = + nthw_register_get_field(p->mp_reg_fec_stat, MAC_PCS_FEC_STAT_AM_LOCK_2); + p->mp_field_fec_stat_am_lock3 = + nthw_register_get_field(p->mp_reg_fec_stat, MAC_PCS_FEC_STAT_AM_LOCK_3); + p->mp_field_fec_stat_fec_lane_algn = + nthw_register_get_field(p->mp_reg_fec_stat, + MAC_PCS_FEC_STAT_FEC_LANE_ALGN); + + p->mp_reg_fec_cw_cnt = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_FEC_CW_CNT); + p->mp_field_fec_cw_cnt_cw_cnt = + nthw_register_get_field(p->mp_reg_fec_cw_cnt, MAC_PCS_FEC_CW_CNT_CW_CNT); + + p->mp_reg_fec_ucw_cnt = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_FEC_UCW_CNT); + p->mp_field_fec_ucw_cnt_ucw_cnt = + nthw_register_get_field(p->mp_reg_fec_ucw_cnt, + MAC_PCS_FEC_UCW_CNT_UCW_CNT); + + /* GTY_PRE_CURSOR */ + p->mp_reg_gty_pre_cursor = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_PRE_CURSOR); + p->mp_field_gty_pre_cursor_tx_pre_csr0 = + nthw_register_get_field(p->mp_reg_gty_pre_cursor, + MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_0); + p->mp_field_gty_pre_cursor_tx_pre_csr1 = + nthw_register_get_field(p->mp_reg_gty_pre_cursor, + MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_1); + p->mp_field_gty_pre_cursor_tx_pre_csr2 = + nthw_register_get_field(p->mp_reg_gty_pre_cursor, + MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_2); + p->mp_field_gty_pre_cursor_tx_pre_csr3 = + nthw_register_get_field(p->mp_reg_gty_pre_cursor, + MAC_PCS_GTY_PRE_CURSOR_TX_PRE_CSR_3); + + /* GTY_DIFF_CTL */ + p->mp_reg_gty_diff_ctl = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_DIFF_CTL); + p->mp_field_gty_gty_diff_ctl_tx_diff_ctl0 = + nthw_register_get_field(p->mp_reg_gty_diff_ctl, + MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_0); + p->mp_field_gty_gty_diff_ctl_tx_diff_ctl1 = + nthw_register_get_field(p->mp_reg_gty_diff_ctl, + MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_1); + p->mp_field_gty_gty_diff_ctl_tx_diff_ctl2 = + nthw_register_get_field(p->mp_reg_gty_diff_ctl, + MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_2); + p->mp_field_gty_gty_diff_ctl_tx_diff_ctl3 = + nthw_register_get_field(p->mp_reg_gty_diff_ctl, + MAC_PCS_GTY_DIFF_CTL_TX_DIFF_CTL_3); + + /* GTY_POST_CURSOR */ + p->mp_reg_gty_post_cursor = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_POST_CURSOR); + p->mp_field_gty_post_cursor_tx_post_csr0 = + nthw_register_get_field(p->mp_reg_gty_post_cursor, + MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_0); + p->mp_field_gty_post_cursor_tx_post_csr1 = + nthw_register_get_field(p->mp_reg_gty_post_cursor, + MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_1); + p->mp_field_gty_post_cursor_tx_post_csr2 = + nthw_register_get_field(p->mp_reg_gty_post_cursor, + MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_2); + p->mp_field_gty_post_cursor_tx_post_csr3 = + nthw_register_get_field(p->mp_reg_gty_post_cursor, + MAC_PCS_GTY_POST_CURSOR_TX_POST_CSR_3); + + /* GTY_CTL */ + p->mp_reg_gty_ctl = nthw_module_query_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_CTL); + + if (p->mp_reg_gty_ctl) { + p->mp_field_gty_ctl_tx_pol0 = + nthw_register_get_field(p->mp_reg_gty_ctl, + MAC_PCS_GTY_CTL_TX_POLARITY_0); + p->mp_field_gty_ctl_tx_pol1 = + nthw_register_get_field(p->mp_reg_gty_ctl, + MAC_PCS_GTY_CTL_TX_POLARITY_1); + p->mp_field_gty_ctl_tx_pol2 = + nthw_register_get_field(p->mp_reg_gty_ctl, + MAC_PCS_GTY_CTL_TX_POLARITY_2); + p->mp_field_gty_ctl_tx_pol3 = + nthw_register_get_field(p->mp_reg_gty_ctl, + MAC_PCS_GTY_CTL_TX_POLARITY_3); + + } else { + p->mp_reg_gty_ctl = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_CTL_RX); + p->mp_reg_gty_ctl_tx = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_GTY_CTL_TX); + p->mp_field_gty_ctl_tx_pol0 = + nthw_register_get_field(p->mp_reg_gty_ctl_tx, + MAC_PCS_GTY_CTL_TX_POLARITY_0); + p->mp_field_gty_ctl_tx_pol1 = + nthw_register_get_field(p->mp_reg_gty_ctl_tx, + MAC_PCS_GTY_CTL_TX_POLARITY_1); + p->mp_field_gty_ctl_tx_pol2 = + nthw_register_get_field(p->mp_reg_gty_ctl_tx, + MAC_PCS_GTY_CTL_TX_POLARITY_2); + p->mp_field_gty_ctl_tx_pol3 = + nthw_register_get_field(p->mp_reg_gty_ctl_tx, + MAC_PCS_GTY_CTL_TX_POLARITY_3); + } + + p->mp_field_gty_ctl_rx_pol0 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_POLARITY_0); + p->mp_field_gty_ctl_rx_pol1 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_POLARITY_1); + p->mp_field_gty_ctl_rx_pol2 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_POLARITY_2); + p->mp_field_gty_ctl_rx_pol3 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_POLARITY_3); + p->mp_field_gty_ctl_rx_lpm_en0 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_LPM_EN_0); + p->mp_field_gty_ctl_rx_lpm_en1 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_LPM_EN_1); + p->mp_field_gty_ctl_rx_lpm_en2 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_LPM_EN_2); + p->mp_field_gty_ctl_rx_lpm_en3 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_LPM_EN_3); + p->mp_field_gty_ctl_rx_equa_rst0 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_EQUA_RST_0); + p->mp_field_gty_ctl_rx_equa_rst1 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_EQUA_RST_1); + p->mp_field_gty_ctl_rx_equa_rst2 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_EQUA_RST_2); + p->mp_field_gty_ctl_rx_equa_rst3 = + nthw_register_get_field(p->mp_reg_gty_ctl, MAC_PCS_GTY_CTL_RX_EQUA_RST_3); + + /* DEBOUNCE_CTRL */ + p->mp_reg_debounce_ctrl = + nthw_module_get_register(p->mp_mod_mac_pcs, MAC_PCS_DEBOUNCE_CTRL); + p->mp_field_debounce_ctrl_nt_port_ctrl = + nthw_register_get_field(p->mp_reg_debounce_ctrl, + MAC_PCS_DEBOUNCE_CTRL_NT_PORT_CTRL); + + p->mp_reg_time_stamp_comp = + nthw_module_query_register(p->mp_mod_mac_pcs, MAC_PCS_TIMESTAMP_COMP); + + if (p->mp_reg_time_stamp_comp) { + /* TIMESTAMP_COMP */ + p->mp_field_time_stamp_comp_rx_dly = + nthw_register_get_field(p->mp_reg_time_stamp_comp, + MAC_PCS_TIMESTAMP_COMP_RX_DLY); + p->mp_field_time_stamp_comp_tx_dly = + nthw_register_get_field(p->mp_reg_time_stamp_comp, + MAC_PCS_TIMESTAMP_COMP_TX_DLY); + } + } + return 0; +} + +void nthw_mac_pcs_set_rx_enable(nthw_mac_pcs_t *p, bool enable) +{ + nthw_field_get_updated(p->mp_fld_pcs_config_rx_enable); + + if (enable) + nthw_field_set_flush(p->mp_fld_pcs_config_rx_enable); + + else + nthw_field_clr_flush(p->mp_fld_pcs_config_rx_enable); +} + +void nthw_mac_pcs_set_tx_enable(nthw_mac_pcs_t *p, bool enable) +{ + nthw_field_get_updated(p->mp_fld_pcs_config_tx_enable); + + if (enable) + nthw_field_set_flush(p->mp_fld_pcs_config_tx_enable); + + else + nthw_field_clr_flush(p->mp_fld_pcs_config_tx_enable); +} + +void nthw_mac_pcs_set_tx_sel_host(nthw_mac_pcs_t *p, bool enable) +{ + nthw_field_get_updated(p->mp_fld_phymac_misc_tx_sel_host); + + if (enable) + nthw_field_set_flush(p->mp_fld_phymac_misc_tx_sel_host); + + else + nthw_field_clr_flush(p->mp_fld_phymac_misc_tx_sel_host); +} + +void nthw_mac_pcs_set_tx_sel_tfg(nthw_mac_pcs_t *p, bool enable) +{ + nthw_field_get_updated(p->mp_fld_phymac_misc_tx_sel_tfg); + + if (enable) + nthw_field_set_flush(p->mp_fld_phymac_misc_tx_sel_tfg); + + else + nthw_field_clr_flush(p->mp_fld_phymac_misc_tx_sel_tfg); +} + +void nthw_mac_pcs_set_ts_eop(nthw_mac_pcs_t *p, bool enable) +{ + if (p->mp_fld_phymac_misc_ts_eop) { + nthw_field_get_updated(p->mp_fld_phymac_misc_ts_eop); + + if (enable) + nthw_field_set_flush(p->mp_fld_phymac_misc_ts_eop); + + else + nthw_field_clr_flush(p->mp_fld_phymac_misc_ts_eop); + } +} + +void nthw_mac_pcs_tx_path_rst(nthw_mac_pcs_t *p, bool enable) +{ + nthw_field_get_updated(p->mp_fld_pcs_config_tx_path_rst); + + if (enable) + nthw_field_set_flush(p->mp_fld_pcs_config_tx_path_rst); + + else + nthw_field_clr_flush(p->mp_fld_pcs_config_tx_path_rst); +} + +void nthw_mac_pcs_rx_path_rst(nthw_mac_pcs_t *p, bool enable) +{ + nthw_field_get_updated(p->mp_fld_pcs_config_rx_path_rst); + + if (enable) + nthw_field_set_flush(p->mp_fld_pcs_config_rx_path_rst); + + else + nthw_field_clr_flush(p->mp_fld_pcs_config_rx_path_rst); +} + +bool nthw_mac_pcs_is_rx_path_rst(nthw_mac_pcs_t *p) +{ + return nthw_field_get_updated(p->mp_fld_pcs_config_rx_path_rst); +} + +void nthw_mac_pcs_set_host_loopback(nthw_mac_pcs_t *p, bool enable) +{ + nthw_register_update(p->mp_reg_gty_loop); + + if (enable) { + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop0, 2); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop1, 2); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop2, 2); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop3, 2); + + } else { + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop0, 0); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop1, 0); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop2, 0); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop3, 0); + } + + nthw_register_flush(p->mp_reg_gty_loop, 1); +} + +void nthw_mac_pcs_set_line_loopback(nthw_mac_pcs_t *p, bool enable) +{ + nthw_register_update(p->mp_reg_gty_loop); + + if (enable) { + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop0, 4); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop1, 4); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop2, 4); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop3, 4); + + } else { + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop0, 0); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop1, 0); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop2, 0); + nthw_field_set_val32(p->mp_fld_gty_loop_gt_loop3, 0); + } + + nthw_register_flush(p->mp_reg_gty_loop, 1); +} + +void nthw_mac_pcs_reset_bip_counters(nthw_mac_pcs_t *p) +{ + uint32_t lane_bit_errors[NTHW_MAC_PCS_LANES]; + nthw_register_update(p->mp_reg_bip_err); + nthw_field_get_val(p->mp_fld_reg_bip_err_bip_err, (uint32_t *)lane_bit_errors, + ARRAY_SIZE(lane_bit_errors)); + + (void)c_pcs_lanes; /* unused - kill warning */ +} + +bool nthw_mac_pcs_get_hi_ber(nthw_mac_pcs_t *p) +{ + return nthw_field_get_updated(p->mp_fld_stat_pcs_rx_hi_ber); +} + +void nthw_mac_pcs_get_link_summary(nthw_mac_pcs_t *p, + uint32_t *p_abs, + uint32_t *p_nt_phy_link_state, + uint32_t *p_lh_abs, + uint32_t *p_ll_nt_phy_link_state, + uint32_t *p_link_down_cnt, + uint32_t *p_nim_interr, + uint32_t *p_lh_local_fault, + uint32_t *p_lh_remote_fault, + uint32_t *p_local_fault, + uint32_t *p_remote_fault) +{ + nthw_register_update(p->mp_reg_link_summary); + + if (p_abs) + *p_abs = nthw_field_get_val32(p->mp_fld_link_summary_abs); + + if (p_nt_phy_link_state) { + *p_nt_phy_link_state = + nthw_field_get_val32(p->mp_fld_link_summary_nt_phy_link_state); + } + + if (p_lh_abs) + *p_lh_abs = nthw_field_get_val32(p->mp_fld_link_summary_lh_abs); + + if (p_ll_nt_phy_link_state) { + *p_ll_nt_phy_link_state = + nthw_field_get_val32(p->mp_fld_link_summary_ll_nt_phy_link_state); + } + + if (p_link_down_cnt) + *p_link_down_cnt = nthw_field_get_val32(p->mp_fld_link_summary_link_down_cnt); + + if (p_nim_interr) + *p_nim_interr = nthw_field_get_val32(p->mp_fld_link_summary_nim_interr); + + if (p_lh_local_fault) + *p_lh_local_fault = nthw_field_get_val32(p->mp_fld_link_summary_lh_local_fault); + + if (p_lh_remote_fault) + *p_lh_remote_fault = nthw_field_get_val32(p->mp_fld_link_summary_lh_remote_fault); + + if (p_local_fault) + *p_local_fault = nthw_field_get_val32(p->mp_fld_link_summary_local_fault); + + if (p_remote_fault) + *p_remote_fault = nthw_field_get_val32(p->mp_fld_link_summary_remote_fault); +} + +/* + * Returns true if the lane/block lock bits indicate that a reset is required. + * This is the case if Block/Lane lock is not all zero but not all set either. + */ +bool nthw_mac_pcs_reset_required(nthw_mac_pcs_t *p) +{ + uint32_t block_lock = nthw_mac_pcs_get_fld_block_lock_lock(p); + uint32_t lane_lock = nthw_mac_pcs_get_fld_lane_lock_lock(p); + uint32_t block_lock_mask = nthw_mac_pcs_get_fld_block_lock_lock_mask(p); + uint32_t lane_lock_mask = nthw_mac_pcs_get_fld_lane_lock_lock_mask(p); + + return ((block_lock != 0) && (block_lock != block_lock_mask)) || + ((lane_lock != 0) && (lane_lock != lane_lock_mask)); +} + +void nthw_mac_pcs_set_fec(nthw_mac_pcs_t *p, bool enable) +{ + NT_LOG(DBG, NTHW, "Port %u: Set FEC: %u\n", p->m_port_no, enable); + + nthw_field_get_updated(p->mp_field_fec_ctrl_reg_rs_fec_ctrl_in); + + if (enable) + nthw_field_set_val_flush32(p->mp_field_fec_ctrl_reg_rs_fec_ctrl_in, 0); + + else + nthw_field_set_val_flush32(p->mp_field_fec_ctrl_reg_rs_fec_ctrl_in, (1 << 5) - 1); + + /* Both Rx and Tx must be reset for new FEC state to become active */ + nthw_mac_pcs_rx_path_rst(p, true); + nthw_mac_pcs_tx_path_rst(p, true); + nt_os_wait_usec(10000); /* 10ms */ + + nthw_mac_pcs_rx_path_rst(p, false); + nthw_mac_pcs_tx_path_rst(p, false); + nt_os_wait_usec(10000); /* 10ms */ +} + +bool nthw_mac_pcs_get_fec_bypass(nthw_mac_pcs_t *p) +{ + return nthw_field_get_updated(p->mp_field_fec_stat_bypass); +} + +bool nthw_mac_pcs_get_fec_valid(nthw_mac_pcs_t *p) +{ + return nthw_field_get_updated(p->mp_field_fec_stat_valid); +} + +bool nthw_mac_pcs_get_fec_stat_all_am_locked(nthw_mac_pcs_t *p) +{ + nthw_register_update(p->mp_reg_fec_stat); + + if ((nthw_field_get_val32(p->mp_field_fec_stat_am_lock0)) && + (nthw_field_get_val32(p->mp_field_fec_stat_am_lock1)) && + (nthw_field_get_val32(p->mp_field_fec_stat_am_lock2)) && + (nthw_field_get_val32(p->mp_field_fec_stat_am_lock3))) { + return true; + } + + return false; +} + +void nthw_mac_pcs_reset_fec_counters(nthw_mac_pcs_t *p) +{ + nthw_register_update(p->mp_reg_fec_cw_cnt); + nthw_register_update(p->mp_reg_fec_ucw_cnt); + + if (nthw_field_get_val32(p->mp_field_fec_cw_cnt_cw_cnt)) { + NT_LOG(DBG, NTHW, "Port %u: FEC_CW_CNT: %u\n", p->m_port_no, + nthw_field_get_val32(p->mp_field_fec_cw_cnt_cw_cnt)); + } + + if (nthw_field_get_val32(p->mp_field_fec_ucw_cnt_ucw_cnt)) { + NT_LOG(DBG, NTHW, "Port %u: FEC_UCW_CNT: %u\n", p->m_port_no, + nthw_field_get_val32(p->mp_field_fec_ucw_cnt_ucw_cnt)); + } +} + +void nthw_mac_pcs_set_gty_tx_tuning(nthw_mac_pcs_t *p, uint8_t lane, uint8_t tx_pre_csr, + uint8_t tx_diff_ctl, uint8_t tx_post_csr) +{ + /* GTY_PRE_CURSOR */ + nthw_register_update(p->mp_reg_gty_pre_cursor); + + switch (lane) { + case 0: + nthw_field_set_val_flush32(p->mp_field_gty_pre_cursor_tx_pre_csr0, + tx_pre_csr & 0x1F); + break; + + case 1: + nthw_field_set_val_flush32(p->mp_field_gty_pre_cursor_tx_pre_csr1, + tx_pre_csr & 0x1F); + break; + + case 2: + nthw_field_set_val_flush32(p->mp_field_gty_pre_cursor_tx_pre_csr2, + tx_pre_csr & 0x1F); + break; + + case 3: + nthw_field_set_val_flush32(p->mp_field_gty_pre_cursor_tx_pre_csr3, + tx_pre_csr & 0x1F); + break; + } + + /* GTY_DIFF_CTL */ + nthw_register_update(p->mp_reg_gty_diff_ctl); + + switch (lane) { + case 0: + nthw_field_set_val_flush32(p->mp_field_gty_gty_diff_ctl_tx_diff_ctl0, + tx_diff_ctl & 0x1F); + break; + + case 1: + nthw_field_set_val_flush32(p->mp_field_gty_gty_diff_ctl_tx_diff_ctl1, + tx_diff_ctl & 0x1F); + break; + + case 2: + nthw_field_set_val_flush32(p->mp_field_gty_gty_diff_ctl_tx_diff_ctl2, + tx_diff_ctl & 0x1F); + break; + + case 3: + nthw_field_set_val_flush32(p->mp_field_gty_gty_diff_ctl_tx_diff_ctl3, + tx_diff_ctl & 0x1F); + break; + } + + /* GTY_POST_CURSOR */ + nthw_register_update(p->mp_reg_gty_post_cursor); + + switch (lane) { + case 0: + nthw_field_set_val_flush32(p->mp_field_gty_post_cursor_tx_post_csr0, + tx_post_csr & 0x1F); + break; + + case 1: + nthw_field_set_val_flush32(p->mp_field_gty_post_cursor_tx_post_csr1, + tx_post_csr & 0x1F); + break; + + case 2: + nthw_field_set_val_flush32(p->mp_field_gty_post_cursor_tx_post_csr2, + tx_post_csr & 0x1F); + break; + + case 3: + nthw_field_set_val_flush32(p->mp_field_gty_post_cursor_tx_post_csr3, + tx_post_csr & 0x1F); + break; + } + + NT_LOG(DBG, NTHW, + "Port %u, lane %u: GTY tx_pre_csr: %d, tx_diff_ctl: %d, tx_post_csr: %d\n", + p->m_port_no, lane, tx_pre_csr, tx_diff_ctl, tx_post_csr); +} + +/* + * Set receiver equalization mode + * 0: enable DFE + * 1: enable LPM + * + * See UltraScale Architecture GTY Transceivers www.xilinx.com page 181, + * UG578 (v1.1) November 24, 2015 + */ +void nthw_mac_pcs_set_receiver_equalization_mode(nthw_mac_pcs_t *p, uint8_t mode) +{ + nthw_register_update(p->mp_reg_gty_ctl); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_lpm_en0, mode & 0x1); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_lpm_en1, mode & 0x1); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_lpm_en2, mode & 0x1); + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_lpm_en3, mode & 0x1); + + /* Toggle reset */ + nthw_field_set_val32(p->mp_field_gty_ctl_rx_equa_rst0, 1); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_equa_rst1, 1); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_equa_rst2, 1); + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_equa_rst3, 1); + + nt_os_wait_usec(1000); /* 1ms */ + + nthw_field_set_val32(p->mp_field_gty_ctl_rx_equa_rst0, 0); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_equa_rst1, 0); + nthw_field_set_val32(p->mp_field_gty_ctl_rx_equa_rst2, 0); + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_equa_rst3, 0); + + NT_LOG(DBG, NTHW, "Port %u: GTY receiver mode: %s\n", p->m_port_no, + (mode == c_mac_pcs_receiver_mode_dfe ? "DFE" : "LPM")); +} + +void nthw_mac_pcs_swap_gty_tx_polarity(nthw_mac_pcs_t *p, uint8_t lane, bool swap) +{ + nthw_register_update(p->mp_reg_gty_ctl); + + switch (lane) { + case 0: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_tx_pol0, swap); + break; + + case 1: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_tx_pol1, swap); + break; + + case 2: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_tx_pol2, swap); + break; + + case 3: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_tx_pol3, swap); + break; + } + + NT_LOG(DBG, NTHW, "Port %u: set GTY Tx lane (%d) polarity: %d\n", p->m_port_no, lane, + swap); +} + +void nthw_mac_pcs_swap_gty_rx_polarity(nthw_mac_pcs_t *p, uint8_t lane, bool swap) +{ + nthw_register_update(p->mp_reg_gty_ctl); + + switch (lane) { + case 0: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_pol0, swap); + break; + + case 1: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_pol1, swap); + break; + + case 2: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_pol2, swap); + break; + + case 3: + nthw_field_set_val_flush32(p->mp_field_gty_ctl_rx_pol3, swap); + break; + } + + NT_LOG(DBG, NTHW, "Port %u: set GTY Rx lane (%d) polarity: %d\n", p->m_port_no, lane, + swap); +} + +void nthw_mac_pcs_set_led_mode(nthw_mac_pcs_t *p, uint8_t mode) +{ + nthw_field_get_updated(p->mp_field_debounce_ctrl_nt_port_ctrl); + nthw_field_set_val_flush32(p->mp_field_debounce_ctrl_nt_port_ctrl, mode); +} + +void nthw_mac_pcs_set_timestamp_comp_rx(nthw_mac_pcs_t *p, uint16_t rx_dly) +{ + if (p->mp_field_time_stamp_comp_rx_dly) { + nthw_field_get_updated(p->mp_field_time_stamp_comp_rx_dly); + nthw_field_set_val_flush32(p->mp_field_time_stamp_comp_rx_dly, rx_dly); + } +} + +void nthw_mac_pcs_set_port_no(nthw_mac_pcs_t *p, uint8_t port_no) +{ + p->m_port_no = port_no; +} + +uint32_t nthw_mac_pcs_get_fld_block_lock_lock(nthw_mac_pcs_t *p) +{ + return nthw_field_get_updated(p->mp_fld_block_lock_lock); +} + +uint32_t nthw_mac_pcs_get_fld_block_lock_lock_mask(nthw_mac_pcs_t *p) +{ + return p->m_fld_block_lock_lock_mask; +} + +uint32_t nthw_mac_pcs_get_fld_lane_lock_lock(nthw_mac_pcs_t *p) +{ + return nthw_field_get_updated(p->mp_fld_vl_demuxed_lock); +} + +uint32_t nthw_mac_pcs_get_fld_lane_lock_lock_mask(nthw_mac_pcs_t *p) +{ + return p->m_fld_vl_demuxed_lock_mask; +}