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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF0001A0FB.mail.protection.outlook.com (10.167.242.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.11 via Frontend Transport; Fri, 26 Jul 2024 01:50:30 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 25 Jul 2024 18:50:18 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 25 Jul 2024 18:50:15 -0700 From: Jiawei Wang To: , , Dariusz Sosnowski , Ori Kam , Suanming Mou , Matan Azrad , Gregory Etelson CC: , , Subject: [PATCH] net/mlx5: fix NVGRE item validation for template API Date: Fri, 26 Jul 2024 04:49:58 +0300 Message-ID: <20240726014958.43843-1-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|SA0PR12MB7076:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ba7b711-b6af-479f-76f9-08dcad1554f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jul 2024 01:50:30.9678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ba7b711-b6af-479f-76f9-08dcad1554f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7076 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The template API NVGRE item can support full mask. This patch updates default NVGRE item mask for the template API. Fixes: 80c676259a04 ("net/mlx5: validate HWS template items") Cc: stable@dpdk.org Signed-off-by: Jiawei Wang Acked-by: Bing Zhao Signed-off-by: Jiawei Wang Acked-by: Bing Zhao --- drivers/net/mlx5/mlx5_flow.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 72fb3a55ba..14720f54ab 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -3867,6 +3867,15 @@ mlx5_flow_validate_item_nvgre(const struct rte_eth_dev *dev, const struct rte_flow_item_nvgre *mask = item->mask; int ret; + const struct rte_flow_item_nvgre hws_nic_mask = { + .c_k_s_rsvd0_ver = RTE_BE16(0xB000), + .protocol = RTE_BE16(UINT16_MAX), + .tni = {0xff, 0xff, 0xff}, + .flow_id = 0xff + }; + const struct rte_flow_item_nvgre *nic_mask = !mlx5_hws_active(dev) ? + &rte_flow_item_nvgre_mask : &hws_nic_mask; + if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, @@ -3884,10 +3893,10 @@ mlx5_flow_validate_item_nvgre(const struct rte_eth_dev *dev, item, "L3 Layer is missing"); } if (!mask) - mask = &rte_flow_item_nvgre_mask; + mask = nic_mask; ret = mlx5_flow_item_acceptable (dev, item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_nvgre_mask, + (const uint8_t *)nic_mask, sizeof(struct rte_flow_item_nvgre), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); if (ret < 0)