From patchwork Fri Jul 26 17:15:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wathsala Wathawana Vithanage X-Patchwork-Id: 142739 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE9E8456A3; Fri, 26 Jul 2024 19:16:01 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C1FEB4325C; Fri, 26 Jul 2024 19:15:47 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 3F0A242EE0 for ; Fri, 26 Jul 2024 19:15:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7EE421655; Fri, 26 Jul 2024 10:16:07 -0700 (PDT) Received: from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com [10.118.91.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 94FD53F5A1; Fri, 26 Jul 2024 10:15:41 -0700 (PDT) From: Wathsala Vithanage To: Thomas Monjalon , Ruifeng Wang Cc: honnappa.nagarahalli@arm.com, dev@dpdk.org, Wathsala Vithanage , Dhruv Tripathi Subject: [PATCH v4 1/4] eal: expand the availability of WFE and related instructions Date: Fri, 26 Jul 2024 17:15:24 +0000 Message-Id: <20240726171528.2245682-1-wathsala.vithanage@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604044401.3577707-1-wathsala.vithanage@arm.com> References: <20240604044401.3577707-1-wathsala.vithanage@arm.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The availability of __RTE_ARM_WFE, __RTE_ARM_SEV, __RTE_ARM_SEVL, and __RTE_ARM_LOAD_EXC_* macros for other applications, such as PMD power management, should not depend on the choice of use of these instructions in rte_wait_until_equal_N functions. Therefore, this patch moves these macros out of control of the RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED macro. Signed-off-by: Wathsala Vithanage Reviewed-by: Dhruv Tripathi --- .mailmap | 1 + lib/eal/arm/include/rte_pause_64.h | 4 ++-- lib/eal/arm/rte_cpuflags.c | 4 ++-- lib/eal/arm/rte_power_intrinsics.c | 9 ++++----- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/.mailmap b/.mailmap index f1e64286a1..9c28b74655 100644 --- a/.mailmap +++ b/.mailmap @@ -338,6 +338,7 @@ Dexia Li Dexuan Cui Dharmik Thakkar Dheemanth Mallikarjun +Dhruv Tripathi Diana Wang Didier Pallard Dilshod Urazov diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h index 9e2dbf3531..8224f09ba7 100644 --- a/lib/eal/arm/include/rte_pause_64.h +++ b/lib/eal/arm/include/rte_pause_64.h @@ -24,8 +24,6 @@ static inline void rte_pause(void) asm volatile("yield" ::: "memory"); } -#ifdef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED - /* Send a local event to quit WFE. */ #define __RTE_ARM_SEVL() { asm volatile("sevl" : : : "memory"); } @@ -148,6 +146,8 @@ static inline void rte_pause(void) __RTE_ARM_LOAD_EXC_128(src, dst, memorder) \ } +#ifdef RTE_WAIT_UNTIL_EQUAL_ARCH_DEFINED + static __rte_always_inline void rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, rte_memory_order memorder) diff --git a/lib/eal/arm/rte_cpuflags.c b/lib/eal/arm/rte_cpuflags.c index 7ba4f8ba97..29884c285f 100644 --- a/lib/eal/arm/rte_cpuflags.c +++ b/lib/eal/arm/rte_cpuflags.c @@ -163,7 +163,7 @@ void rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics) { memset(intrinsics, 0, sizeof(*intrinsics)); -#ifdef RTE_ARM_USE_WFE +#ifdef RTE_ARCH_64 intrinsics->power_monitor = 1; -#endif +#endif /* RTE_ARCH_64 */ } diff --git a/lib/eal/arm/rte_power_intrinsics.c b/lib/eal/arm/rte_power_intrinsics.c index f54cf59e80..b0056cce8b 100644 --- a/lib/eal/arm/rte_power_intrinsics.c +++ b/lib/eal/arm/rte_power_intrinsics.c @@ -17,7 +17,7 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc, { RTE_SET_USED(tsc_timestamp); -#ifdef RTE_ARM_USE_WFE +#ifdef RTE_ARCH_64 const unsigned int lcore_id = rte_lcore_id(); uint64_t cur_value; @@ -57,7 +57,7 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc, RTE_SET_USED(pmc); return -ENOTSUP; -#endif +#endif /* RTE_ARCH_64 */ } /** @@ -81,13 +81,12 @@ rte_power_monitor_wakeup(const unsigned int lcore_id) { RTE_SET_USED(lcore_id); -#ifdef RTE_ARM_USE_WFE +#ifdef RTE_ARCH_64 __RTE_ARM_SEV() - return 0; #else return -ENOTSUP; -#endif +#endif /* RTE_ARCH_64 */ } int From patchwork Fri Jul 26 17:15:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wathsala Wathawana Vithanage X-Patchwork-Id: 142736 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 505B9456A3; Fri, 26 Jul 2024 19:15:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B2E942E4C; Fri, 26 Jul 2024 19:15:44 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id AD7AB410F6 for ; Fri, 26 Jul 2024 19:15:42 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 73BE61042; Fri, 26 Jul 2024 10:16:07 -0700 (PDT) Received: from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com [10.118.91.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BED043F8A4; Fri, 26 Jul 2024 10:15:41 -0700 (PDT) From: Wathsala Vithanage To: Ruifeng Wang , Bruce Richardson Cc: honnappa.nagarahalli@arm.com, dev@dpdk.org, Wathsala Vithanage , Dhruv Tripathi Subject: [PATCH v4 2/4] config/arm: adds Arm Neoverse N3 SoC Date: Fri, 26 Jul 2024 17:15:25 +0000 Message-Id: <20240726171528.2245682-2-wathsala.vithanage@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240726171528.2245682-1-wathsala.vithanage@arm.com> References: <20240604044401.3577707-1-wathsala.vithanage@arm.com> <20240726171528.2245682-1-wathsala.vithanage@arm.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add Arm Neoverse N3 part number to build configuration. Signed-off-by: Wathsala Vithanage Reviewed-by: Dhruv Tripathi --- config/arm/meson.build | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 012935d5d7..acf8e933ab 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -116,6 +116,27 @@ part_number_config_arm = { ['RTE_MAX_LCORE', 144], ['RTE_MAX_NUMA_NODES', 2] ] + }, + '0xd8e': { +# Only when -march=armv9-a+wfxt is used will the WFET +# feature be compiled with armv9 instructions. +# However, +wfxt is not supported by GCC at the moment. +# Although armv9-a is the fitting version of Arm ISA for +# Neoverse N3, it cannot be used when enabling wfxt for +# the above reasons. +# The workaround for this is to use armv8.7-a, which +# doesn't require +wfxt for binutils version 2.36 or +# greater. + 'march': 'armv8.7-a', + 'march_features': ['sve2'], + 'fallback_march': 'armv8.5-a', + 'flags': [ + ['RTE_MACHINE', '"neoverse-n3"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_ARM_FEATURE_WFXT', true], + ['RTE_MAX_LCORE', 192], + ['RTE_MAX_NUMA_NODES', 2] + ] } } implementer_arm = { @@ -572,6 +593,13 @@ soc_n2 = { 'numa': false } +soc_n3 = { + 'description': 'Arm Neoverse N3', + 'implementer': '0x41', + 'part_number': '0xd8e', + 'numa': false +} + soc_odyssey = { 'description': 'Marvell Odyssey', 'implementer': '0x41', @@ -699,6 +727,7 @@ socs = { 'kunpeng930': soc_kunpeng930, 'n1sdp': soc_n1sdp, 'n2': soc_n2, + 'n3': soc_n3, 'odyssey' : soc_odyssey, 'stingray': soc_stingray, 'thunderx2': soc_thunderx2, @@ -852,7 +881,7 @@ if update_flags if part_number_config.get('force_march', false) candidate_march = part_number_config['march'] else - supported_marchs = ['armv9-a', 'armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', + supported_marchs = ['armv9-a', 'armv8.7-a', 'armv8.6-a', 'armv8.5-a', 'armv8.4-a', 'armv8.3-a', 'armv8.2-a', 'armv8.1-a', 'armv8-a'] check_compiler_support = false foreach supported_march: supported_marchs From patchwork Fri Jul 26 17:15:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Wathsala Wathawana Vithanage X-Patchwork-Id: 142737 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A629B456A3; Fri, 26 Jul 2024 19:15:49 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C3A242FBB; Fri, 26 Jul 2024 19:15:45 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id DF03642E4C for ; Fri, 26 Jul 2024 19:15:42 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C49901007; Fri, 26 Jul 2024 10:16:07 -0700 (PDT) Received: from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com [10.118.91.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EEF453FB75; Fri, 26 Jul 2024 10:15:41 -0700 (PDT) From: Wathsala Vithanage To: Thomas Monjalon , Tyler Retzlaff , Ruifeng Wang Cc: honnappa.nagarahalli@arm.com, dev@dpdk.org, Wathsala Vithanage , Dhruv Tripathi , Jack Bond-Preston , Nick Connolly , Vinod Krishna Subject: [PATCH v4 3/4] eal: add Arm WFET in power management intrinsics Date: Fri, 26 Jul 2024 17:15:26 +0000 Message-Id: <20240726171528.2245682-3-wathsala.vithanage@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240726171528.2245682-1-wathsala.vithanage@arm.com> References: <20240604044401.3577707-1-wathsala.vithanage@arm.com> <20240726171528.2245682-1-wathsala.vithanage@arm.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Wait for event with timeout (WFET) puts the CPU in a low power mode and stays there until an event is signalled (SEV), loss of an exclusive monitor or a timeout. WFET is enabled selectively by checking FEAT_WFxT in Linux auxiliary vector. If FEAT_WFxT is not available power management will fallback to WFE. WFE is available on all the Arm platforms supported by DPDK. Therefore, the RTE_ARM_USE_WFE macro is not required to enable the WFE feature for PMD power monitoring.  RTE_ARM_USE_WFE is used at the build time to use the WFE instruction where applicable in the code at the developer's discretion rather than as an indicator of the instruction's availability. Signed-off-by: Wathsala Vithanage Reviewed-by: Dhruv Tripathi Reviewed-by: Honnappa Nagarahalli Reviewed-by: Jack Bond-Preston Reviewed-by: Nick Connolly Reviewed-by: Vinod Krishna --- .mailmap | 1 + app/test/test_cpuflags.c | 3 +++ lib/eal/arm/include/rte_cpuflags_64.h | 3 +++ lib/eal/arm/include/rte_pause_64.h | 16 +++++++++-- lib/eal/arm/rte_cpuflags.c | 1 + lib/eal/arm/rte_power_intrinsics.c | 39 ++++++++++++++++++--------- 6 files changed, 49 insertions(+), 14 deletions(-) diff --git a/.mailmap b/.mailmap index 9c28b74655..a5c49d3702 100644 --- a/.mailmap +++ b/.mailmap @@ -1540,6 +1540,7 @@ Vincent Li Vincent S. Cojot Vinh Tran Vipin Padmam Ramesh +Vinod Krishna Vipin Varghese Vipul Ashri Visa Hankala diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c index a0ff74720c..22ab4dff0a 100644 --- a/app/test/test_cpuflags.c +++ b/app/test/test_cpuflags.c @@ -156,6 +156,9 @@ test_cpuflags(void) printf("Check for SVEBF16:\t"); CHECK_FOR_FLAG(RTE_CPUFLAG_SVEBF16); + + printf("Check for WFXT:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_WFXT); #endif #if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) diff --git a/lib/eal/arm/include/rte_cpuflags_64.h b/lib/eal/arm/include/rte_cpuflags_64.h index afe70209c3..993d980a02 100644 --- a/lib/eal/arm/include/rte_cpuflags_64.h +++ b/lib/eal/arm/include/rte_cpuflags_64.h @@ -36,6 +36,9 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_SVEF64MM, RTE_CPUFLAG_SVEBF16, RTE_CPUFLAG_AARCH64, + + /* WFET and WFIT instructions */ + RTE_CPUFLAG_WFXT, }; #include "generic/rte_cpuflags.h" diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte_pause_64.h index 8224f09ba7..809403bffa 100644 --- a/lib/eal/arm/include/rte_pause_64.h +++ b/lib/eal/arm/include/rte_pause_64.h @@ -24,15 +24,27 @@ static inline void rte_pause(void) asm volatile("yield" ::: "memory"); } -/* Send a local event to quit WFE. */ +/* Send a local event to quit WFE/WFxT. */ #define __RTE_ARM_SEVL() { asm volatile("sevl" : : : "memory"); } -/* Send a global event to quit WFE for all cores. */ +/* Send a global event to quit WFE/WFxT for all cores. */ #define __RTE_ARM_SEV() { asm volatile("sev" : : : "memory"); } /* Put processor into low power WFE(Wait For Event) state. */ #define __RTE_ARM_WFE() { asm volatile("wfe" : : : "memory"); } +/* Put processor into low power WFET (WFE with Timeout) state. */ +#ifdef RTE_ARM_FEATURE_WFXT +#define __RTE_ARM_WFET(t) { \ + asm volatile("wfet %x[to]" \ + : \ + : [to] "r" (t) \ + : "memory"); \ + } +#else +#define __RTE_ARM_WFET(t) { RTE_SET_USED(t); } +#endif + /* * Atomic exclusive load from addr, it returns the 8-bit content of * *addr while making it 'monitored', when it is written by someone diff --git a/lib/eal/arm/rte_cpuflags.c b/lib/eal/arm/rte_cpuflags.c index 29884c285f..88e10c6da0 100644 --- a/lib/eal/arm/rte_cpuflags.c +++ b/lib/eal/arm/rte_cpuflags.c @@ -115,6 +115,7 @@ const struct feature_entry rte_cpu_feature_table[] = { FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) FEAT_DEF(SVEBF16, REG_HWCAP2, 12) + FEAT_DEF(WFXT, REG_HWCAP2, 31) FEAT_DEF(AARCH64, REG_PLATFORM, 0) }; #endif /* RTE_ARCH */ diff --git a/lib/eal/arm/rte_power_intrinsics.c b/lib/eal/arm/rte_power_intrinsics.c index b0056cce8b..6475bbca04 100644 --- a/lib/eal/arm/rte_power_intrinsics.c +++ b/lib/eal/arm/rte_power_intrinsics.c @@ -4,19 +4,32 @@ #include +#include "rte_cpuflags.h" #include "rte_power_intrinsics.h" /** - * This function uses WFE instruction to make lcore suspend + * Set wfet_en if WFET is supported + */ +#ifdef RTE_ARCH_64 +static uint8_t wfet_en; +#endif /* RTE_ARCH_64 */ + +RTE_INIT(rte_power_intrinsics_init) +{ +#ifdef RTE_ARCH_64 + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WFXT)) + wfet_en = 1; +#endif /* RTE_ARCH_64 */ +} + +/** + * This function uses WFE/WFET instruction to make lcore suspend * execution on ARM. - * Note that timestamp based timeout is not supported yet. */ int rte_power_monitor(const struct rte_power_monitor_cond *pmc, const uint64_t tsc_timestamp) { - RTE_SET_USED(tsc_timestamp); - #ifdef RTE_ARCH_64 const unsigned int lcore_id = rte_lcore_id(); uint64_t cur_value; @@ -33,28 +46,30 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc, switch (pmc->size) { case sizeof(uint8_t): - __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, rte_memory_order_relaxed) - __RTE_ARM_WFE() + __RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, rte_memory_order_relaxed); break; case sizeof(uint16_t): - __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, rte_memory_order_relaxed) - __RTE_ARM_WFE() + __RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, rte_memory_order_relaxed); break; case sizeof(uint32_t): - __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, rte_memory_order_relaxed) - __RTE_ARM_WFE() + __RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, rte_memory_order_relaxed); break; case sizeof(uint64_t): - __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, rte_memory_order_relaxed) - __RTE_ARM_WFE() + __RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, rte_memory_order_relaxed); break; default: return -EINVAL; /* unexpected size */ } + if (wfet_en) + __RTE_ARM_WFET(tsc_timestamp) + else + __RTE_ARM_WFE() + return 0; #else RTE_SET_USED(pmc); + RTE_SET_USED(tsc_timestamp); return -ENOTSUP; #endif /* RTE_ARCH_64 */ From patchwork Fri Jul 26 17:15:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wathsala Wathawana Vithanage X-Patchwork-Id: 142738 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B55E3456A3; Fri, 26 Jul 2024 19:15:55 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 97F4942FF9; Fri, 26 Jul 2024 19:15:46 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 1DE0E410F6 for ; Fri, 26 Jul 2024 19:15:43 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E4471165C; Fri, 26 Jul 2024 10:16:07 -0700 (PDT) Received: from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com [10.118.91.158]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 29C8B3F8A4; Fri, 26 Jul 2024 10:15:42 -0700 (PDT) From: Wathsala Vithanage To: Ruifeng Wang Cc: honnappa.nagarahalli@arm.com, dev@dpdk.org, Wathsala Vithanage , Dhruv Tripathi Subject: [PATCH v4 4/4] eal: describe Arm CPU features including WFXT Date: Fri, 26 Jul 2024 17:15:27 +0000 Message-Id: <20240726171528.2245682-4-wathsala.vithanage@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240726171528.2245682-1-wathsala.vithanage@arm.com> References: <20240604044401.3577707-1-wathsala.vithanage@arm.com> <20240726171528.2245682-1-wathsala.vithanage@arm.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add descriptive comments to each Arm feature listed in rte_cpu_flag_t. Signed-off-by: Wathsala Vithanage Reviewed-by: Honnappa Nagarahalli Reviewed-by: Dhruv Tripathi --- lib/eal/arm/include/rte_cpuflags_64.h | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/lib/eal/arm/include/rte_cpuflags_64.h b/lib/eal/arm/include/rte_cpuflags_64.h index 993d980a02..eed67bf6ec 100644 --- a/lib/eal/arm/include/rte_cpuflags_64.h +++ b/lib/eal/arm/include/rte_cpuflags_64.h @@ -13,28 +13,76 @@ extern "C" { * Enumeration of all CPU features supported */ enum rte_cpu_flag_t { + /* Floating point capability */ RTE_CPUFLAG_FP = 0, + + /* Arm Neon extension */ RTE_CPUFLAG_NEON, + + /* Generic timer event stream */ RTE_CPUFLAG_EVTSTRM, + + /* AES instructions */ RTE_CPUFLAG_AES, + + /* Polynomial multiply long instruction */ RTE_CPUFLAG_PMULL, + + /* SHA1 instructions */ RTE_CPUFLAG_SHA1, + + /* SHA2 instructions */ RTE_CPUFLAG_SHA2, + + /* CRC32 instruction */ RTE_CPUFLAG_CRC32, + + /* + * LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, + * CASP, and SWP instructions + */ RTE_CPUFLAG_ATOMICS, + + /* Arm SVE extension */ RTE_CPUFLAG_SVE, + + /* Arm SVE2 extension */ RTE_CPUFLAG_SVE2, + + /* SVE-AES instructions */ RTE_CPUFLAG_SVEAES, + + /* SVE-PMULL instruction */ RTE_CPUFLAG_SVEPMULL, + + /* SVE bit permute instructions */ RTE_CPUFLAG_SVEBITPERM, + + /* SVE-SHA3 instructions */ RTE_CPUFLAG_SVESHA3, + + /* SVE-SM4 instructions */ RTE_CPUFLAG_SVESM4, + + /* CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions */ RTE_CPUFLAG_FLAGM2, + + /* FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions */ RTE_CPUFLAG_FRINT, + + /* SVE Int8 matrix multiplication instructions */ RTE_CPUFLAG_SVEI8MM, + + /* SVE FP32 floating-point matrix multiplication instructions */ RTE_CPUFLAG_SVEF32MM, + + /* SVE FP64 floating-point matrix multiplication instructions */ RTE_CPUFLAG_SVEF64MM, + + /* SVE BFloat16 instructions */ RTE_CPUFLAG_SVEBF16, + + /* 64 bit execution state of the Arm architecture */ RTE_CPUFLAG_AARCH64, /* WFET and WFIT instructions */