From patchwork Thu Aug 1 04:40:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Soumyadeep Hore X-Patchwork-Id: 142803 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B59B345708; Thu, 1 Aug 2024 07:31:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8A048402BD; Thu, 1 Aug 2024 07:31:22 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by mails.dpdk.org (Postfix) with ESMTP id 8CC914027E; Thu, 1 Aug 2024 07:31:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1722490281; x=1754026281; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=scM0McVdLTgwfYISkf3l3JEhwJ/uH2dyjDRxzMNJ2Ag=; b=DvQzRuCt81ypXkNSRiWIIbRdb0dg8NE1GFn2rSNLgu4vbSlfMT7Cl/ou jYbWImUYQETte1cShJlXxV1wyxBPRtP1wyUud9JnfJC0U70saUdd9PufH 0j5wFvzSlvl33mpLOt0vY6evtFEKd3Yn49Bnn1aSoMzNa4sonqp3gPXp8 BWG0KrZMxQGZ8sbnx9Lf5f4wgwkLNvRvD31KUILnzpBEUGtsaXsr0XkaN L+nXMok84L+tGAvJ00HgeCORdAwP+34Sir0ORL/zAA9RHOCFfw0TuXw3Y i8Rr5+3DXYmhdUUwCLvGzQfA5OkZS2oolqzqdrRWsRBeByklVNW8sjyQF A==; X-CSE-ConnectionGUID: 0zFN4qeWTD+z7OiApNFGjA== X-CSE-MsgGUID: bczHysJ+SdCR9pyY4hBGFA== X-IronPort-AV: E=McAfee;i="6700,10204,11150"; a="20001794" X-IronPort-AV: E=Sophos;i="6.09,253,1716274800"; d="scan'208";a="20001794" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2024 22:31:19 -0700 X-CSE-ConnectionGUID: jqNtI9evQqyCFM1QAz04qQ== X-CSE-MsgGUID: XeVQjHFTQMqKE8hSFp+dDg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,253,1716274800"; d="scan'208";a="54831832" Received: from unknown (HELO npf-hyd-clx-03..) ([10.145.170.182]) by orviesa010.jf.intel.com with ESMTP; 31 Jul 2024 22:31:17 -0700 From: Soumyadeep Hore To: bruce.richardson@intel.com, anatoly.burakov@intel.com, aman.deep.singh@intel.com Cc: dev@dpdk.org, stable@dpdk.org Subject: [PATCH v1] net/ice: fix ice Rx timestamp for E822 NICs Date: Thu, 1 Aug 2024 04:40:15 +0000 Message-ID: <20240801044015.3204579-1-soumyadeep.hore@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org E822 PHY does not support switching from bypass to Vernier mode. Remove ice_phy_exit_bypass_e822() and program fixed offsets for bypass mode. Fixes: ce9ad8c5bc6d ("net/ice/base: remove PHY port timer bypass mode") Cc: stable@dpdk.org Signed-off-by: Soumyadeep Hore --- drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++++-- drivers/net/ice/base/ice_ptp_hw.h | 2 +- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 113 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 004f659eae..7041b54d7b 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -4465,18 +4465,103 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) return 0; } +/** + * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode + * @hw: pointer to the HW struct + * @port: the PHY port to configure + * + * Calculate and program the fixed Tx offset, and indicate that the offset is + * ready. This can be used when operating in bypass mode. + */ +static int ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) +{ + enum ice_ptp_link_spd link_spd; + enum ice_ptp_fec_mode fec_mode; + u64 total_offset; + int err; + + err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); + if (err) + return err; + + total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); + + /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L + * register, then indicate that the Tx offset is ready. After this, + * timestamps will be enabled. + * + * Note that this skips including the more precise offsets generated + * by the Vernier calibration. + */ + + err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, + total_offset); + if (err) + return err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); + if (err) + return err; + + return ICE_SUCCESS; +} + +/** + * ice_phy_cfg_rx_offset_e822 - Configure fixed Rx offset for bypass mode + * @hw: pointer to the HW struct + * @port: the PHY port to configure + * + * Calculate and program the fixed Rx offset, and indicate that the offset is + * ready. This can be used when operating in bypass mode. + */ +static int ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) +{ + enum ice_ptp_link_spd link_spd; + enum ice_ptp_fec_mode fec_mode; + u64 total_offset; + int err; + + err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); + if (err) + return err; + + total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); + + /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L + * register, then indicate that the Rx offset is ready. After this, + * timestamps will be enabled. + * + * Note that this skips including the more precise offsets generated + * by Vernier calibration. + */ + err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, + total_offset); + if (err) + return err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); + if (err) + return err; + + return ICE_SUCCESS; +} + /** * ice_start_phy_timer_e822 - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start + * @bypass: if true, start the PHY in bypass mode * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * - * Hardware will take Vernier measurements on Tx or Rx of packets. + * Bypass mode enables timestamps immediately without waiting for Vernier + * calibration to complete. Hardware will still continue taking Vernier + * measurements on Tx or Rx of packets, but they will not be applied to + * timestamps. */ -int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) +int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) { u32 lo, hi, val; u64 incval; @@ -4541,15 +4626,35 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) ice_ptp_exec_tmr_cmd(hw); + if (bypass) { + /* Enter BYPASS mode, enabling timestamps immediately. */ + val |= P_REG_PS_BYPASS_MODE_M; + err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); + if (err) + return err; + } + val |= P_REG_PS_ENA_CLK_M; err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); if (err) return err; - val |= P_REG_PS_LOAD_OFFSET_M; - err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (err) - return err; + if (bypass) { + /* Program the fixed Tx offset */ + err = ice_phy_cfg_fixed_tx_offset_e822(hw, port); + if (err) + return err; + + /* Program the fixed Rx offset */ + err = ice_phy_cfg_fixed_rx_offset_e822(hw, port); + if (err) + return err; + } else { + val |= P_REG_PS_LOAD_OFFSET_M; + err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); + if (err) + return err; + } ice_ptp_exec_tmr_cmd(hw); diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 9357dfd327..f4f6a2efdf 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -256,7 +256,7 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port, void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port); int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); -int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); +int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass); int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port); int diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 304f959b7e..5e96fb598c 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2500,7 +2500,7 @@ ice_dev_init(struct rte_eth_dev *dev) ice_ptp_init_phy_model(hw); if (hw->phy_model == ICE_PHY_E822) { - ret = ice_start_phy_timer_e822(hw, hw->pf_id); + ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer\n"); }