From patchwork Thu Sep 5 15:07:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 143674 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6BA764590E; Thu, 5 Sep 2024 17:07:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDBCB42E61; Thu, 5 Sep 2024 17:07:30 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by mails.dpdk.org (Postfix) with ESMTP id 1D7BF427E7 for ; Thu, 5 Sep 2024 17:07:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725548849; x=1757084849; h=from:to:cc:subject:date:message-id; bh=tIYtbfYZNl35VBau4tJ9/NCWmhFrGPIrFcSksGnGr0w=; b=a8mvovLT95EjQ0SU9pII0PM/v67dYGYv0tuQRlnIzs6CALSH8KvkE239 K2yeE8G0rVWGLmWNVtZSYgysw+O7apdw7FJpMkxnR7bHGKJ6OG068YK5H s8ENwitaHM7ENmBNMGEcy2XiqO7LdIJ7GMPj7h52hzTEHsP9lNMQbFf5y RqR4bgE/+LawEpzEr/LHxCfQSPnf3Zki4sR2sU9Vo83VXOwl2thurGZYR R7KUi8QQaJ4E+FPeusT3fP3xc5LlJIvukcTO7+CfQl0gj2C8lvRXE9/Lh 249TUzp3FP9ojP1os5YGeDTFijHDIFxeKVz4tlLrssw2KaStSs7Saz+ba g==; X-CSE-ConnectionGUID: AGa8wKWcQmygV94KfJeZpg== X-CSE-MsgGUID: nn3uEwyWRH6V9QouBzwe0Q== X-IronPort-AV: E=McAfee;i="6700,10204,11186"; a="27200004" X-IronPort-AV: E=Sophos;i="6.10,205,1719903600"; d="scan'208";a="27200004" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2024 08:07:28 -0700 X-CSE-ConnectionGUID: pHs37FpXQ7yK4R6Ve5sqvQ== X-CSE-MsgGUID: 0QkWAHSWTp68492yMnNGcA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,205,1719903600"; d="scan'208";a="65311456" Received: from silpixa00400308.ir.intel.com ([10.237.214.154]) by fmviesa006.fm.intel.com with ESMTP; 05 Sep 2024 08:07:27 -0700 From: Arkadiusz Kusztal To: dev@dpdk.org Cc: kai.ji@intel.com, brian.dooley@intel.com, Arkadiusz Kusztal Subject: [PATCH 1/2] net: add thread-safe crc api Date: Thu, 5 Sep 2024 16:07:21 +0100 Message-Id: <20240905150722.27789-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The current net CRC API is not thread-safe, this patch solves this by adding another, thread-safe API functions. These functions are not safe when using between different processes, though. Signed-off-by: Arkadiusz Kusztal --- lib/net/rte_net_crc.c | 40 +++++++++++++++++++++++++++++++++++++--- lib/net/rte_net_crc.h | 14 ++++++++++++++ lib/net/version.map | 2 ++ 3 files changed, 53 insertions(+), 3 deletions(-) diff --git a/lib/net/rte_net_crc.c b/lib/net/rte_net_crc.c index 346c285c15..87808a31dc 100644 --- a/lib/net/rte_net_crc.c +++ b/lib/net/rte_net_crc.c @@ -35,9 +35,6 @@ rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len); static uint32_t rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len); -typedef uint32_t -(*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len); - static rte_net_crc_handler handlers_default[] = { [RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_default_handler, [RTE_NET_CRC32_ETH] = rte_crc32_eth_default_handler, @@ -331,6 +328,43 @@ rte_net_crc_calc(const void *data, return ret; } +struct rte_net_crc rte_net_crc_set(enum rte_net_crc_type type, + enum rte_net_crc_alg alg) +{ + const rte_net_crc_handler *handlers = NULL; + + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_vect_get_max_simd_bitwidth(); + + switch (alg) { + case RTE_NET_CRC_AVX512: + handlers = avx512_vpclmulqdq_get_handlers(); + if (handlers != NULL) + break; + /* fall-through */ + case RTE_NET_CRC_SSE42: + handlers = sse42_pclmulqdq_get_handlers(); + break; + case RTE_NET_CRC_NEON: + handlers = neon_pmull_get_handlers(); + /* fall-through */ + case RTE_NET_CRC_SCALAR: + /* fall-through */ + default: + break; + } + if (handlers == NULL) + handlers = handlers_scalar; + + return (struct rte_net_crc){ type, handlers[type] }; +} + +uint32_t rte_net_crc(const struct rte_net_crc *ctx, + const void *data, const uint32_t data_len) +{ + return ctx->crc(data, data_len); +} + /* Call initialisation helpers for all crc algorithm handlers */ RTE_INIT(rte_net_crc_init) { diff --git a/lib/net/rte_net_crc.h b/lib/net/rte_net_crc.h index 72d3e10ff6..f5c8f7173f 100644 --- a/lib/net/rte_net_crc.h +++ b/lib/net/rte_net_crc.h @@ -11,6 +11,9 @@ extern "C" { #endif +typedef uint32_t +(*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len); + /** CRC types */ enum rte_net_crc_type { RTE_NET_CRC16_CCITT = 0, @@ -26,6 +29,11 @@ enum rte_net_crc_alg { RTE_NET_CRC_AVX512, }; +struct rte_net_crc { + enum rte_net_crc_type type; + rte_net_crc_handler crc; +}; + /** * This API set the CRC computation algorithm (i.e. scalar version, * x86 64-bit sse4.2 intrinsic version, etc.) and internal data @@ -59,6 +67,12 @@ rte_net_crc_calc(const void *data, uint32_t data_len, enum rte_net_crc_type type); +struct rte_net_crc rte_net_crc_set(enum rte_net_crc_type type, + enum rte_net_crc_alg alg); + +uint32_t rte_net_crc(const struct rte_net_crc *ctx, + const void *data, const uint32_t data_len); + #ifdef __cplusplus } #endif diff --git a/lib/net/version.map b/lib/net/version.map index bec4ce23ea..5c3dbffba7 100644 --- a/lib/net/version.map +++ b/lib/net/version.map @@ -4,6 +4,8 @@ DPDK_25 { rte_eth_random_addr; rte_ether_format_addr; rte_ether_unformat_addr; + rte_net_crc; + rte_net_crc_set; rte_net_crc_calc; rte_net_crc_set_alg; rte_net_get_ptype; From patchwork Thu Sep 5 15:07:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 143675 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C73204590E; Thu, 5 Sep 2024 17:07:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0980942EA0; Thu, 5 Sep 2024 17:07:32 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by mails.dpdk.org (Postfix) with ESMTP id 6F399427E7 for ; Thu, 5 Sep 2024 17:07:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725548850; x=1757084850; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=nXPvhQE+jnlaIc7HRNT9Vd7+Wjf9T2VKVaNXY9xjamw=; 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05 Sep 2024 08:07:29 -0700 From: Arkadiusz Kusztal To: dev@dpdk.org Cc: kai.ji@intel.com, brian.dooley@intel.com, Arkadiusz Kusztal Subject: [PATCH 2/2] crypto/qat: fix thread-safety issue in the crc Date: Thu, 5 Sep 2024 16:07:22 +0100 Message-Id: <20240905150722.27789-2-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240905150722.27789-1-arkadiuszx.kusztal@intel.com> References: <20240905150722.27789-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch fixes CRC thread-safety issue in the QAT PMD. Signed-off-by: Arkadiusz Kusztal --- drivers/crypto/qat/qat_sym.h | 3 +-- drivers/crypto/qat/qat_sym_session.c | 3 +++ drivers/crypto/qat/qat_sym_session.h | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index eedf5de755..8db6044390 100644 --- a/drivers/crypto/qat/qat_sym.h +++ b/drivers/crypto/qat/qat_sym.h @@ -291,8 +291,7 @@ qat_crc_generate(struct qat_sym_session *ctx, crc_data = rte_pktmbuf_mtod_offset(sym_op->m_src, uint8_t *, sym_op->auth.data.offset); crc = (uint32_t *)(crc_data + crc_data_len); - *crc = rte_net_crc_calc(crc_data, crc_data_len, - RTE_NET_CRC32_ETH); + *crc = rte_net_crc(&ctx->crc, crc_data, crc_data_len); } } diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index eb267db424..828466edea 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -3176,6 +3176,9 @@ qat_sec_session_set_docsis_parameters(struct rte_cryptodev *dev, ret = qat_sym_session_configure_crc(dev, xform, session); if (ret < 0) return ret; + } else { + /* Initialize crc algorithm */ + session->crc = rte_net_crc_set(RTE_NET_CRC32_ETH, RTE_NET_CRC_AVX512); } qat_sym_session_finalize(session); diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index f2634774ec..680ac9126c 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -7,6 +7,7 @@ #include #include #include +#include #include "qat_common.h" #include "icp_qat_hw.h" @@ -150,6 +151,7 @@ struct qat_sym_session { uint8_t is_wireless; uint32_t slice_types; enum qat_sym_proto_flag qat_proto_flag; + struct rte_net_crc crc; qat_sym_build_request_t build_request[2]; #ifndef RTE_QAT_OPENSSL IMB_MGR *mb_mgr;