From patchwork Tue Oct 1 06:00:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144768 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35C0345A74; Tue, 1 Oct 2024 08:01:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1AA7A4029B; Tue, 1 Oct 2024 08:01:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 322B44027A for ; Tue, 1 Oct 2024 08:01:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48ULfAp1000750 for ; Mon, 30 Sep 2024 23:01:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pfpt0220; bh=IDE9bnZn0/D5cwKP/dlddhI aqzbvS899jUEuArLTx2U=; b=F7VNiSni6A6vDgkRGoXdrlc8vI79JOBJ4fuuuYq 9eNZnREPTkgP1Man34hJEcROGqCtIOe6IrM/eBGkVXodMytQDh6BGSPhhsl6VX4n +JJT2zKbUbvhcLTku1oiNKLg4sDWP20uyBn7pWsjowkQBTkMAOfJ9NbukfqQTTPY 7QaWxynyKSqHPrsatDkhKJJvO74hJbsxDQPhcF+ar0BUjp5SJD3Cs3RAGLwCassy dHyHGFQzUgOPRZFBDrkM6/Eh8Ljmq+8nk86L5U5f/HJ+TFma4+Nv4JnjZ4AkYNhx n/7fpcoc3CfOvkFhUsSlFHKOsPmw85memaiGLVnWnlSYS8A== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41yt6gbxh1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 30 Sep 2024 23:01:04 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:02 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C61C65C68E3; Mon, 30 Sep 2024 23:00:58 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rakesh Kudurumalla Subject: [PATCH v2 01/17] net/cnxk: added telemetry support do dump SA information Date: Tue, 1 Oct 2024 11:30:39 +0530 Message-ID: <20241001060055.3747591-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Proofpoint-GUID: VvHEHWyHdOmR-3HHwW0_5sNjjQ5AVw77 X-Proofpoint-ORIG-GUID: VvHEHWyHdOmR-3HHwW0_5sNjjQ5AVw77 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla Added new telemetry command to dump SA taking portid and SA index as parameters. Ex: /cnxk/ipsec/sa_info,0,3 dumps inbound and outbound SA information of SA index 3 Signed-off-by: Rakesh Kudurumalla --- v2: - Splitted series from "[PATCH 00/33] add Marvell cn20k SOC support for mempool and net" - Added 16/17, 17/17 PMD updates to the series. drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c | 145 ++++++++++++++++--- 1 file changed, 128 insertions(+), 17 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c b/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c index 386278cfc9..86c2453c09 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec_telemetry.c @@ -207,17 +207,121 @@ copy_inb_sa_10k(struct rte_tel_data *d, uint32_t i, void *sa) return 0; } +/* n_vals is the number of params to be parsed. */ +static int +parse_params(const char *params, uint32_t *vals, size_t n_vals) +{ + char dlim[2] = ","; + char *params_args; + size_t count = 0; + char *token; + + if (vals == NULL || params == NULL || strlen(params) == 0) + return -1; + + /* strtok expects char * and param is const char *. Hence on using + * params as "const char *" compiler throws warning. + */ + params_args = strdup(params); + if (params_args == NULL) + return -1; + + token = strtok(params_args, dlim); + while (token && isdigit(*token) && count < n_vals) { + vals[count++] = strtoul(token, NULL, 10); + token = strtok(NULL, dlim); + } + + free(params_args); + + if (count < n_vals) + return -1; + + return 0; +} + +static int +ethdev_sec_tel_handle_sa_info(const char *cmd __rte_unused, const char *params, + struct rte_tel_data *d) +{ + struct cnxk_eth_sec_sess *eth_sec, *tvar; + struct rte_eth_dev *eth_dev; + struct cnxk_eth_dev *dev; + uint32_t port_id, sa_idx; + uint32_t vals[2] = {0}; + uint32_t i; + int ret; + + if (params == NULL || strlen(params) == 0 || !isdigit(*params)) + return -EINVAL; + + if (parse_params(params, vals, RTE_DIM(vals)) < 0) + return -EINVAL; + + port_id = vals[0]; + sa_idx = vals[1]; + + if (!rte_eth_dev_is_valid_port(port_id)) { + plt_err("Invalid port id %u", port_id); + return -EINVAL; + } + + eth_dev = &rte_eth_devices[port_id]; + if (!eth_dev) { + plt_err("Ethdev not available"); + return -EINVAL; + } + dev = cnxk_eth_pmd_priv(eth_dev); + + rte_tel_data_start_dict(d); + + i = 0; + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) { + tvar = NULL; + RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar) { + if (eth_sec->sa_idx == sa_idx) { + rte_tel_data_add_dict_int(d, "outb_sa", 1); + if (roc_model_is_cn10k()) + ret = copy_outb_sa_10k(d, i, eth_sec->sa); + else + ret = copy_outb_sa_9k(d, i, eth_sec->sa); + if (ret < 0) + return ret; + break; + } + } + } + + i = 0; + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { + tvar = NULL; + RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar) { + if (eth_sec->sa_idx == sa_idx) { + rte_tel_data_add_dict_int(d, "inb_sa", 1); + if (roc_model_is_cn10k()) + ret = copy_inb_sa_10k(d, i, eth_sec->sa); + else + ret = copy_inb_sa_9k(d, i, eth_sec->sa); + if (ret < 0) + return ret; + break; + } + } + } + return 0; +} + static int ethdev_sec_tel_handle_info(const char *cmd __rte_unused, const char *params, struct rte_tel_data *d) { + uint32_t min_outb_sa = UINT32_MAX, max_outb_sa = 0; + uint32_t min_inb_sa = UINT32_MAX, max_inb_sa = 0; struct cnxk_eth_sec_sess *eth_sec, *tvar; struct rte_eth_dev *eth_dev; struct cnxk_eth_dev *dev; uint16_t port_id; char *end_p; - uint32_t i; - int ret; if (params == NULL || strlen(params) == 0 || !isdigit(*params)) return -EINVAL; @@ -246,32 +350,36 @@ ethdev_sec_tel_handle_info(const char *cmd __rte_unused, const char *params, rte_tel_data_add_dict_int(d, "nb_outb_sa", dev->outb.nb_sess); - i = 0; + if (!dev->outb.nb_sess) + min_outb_sa = 0; + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) { tvar = NULL; RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->outb.list, entry, tvar) { - if (roc_model_is_cn10k()) - ret = copy_outb_sa_10k(d, i++, eth_sec->sa); - else - ret = copy_outb_sa_9k(d, i++, eth_sec->sa); - if (ret < 0) - return ret; + if (eth_sec->sa_idx < min_outb_sa) + min_outb_sa = eth_sec->sa_idx; + if (eth_sec->sa_idx > max_outb_sa) + max_outb_sa = eth_sec->sa_idx; } + rte_tel_data_add_dict_int(d, "min_outb_sa", min_outb_sa); + rte_tel_data_add_dict_int(d, "max_outb_sa", max_outb_sa); } rte_tel_data_add_dict_int(d, "nb_inb_sa", dev->inb.nb_sess); - i = 0; + if (!dev->inb.nb_sess) + min_inb_sa = 0; + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { tvar = NULL; RTE_TAILQ_FOREACH_SAFE(eth_sec, &dev->inb.list, entry, tvar) { - if (roc_model_is_cn10k()) - ret = copy_inb_sa_10k(d, i++, eth_sec->sa); - else - ret = copy_inb_sa_9k(d, i++, eth_sec->sa); - if (ret < 0) - return ret; + if (eth_sec->sa_idx < min_inb_sa) + min_inb_sa = eth_sec->sa_idx; + if (eth_sec->sa_idx > max_inb_sa) + max_inb_sa = eth_sec->sa_idx; } + rte_tel_data_add_dict_int(d, "min_inb_sa", min_inb_sa); + rte_tel_data_add_dict_int(d, "max_inb_sa", max_inb_sa); } return 0; @@ -281,5 +389,8 @@ RTE_INIT(cnxk_ipsec_init_telemetry) { rte_telemetry_register_cmd("/cnxk/ipsec/info", ethdev_sec_tel_handle_info, - "Returns ipsec info. Parameters: port id"); + "Returns number of SA's and Max and Min SA. Parameters: port id"); + rte_telemetry_register_cmd("/cnxk/ipsec/sa_info", + ethdev_sec_tel_handle_sa_info, + "Returns ipsec info. Parameters: port id & sa_idx"); } From patchwork Tue Oct 1 06:00:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144769 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3AAE845A74; Tue, 1 Oct 2024 08:01:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6CB6C402E3; Tue, 1 Oct 2024 08:01:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 05FE940654 for ; Tue, 1 Oct 2024 08:01:07 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48UNtA7D000399 for ; Mon, 30 Sep 2024 23:01:07 -0700 DKIM-Signature: v=1; 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Mon, 30 Sep 2024 23:01:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:05 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 5BE035C68E6; Mon, 30 Sep 2024 23:01:02 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rakesh Kudurumalla Subject: [PATCH v2 02/17] net/cnxk: handle timestamp correctly for VF Date: Tue, 1 Oct 2024 11:30:40 +0530 Message-ID: <20241001060055.3747591-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RWbcOmjQDnfHDyUFQDhhIOew9eJ_dZbP X-Proofpoint-GUID: RWbcOmjQDnfHDyUFQDhhIOew9eJ_dZbP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla When timestamp is enabled on PF in kernel and respective VF is attached to application in DPDK mbuf_addr is getting corrupted in cnxk_nix_timestamp_dynfield() as "tstamp_dynfield_offset" is zero for PTP enabled PF This patch fixes the same Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cn10k_ethdev.c | 12 +++++++++++- drivers/net/cnxk/cn9k_ethdev.c | 12 +++++++++++- drivers/net/cnxk/cnxk_ethdev.c | 2 +- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 55ed54bb0f..099890e959 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -473,7 +473,7 @@ cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix; struct rte_eth_dev *eth_dev; struct cn10k_eth_rxq *rxq; - int i; + int i, rc; if (!dev) return -EINVAL; @@ -496,7 +496,17 @@ cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) * and MTU setting also requires MBOX message to be * sent(VF->PF) */ + if (dev->ptp_en) { + rc = rte_mbuf_dyn_rx_timestamp_register + (&dev->tstamp.tstamp_dynfield_offset, + &dev->tstamp.rx_tstamp_dynflag); + if (rc != 0) { + plt_err("Failed to register Rx timestamp field/flag"); + return -EINVAL; + } + } eth_dev->rx_pkt_burst = nix_ptp_vf_burst; + rte_eth_fp_ops[eth_dev->data->port_id].rx_pkt_burst = eth_dev->rx_pkt_burst; rte_mb(); } diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c index ea92b1dcb6..4851e60f16 100644 --- a/drivers/net/cnxk/cn9k_ethdev.c +++ b/drivers/net/cnxk/cn9k_ethdev.c @@ -432,7 +432,7 @@ cn9k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix; struct rte_eth_dev *eth_dev; struct cn9k_eth_rxq *rxq; - int i; + int i, rc; if (!dev) return -EINVAL; @@ -455,7 +455,17 @@ cn9k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) * and MTU setting also requires MBOX message to be * sent(VF->PF) */ + if (dev->ptp_en) { + rc = rte_mbuf_dyn_rx_timestamp_register + (&dev->tstamp.tstamp_dynfield_offset, + &dev->tstamp.rx_tstamp_dynflag); + if (rc != 0) { + plt_err("Failed to register Rx timestamp field/flag"); + return -EINVAL; + } + } eth_dev->rx_pkt_burst = nix_ptp_vf_burst; + rte_eth_fp_ops[eth_dev->data->port_id].rx_pkt_burst = eth_dev->rx_pkt_burst; rte_mb(); } diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 38746c81c5..dd065c8269 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1751,7 +1751,7 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev) else cnxk_eth_dev_ops.timesync_disable(eth_dev); - if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) { + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP || dev->ptp_en) { rc = rte_mbuf_dyn_rx_timestamp_register (&dev->tstamp.tstamp_dynfield_offset, &dev->tstamp.rx_tstamp_dynflag); From patchwork Tue Oct 1 06:00:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144770 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 24DE245A74; Tue, 1 Oct 2024 08:01:19 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA3774068E; Tue, 1 Oct 2024 08:01:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 8E8294027A for ; Tue, 1 Oct 2024 08:01:13 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48UNa9CV030367 for ; Mon, 30 Sep 2024 23:01:12 -0700 DKIM-Signature: v=1; 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Mon, 30 Sep 2024 23:01:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:09 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D00005C68E3; Mon, 30 Sep 2024 23:01:05 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rakesh Kudurumalla Subject: [PATCH v2 03/17] net/cnxk: update Rx offloads to handle timestamp Date: Tue, 1 Oct 2024 11:30:41 +0530 Message-ID: <20241001060055.3747591-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: zoMURVdlxN03OsJ9yy48u236nx8zduzm X-Proofpoint-GUID: zoMURVdlxN03OsJ9yy48u236nx8zduzm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla RX offloads flags are updated to handle timestamp in VF when ptp is enabled in respective PF in kernle Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cn10k_ethdev.c | 6 +++++- drivers/net/cnxk/cn9k_ethdev.c | 5 ++++- drivers/net/cnxk/cnxk_ethdev.h | 7 +++++++ 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 099890e959..d335f3971b 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -30,7 +30,7 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev) if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) flags |= NIX_RX_MULTI_SEG_F; - if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)) + if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) flags |= NIX_RX_OFFLOAD_TSTAMP_F; if (!dev->ptype_disable) @@ -508,6 +508,10 @@ cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) eth_dev->rx_pkt_burst = nix_ptp_vf_burst; rte_eth_fp_ops[eth_dev->data->port_id].rx_pkt_burst = eth_dev->rx_pkt_burst; rte_mb(); + if (dev->cnxk_sso_ptp_tstamp_cb) + dev->cnxk_sso_ptp_tstamp_cb(eth_dev->data->port_id, + NIX_RX_OFFLOAD_TSTAMP_F, dev->ptp_en); + } return 0; diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c index 4851e60f16..d1810e8f4d 100644 --- a/drivers/net/cnxk/cn9k_ethdev.c +++ b/drivers/net/cnxk/cn9k_ethdev.c @@ -30,7 +30,7 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev) if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) flags |= NIX_RX_MULTI_SEG_F; - if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)) + if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) || dev->ptp_en) flags |= NIX_RX_OFFLOAD_TSTAMP_F; if (!dev->ptype_disable) @@ -467,6 +467,9 @@ cn9k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) eth_dev->rx_pkt_burst = nix_ptp_vf_burst; rte_eth_fp_ops[eth_dev->data->port_id].rx_pkt_burst = eth_dev->rx_pkt_burst; rte_mb(); + if (dev->cnxk_sso_ptp_tstamp_cb) + dev->cnxk_sso_ptp_tstamp_cb(eth_dev->data->port_id, + NIX_RX_OFFLOAD_TSTAMP_F, dev->ptp_en); } return 0; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 687c60c27d..5920488e1a 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -433,6 +433,13 @@ struct cnxk_eth_dev { /* Eswitch domain ID */ uint16_t switch_domain_id; + + /* SSO event dev */ + void *evdev_priv; + + /* SSO event dev ptp */ + void (*cnxk_sso_ptp_tstamp_cb) + (uint16_t port_id, uint16_t flags, bool ptp_en); }; struct cnxk_eth_rxq_sp { From patchwork Tue Oct 1 06:00:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144771 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 472C445A74; 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Mon, 30 Sep 2024 23:01:13 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:12 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:12 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4FBD25C68E7; Mon, 30 Sep 2024 23:01:09 -0700 (PDT) From: Nithin Dabilpuram To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Rakesh Kudurumalla Subject: [PATCH v2 04/17] event/cnxk: handle timestamp for event mode Date: Tue, 1 Oct 2024 11:30:42 +0530 Message-ID: <20241001060055.3747591-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: jo59VfE-9EbY1RiOSChWjmrrti4ybSkh X-Proofpoint-GUID: jo59VfE-9EbY1RiOSChWjmrrti4ybSkh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla handle timestamp correctly for VF when ptp is enabled before running application in event mode by updating RX offload flags in link up notification Signed-off-by: Rakesh Kudurumalla --- drivers/event/cnxk/cn10k_eventdev.c | 32 ++++++++++++++++++++++++ drivers/event/cnxk/cn9k_eventdev.c | 31 +++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev_adptr.c | 2 +- 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 2d7b169974..229d7a03fe 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -825,12 +825,40 @@ cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem) } } +static void +eventdev_fops_tstamp_update(struct rte_eventdev *event_dev) +{ + struct rte_event_fp_ops *fp_op = + rte_event_fp_ops + event_dev->data->dev_id; + + fp_op->dequeue = event_dev->dequeue; + fp_op->dequeue_burst = event_dev->dequeue_burst; +} + +static void +cn10k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct cnxk_eth_dev *cnxk_eth_dev = dev->data->dev_private; + struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv; + struct cnxk_sso_evdev *evdev = cnxk_sso_pmd_priv(event_dev); + + evdev->rx_offloads |= flags; + if (ptp_en) + evdev->tstamp[port_id] = &cnxk_eth_dev->tstamp; + else + evdev->tstamp[port_id] = NULL; + cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + eventdev_fops_tstamp_update(event_dev); +} + static int cn10k_sso_rx_adapter_queue_add( const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev, int32_t rx_queue_id, const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) { + struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); struct roc_sso_hwgrp_stash stash; struct cn10k_eth_rxq *rxq; @@ -845,6 +873,10 @@ cn10k_sso_rx_adapter_queue_add( queue_conf); if (rc) return -EINVAL; + + cnxk_eth_dev->cnxk_sso_ptp_tstamp_cb = cn10k_sso_tstamp_hdl_update; + cnxk_eth_dev->evdev_priv = (struct rte_eventdev *)(uintptr_t)event_dev; + rxq = eth_dev->data->rx_queues[0]; lookup_mem = rxq->lookup_mem; cn10k_sso_set_priv_mem(event_dev, lookup_mem); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 28350d1275..377e910837 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -911,12 +911,40 @@ cn9k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem) } } +static void +eventdev_fops_tstamp_update(struct rte_eventdev *event_dev) +{ + struct rte_event_fp_ops *fp_op = + rte_event_fp_ops + event_dev->data->dev_id; + + fp_op->dequeue = event_dev->dequeue; + fp_op->dequeue_burst = event_dev->dequeue_burst; +} + +static void +cn9k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct cnxk_eth_dev *cnxk_eth_dev = dev->data->dev_private; + struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv; + struct cnxk_sso_evdev *evdev = cnxk_sso_pmd_priv(event_dev); + + evdev->rx_offloads |= flags; + if (ptp_en) + evdev->tstamp[port_id] = &cnxk_eth_dev->tstamp; + else + evdev->tstamp[port_id] = NULL; + cn9k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + eventdev_fops_tstamp_update(event_dev); +} + static int cn9k_sso_rx_adapter_queue_add( const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev, int32_t rx_queue_id, const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) { + struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private; struct cn9k_eth_rxq *rxq; void *lookup_mem; int rc; @@ -930,6 +958,9 @@ cn9k_sso_rx_adapter_queue_add( if (rc) return -EINVAL; + cnxk_eth_dev->cnxk_sso_ptp_tstamp_cb = cn9k_sso_tstamp_hdl_update; + cnxk_eth_dev->evdev_priv = (struct rte_eventdev *)(uintptr_t)event_dev; + rxq = eth_dev->data->rx_queues[0]; lookup_mem = rxq->lookup_mem; cn9k_sso_set_priv_mem(event_dev, lookup_mem); diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index 2c049e7041..3cac42111a 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -213,7 +213,7 @@ static void cnxk_sso_tstamp_cfg(uint16_t port_id, struct cnxk_eth_dev *cnxk_eth_dev, struct cnxk_sso_evdev *dev) { - if (cnxk_eth_dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) + if (cnxk_eth_dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP || cnxk_eth_dev->ptp_en) dev->tstamp[port_id] = &cnxk_eth_dev->tstamp; } From patchwork Tue Oct 1 06:00:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144772 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD30D45A74; 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Mon, 30 Sep 2024 23:01:16 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:15 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E82025C68E3; Mon, 30 Sep 2024 23:01:11 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rakesh Kudurumalla Subject: [PATCH v2 05/17] net/cnxk: update mbuf and rearm data for Rx inject packets Date: Tue, 1 Oct 2024 11:30:43 +0530 Message-ID: <20241001060055.3747591-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: lIYQd8JVt4z6nMDaRFdhhAH9h-MrylYd X-Proofpoint-ORIG-GUID: lIYQd8JVt4z6nMDaRFdhhAH9h-MrylYd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla When nix receives second pass packets injected to CPT next segments of primary mbuf are accessed directly using mbuf next pointer since we do not know at what offset mbuf is available.To achieve this we do no update mbut next pointer to NULL for Rx injected packets. Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cn10k_rx.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 9dde2bea57..990dfbee3e 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -709,6 +709,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint16_t later_skip = 0; struct rte_mbuf *head; const rte_iova_t *eol; + bool rx_inj = false; uint64_t cq_w5 = 0; uint16_t ihl = 0; uint64_t fsz = 0; @@ -729,7 +730,9 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, /* Rx Inject packet must have Match ID 0xFFFF and for this * wqe will get from address stored at mbuf+1 location */ - if ((flags & NIX_RX_REAS_F) && hdr->w0.match_id == 0xFFFFU) + rx_inj = ((flags & NIX_RX_REAS_F) && ((hdr->w0.match_id == 0xFFFFU) || + (hdr->w0.cookie == 0xFFFFFFFFU))); + if (rx_inj) wqe = (const uint64_t *)*((uint64_t *)(mbuf + 1)); else wqe = (const uint64_t *)(mbuf + 1); @@ -786,7 +789,8 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf; while (nb_segs) { - mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip); + if (!(flags & NIX_RX_REAS_F) || !rx_inj) + mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip); mbuf = mbuf->next; RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1); @@ -804,7 +808,8 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, mbuf->data_len = sg_len; sg = sg >> 16; p = (uintptr_t)&mbuf->rearm_data; - *(uint64_t *)p = rearm & ~0xFFFF; + if (!(flags & NIX_RX_REAS_F) || !rx_inj) + *(uint64_t *)p = rearm & ~0xFFFF; nb_segs--; iova_list++; @@ -1259,7 +1264,6 @@ cn10k_nix_rx_inj_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd) slist++; } m_next = m->next; - m->next = NULL; m = m_next; } while (nb_segs); From patchwork Tue Oct 1 06:00:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144773 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD45945A74; 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Mon, 30 Sep 2024 23:01:20 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:18 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 643F25E6862; Mon, 30 Sep 2024 23:01:15 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v2 06/17] common/cnxk: remove restriction to clear RPM stats Date: Tue, 1 Oct 2024 11:30:44 +0530 Message-ID: <20241001060055.3747591-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: DNWNLnqiReLtsXYQZuyFwPV-CouStq7g X-Proofpoint-ORIG-GUID: DNWNLnqiReLtsXYQZuyFwPV-CouStq7g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Linux does not support clearing RPM stats on cn10k platform. Hence restriction is added that when user requests to clear xstats then request is discarded silently. Hence removing restriction for cn10k. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix_mac.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index f79aaec4a5..0ffd05e4d4 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -363,11 +363,6 @@ roc_nix_mac_stats_reset(struct roc_nix *roc_nix) struct msg_req *req; int rc = -ENOSPC; - if (roc_model_is_cn10k()) { - rc = 0; - goto exit; - } - if (roc_nix_is_vf_or_sdp(roc_nix)) { rc = 0; goto exit; From patchwork Tue Oct 1 06:00:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144774 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A737145A74; Tue, 1 Oct 2024 08:01:49 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 21B9340B99; Tue, 1 Oct 2024 08:01:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 439B840A75 for ; Tue, 1 Oct 2024 08:01:24 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49145mhL010987 for ; Mon, 30 Sep 2024 23:01:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=e qwAHXCF0Yo/M93BUFtMxwcYOmjg4WLo2aJjx4DY1Gg=; b=fInmWjEnbSW+vvGh1 Ezkuy0QmoHM8kZLsylqdwuDkkuu1UMLQ7yHHUMSRxbLeTkYB6+PHzrp57XI0zMHW qgwThHzP/YKAHypyg0qC/cnUOja4sqRpSTmcvOjxPIbVNaIQ8KU35tYgTjOWKvab qOUxk/22FD6zaGSbYWAppLf2R/oqEWJwHBuGBYa2tjcaXqpebsZrE9Z546MRb5uQ uWSIEq9fcxuE/0Ihzva0QR4BVuY8RVS1KmZA7qTF9de17Z7dY7LkjsUdbiGrzEbH j1m2R2L2iqSY4qr5EMP1lOxH0q9BPqP/DFZ3qNTndOfNWvfRqSExN1vzSkOnT++9 omriA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41xf5m2enh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 30 Sep 2024 23:01:23 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:21 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 989B03F7072; Mon, 30 Sep 2024 23:01:18 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v2 07/17] common/cnxk: allow MAC address set/add with active VFs Date: Tue, 1 Oct 2024 11:30:45 +0530 Message-ID: <20241001060055.3747591-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: h44gjm_MwBMbwDxnGs3hYco_7hmltEyX X-Proofpoint-GUID: h44gjm_MwBMbwDxnGs3hYco_7hmltEyX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori If device is in reconfigure state then it throws error while changing default MAC or adding new MAC in LMAC filter table if there are active VFs on a PF. Allowing MAC address set/add even active VFs are present on PF. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_nix_mac.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index 0ffd05e4d4..54db1adf17 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -91,11 +91,6 @@ roc_nix_mac_addr_set(struct roc_nix *roc_nix, const uint8_t addr[]) goto exit; } - if (dev_active_vfs(&nix->dev)) { - rc = NIX_ERR_OP_NOTSUP; - goto exit; - } - req = mbox_alloc_msg_cgx_mac_addr_set(mbox); if (req == NULL) goto exit; @@ -152,11 +147,6 @@ roc_nix_mac_addr_add(struct roc_nix *roc_nix, uint8_t addr[]) goto exit; } - if (dev_active_vfs(&nix->dev)) { - rc = NIX_ERR_OP_NOTSUP; - goto exit; - } - req = mbox_alloc_msg_cgx_mac_addr_add(mbox); mbox_memcpy(req->mac_addr, addr, PLT_ETHER_ADDR_LEN); From patchwork Tue Oct 1 06:00:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144775 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06B8445A74; Tue, 1 Oct 2024 08:01:57 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8767040BA2; Tue, 1 Oct 2024 08:01:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9B66240B9D for ; Tue, 1 Oct 2024 08:01:26 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49107VRS021053 for ; Mon, 30 Sep 2024 23:01:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=b lzzipDC25BeYwP/DL8c0un09GxVwgZbpap6HmUqrMk=; b=UEwafXjL8OqFF8cIM 6KCbjfaE9qABUh2ww0IjJC/KjlCrG/uRDRie3fUprncCBXG8/+TgUed+XgFv0ES8 fV5HIkiKMtNWsIfoXbXb1fjMfo+fssXwquFfP3AtzFlm9QsAET/Mqmz1UdAU6INf bSKhWhhHhZ2AUAvZ8ah2Z+jkl7E6lhUu4zDi/kg9Za6Gj3tme7dpxg5gEukR6GpR kkzWCxUzyHa6VjB2+J9P7ETrubd5umq7dBa5Wvp4wa54QOjLYm4fFRPwQSsn4+qX Oz3Ue8eiUKpUoAWBZJ089F2s30/4mh3/luoRLGuabppMORbYdH5WzM6o0zqrNdZ7 +QOWQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41yt6gbxkg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 30 Sep 2024 23:01:25 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:25 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D7EDB3F7072; Mon, 30 Sep 2024 23:01:21 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v2 08/17] net/cnxk: move PMD function defines to common code Date: Tue, 1 Oct 2024 11:30:46 +0530 Message-ID: <20241001060055.3747591-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: W8nhuQKDDV7ibXDjq9thz75spKkHp2uX X-Proofpoint-ORIG-GUID: W8nhuQKDDV7ibXDjq9thz75spKkHp2uX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move PMD function definitions to common code for cn9k/cn10k since they are declared commonly. Also remove the reference to 'struct rte_security_session' since it is now a driver internal structure and not exported to application code. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev_sec.c | 61 ---------------------------- drivers/net/cnxk/cnxk_ethdev_sec.c | 63 +++++++++++++++++++++++++++++ drivers/net/cnxk/rte_pmd_cnxk.h | 8 ++-- 3 files changed, 67 insertions(+), 65 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 5e509e97d4..074bb09822 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -1208,67 +1208,6 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess, return 0; } -int -rte_pmd_cnxk_hw_sa_read(void *device, struct rte_security_session *sess, - union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len) -{ - struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; - struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - struct cnxk_eth_sec_sess *eth_sec; - int rc; - - eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); - if (eth_sec == NULL) - return -EINVAL; - - rc = roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb, - ROC_NIX_INL_SA_OP_FLUSH); - if (rc) - return -EINVAL; - rte_delay_ms(1); - memcpy(data, eth_sec->sa, len); - - return 0; -} - -int -rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess, - union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len) -{ - struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; - struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - struct cnxk_eth_sec_sess *eth_sec; - int rc = -EINVAL; - - eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); - if (eth_sec == NULL) - return rc; - rc = roc_nix_inl_ctx_write(&dev->nix, data, eth_sec->sa, eth_sec->inb, - len); - if (rc) - return rc; - - return 0; -} - -union rte_pmd_cnxk_cpt_res_s * -rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf) -{ - const union nix_rx_parse_u *rx; - uint16_t desc_size; - uintptr_t wqe; - - if (!mbuf || !(mbuf->ol_flags & RTE_MBUF_F_RX_SEC_OFFLOAD)) - return NULL; - - wqe = (uintptr_t)(mbuf + 1); - rx = (const union nix_rx_parse_u *)(wqe + 8); - desc_size = (rx->desc_sizem1 + 1) * 16; - - /* rte_pmd_cnxk_cpt_res_s sits after SG list at 16B aligned address */ - return (void *)(wqe + 64 + desc_size); -} - static int cn10k_eth_sec_session_stats_get(void *device, struct rte_security_session *sess, struct rte_security_stats *stats) diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 6f5319e534..cdd5656817 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -2,6 +2,8 @@ * Copyright(C) 2021 Marvell. */ +#include + #include #include @@ -295,6 +297,67 @@ cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev, return NULL; } +int +rte_pmd_cnxk_hw_sa_read(void *device, void *__sess, union rte_pmd_cnxk_ipsec_hw_sa *data, + uint32_t len) +{ + struct rte_security_session *sess = __sess; + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_eth_sec_sess *eth_sec; + int rc; + + eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); + if (eth_sec == NULL) + return -EINVAL; + + rc = roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb, ROC_NIX_INL_SA_OP_FLUSH); + if (rc) + return -EINVAL; + rte_delay_ms(1); + memcpy(data, eth_sec->sa, len); + + return 0; +} + +int +rte_pmd_cnxk_hw_sa_write(void *device, void *__sess, union rte_pmd_cnxk_ipsec_hw_sa *data, + uint32_t len) +{ + struct rte_security_session *sess = __sess; + struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct cnxk_eth_sec_sess *eth_sec; + int rc = -EINVAL; + + eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); + if (eth_sec == NULL) + return rc; + rc = roc_nix_inl_ctx_write(&dev->nix, data, eth_sec->sa, eth_sec->inb, len); + if (rc) + return rc; + + return 0; +} + +union rte_pmd_cnxk_cpt_res_s * +rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf) +{ + const union nix_rx_parse_u *rx; + uint16_t desc_size; + uintptr_t wqe; + + if (!mbuf || !(mbuf->ol_flags & RTE_MBUF_F_RX_SEC_OFFLOAD)) + return NULL; + + wqe = (uintptr_t)(mbuf + 1); + rx = (const union nix_rx_parse_u *)(wqe + 8); + desc_size = (rx->desc_sizem1 + 1) * 16; + + /* rte_pmd_cnxk_cpt_res_s sits after SG list at 16B aligned address */ + return (void *)(wqe + 64 + desc_size); +} + static unsigned int cnxk_eth_sec_session_get_size(void *device __rte_unused) { diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h index 88030046db..70f2f96fd4 100644 --- a/drivers/net/cnxk/rte_pmd_cnxk.h +++ b/drivers/net/cnxk/rte_pmd_cnxk.h @@ -495,7 +495,7 @@ union rte_pmd_cnxk_cpt_res_s { * @param device * Port identifier of Ethernet device. * @param sess - * Handle of the security session. + * Handle of the security session as void *. * @param[out] data * Destination pointer to copy SA context for application. * @param len @@ -505,7 +505,7 @@ union rte_pmd_cnxk_cpt_res_s { * 0 on success, a negative errno value otherwise. */ __rte_experimental -int rte_pmd_cnxk_hw_sa_read(void *device, struct rte_security_session *sess, +int rte_pmd_cnxk_hw_sa_read(void *device, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len); /** * Write HW SA context to session. @@ -513,7 +513,7 @@ int rte_pmd_cnxk_hw_sa_read(void *device, struct rte_security_session *sess, * @param device * Port identifier of Ethernet device. * @param sess - * Handle of the security session. + * Handle of the security session as void *. * @param[in] data * Source data pointer from application to copy SA context into session. * @param len @@ -523,7 +523,7 @@ int rte_pmd_cnxk_hw_sa_read(void *device, struct rte_security_session *sess, * 0 on success, a negative errno value otherwise. */ __rte_experimental -int rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess, +int rte_pmd_cnxk_hw_sa_write(void *device, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len); /** From patchwork Tue Oct 1 06:00:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144776 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 516D345A74; Tue, 1 Oct 2024 08:02:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A00E40B92; Tue, 1 Oct 2024 08:01:33 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1E8EF40A7F for ; Tue, 1 Oct 2024 08:01:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4914DbnO023533 for ; Mon, 30 Sep 2024 23:01:30 -0700 DKIM-Signature: v=1; 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Mon, 30 Sep 2024 23:01:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:28 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0EAD93F7070; Mon, 30 Sep 2024 23:01:24 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: Subject: [PATCH v2 09/17] common/cnxk: add flush wait after write of inline ctx Date: Tue, 1 Oct 2024 11:30:47 +0530 Message-ID: <20241001060055.3747591-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: DqZXnyPTjOpAw6i2MIA_cWkX_78BKpVe X-Proofpoint-GUID: DqZXnyPTjOpAw6i2MIA_cWkX_78BKpVe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Reading a CPT_LF_CTX_ERR csr will ensure writes for FLUSH are complete and also tell whether flush is complete or not. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_inl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index a984ac56d9..d0328921a7 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1748,6 +1748,7 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, struct nix_inl_dev *inl_dev = NULL; struct roc_cpt_lf *outb_lf = NULL; union cpt_lf_ctx_flush flush; + union cpt_lf_ctx_err err; bool get_inl_lf = true; uintptr_t rbase; struct nix *nix; @@ -1789,6 +1790,13 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, flush.s.cptr = ((uintptr_t)sa_cptr) >> 7; plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH); + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + + /* Read a CSR to ensure that the FLUSH operation is complete */ + err.u = plt_read64(rbase + CPT_LF_CTX_ERR); + + if (err.s.flush_st_flt) + plt_warn("CTX flush could not complete"); return 0; } plt_nix_dbg("Could not get CPT LF for CTX write"); From patchwork Tue Oct 1 06:00:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144777 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 58E8D45A74; Tue, 1 Oct 2024 08:02:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 90D0640DCB; Tue, 1 Oct 2024 08:01:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5A86040C35; Tue, 1 Oct 2024 08:01:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49102uvJ022409; Mon, 30 Sep 2024 23:01:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=K ZSXiQ2v5tj4Bfknc5z3T4u5QMAmglKdt4RhcZ6Vq9c=; b=H9YavftN/GivWWMmd /cy9GH5Rfba25BVlTb5WJ0Q7sd8SrXEck1dg1gx8W3CxeB5Y3Rt/3fueWdi2VpTq cTgkOZ11h3F2xVpQtGrbi7JJ0zHelx4uKTTD7P73py1B2Tep2On4pQKCPhUOiifa btky0OvHhooRkkUklfF9eUGQAu/yImvcMhWfyX8qQLGTxdkD6XuoWRFEYpvqy3Iw 7G0cFJgLV2KbMpejoY5v6BrkxH4vuqxTM7xEHNVzaOvel0b6gZ3INkrztqVGfRMj ZpvXQE8xSyrNbVmu7X1ZRPEWMPIjyI0ah7nqoWl0repgvR9xKFu9oQfrkV4jG0/q UNO9A== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41yt6gbxmn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Sep 2024 23:01:33 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:31 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 431F33F7070; Mon, 30 Sep 2024 23:01:27 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Subject: [PATCH v2 10/17] common/cnxk: fix CPT HW word size for outbound SA Date: Tue, 1 Oct 2024 11:30:48 +0530 Message-ID: <20241001060055.3747591-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: S1QxRF-teHXOx61OiKCwcEMSeyefxY6h X-Proofpoint-ORIG-GUID: S1QxRF-teHXOx61OiKCwcEMSeyefxY6h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix the CPT HW word size inited for outbound SA to be two words. Fixes: 5ece02e736c3 ("common/cnxk: use common SA init API for default options") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_ie_ot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c index 465b2bc1fb..1b436dba72 100644 --- a/drivers/common/cnxk/roc_ie_ot.c +++ b/drivers/common/cnxk/roc_ie_ot.c @@ -38,5 +38,6 @@ roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa) offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx); sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1; sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN; + sa->w0.s.ctx_hdr_size = ROC_IE_OT_SA_CTX_HDR_SIZE; sa->w0.s.aop_valid = 1; } From patchwork Tue Oct 1 06:00:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144778 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D387F45A74; Tue, 1 Oct 2024 08:02:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9CDCC40DD0; Tue, 1 Oct 2024 08:01:39 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5008740A7F for ; Tue, 1 Oct 2024 08:01:37 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4914DbnQ023533 for ; Mon, 30 Sep 2024 23:01:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=s bQmBKjEngKv5weuPtUfrqlQRG+BKt3O+a+9R7C6cY0=; b=WcQAoUGklqDzYlNRL OMVMCUQzsPMHu0wKT7laWExG8nqjv2dKmQmejkT9j8aVDiPpCk5wDJMJDFViIKcH rfLo7Hlm+k1E4fsw6iRe0Veww8T/zXRFgDV05xih0DQS+QUlBPSb4pwruYTsR8QQ Co8HcICdTRMHx7TaGpcn6kxXUbrOovqcubA+Hka0boVFFXd/jNEqEWV5HSWqaaJG ZZzyy6Ntil45y3Vyr2L4i1pas5099UR3GTrhkUuKstWt2zWxRrL1pjuvxbSI1Nbi lZatagg6I91yswDMS7SGC5UhUFBf3WBFRCCJC8ciUWBEhyTlXa/XX58x5bzcYePR Esqdw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41xf5m2erm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 30 Sep 2024 23:01:36 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:35 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C08AB3F7066; Mon, 30 Sep 2024 23:01:31 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Srujana Challa Subject: [PATCH v2 11/17] net/cnxk: add PMD APIs for IPsec SA base and flush Date: Tue, 1 Oct 2024 11:30:49 +0530 Message-ID: <20241001060055.3747591-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: KIzoElJ1yLJDzhtoSWjBLE2x8zakoSuU X-Proofpoint-GUID: KIzoElJ1yLJDzhtoSWjBLE2x8zakoSuU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Introduces new PMD APIs for Inline IPsec, including hardware SA flush and obtaining the base address for the inline device sa table. This allows applications to directly manage IPsec SAs. This patch also updates the rte_pmd_cnxk_hw_sa_read|write() API's to get use portid instead of device pointer as input. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_nix_inl.c | 9 +++++ drivers/net/cnxk/cnxk_ethdev_sec.c | 64 ++++++++++++++++++++---------- drivers/net/cnxk/rte_pmd_cnxk.h | 48 +++++++++++++++++++--- drivers/net/cnxk/version.map | 2 + 4 files changed, 97 insertions(+), 26 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index d0328921a7..23ffd4391a 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1685,6 +1685,7 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, struct roc_cpt_lf *outb_lf = NULL; union cpt_lf_ctx_reload reload; union cpt_lf_ctx_flush flush; + union cpt_lf_ctx_err err; bool get_inl_lf = true; uintptr_t rbase; struct nix *nix; @@ -1726,6 +1727,14 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb, case ROC_NIX_INL_SA_OP_FLUSH: flush.s.cptr = ((uintptr_t)sa) >> 7; plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH); + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); + /* Read a CSR to ensure that the FLUSH operation is complete */ + err.u = plt_read64(rbase + CPT_LF_CTX_ERR); + + if (err.s.flush_st_flt) { + plt_warn("CTX flush could not complete"); + return -EIO; + } break; case ROC_NIX_INL_SA_OP_RELOAD: reload.s.cptr = ((uintptr_t)sa) >> 7; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index cdd5656817..ec129b6584 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -297,47 +297,71 @@ cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev, return NULL; } +union rte_pmd_cnxk_ipsec_hw_sa * +rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb) +{ + struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uintptr_t sa_base; + + if (inb) + sa_base = roc_nix_inl_inb_sa_base_get(&dev->nix, dev->inb.inl_dev); + else + sa_base = roc_nix_inl_outb_sa_base_get(&dev->nix); + + return (union rte_pmd_cnxk_ipsec_hw_sa *)sa_base; +} + +int +rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb) +{ + struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + + return roc_nix_inl_sa_sync(&dev->nix, sess, inb, ROC_NIX_INL_SA_OP_FLUSH); +} + int -rte_pmd_cnxk_hw_sa_read(void *device, void *__sess, union rte_pmd_cnxk_ipsec_hw_sa *data, - uint32_t len) +rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, + uint32_t len, bool inb) { - struct rte_security_session *sess = __sess; - struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); struct cnxk_eth_sec_sess *eth_sec; + void *sa; int rc; eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); - if (eth_sec == NULL) - return -EINVAL; + if (eth_sec) + sa = eth_sec->sa; + else + sa = sess; - rc = roc_nix_inl_sa_sync(&dev->nix, eth_sec->sa, eth_sec->inb, ROC_NIX_INL_SA_OP_FLUSH); + rc = roc_nix_inl_sa_sync(&dev->nix, sa, inb, ROC_NIX_INL_SA_OP_FLUSH); if (rc) return -EINVAL; - rte_delay_ms(1); - memcpy(data, eth_sec->sa, len); + + memcpy(data, sa, len); return 0; } int -rte_pmd_cnxk_hw_sa_write(void *device, void *__sess, union rte_pmd_cnxk_ipsec_hw_sa *data, - uint32_t len) +rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, + uint32_t len, bool inb) { - struct rte_security_session *sess = __sess; - struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)device; + struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); struct cnxk_eth_sec_sess *eth_sec; - int rc = -EINVAL; + void *sa; eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); - if (eth_sec == NULL) - return rc; - rc = roc_nix_inl_ctx_write(&dev->nix, data, eth_sec->sa, eth_sec->inb, len); - if (rc) - return rc; + if (eth_sec) + sa = eth_sec->sa; + else + sa = sess; - return 0; + return roc_nix_inl_ctx_write(&dev->nix, data, sa, inb, len); } union rte_pmd_cnxk_cpt_res_s * diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h index 70f2f96fd4..ecd112e881 100644 --- a/drivers/net/cnxk/rte_pmd_cnxk.h +++ b/drivers/net/cnxk/rte_pmd_cnxk.h @@ -492,7 +492,7 @@ union rte_pmd_cnxk_cpt_res_s { /** * Read HW SA context from session. * - * @param device + * @param portid * Port identifier of Ethernet device. * @param sess * Handle of the security session as void *. @@ -500,17 +500,19 @@ union rte_pmd_cnxk_cpt_res_s { * Destination pointer to copy SA context for application. * @param len * Length of SA context to copy into data parameter. + * @param inb + * Determines the type of specified SA. * * @return * 0 on success, a negative errno value otherwise. */ __rte_experimental -int rte_pmd_cnxk_hw_sa_read(void *device, void *sess, - union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len); +int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, + uint32_t len, bool inb); /** * Write HW SA context to session. * - * @param device + * @param portid * Port identifier of Ethernet device. * @param sess * Handle of the security session as void *. @@ -518,13 +520,15 @@ int rte_pmd_cnxk_hw_sa_read(void *device, void *sess, * Source data pointer from application to copy SA context into session. * @param len * Length of SA context to copy from data parameter. + * @param inb + * Determines the type of specified SA. * * @return * 0 on success, a negative errno value otherwise. */ __rte_experimental -int rte_pmd_cnxk_hw_sa_write(void *device, void *sess, - union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len); +int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, + uint32_t len, bool inb); /** * Get pointer to CPT result info for inline inbound processed pkt. @@ -542,4 +546,36 @@ int rte_pmd_cnxk_hw_sa_write(void *device, void *sess, */ __rte_experimental union rte_pmd_cnxk_cpt_res_s *rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf); + +/** + * Get pointer to the Inline Inbound or Outbound SA table base. + * + * @param portid + * Port identifier of Ethernet device. + * @param inb + * Determines the type of SA base to be returned. + * When inb is true, the method returns the Inbound SA base. + * When inb is false, the method returns the Outbound SA base. + * + * @return + * Pointer to Inbound or Outbound SA base. + */ +__rte_experimental +union rte_pmd_cnxk_ipsec_hw_sa *rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb); + +/** + * Executes a CPT flush on the specified session. + * + * @param portid + * Port identifier of Ethernet device. + * @param sess + * Handle of the session on which the CPT flush will be executed. + * @param inb + * Determines the type of SA to be flushed, Inbound or Outbound. + * + * @return + * 0 upon success, a negative errno value otherwise. + */ +__rte_experimental +int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb); #endif /* _PMD_CNXK_H_ */ diff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map index 1ad0616bdf..7e8703df5c 100644 --- a/drivers/net/cnxk/version.map +++ b/drivers/net/cnxk/version.map @@ -10,7 +10,9 @@ EXPERIMENTAL { rte_pmd_cnxk_hw_sa_write; # added in 23.11 + rte_pmd_cnxk_hw_session_base_get; rte_pmd_cnxk_inl_ipsec_res; + rte_pmd_cnxk_sa_flush; }; INTERNAL { From patchwork Tue Oct 1 06:00:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144779 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7D1D445A74; Tue, 1 Oct 2024 08:02:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 793A540DD1; Tue, 1 Oct 2024 08:01:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id AC40440A7F for ; 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Mon, 30 Sep 2024 23:01:39 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:38 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 510FF3F7066; Mon, 30 Sep 2024 23:01:35 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Srujana Challa Subject: [PATCH v2 12/17] net/cnxk: add PMD APIs to submit CPT instruction Date: Tue, 1 Oct 2024 11:30:50 +0530 Message-ID: <20241001060055.3747591-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: EdV9xGfZIsxg0p8Hf7B0XWCGUTAGY1sz X-Proofpoint-ORIG-GUID: EdV9xGfZIsxg0p8Hf7B0XWCGUTAGY1sz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Introduces new PMD APIs for submitting CPT instructions to the Inline Device. These APIs allows applications to directly submit CPT instructions to the Inline Device. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_nix_inl.h | 12 ++++++- drivers/common/cnxk/roc_nix_inl_dev.c | 32 +++++++++++++++++ drivers/common/cnxk/roc_nix_inl_priv.h | 2 ++ drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cn10k_ethdev_sec.c | 42 ++++++++++++++++++++++ drivers/net/cnxk/cn9k_ethdev_sec.c | 14 ++++++++ drivers/net/cnxk/cnxk_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev.h | 48 ++++++++++++++++++++++++++ drivers/net/cnxk/cnxk_ethdev_sec.c | 19 ++++++++++ drivers/net/cnxk/rte_pmd_cnxk.h | 35 +++++++++++++++++++ drivers/net/cnxk/version.map | 2 ++ 11 files changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 1a4bf8808c..974834a0f3 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -99,10 +99,19 @@ struct roc_nix_inl_dev { uint8_t rx_inj_ena; /* Rx Inject Enable */ /* End of input parameters */ -#define ROC_NIX_INL_MEM_SZ (1408) +#define ROC_NIX_INL_MEM_SZ (2048) uint8_t reserved[ROC_NIX_INL_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; +struct roc_nix_inl_dev_q { + uint32_t nb_desc; + uintptr_t rbase; + uintptr_t lmt_base; + uint64_t *fc_addr; + uint64_t io_addr; + int32_t fc_addr_sw; +} __plt_cache_aligned; + /* NIX Inline Device API */ int __roc_api roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev); int __roc_api roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev); @@ -176,5 +185,6 @@ int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, bool inb, uint16_t sa_len); void __roc_api roc_nix_inl_outb_cpt_lfs_dump(struct roc_nix *roc_nix, FILE *file); uint64_t __roc_api roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix); +void *__roc_api roc_nix_inl_dev_qptr_get(uint8_t qid); #endif /* _ROC_NIX_INL_H_ */ diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index e2bbe3a67b..84c69a44c5 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -168,6 +168,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena) static int nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso) { + struct roc_nix_inl_dev_q *q_info; struct dev *dev = &inl_dev->dev; bool ctx_ilen_valid = false; struct roc_cpt_lf *lf; @@ -209,6 +210,13 @@ nix_inl_cpt_setup(struct nix_inl_dev *inl_dev, bool inl_dev_sso) goto lf_free; } + q_info = &inl_dev->q_info[i]; + q_info->nb_desc = lf->nb_desc; + q_info->fc_addr = lf->fc_addr; + q_info->io_addr = lf->io_addr; + q_info->lmt_base = lf->lmt_base; + q_info->rbase = lf->rbase; + roc_cpt_iq_enable(lf); } return 0; @@ -835,6 +843,30 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev) return rc; } +void * +roc_nix_inl_dev_qptr_get(uint8_t qid) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev = NULL; + + if (idev) + inl_dev = idev->nix_inl_dev; + + if (!inl_dev) { + plt_err("Inline Device could not be detected\n"); + return NULL; + } + if (!inl_dev->attach_cptlf) { + plt_err("No CPT LFs are attached to Inline Device\n"); + return NULL; + } + if (qid >= inl_dev->nb_cptlf) { + plt_err("Invalid qid: %u total queues: %d\n", qid, inl_dev->nb_cptlf); + return NULL; + } + return &inl_dev->q_info[qid]; +} + int roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats) { diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index 5afc7d6655..64b8b3977d 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -100,6 +100,8 @@ struct nix_inl_dev { uint32_t curr_ipsec_idx; uint32_t max_ipsec_rules; uint32_t alloc_ipsec_rules; + + struct roc_nix_inl_dev_q q_info[NIX_INL_CPT_LF]; }; int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index f98738d07e..8832c75eef 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -267,6 +267,7 @@ INTERNAL { roc_nix_inl_meta_pool_cb_register; roc_nix_inl_custom_meta_pool_cb_register; roc_nix_inb_mode_set; + roc_nix_inl_dev_qptr_get; roc_nix_inl_outb_fini; roc_nix_inl_outb_init; roc_nix_inl_outb_lf_base_get; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 074bb09822..f22f2ae12d 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -1305,6 +1305,45 @@ cn10k_eth_sec_rx_inject_config(void *device, uint16_t port_id, bool enable) return 0; } +#define CPT_LMTST_BURST 32 +static uint16_t +cn10k_inl_dev_submit(struct roc_nix_inl_dev_q *q, void *inst, uint16_t nb_inst) +{ + uintptr_t lbase = q->lmt_base; + uint8_t lnum, shft, loff; + uint16_t left, burst; + rte_iova_t io_addr; + uint16_t lmt_id; + + /* Check the flow control to avoid the queue overflow */ + if (cnxk_nix_inl_fc_check(q->fc_addr, &q->fc_addr_sw, q->nb_desc, nb_inst)) + return 0; + + io_addr = q->io_addr; + ROC_LMT_CPT_BASE_ID_GET(lbase, lmt_id); + + left = nb_inst; +again: + burst = left > CPT_LMTST_BURST ? CPT_LMTST_BURST : left; + + lnum = 0; + loff = 0; + shft = 16; + memcpy(PLT_PTR_CAST(lbase), inst, burst * sizeof(struct cpt_inst_s)); + loff = (burst % 2) ? 1 : 0; + lnum = (burst / 2); + shft = shft + (lnum * 3); + + left -= burst; + cn10k_nix_sec_steorl(io_addr, lmt_id, lnum, loff, shft); + rte_io_wmb(); + if (left) { + inst = RTE_PTR_ADD(inst, burst * sizeof(struct cpt_inst_s)); + goto again; + } + return nb_inst; +} + void cn10k_eth_sec_ops_override(void) { @@ -1341,4 +1380,7 @@ cn10k_eth_sec_ops_override(void) cnxk_eth_sec_ops.macsec_sa_stats_get = cnxk_eth_macsec_sa_stats_get; cnxk_eth_sec_ops.rx_inject_configure = cn10k_eth_sec_rx_inject_config; cnxk_eth_sec_ops.inb_pkt_rx_inject = cn10k_eth_sec_inb_rx_inject; + + /* Update platform specific rte_pmd_cnxk ops */ + cnxk_pmd_ops.inl_dev_submit = cn10k_inl_dev_submit; } diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c index a0e0a73639..ae8d04be69 100644 --- a/drivers/net/cnxk/cn9k_ethdev_sec.c +++ b/drivers/net/cnxk/cn9k_ethdev_sec.c @@ -845,6 +845,17 @@ cn9k_eth_sec_capabilities_get(void *device __rte_unused) return cn9k_eth_sec_capabilities; } +static uint16_t +cn9k_inl_dev_submit(struct roc_nix_inl_dev_q *q, void *inst, uint16_t nb_inst) +{ + /* Not supported */ + PLT_SET_USED(q); + PLT_SET_USED(inst); + PLT_SET_USED(nb_inst); + + return 0; +} + void cn9k_eth_sec_ops_override(void) { @@ -859,4 +870,7 @@ cn9k_eth_sec_ops_override(void) cnxk_eth_sec_ops.session_update = cn9k_eth_sec_session_update; cnxk_eth_sec_ops.session_destroy = cn9k_eth_sec_session_destroy; cnxk_eth_sec_ops.capabilities_get = cn9k_eth_sec_capabilities_get; + + /* Update platform specific rte_pmd_cnxk ops */ + cnxk_pmd_ops.inl_dev_submit = cn9k_inl_dev_submit; } diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index dd065c8269..13b7e8a38c 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -135,6 +135,7 @@ nix_security_setup(struct cnxk_eth_dev *dev) rc = -ENOMEM; goto cleanup; } + dev->inb.inl_dev_q = roc_nix_inl_dev_qptr_get(0); } if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY || diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 5920488e1a..d4440b25ac 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -260,6 +260,9 @@ struct cnxk_eth_dev_sec_inb { /* Disable custom meta aura */ bool custom_meta_aura_dis; + + /* Inline device CPT queue info */ + struct roc_nix_inl_dev_q *inl_dev_q; }; /* Outbound security data */ @@ -499,6 +502,42 @@ cnxk_nix_tx_queue_sec_count(uint64_t *mem, uint16_t sqes_per_sqb_log2, uint64_t return (val & 0xFFFF); } +static inline int +cnxk_nix_inl_fc_check(uint64_t *fc, int32_t *fc_sw, uint32_t nb_desc, uint16_t nb_inst) +{ + uint8_t retry_count = 32; + int32_t val, newval; + + /* Check if there is any CPT instruction to submit */ + if (!nb_inst) + return -EINVAL; + +retry: + val = rte_atomic_fetch_sub_explicit((RTE_ATOMIC(int32_t)*)fc_sw, nb_inst, + rte_memory_order_relaxed) - nb_inst; + if (likely(val >= 0)) + return 0; + + newval = (int64_t)nb_desc - rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)fc, + rte_memory_order_relaxed); + newval -= nb_inst; + + if (!rte_atomic_compare_exchange_strong_explicit((RTE_ATOMIC(int32_t)*)fc_sw, &val, newval, + rte_memory_order_release, + rte_memory_order_relaxed)) { + if (retry_count) { + retry_count--; + goto retry; + } else { + return -EAGAIN; + } + } + if (unlikely(newval < 0)) + return -EAGAIN; + + return 0; +} + /* Common ethdev ops */ extern struct eth_dev_ops cnxk_eth_dev_ops; @@ -511,6 +550,15 @@ extern struct rte_security_ops cnxk_eth_sec_ops; /* Common tm ops */ extern struct rte_tm_ops cnxk_tm_ops; +/* Platform specific rte pmd cnxk ops */ +typedef uint16_t (*cnxk_inl_dev_submit_cb_t)(struct roc_nix_inl_dev_q *q, void *inst, + uint16_t nb_inst); + +struct cnxk_ethdev_pmd_ops { + cnxk_inl_dev_submit_cb_t inl_dev_submit; +}; +extern struct cnxk_ethdev_pmd_ops cnxk_pmd_ops; + /* Ops */ int cnxk_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev); diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index ec129b6584..7e5103bf54 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -33,6 +33,8 @@ struct inl_cpt_channel { #define CNXK_NIX_INL_DEV_NAME_LEN \ (sizeof(CNXK_NIX_INL_DEV_NAME) + PCI_PRI_STR_SIZE) +struct cnxk_ethdev_pmd_ops cnxk_pmd_ops; + static inline int bitmap_ctzll(uint64_t slab) { @@ -297,6 +299,18 @@ cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev, return NULL; } +uint16_t +rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst, uint16_t nb_inst) +{ + return cnxk_pmd_ops.inl_dev_submit((struct roc_nix_inl_dev_q *)qptr, inst, nb_inst); +} + +struct rte_pmd_cnxk_inl_dev_q * +rte_pmd_cnxk_inl_dev_qptr_get(void) +{ + return roc_nix_inl_dev_qptr_get(0); +} + union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb) { @@ -353,6 +367,7 @@ rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_h struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); struct cnxk_eth_sec_sess *eth_sec; + struct roc_nix_inl_dev_q *q; void *sa; eth_sec = cnxk_eth_sec_sess_get_by_sess(dev, sess); @@ -361,6 +376,10 @@ rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_h else sa = sess; + q = dev->inb.inl_dev_q; + if (q && cnxk_nix_inl_fc_check(q->fc_addr, &q->fc_addr_sw, q->nb_desc, 1)) + return -EAGAIN; + return roc_nix_inl_ctx_write(&dev->nix, data, sa, inb, len); } diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h index ecd112e881..798547e731 100644 --- a/drivers/net/cnxk/rte_pmd_cnxk.h +++ b/drivers/net/cnxk/rte_pmd_cnxk.h @@ -489,6 +489,13 @@ union rte_pmd_cnxk_cpt_res_s { uint64_t u64[2]; }; +/** Forward structure declaration for inline device queue. Applications obtain a pointer + * to this structure using the ``rte_pmd_cnxk_inl_dev_qptr_get`` API and use it to submit + * CPT instructions (cpt_inst_s) to the inline device via the + * ``rte_pmd_cnxk_inl_dev_submit`` API. + */ +struct rte_pmd_cnxk_inl_dev_q; + /** * Read HW SA context from session. * @@ -578,4 +585,32 @@ union rte_pmd_cnxk_ipsec_hw_sa *rte_pmd_cnxk_hw_session_base_get(uint16_t portid */ __rte_experimental int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb); + +/** + * Get queue pointer of Inline Device. + * + * @return + * - Pointer to queue structure that would be the input to submit API. + * - NULL upon failure. + */ +__rte_experimental +struct rte_pmd_cnxk_inl_dev_q *rte_pmd_cnxk_inl_dev_qptr_get(void); + +/** + * Submit CPT instruction(s) (cpt_inst_s) to Inline Device. + * + * @param qptr + * Pointer obtained with ``rte_pmd_cnxk_inl_dev_qptr_get``. + * @param inst + * Pointer to an array of ``cpt_inst_s`` prapared by application. + * @param nb_inst + * Number of instructions to be processed. + * + * @return + * Number of instructions processed. + */ +__rte_experimental +uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst, + uint16_t nb_inst); + #endif /* _PMD_CNXK_H_ */ diff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map index 7e8703df5c..58dcb1fac0 100644 --- a/drivers/net/cnxk/version.map +++ b/drivers/net/cnxk/version.map @@ -11,6 +11,8 @@ EXPERIMENTAL { # added in 23.11 rte_pmd_cnxk_hw_session_base_get; + rte_pmd_cnxk_inl_dev_qptr_get; + rte_pmd_cnxk_inl_dev_submit; rte_pmd_cnxk_inl_ipsec_res; rte_pmd_cnxk_sa_flush; }; From patchwork Tue Oct 1 06:00:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144780 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C654345A74; Tue, 1 Oct 2024 08:02:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C5B940668; 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Mon, 30 Sep 2024 23:01:43 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:42 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C996B3F7066; Mon, 30 Sep 2024 23:01:38 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Srujana Challa Subject: [PATCH v2 13/17] net/cnxk: add PMD API to retrieve CPT queue statistics Date: Tue, 1 Oct 2024 11:30:51 +0530 Message-ID: <20241001060055.3747591-13-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: g2Z6scKJZNBYrS7Hm_lopo8rBd_nszsh X-Proofpoint-ORIG-GUID: g2Z6scKJZNBYrS7Hm_lopo8rBd_nszsh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Introduces a new PMD API to obtain CPT queue statistics, including: - CPT_LF_CTX_ENC_BYTE_CNT - Encrypted byte count on the given queue - CPT_LF_CTX_ENC_PKT_CNT - Encrypted packet count on the given queue - CPT_LF_CTX_DEC_BYTE_CNT - Decrypted byte count on the given queue - CPT_LF_CTX_DEC_PKT_CNT - Decrypted packet count on the given queue This API enables applications to access CPT queue statistics directly. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_nix_inl.c | 67 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 15 +++++++ drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev_sec.c | 11 +++++ drivers/net/cnxk/rte_pmd_cnxk.h | 43 +++++++++++++++++++ drivers/net/cnxk/version.map | 1 + 6 files changed, 138 insertions(+) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 23ffd4391a..dd3a8f6ec0 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1812,6 +1812,73 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, return -ENOTSUP; } +static inline int +nix_inl_dev_cpt_lf_stats_get(struct roc_nix *roc_nix, struct roc_nix_cpt_lf_stats *stats, + uint16_t idx) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev = NULL; + struct roc_cpt_lf *lf = NULL; + + PLT_SET_USED(roc_nix); + if (idev) + inl_dev = idev->nix_inl_dev; + + if (inl_dev && inl_dev->attach_cptlf) { + if (idx >= inl_dev->nb_cptlf) { + plt_err("Invalid idx: %u total lfs: %d\n", idx, inl_dev->nb_cptlf); + return -EINVAL; + } + lf = &inl_dev->cpt_lf[idx]; + } else { + plt_err("No CPT LF(s) are found for Inline Device\n"); + return -EINVAL; + } + stats->enc_pkts = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT); + stats->enc_bytes = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT); + stats->dec_pkts = plt_read64(lf->rbase + CPT_LF_CTX_DEC_PKT_CNT); + stats->dec_bytes = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT); + + return 0; +} + +static inline int +nix_eth_dev_cpt_lf_stats_get(struct roc_nix *roc_nix, struct roc_nix_cpt_lf_stats *stats, + uint16_t idx) +{ + struct roc_cpt_lf *lf; + struct nix *nix; + + if (!roc_nix) + return -EINVAL; + nix = roc_nix_to_nix_priv(roc_nix); + if (idx >= nix->nb_cpt_lf) { + plt_err("Invalid idx: %u total lfs: %d\n", idx, nix->nb_cpt_lf); + return -EINVAL; + } + lf = &nix->cpt_lf_base[idx]; + stats->enc_pkts = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT); + stats->enc_bytes = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT); + stats->dec_pkts = plt_read64(lf->rbase + CPT_LF_CTX_DEC_PKT_CNT); + stats->dec_bytes = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT); + + return 0; +} + +int +roc_nix_inl_cpt_lf_stats_get(struct roc_nix *roc_nix, enum roc_nix_cpt_lf_stats_type type, + struct roc_nix_cpt_lf_stats *stats, uint16_t idx) +{ + switch (type) { + case ROC_NIX_CPT_LF_STATS_INL_DEV: + return nix_inl_dev_cpt_lf_stats_get(roc_nix, stats, idx); + case ROC_NIX_CPT_LF_STATS_ETHDEV: + return nix_eth_dev_cpt_lf_stats_get(roc_nix, stats, idx); + default: + return -EINVAL; + } +} + int roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 974834a0f3..16cead7fa4 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -112,6 +112,13 @@ struct roc_nix_inl_dev_q { int32_t fc_addr_sw; } __plt_cache_aligned; +struct roc_nix_cpt_lf_stats { + uint64_t enc_pkts; + uint64_t enc_bytes; + uint64_t dec_pkts; + uint64_t dec_bytes; +}; + /* NIX Inline Device API */ int __roc_api roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev); int __roc_api roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev); @@ -187,4 +194,12 @@ void __roc_api roc_nix_inl_outb_cpt_lfs_dump(struct roc_nix *roc_nix, FILE *file uint64_t __roc_api roc_nix_inl_eng_caps_get(struct roc_nix *roc_nix); void *__roc_api roc_nix_inl_dev_qptr_get(uint8_t qid); +enum roc_nix_cpt_lf_stats_type { + ROC_NIX_CPT_LF_STATS_INL_DEV, + ROC_NIX_CPT_LF_STATS_KERNEL, + ROC_NIX_CPT_LF_STATS_ETHDEV = 2, +}; +int __roc_api roc_nix_inl_cpt_lf_stats_get(struct roc_nix *roc_nix, + enum roc_nix_cpt_lf_stats_type type, + struct roc_nix_cpt_lf_stats *stats, uint16_t idx); #endif /* _ROC_NIX_INL_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8832c75eef..6f8a2e02da 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -267,6 +267,7 @@ INTERNAL { roc_nix_inl_meta_pool_cb_register; roc_nix_inl_custom_meta_pool_cb_register; roc_nix_inb_mode_set; + roc_nix_inl_cpt_lf_stats_get; roc_nix_inl_dev_qptr_get; roc_nix_inl_outb_fini; roc_nix_inl_outb_init; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 7e5103bf54..32b6946ac1 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -311,6 +311,17 @@ rte_pmd_cnxk_inl_dev_qptr_get(void) return roc_nix_inl_dev_qptr_get(0); } +int +rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type, + struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx) +{ + struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + + return roc_nix_inl_cpt_lf_stats_get(&dev->nix, (enum roc_nix_cpt_lf_stats_type)type, + (struct roc_nix_cpt_lf_stats *)stats, idx); +} + union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb) { diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h index 798547e731..dcb4f334fe 100644 --- a/drivers/net/cnxk/rte_pmd_cnxk.h +++ b/drivers/net/cnxk/rte_pmd_cnxk.h @@ -47,6 +47,30 @@ enum rte_pmd_cnxk_sec_action_alg { RTE_PMD_CNXK_SEC_ACTION_ALG4, }; +/** CPT queue type for obtaining queue hardware statistics. */ +enum rte_pmd_cnxk_cpt_q_stats_type { + /** Type to get Inline Device LF(s) statistics */ + RTE_PMD_CNXK_CPT_Q_STATS_INL_DEV, + /** Type to get Inline Inbound LF which is attached to kernel device + * statistics. + */ + RTE_PMD_CNXK_CPT_Q_STATS_KERNEL, + /** Type to get CPT LF which is attached to ethdev statistics */ + RTE_PMD_CNXK_CPT_Q_STATS_ETHDEV = 2, +}; + +/** CPT queue hardware statistics */ +struct rte_pmd_cnxk_cpt_q_stats { + /** Encrypted packet count */ + uint64_t enc_pkts; + /** Encrypted byte count */ + uint64_t enc_bytes; + /** Decrypted packet count */ + uint64_t dec_pkts; + /** Decrypted byte count */ + uint64_t dec_bytes; +}; + struct rte_pmd_cnxk_sec_action { /** Used as lookup result for ALG3 */ uint32_t sa_index; @@ -613,4 +637,23 @@ __rte_experimental uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst, uint16_t nb_inst); +/** + * Retrieves the hardware statistics of a given port and stats type. + * + * @param portid + * Port identifier of Ethernet device. + * @param type + * The type of hardware statistics to retrieve, as defined in the + * ``enum rte_pmd_cnxk_cpt_q_stats_type``. + * @param stats + * Pointer where the retrieved statistics will be stored. + * @param idx + * The index of the queue of a given type. + * + * @return + * 0 upon success, a negative errno value otherwise. + */ +__rte_experimental +int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type, + struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx); #endif /* _PMD_CNXK_H_ */ diff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map index 58dcb1fac0..02a02edc25 100644 --- a/drivers/net/cnxk/version.map +++ b/drivers/net/cnxk/version.map @@ -10,6 +10,7 @@ EXPERIMENTAL { rte_pmd_cnxk_hw_sa_write; # added in 23.11 + rte_pmd_cnxk_cpt_q_stats_get; rte_pmd_cnxk_hw_session_base_get; rte_pmd_cnxk_inl_dev_qptr_get; rte_pmd_cnxk_inl_dev_submit; From patchwork Tue Oct 1 06:00:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144781 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 11A8445A74; Tue, 1 Oct 2024 08:02:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 67A4840A87; Tue, 1 Oct 2024 08:01:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D91CD40DF8 for ; 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Mon, 30 Sep 2024 23:01:46 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:45 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 624A63F7066; Mon, 30 Sep 2024 23:01:42 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Srujana Challa Subject: [PATCH v2 14/17] net/cnxk: add option to enable custom inbound sa usage Date: Tue, 1 Oct 2024 11:30:52 +0530 Message-ID: <20241001060055.3747591-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 5cFV_CE28PxyC_YnznOSMzwsvYdnF0PP X-Proofpoint-GUID: 5cFV_CE28PxyC_YnznOSMzwsvYdnF0PP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa Introduces a device argument (custom_inb_sa) to activate the usage of custom inbound SA. If inline device is used then this device argument will be required for both inline device and eth device. With custom_inb_sa configuration, application can do the post processing of inline IPsec inbound packet directly. This patch also adds a RTE PMD API for inline inbound param1 and param2 configuration. Signed-off-by: Srujana Challa --- doc/guides/nics/cnxk.rst | 25 +++++++++++++++++++++ drivers/common/cnxk/roc_nix.h | 3 +++ drivers/common/cnxk/roc_nix_inl.c | 19 +++++++++++++--- drivers/common/cnxk/roc_nix_inl.h | 2 ++ drivers/common/cnxk/roc_nix_inl_dev.c | 3 +++ drivers/common/cnxk/roc_nix_inl_priv.h | 1 + drivers/net/cnxk/cn10k_ethdev.c | 2 +- drivers/net/cnxk/cn10k_ethdev_sec.c | 5 +++++ drivers/net/cnxk/cnxk_ethdev.c | 3 +++ drivers/net/cnxk/cnxk_ethdev_devargs.c | 4 ++++ drivers/net/cnxk/cnxk_ethdev_sec.c | 21 +++++++++++++++--- drivers/net/cnxk/rte_pmd_cnxk.h | 30 +++++++++++++++++++++++--- drivers/net/cnxk/version.map | 1 + 13 files changed, 109 insertions(+), 10 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index ff380c10e9..85ca555115 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -457,6 +457,19 @@ Runtime Config Options With the above configuration, the driver would disable custom meta aura feature for the device ``0002:02:00.0``. +- ``Enable custom sa for inbound inline IPsec`` (default ``0``) + + Custom SA for inbound inline IPsec can be enabled by specifying ``custom_inb_sa`` + ``devargs`` parameter. This option needs to be given to both ethdev and inline + device. + + For example:: + + -a 0002:02:00.0,custom_inb_sa=1 + + With the above configuration, inline inbound IPsec post processing should be done + by the application. + .. note:: Above devarg parameters are configurable per device, user needs to pass the @@ -655,6 +668,18 @@ Runtime Config Options for inline device With the above configuration, driver would enable packet inject from ARM cores to crypto to process and send back in Rx path. +- ``Enable custom sa for inbound inline IPsec`` (default ``0``) + + Custom SA for inbound inline IPsec can be enabled by specifying ``custom_inb_sa`` + ``devargs`` parameter with both inline device and ethdev. + + For example:: + + -a 0002:1d:00.0,custom_inb_sa=1 + + With the above configuration, inline inbound IPsec post processing should be done + by the application. + Port Representors ----------------- diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 25cf261348..f213823b9b 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -473,7 +473,10 @@ struct roc_nix { bool force_rx_aura_bp; bool custom_meta_aura_ena; bool rx_inj_ena; + bool custom_inb_sa; uint32_t root_sched_weight; + uint16_t inb_cfg_param1; + uint16_t inb_cfg_param2; /* End of input parameters */ /* LMT line base for "Per Core Tx LMT line" mode*/ uintptr_t lmt_base; diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index dd3a8f6ec0..9f350defac 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -406,6 +406,8 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix) /* CN9K SA size is different */ if (roc_model_is_cn9k()) inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ; + else if (roc_nix->custom_inb_sa) + inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ; else inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ; @@ -910,6 +912,11 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) cfg.param1 = u.u16; cfg.param2 = 0; cfg.opcode = (ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC | (1 << 6)); + + if (roc_nix->custom_inb_sa) { + cfg.param1 = roc_nix->inb_cfg_param1; + cfg.param2 = roc_nix->inb_cfg_param2; + } rc = roc_nix_bpids_alloc(roc_nix, ROC_NIX_INTF_TYPE_CPT_NIX, 1, bpids); if (rc > 0) { nix->cpt_nixbpid = bpids[0]; @@ -1767,7 +1774,6 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, if (roc_model_is_cn9k()) { return 0; } - if (idev) inl_dev = idev->nix_inl_dev; @@ -1775,6 +1781,11 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, return -EINVAL; if (roc_nix) { + if (inb && roc_nix->custom_inb_sa && sa_len > ROC_NIX_INL_INB_CUSTOM_SA_SZ) { + plt_nix_dbg("SA length: %u is more than allocated length: %u\n", sa_len, + ROC_NIX_INL_INB_CUSTOM_SA_SZ); + return -EINVAL; + } nix = roc_nix_to_nix_priv(roc_nix); outb_lf = nix->cpt_lf_base; @@ -1889,6 +1900,7 @@ roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev) uint16_t max_spi = 0; uint32_t rq_refs = 0; uint8_t pkind = 0; + size_t inb_sa_sz; int i; if (roc_model_is_cn9k()) @@ -1906,6 +1918,7 @@ roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev) if (!nix->inl_inb_ena) return 0; sa_base = nix->inb_sa_base; + inb_sa_sz = nix->inb_sa_sz; max_spi = roc_nix->ipsec_in_max_spi; } @@ -1917,6 +1930,7 @@ roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev) inl_dev->ts_ena = ts_ena; max_spi = inl_dev->ipsec_in_max_spi; sa_base = inl_dev->inb_sa_base; + inb_sa_sz = inl_dev->inb_sa_sz; } else if (inl_dev->ts_ena != ts_ena) { if (inl_dev->ts_ena) plt_err("Inline device is already configured with TS enable"); @@ -1935,8 +1949,7 @@ roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev) return 0; for (i = 0; i < max_spi; i++) { - sa = ((uint8_t *)sa_base) + - (i * ROC_NIX_INL_OT_IPSEC_INB_SA_SZ); + sa = ((uint8_t *)sa_base) + (i * inb_sa_sz); ((struct roc_ot_ipsec_inb_sa *)sa)->w0.s.pkind = pkind; } return 0; diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 16cead7fa4..e26e3fe38c 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -33,6 +33,7 @@ #define ROC_NIX_INL_MAX_SOFT_EXP_RNGS \ (PLT_MAX_ETHPORTS * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS) +#define ROC_NIX_INL_INB_CUSTOM_SA_SZ 512 /* Reassembly configuration */ #define ROC_NIX_INL_REAS_ACTIVE_LIMIT 0xFFF @@ -97,6 +98,7 @@ struct roc_nix_inl_dev { uint32_t meta_buf_sz; uint32_t max_ipsec_rules; uint8_t rx_inj_ena; /* Rx Inject Enable */ + uint8_t custom_inb_sa; /* End of input parameters */ #define ROC_NIX_INL_MEM_SZ (2048) diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 84c69a44c5..753b60563a 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -420,6 +420,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev) /* CN9K SA is different */ if (roc_model_is_cn9k()) inb_sa_sz = ROC_NIX_INL_ON_IPSEC_INB_SA_SZ; + else if (inl_dev->custom_inb_sa) + inb_sa_sz = ROC_NIX_INL_INB_CUSTOM_SA_SZ; else inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ; @@ -942,6 +944,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs; inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz; inl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq; + inl_dev->custom_inb_sa = roc_inl_dev->custom_inb_sa; if (roc_inl_dev->rx_inj_ena) { inl_dev->rx_inj_ena = 1; diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index 64b8b3977d..e5494fd71a 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -94,6 +94,7 @@ struct nix_inl_dev { uint32_t nb_meta_bufs; uint32_t meta_buf_sz; uint8_t rx_inj_ena; /* Rx Inject Enable */ + uint8_t custom_inb_sa; /* NPC */ int *ipsec_index; diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index d335f3971b..bf9c97020a 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -36,7 +36,7 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev) if (!dev->ptype_disable) flags |= NIX_RX_OFFLOAD_PTYPE_F; - if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && !dev->nix.custom_inb_sa) flags |= NIX_RX_OFFLOAD_SECURITY_F; return flags; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index f22f2ae12d..84e570f5b9 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -754,6 +754,9 @@ cn10k_eth_sec_session_create(void *device, else if (conf->protocol != RTE_SECURITY_PROTOCOL_IPSEC) return -ENOTSUP; + if (nix->custom_inb_sa) + return -ENOTSUP; + if (rte_security_dynfield_register() < 0) return -ENOTSUP; @@ -1038,6 +1041,8 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess) return cnxk_eth_macsec_session_destroy(dev, sess); return -ENOENT; } + if (dev->nix.custom_inb_sa) + return -ENOTSUP; lock = eth_sec->inb ? &dev->inb.lock : &dev->outb.lock; rte_spinlock_lock(lock); diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 13b7e8a38c..c7723800ef 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1269,6 +1269,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev) dev->rx_offloads = rxmode->offloads; dev->tx_offloads = txmode->offloads; + if (nix->custom_inb_sa) + dev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SECURITY; + /* Prepare rx cfg */ rx_cfg = ROC_NIX_LF_RX_CFG_DIS_APAD; if (dev->rx_offloads & diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index 3454295d7d..5bd50bb9a1 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -281,6 +281,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args) #define CNXK_FLOW_AGING_POLL_FREQ "aging_poll_freq" #define CNXK_NIX_RX_INJ_ENABLE "rx_inj_ena" #define CNXK_CUSTOM_META_AURA_DIS "custom_meta_aura_dis" +#define CNXK_CUSTOM_INB_SA "custom_inb_sa" int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) @@ -304,6 +305,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) uint16_t scalar_enable = 0; uint16_t tx_compl_ena = 0; uint16_t custom_sa_act = 0; + uint8_t custom_inb_sa = 0; struct rte_kvargs *kvlist; uint32_t meta_buf_sz = 0; uint16_t no_inl_dev = 0; @@ -362,6 +364,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) rte_kvargs_process(kvlist, CNXK_NIX_RX_INJ_ENABLE, &parse_flag, &rx_inj_ena); rte_kvargs_process(kvlist, CNXK_CUSTOM_META_AURA_DIS, &parse_flag, &custom_meta_aura_dis); + rte_kvargs_process(kvlist, CNXK_CUSTOM_INB_SA, &parse_flag, &custom_inb_sa); rte_kvargs_free(kvlist); null_devargs: @@ -381,6 +384,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->nix.lock_rx_ctx = lock_rx_ctx; dev->nix.custom_sa_action = custom_sa_act; dev->nix.sqb_slack = sqb_slack; + dev->nix.custom_inb_sa = custom_inb_sa; if (roc_feature_nix_has_own_meta_aura()) dev->nix.meta_buf_sz = meta_buf_sz; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 32b6946ac1..051588e65e 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -19,6 +19,7 @@ #define CNXK_NIX_SOFT_EXP_POLL_FREQ "soft_exp_poll_freq" #define CNXK_MAX_IPSEC_RULES "max_ipsec_rules" #define CNXK_NIX_INL_RX_INJ_ENABLE "rx_inj_ena" +#define CNXK_NIX_CUSTOM_INB_SA "custom_inb_sa" /* Default soft expiry poll freq in usec */ #define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100 @@ -198,7 +199,7 @@ parse_max_ipsec_rules(const char *key, const char *value, void *extra_args) } static int -parse_inl_rx_inj_ena(const char *key, const char *value, void *extra_args) +parse_val_u8(const char *key, const char *value, void *extra_args) { RTE_SET_USED(key); uint32_t val; @@ -412,6 +413,16 @@ rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf) return (void *)(wqe + 64 + desc_size); } +void +rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg) +{ + struct rte_eth_dev *eth_dev = &rte_eth_devices[portid]; + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + + dev->nix.inb_cfg_param1 = cfg->param1; + dev->nix.inb_cfg_param2 = cfg->param2; +} + static unsigned int cnxk_eth_sec_session_get_size(void *device __rte_unused) { @@ -481,6 +492,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, struct inl_cpt_channel cpt_channel; uint32_t max_ipsec_rules = 0; struct rte_kvargs *kvlist; + uint8_t custom_inb_sa = 0; uint32_t nb_meta_bufs = 0; uint32_t meta_buf_sz = 0; uint8_t rx_inj_ena = 0; @@ -510,7 +522,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, rte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ, &parse_val_u32, &soft_exp_poll_freq); rte_kvargs_process(kvlist, CNXK_MAX_IPSEC_RULES, &parse_max_ipsec_rules, &max_ipsec_rules); - rte_kvargs_process(kvlist, CNXK_NIX_INL_RX_INJ_ENABLE, &parse_inl_rx_inj_ena, &rx_inj_ena); + rte_kvargs_process(kvlist, CNXK_NIX_INL_RX_INJ_ENABLE, &parse_val_u8, &rx_inj_ena); + rte_kvargs_process(kvlist, CNXK_NIX_CUSTOM_INB_SA, &parse_val_u8, &custom_inb_sa); rte_kvargs_free(kvlist); null_devargs: @@ -526,6 +539,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, inl_dev->max_ipsec_rules = max_ipsec_rules; if (roc_feature_nix_has_rx_inject()) inl_dev->rx_inj_ena = rx_inj_ena; + inl_dev->custom_inb_sa = custom_inb_sa; return 0; exit: return -EINVAL; @@ -654,4 +668,5 @@ RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl, CNXK_NIX_INL_META_BUF_SZ "=<1-U32_MAX>" CNXK_NIX_SOFT_EXP_POLL_FREQ "=<0-U32_MAX>" CNXK_MAX_IPSEC_RULES "=<1-4095>" - CNXK_NIX_INL_RX_INJ_ENABLE "=1"); + CNXK_NIX_INL_RX_INJ_ENABLE "=1" + CNXK_NIX_CUSTOM_INB_SA "=1"); diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h index dcb4f334fe..e207f43c80 100644 --- a/drivers/net/cnxk/rte_pmd_cnxk.h +++ b/drivers/net/cnxk/rte_pmd_cnxk.h @@ -49,13 +49,13 @@ enum rte_pmd_cnxk_sec_action_alg { /** CPT queue type for obtaining queue hardware statistics. */ enum rte_pmd_cnxk_cpt_q_stats_type { - /** Type to get Inline Device LF(s) statistics */ + /** Type to get Inline Device queue(s) statistics */ RTE_PMD_CNXK_CPT_Q_STATS_INL_DEV, - /** Type to get Inline Inbound LF which is attached to kernel device + /** Type to get Inline Inbound queue which is attached to kernel device * statistics. */ RTE_PMD_CNXK_CPT_Q_STATS_KERNEL, - /** Type to get CPT LF which is attached to ethdev statistics */ + /** Type to get CPT queue which is attached to ethdev statistics */ RTE_PMD_CNXK_CPT_Q_STATS_ETHDEV = 2, }; @@ -513,6 +513,18 @@ union rte_pmd_cnxk_cpt_res_s { uint64_t u64[2]; }; +/** Inline IPsec inbound queue configuration */ +struct rte_pmd_cnxk_ipsec_inb_cfg { + /** Param1 of PROCESS_INBOUND_IPSEC_PACKET as mentioned in the CPT + * microcode document. + */ + uint16_t param1; + /** Param2 of PROCESS_INBOUND_IPSEC_PACKET as mentioned in the CPT + * microcode document. + */ + uint16_t param2; +}; + /** Forward structure declaration for inline device queue. Applications obtain a pointer * to this structure using the ``rte_pmd_cnxk_inl_dev_qptr_get`` API and use it to submit * CPT instructions (cpt_inst_s) to the inline device via the @@ -656,4 +668,16 @@ uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void * __rte_experimental int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type, struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx); + +/** + * Set the configuration for hardware inline inbound IPsec processing. This API must be + * called before calling the ``rte_eth_dev_configure`` API. + * + * @param portid + * Port identifier of Ethernet device. + * @param cfg + * Pointer to the IPsec inbound configuration structure. + */ +__rte_experimental +void rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg); #endif /* _PMD_CNXK_H_ */ diff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map index 02a02edc25..dd41e7bd56 100644 --- a/drivers/net/cnxk/version.map +++ b/drivers/net/cnxk/version.map @@ -11,6 +11,7 @@ EXPERIMENTAL { # added in 23.11 rte_pmd_cnxk_cpt_q_stats_get; + rte_pmd_cnxk_hw_inline_inb_cfg_set; rte_pmd_cnxk_hw_session_base_get; rte_pmd_cnxk_inl_dev_qptr_get; rte_pmd_cnxk_inl_dev_submit; From patchwork Tue Oct 1 06:00:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144782 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5C7345A74; Tue, 1 Oct 2024 08:02:47 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8024E40DF6; Tue, 1 Oct 2024 08:01:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 984FD40E01 for ; Tue, 1 Oct 2024 08:01:51 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4914GiqU004021 for ; Mon, 30 Sep 2024 23:01:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=T EhdCzfIUD/Jz6eAqr2jnhjIpqYfEh8LlrlEOeb4XUo=; b=IIoW2e4XQkL9mgj+x Y8tDVhVn3YtmuwPzjIyU/M6vBRCTwGtp78vAHYO/Svi6F6pAp9i1Bgr+gNDFkJZg Uu6WjD5gY69g7CApvr1pkE8wZEAY+XWQT+rge5rSgOmuVaD6cmIn9omuzZdiLejZ AnbFEGO9/HfaBszR/irRuKsscfO2UKROLLs3NsHHS8RHm6Q6egZ5d32cDTJpWjBy kouhNZWh9PVTSPthRZB29on4vAQvZWiLslddJVoNCm2riqri70hXV2ChErK86kVe goMCP9+EorBX4dTC5mGdeoTH1M46rlAeMQatG3ybAYu1KD2Dxe32wTa42Qkc66ZU Tnl9A== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 41xf5m2etm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 30 Sep 2024 23:01:50 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:49 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D51A73F7066; Mon, 30 Sep 2024 23:01:45 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Srujana Challa Subject: [PATCH v2 15/17] net/cnxk: add PMD API to retrieve the model string Date: Tue, 1 Oct 2024 11:30:53 +0530 Message-ID: <20241001060055.3747591-15-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: rJTU7uzDot4l7tZd7gUT-XaTqGgX_dA8 X-Proofpoint-GUID: rJTU7uzDot4l7tZd7gUT-XaTqGgX_dA8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Srujana Challa This patch adds PMD API to retrieve the model string. This API allows applications to get the HW model string directly. Signed-off-by: Srujana Challa --- drivers/net/cnxk/cnxk_ethdev.c | 7 +++++++ drivers/net/cnxk/rte_pmd_cnxk.h | 9 +++++++++ drivers/net/cnxk/version.map | 1 + 3 files changed, 17 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index c7723800ef..23dc2a26cc 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -4,11 +4,18 @@ #include #include +#include #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) #define NIX_TM_DFLT_RR_WT 71 +const char * +rte_pmd_cnxk_model_str_get(void) +{ + return roc_model->name; +} + static inline uint64_t nix_get_rx_offload_capa(struct cnxk_eth_dev *dev) { diff --git a/drivers/net/cnxk/rte_pmd_cnxk.h b/drivers/net/cnxk/rte_pmd_cnxk.h index e207f43c80..a20b4f277d 100644 --- a/drivers/net/cnxk/rte_pmd_cnxk.h +++ b/drivers/net/cnxk/rte_pmd_cnxk.h @@ -680,4 +680,13 @@ int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_ */ __rte_experimental void rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg); + +/** + * Retrieves model name on which it is running as a string. + * + * @return + * Returns model string, ex."cn10ka_a1" + */ +__rte_experimental +const char *rte_pmd_cnxk_model_str_get(void); #endif /* _PMD_CNXK_H_ */ diff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map index dd41e7bd56..099c518ecf 100644 --- a/drivers/net/cnxk/version.map +++ b/drivers/net/cnxk/version.map @@ -16,6 +16,7 @@ EXPERIMENTAL { rte_pmd_cnxk_inl_dev_qptr_get; rte_pmd_cnxk_inl_dev_submit; rte_pmd_cnxk_inl_ipsec_res; + rte_pmd_cnxk_model_str_get; rte_pmd_cnxk_sa_flush; }; From patchwork Tue Oct 1 06:00:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144783 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06C9A45A74; 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Mon, 30 Sep 2024 23:01:53 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 30 Sep 2024 23:01:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:52 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 558F73F7066; Mon, 30 Sep 2024 23:01:49 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Harman Kalra CC: , Rakesh Kudurumalla Subject: [PATCH v2 16/17] net/cnxk: handle OOP for inbound packet Date: Tue, 1 Oct 2024 11:30:54 +0530 Message-ID: <20241001060055.3747591-16-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5p2QX1hvf-70WDyvlty6ZjVr274PoXdS X-Proofpoint-ORIG-GUID: 5p2QX1hvf-70WDyvlty6ZjVr274PoXdS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla To handle OOP for inbound packet, processing is done based on NIX_RX_REAS_F flag. but for boards that does not support reassembly Inbound Out-Of-Place processing test case fails because reassembly flag is not updated in event mode. This patch fixes the same. Signed-off-by: Rakesh Kudurumalla --- drivers/net/cnxk/cn10k_ethdev_sec.c | 10 ++++++++++ drivers/net/cnxk/cnxk_ethdev.h | 4 ++++ drivers/net/cnxk/version.map | 1 + 3 files changed, 15 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 84e570f5b9..e911c3730b 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -28,6 +28,13 @@ PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WIN_SIZE_MAX == ROC_AR_WIN_SIZE_MAX); PLT_STATIC_ASSERT(RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 == ROC_LOG_MIN_AR_WIN_SIZE_M1); PLT_STATIC_ASSERT(RTE_PMD_CNXK_AR_WINBITS_SZ == ROC_AR_WINBITS_SZ); +cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; +void +cnxk_ethdev_rx_offload_cb_register(cnxk_ethdev_rx_offload_cb_t cb) +{ + cnxk_ethdev_rx_offload_cb = cb; +} + static struct rte_cryptodev_capabilities cn10k_eth_sec_crypto_caps[] = { { /* AES GCM */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, @@ -908,6 +915,9 @@ cn10k_eth_sec_session_create(void *device, !(dev->rx_offload_flags & NIX_RX_REAS_F)) { dev->rx_offload_flags |= NIX_RX_REAS_F; cn10k_eth_set_rx_function(eth_dev); + if (cnxk_ethdev_rx_offload_cb) + cnxk_ethdev_rx_offload_cb(eth_dev->data->port_id, + NIX_RX_REAS_F); } } else { struct roc_ot_ipsec_outb_sa *outb_sa, *outb_sa_dptr; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index d4440b25ac..350adc1161 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -725,6 +725,10 @@ int cnxk_nix_lookup_mem_metapool_set(struct cnxk_eth_dev *dev); int cnxk_nix_lookup_mem_metapool_clear(struct cnxk_eth_dev *dev); __rte_internal int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev); +typedef void (*cnxk_ethdev_rx_offload_cb_t)(uint16_t port_id, uint64_t flags); +__rte_internal +void cnxk_ethdev_rx_offload_cb_register(cnxk_ethdev_rx_offload_cb_t cb); + struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev, uint32_t spi, bool inb); struct cnxk_eth_sec_sess * diff --git a/drivers/net/cnxk/version.map b/drivers/net/cnxk/version.map index 099c518ecf..edb0a1c059 100644 --- a/drivers/net/cnxk/version.map +++ b/drivers/net/cnxk/version.map @@ -23,4 +23,5 @@ EXPERIMENTAL { INTERNAL { global: cnxk_nix_inb_mode_set; + cnxk_ethdev_rx_offload_cb_register; }; From patchwork Tue Oct 1 06:00:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 144784 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC27D45A74; Tue, 1 Oct 2024 08:03:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3F7DC40E17; Tue, 1 Oct 2024 08:01:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 922C540E17 for ; Tue, 1 Oct 2024 08:01:57 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49102pvQ023192 for ; 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Mon, 30 Sep 2024 23:01:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 30 Sep 2024 23:01:55 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C3D6C3F7066; Mon, 30 Sep 2024 23:01:52 -0700 (PDT) From: Nithin Dabilpuram To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Rakesh Kudurumalla Subject: [PATCH v2 17/17] event/cnxk: handle inbound out of place processing Date: Tue, 1 Oct 2024 11:30:55 +0530 Message-ID: <20241001060055.3747591-17-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241001060055.3747591-1-ndabilpuram@marvell.com> References: <20241001060055.3747591-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: HJsncMcru9ChEa5n0bf468HykoewjNUA X-Proofpoint-ORIG-GUID: HJsncMcru9ChEa5n0bf468HykoewjNUA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla update event device with NIX_RX_REAS_F to handle out of place processing for boards that does not support reassembly as cn10k driver process OOP with NIX_RX_REAS_F enabled. Signed-off-by: Rakesh Kudurumalla --- drivers/event/cnxk/cn10k_eventdev.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 229d7a03fe..4e2968f91e 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -826,7 +826,7 @@ cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem) } static void -eventdev_fops_tstamp_update(struct rte_eventdev *event_dev) +eventdev_fops_update(struct rte_eventdev *event_dev) { struct rte_event_fp_ops *fp_op = rte_event_fp_ops + event_dev->data->dev_id; @@ -849,7 +849,20 @@ cn10k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en) else evdev->tstamp[port_id] = NULL; cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); - eventdev_fops_tstamp_update(event_dev); + eventdev_fops_update(event_dev); +} + +static void +cn10k_sso_rx_offload_cb(uint16_t port_id, uint64_t flags) +{ + struct rte_eth_dev *dev = &rte_eth_devices[port_id]; + struct cnxk_eth_dev *cnxk_eth_dev = dev->data->dev_private; + struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv; + struct cnxk_sso_evdev *evdev = cnxk_sso_pmd_priv(event_dev); + + evdev->rx_offloads |= flags; + cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev); + eventdev_fops_update(event_dev); } static int @@ -1224,6 +1237,7 @@ cn10k_sso_init(struct rte_eventdev *event_dev) return rc; } + cnxk_ethdev_rx_offload_cb_register(cn10k_sso_rx_offload_cb); event_dev->dev_ops = &cn10k_sso_dev_ops; /* For secondary processes, the primary has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) {