From patchwork Sat Apr 13 20:19:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 52751 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2E4825F72; Sat, 13 Apr 2019 22:19:56 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id C4C765F62 for ; Sat, 13 Apr 2019 22:19:54 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3DKJrQ9019165; Sat, 13 Apr 2019 13:19:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=/TRA5ZekUlcwbZ5fVN5zkuekbsk4OYcibnRSRi7Gh4k=; b=hSgLq5rwGkU/WyOwgGwRyqoZt0b1paQP121+EAKVDZ7/FvFmyy5HW6PGWN9WPD+quzPq InpIutc4/yNiG/+lU/tkWkTMqYaf6wrCUax/SALbJ6y9iy5njScHx/mnkSxOjPu6qIVZ tMN08ct19Z6YulkNjIe3pckXzAX62jkd/6coXHdsxz3upCfL2wU/14uVLVzvHY7UHel2 Hzi82vrEBltGS6C9PHJ4HnjlQlqZh2hlaMZsmFged/wv6BM/JFRuuhg+GSflYsHnawfe vpJvmKie53Rr77NKpmomPdcVer3+vaofdOnnUoHVrdWhvWE1SvMoqveQRNZLcX458aIx Bg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0a-0016f401.pphosted.com with ESMTP id 2rud4nhb55-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 13 Apr 2019 13:19:53 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 13 Apr 2019 13:19:52 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 13 Apr 2019 13:19:52 -0700 Received: from jerin-lab.marvell.com (unknown [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 4651F3F703F; Sat, 13 Apr 2019 13:19:51 -0700 (PDT) From: To: , Thomas Monjalon CC: , Jerin Jacob , Pavan Nikhilesh Date: Sun, 14 Apr 2019 01:49:43 +0530 Message-ID: <20190413201946.36566-1-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413190121.15416-1-jerinj@marvell.com> References: <20190413190121.15416-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_06:, , signatures=0 Subject: [dpdk-dev] [PATCH v10 1/4] mk: introduce helper to check valid compiler argument X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Introduce rte_cc_has_argument() Makefile helper to check a given argument is support by the compiler. Example Usage: include $(RTE_SDK)/mk/rte.helper.mk MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2) This would allow adding -mcpu=octeontx2 in MACHINE_CFLAGS if it is only supported by the compiler. The use case for such scheme is to enable the mcpu optimization if the compiler supports else it needs to compile the source code without any errors. This patch also moves inclusion of toolchain's rte.vars.mk to before the machine's rte.vars.mk inclusion to make correct CC available for the cross compile case. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh --- Change history of this series: v10 Changes: - Fix the following checkpatch warning http://mails.dpdk.org/archives/test-report/2019-April/080453.html v9 Changes: - Remove compiler version check as it is now done using cc.has_argument(). v8 Changes: - Remove redudant lists (rebase aritfacts). (Yongseok Koh) v7 Changes: - Updated cross compile config files align with "build: improve pcap dependency handling" changeset to fix build issue with meson - Some compiler needs the following depended patch to compile with meson http://patches.dpdk.org/patch/52367/ v6 Changes: - Rework to change the config files to sync with "mk: use linux and freebsd in config names" - Fix the following error with latest gcc by fixing the mcpu type cc1: error: switch -mcpu=armv8.2-a conflicts with -march=armv8-a switch v5 Changes: - Fix incorrect meson flag parsing(Phil Yang) - Squash meson cross build patch(5/5) into configuration update patches for thunderx2(3/5) and octeontx2(4/5)(Thomas) - Changed octeontx2's march as armv8-a and added the extension required instead of armv8-2a(Phil Yang) - Improved rte_cc_has_argument() implementaion by removing the temp file(Thomas) v4 Changes: - Fix incorrect signoff marrvell -> marvell. v3 Changes: - Squash meson build support into config support for thunderx2/octeontx2. v2 Changes: - Add meson build support. --- mk/rte.helper.mk | 10 ++++++++++ mk/target/generic/rte.vars.mk | 22 +++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) create mode 100644 mk/rte.helper.mk diff --git a/mk/rte.helper.mk b/mk/rte.helper.mk new file mode 100644 index 000000000..6e7fd03d7 --- /dev/null +++ b/mk/rte.helper.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd + +# rte_cc_has_argument +# Usage: MACHINE_CFLAGS += $(call rte_cc_has_argument, -mno-avx512f) +# Return the argument if the argument is supported by the compiler. +# +define rte_cc_has_argument + $(shell $(CC) -E $(1) -xc /dev/null 1>/dev/null 2>/dev/null && echo $(1)) +endef diff --git a/mk/target/generic/rte.vars.mk b/mk/target/generic/rte.vars.mk index dd149acc9..25a578ad7 100644 --- a/mk/target/generic/rte.vars.mk +++ b/mk/target/generic/rte.vars.mk @@ -7,6 +7,17 @@ # executive environment. # +# +# toolchain: +# +# - define CC, LD, AR, AS, ... +# - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value) +# - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value) +# - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value) +# - may override any previously defined variable +# +include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk + # # machine: # @@ -45,17 +56,6 @@ endif # include $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk -# -# toolchain: -# -# - define CC, LD, AR, AS, ... -# - define TOOLCHAIN_CFLAGS variable (overridden by cmdline value) -# - define TOOLCHAIN_LDFLAGS variable (overridden by cmdline value) -# - define TOOLCHAIN_ASFLAGS variable (overridden by cmdline value) -# - may override any previously defined variable -# -include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk - # # exec-env: # From patchwork Sat Apr 13 20:19:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 52752 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 719211B134; Sat, 13 Apr 2019 22:20:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 5BB4B1B0FF for ; Sat, 13 Apr 2019 22:19:58 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3DKJvaq019196; Sat, 13 Apr 2019 13:19:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=faP7VBLbze4zc1OBJJObPh4Wd6nVe8Humq3vMGnCpRQ=; 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Sat, 13 Apr 2019 13:19:54 -0700 (PDT) From: To: , Thomas Monjalon CC: , Pavan Nikhilesh , "Jerin Jacob" Date: Sun, 14 Apr 2019 01:49:44 +0530 Message-ID: <20190413201946.36566-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413201946.36566-1-jerinj@marvell.com> References: <20190413190121.15416-1-jerinj@marvell.com> <20190413201946.36566-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_06:, , signatures=0 Subject: [dpdk-dev] [PATCH v10 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 67 +++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 170a4981a..104acd6d4 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine) arm_force_native_march = false -machine_args_generic = [ - ['default', ['-march=armv8-a+crc+crypto']], - ['native', ['-march=native']], - ['0xd03', ['-mcpu=cortex-a53']], - ['0xd04', ['-mcpu=cortex-a35']], - ['0xd05', ['-mcpu=cortex-a55']], - ['0xd07', ['-mcpu=cortex-a57']], - ['0xd08', ['-mcpu=cortex-a72']], - ['0xd09', ['-mcpu=cortex-a73']], - ['0xd0a', ['-mcpu=cortex-a75']], - ['0xd0b', ['-mcpu=cortex-a76']], -] -machine_args_cavium = [ - ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], - ['native', ['-march=native']], - ['0xa1', ['-mcpu=thunderxt88']], - ['0xa2', ['-mcpu=thunderxt81']], - ['0xa3', ['-mcpu=thunderxt83']]] - flags_common_default = [ # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file @@ -52,12 +33,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +50,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -145,20 +145,19 @@ else dpdk_conf.set(flag[0], flag[1]) endif endforeach - # Primary part number based mcpu flags are supported - # for gcc versions > 7 - if cc.version().version_compare( - '<7.0') or cmd_output.length() == 0 - if not meson.is_cross_build() and arm_force_native_march == true - impl_pn = 'native' - else - impl_pn = 'default' - endif - endif + foreach marg: machine[2] if marg[0] == impl_pn - foreach f: marg[1] - machine_args += f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach From patchwork Sat Apr 13 20:19:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 52753 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B0EC71B140; Sat, 13 Apr 2019 22:20:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A5E551B13B for ; Sat, 13 Apr 2019 22:20:05 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3DKJvAG019221; Sat, 13 Apr 2019 13:20:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=r6JPkKtoSX/074dRAQb8GSyfLgcO6soDJNuab/uWlmE=; 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Sat, 13 Apr 2019 13:19:59 -0700 (PDT) From: To: , Thomas Monjalon CC: , Jerin Jacob , Pavan Nikhilesh , Gavin Hu Date: Sun, 14 Apr 2019 01:49:45 +0530 Message-ID: <20190413201946.36566-3-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413201946.36566-1-jerinj@marvell.com> References: <20190413190121.15416-1-jerinj@marvell.com> <20190413201946.36566-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_06:, , signatures=0 Subject: [dpdk-dev] [PATCH v10 3/4] config: add thunderx2 machine config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Optimized configuration for Marvell thunderx2 SoC. Updated meson build to support Marvell thunderx2 SoC. Added meson cross compile target. Product details are here: https://www.marvell.com/server-processors/thunderx2-arm-processors/ Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh Reviewed-by: Gavin Hu --- config/arm/arm64_thunderx2_linux_gcc | 16 +++++++++ config/arm/meson.build | 9 ++++- config/defconfig_arm64-thunderx2-linux-gcc | 1 + config/defconfig_arm64-thunderx2-linuxapp-gcc | 11 ++++++ mk/machine/thunderx2/rte.vars.mk | 34 +++++++++++++++++++ 5 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 config/arm/arm64_thunderx2_linux_gcc create mode 120000 config/defconfig_arm64-thunderx2-linux-gcc create mode 100644 config/defconfig_arm64-thunderx2-linuxapp-gcc create mode 100644 mk/machine/thunderx2/rte.vars.mk diff --git a/config/arm/arm64_thunderx2_linux_gcc b/config/arm/arm64_thunderx2_linux_gcc new file mode 100644 index 000000000..0dc275644 --- /dev/null +++ b/config/arm/arm64_thunderx2_linux_gcc @@ -0,0 +1,16 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x43' +implementor_pn = '0xaf' diff --git a/config/arm/meson.build b/config/arm/meson.build index 104acd6d4..ccf806e73 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -54,6 +54,12 @@ flags_default_extra = [] flags_thunderx_extra = [ ['RTE_MACHINE', '"thunderx"'], ['RTE_USE_C11_MEM_MODEL', false]] +flags_thunderx2_extra = [ + ['RTE_MACHINE', '"thunderx2"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_NUMA_NODES', 2], + ['RTE_MAX_LCORE', 256], + ['RTE_USE_C11_MEM_MODEL', true]] machine_args_generic = [ ['default', ['-march=armv8-a+crc+crypto']], @@ -70,7 +76,8 @@ machine_args_cavium = [ ['native', ['-march=native']], ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], - ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra], + ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] diff --git a/config/defconfig_arm64-thunderx2-linux-gcc b/config/defconfig_arm64-thunderx2-linux-gcc new file mode 120000 index 000000000..b40a760b1 --- /dev/null +++ b/config/defconfig_arm64-thunderx2-linux-gcc @@ -0,0 +1 @@ +defconfig_arm64-thunderx2-linuxapp-gcc \ No newline at end of file diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc b/config/defconfig_arm64-thunderx2-linuxapp-gcc new file mode 100644 index 000000000..cc5c64ba0 --- /dev/null +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +#include "defconfig_arm64-armv8a-linux-gcc" + +CONFIG_RTE_MACHINE="thunderx2" + +CONFIG_RTE_CACHE_LINE_SIZE=64 +CONFIG_RTE_MAX_NUMA_NODES=2 +CONFIG_RTE_MAX_LCORE=256 diff --git a/mk/machine/thunderx2/rte.vars.mk b/mk/machine/thunderx2/rte.vars.mk new file mode 100644 index 000000000..b80dc8680 --- /dev/null +++ b/mk/machine/thunderx2/rte.vars.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +# +# machine: +# +# - can define ARCH variable (overridden by cmdline value) +# - can define CROSS variable (overridden by cmdline value) +# - define MACHINE_CFLAGS variable (overridden by cmdline value) +# - define MACHINE_LDFLAGS variable (overridden by cmdline value) +# - define MACHINE_ASFLAGS variable (overridden by cmdline value) +# - can define CPU_CFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_LDFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_ASFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - may override any previously defined variable +# + +# ARCH = +# CROSS = +# MACHINE_CFLAGS = +# MACHINE_LDFLAGS = +# MACHINE_ASFLAGS = +# CPU_CFLAGS = +# CPU_LDFLAGS = +# CPU_ASFLAGS = + +include $(RTE_SDK)/mk/rte.helper.mk + +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=armv8.1-a+crc+crypto) +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=thunderx2t99) From patchwork Sat Apr 13 20:19:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 52754 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 95F3E1B14D; Sat, 13 Apr 2019 22:20:12 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 4B3051B144 for ; Sat, 13 Apr 2019 22:20:09 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3DKJvTH019205; Sat, 13 Apr 2019 13:20:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=cNUd8YujhGm12p8bCIHw8PnMQYu7nXUgjqWdNOLKjH4=; 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Sat, 13 Apr 2019 13:20:03 -0700 (PDT) From: To: , Thomas Monjalon CC: , Jerin Jacob , Pavan Nikhilesh , Gavin Hu Date: Sun, 14 Apr 2019 01:49:46 +0530 Message-ID: <20190413201946.36566-4-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413201946.36566-1-jerinj@marvell.com> References: <20190413190121.15416-1-jerinj@marvell.com> <20190413201946.36566-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_06:, , signatures=0 Subject: [dpdk-dev] [PATCH v10 4/4] config: add octeontx2 machine config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Optimized configuration for Marvell octeontx2 SoC. Updated meson build to support Marvell octeontx2 SoC. Added meson cross build target for octeontx2. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh Reviewed-by: Gavin Hu --- config/arm/arm64_octeontx2_linux_gcc | 16 +++++++++ config/arm/meson.build | 9 ++++- config/defconfig_arm64-octeontx2-linux-gcc | 1 + config/defconfig_arm64-octeontx2-linuxapp-gcc | 18 ++++++++++ mk/machine/octeontx2/rte.vars.mk | 34 +++++++++++++++++++ 5 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 config/arm/arm64_octeontx2_linux_gcc create mode 120000 config/defconfig_arm64-octeontx2-linux-gcc create mode 100644 config/defconfig_arm64-octeontx2-linuxapp-gcc create mode 100644 mk/machine/octeontx2/rte.vars.mk diff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_octeontx2_linux_gcc new file mode 100644 index 000000000..e2c0b8f72 --- /dev/null +++ b/config/arm/arm64_octeontx2_linux_gcc @@ -0,0 +1,16 @@ +[binaries] +c = 'aarch64-linux-gnu-gcc' +cpp = 'aarch64-linux-gnu-cpp' +ar = 'aarch64-linux-gnu-gcc-ar' +strip = 'aarch64-linux-gnu-strip' +pcap-config = '' + +[host_machine] +system = 'linux' +cpu_family = 'aarch64' +cpu = 'armv8-a' +endian = 'little' + +[properties] +implementor_id = '0x43' +implementor_pn = '0xb2' diff --git a/config/arm/meson.build b/config/arm/meson.build index ccf806e73..22a062bad 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -60,6 +60,12 @@ flags_thunderx2_extra = [ ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 256], ['RTE_USE_C11_MEM_MODEL', true]] +flags_octeontx2_extra = [ + ['RTE_MACHINE', '"octeontx2"'], + ['RTE_MAX_NUMA_NODES', 1], + ['RTE_MAX_LCORE', 24], + ['RTE_EAL_IGB_UIO', false], + ['RTE_USE_C11_MEM_MODEL', true]] machine_args_generic = [ ['default', ['-march=armv8-a+crc+crypto']], @@ -77,7 +83,8 @@ machine_args_cavium = [ ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra], - ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra]] + ['0xaf', ['-mcpu=thunderx2t99'], flags_thunderx2_extra], + ['0xb2', ['-mcpu=octeontx2'], flags_octeontx2_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] diff --git a/config/defconfig_arm64-octeontx2-linux-gcc b/config/defconfig_arm64-octeontx2-linux-gcc new file mode 120000 index 000000000..e25150531 --- /dev/null +++ b/config/defconfig_arm64-octeontx2-linux-gcc @@ -0,0 +1 @@ +defconfig_arm64-octeontx2-linuxapp-gcc \ No newline at end of file diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc new file mode 100644 index 000000000..9eae84538 --- /dev/null +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +#include "defconfig_arm64-armv8a-linux-gcc" + +CONFIG_RTE_MACHINE="octeontx2" + +CONFIG_RTE_CACHE_LINE_SIZE=128 +CONFIG_RTE_MAX_NUMA_NODES=1 +CONFIG_RTE_MAX_LCORE=24 + +# Doesn't support NUMA +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_LIBRTE_VHOST_NUMA=n + +# Recommend to use VFIO as co-processors needs SMMU/IOMMU +CONFIG_RTE_EAL_IGB_UIO=n diff --git a/mk/machine/octeontx2/rte.vars.mk b/mk/machine/octeontx2/rte.vars.mk new file mode 100644 index 000000000..cbec7f14d --- /dev/null +++ b/mk/machine/octeontx2/rte.vars.mk @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Marvell International Ltd +# + +# +# machine: +# +# - can define ARCH variable (overridden by cmdline value) +# - can define CROSS variable (overridden by cmdline value) +# - define MACHINE_CFLAGS variable (overridden by cmdline value) +# - define MACHINE_LDFLAGS variable (overridden by cmdline value) +# - define MACHINE_ASFLAGS variable (overridden by cmdline value) +# - can define CPU_CFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_LDFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - can define CPU_ASFLAGS variable (overridden by cmdline value) that +# overrides the one defined in arch. +# - may override any previously defined variable +# + +# ARCH = +# CROSS = +# MACHINE_CFLAGS = +# MACHINE_LDFLAGS = +# MACHINE_ASFLAGS = +# CPU_CFLAGS = +# CPU_LDFLAGS = +# CPU_ASFLAGS = + +include $(RTE_SDK)/mk/rte.helper.mk + +MACHINE_CFLAGS += $(call rte_cc_has_argument, -march=-mcpu=armv8.2-a+crc+crypto+lse) +MACHINE_CFLAGS += $(call rte_cc_has_argument, -mcpu=octeontx2)