From patchwork Fri Jun 21 08:40:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 55146 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 789D81D4B7; Fri, 21 Jun 2019 02:55:06 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 4B6391D4B6; Fri, 21 Jun 2019 02:55:05 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jun 2019 17:55:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,398,1557212400"; d="scan'208";a="358717131" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.146]) by fmsmga005.fm.intel.com with ESMTP; 20 Jun 2019 17:55:02 -0700 From: Tianfei zhang To: dev@dpdk.org, ferruh.yigit@intel.com Cc: rosen.xu@intel.com, stable@dpdk.org, Tianfei zhang Date: Fri, 21 Jun 2019 16:40:13 +0800 Message-Id: <20190621084017.6763-1-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH v4 1/5] raw/ifpga_rawdev: fix use of untrusted scalar value X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add checking the buffer size and use const char * for buffer declaration. Coverity issue: 279449 Fixes: ef1e8ede ("raw/ifpga: add Intel FPGA bus rawdev driver") Cc: stable@dpdk.org Signed-off-by: Tianfei zhang Acked-by: Rosen Xu Acked-by: Rosen Xu --- drivers/raw/ifpga_rawdev/base/ifpga_api.c | 4 +-- drivers/raw/ifpga_rawdev/base/ifpga_api.h | 2 +- .../raw/ifpga_rawdev/base/ifpga_feature_dev.h | 2 +- drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c | 27 +++++++++++-------- drivers/raw/ifpga_rawdev/base/opae_hw_api.c | 4 +-- drivers/raw/ifpga_rawdev/base/opae_hw_api.h | 4 +-- drivers/raw/ifpga_rawdev/ifpga_rawdev.c | 7 ++++- 7 files changed, 30 insertions(+), 20 deletions(-) diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.c b/drivers/raw/ifpga_rawdev/base/ifpga_api.c index 3ddbcdc2a..53d101daf 100644 --- a/drivers/raw/ifpga_rawdev/base/ifpga_api.c +++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.c @@ -182,7 +182,7 @@ struct opae_bridge_ops ifpga_br_ops = { }; /* Manager APIs */ -static int ifpga_mgr_flash(struct opae_manager *mgr, int id, void *buf, +static int ifpga_mgr_flash(struct opae_manager *mgr, int id, const char *buf, u32 size, u64 *status) { struct ifpga_fme_hw *fme = mgr->data; @@ -324,7 +324,7 @@ struct opae_adapter_ops ifpga_adapter_ops = { * - 0: Success, partial reconfiguration finished. * - <0: Error code returned in partial reconfiguration. **/ -int ifpga_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, +int ifpga_pr(struct ifpga_hw *hw, u32 port_id, const char *buffer, u32 size, u64 *status) { if (!is_valid_port_id(hw, port_id)) diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.h b/drivers/raw/ifpga_rawdev/base/ifpga_api.h index 4a247698c..051ab8276 100644 --- a/drivers/raw/ifpga_rawdev/base/ifpga_api.h +++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.h @@ -23,7 +23,7 @@ int ifpga_set_irq(struct ifpga_hw *hw, u32 fiu_id, u32 port_id, u32 feature_id, void *irq_set); /* FME APIs */ -int ifpga_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, +int ifpga_pr(struct ifpga_hw *hw, u32 port_id, const char *buffer, u32 size, u64 *status); #endif /* _IFPGA_API_H_ */ diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h index bb9fcc289..e243d4273 100644 --- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h +++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h @@ -149,7 +149,7 @@ static inline int fpga_port_reset(struct ifpga_port_hw *port) return ret; } -int do_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, +int do_pr(struct ifpga_hw *hw, u32 port_id, const char *buffer, u32 size, u64 *status); int fme_get_prop(struct ifpga_fme_hw *fme, struct feature_prop *prop); diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c b/drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c index efa72660f..9997942d2 100644 --- a/drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c +++ b/drivers/raw/ifpga_rawdev/base/ifpga_fme_pr.c @@ -223,8 +223,8 @@ static int fpga_pr_buf_load(struct ifpga_fme_hw *fme_dev, return 0; } -static int fme_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, - u64 *status) +static int fme_pr(struct ifpga_hw *hw, u32 port_id, const char *buffer, + u32 size, u64 *status) { struct feature_fme_header *fme_hdr; struct feature_fme_capability fme_capability; @@ -269,7 +269,7 @@ static int fme_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, /* Disable Port before PR */ fpga_port_disable(port); - ret = fpga_pr_buf_load(fme, &info, (void *)buffer, size); + ret = fpga_pr_buf_load(fme, &info, buffer, size); *status = info.pr_err; @@ -280,27 +280,32 @@ static int fme_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, return ret; } -int do_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size, u64 *status) +int do_pr(struct ifpga_hw *hw, u32 port_id, const char *buffer, + u32 size, u64 *status) { - struct bts_header *bts_hdr; - void *buf; + const struct bts_header *bts_hdr; + const char *buf; struct ifpga_port_hw *port; int ret; + u32 header_size; if (!buffer || size == 0) { dev_err(hw, "invalid parameter\n"); return -EINVAL; } - bts_hdr = (struct bts_header *)buffer; + bts_hdr = (const struct bts_header *)buffer; if (is_valid_bts(bts_hdr)) { dev_info(hw, "this is a valid bitsteam..\n"); - size -= (sizeof(struct bts_header) + - bts_hdr->metadata_len); - buf = (u8 *)buffer + sizeof(struct bts_header) + - bts_hdr->metadata_len; + header_size = sizeof(struct bts_header) + + bts_hdr->metadata_len; + if (size < header_size) + return -EINVAL; + size -= header_size; + buf = buffer + header_size; } else { + dev_err(hw, "this is an invalid bitstream..\n"); return -EINVAL; } diff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c index 0e117d05e..8964e7984 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c +++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c @@ -244,8 +244,8 @@ opae_manager_alloc(const char *name, struct opae_manager_ops *ops, * * Return: 0 on success, otherwise error code. */ -int opae_manager_flash(struct opae_manager *mgr, int id, void *buf, u32 size, - u64 *status) +int opae_manager_flash(struct opae_manager *mgr, int id, const char *buf, + u32 size, u64 *status) { if (!mgr) return -EINVAL; diff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h index 383e751cb..63405a471 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h +++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h @@ -44,7 +44,7 @@ struct opae_manager { /* FIXME: add more management ops, e.g power/thermal and etc */ struct opae_manager_ops { - int (*flash)(struct opae_manager *mgr, int id, void *buffer, + int (*flash)(struct opae_manager *mgr, int id, const char *buffer, u32 size, u64 *status); int (*get_eth_group_region_info)(struct opae_manager *mgr, struct opae_eth_group_region_info *info); @@ -74,7 +74,7 @@ struct opae_manager * opae_manager_alloc(const char *name, struct opae_manager_ops *ops, struct opae_manager_networking_ops *network_ops, void *data); #define opae_manager_free(mgr) opae_free(mgr) -int opae_manager_flash(struct opae_manager *mgr, int acc_id, void *buf, +int opae_manager_flash(struct opae_manager *mgr, int acc_id, const char *buf, u32 size, u64 *status); int opae_manager_get_eth_group_region_info(struct opae_manager *mgr, u8 group_id, struct opae_eth_group_region_info *info); diff --git a/drivers/raw/ifpga_rawdev/ifpga_rawdev.c b/drivers/raw/ifpga_rawdev/ifpga_rawdev.c index 41be1a205..01aa917de 100644 --- a/drivers/raw/ifpga_rawdev/ifpga_rawdev.c +++ b/drivers/raw/ifpga_rawdev/ifpga_rawdev.c @@ -225,7 +225,7 @@ ifpga_rawdev_reset(struct rte_rawdev *dev) } static int -fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, u64 *buffer, u32 size, +fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size, u64 *status) { @@ -296,6 +296,11 @@ rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id, goto close_fd; } buffer_size = file_stat.st_size; + if (buffer_size <= 0) { + ret = -EINVAL; + goto close_fd; + } + IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size); buffer = rte_malloc(NULL, buffer_size, 0); if (!buffer) { From patchwork Fri Jun 21 08:40:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 55147 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EE5BC1D4D6; Fri, 21 Jun 2019 02:55:25 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 5CBEA1D4C5; Fri, 21 Jun 2019 02:55:24 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jun 2019 17:55:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,398,1557212400"; d="scan'208";a="358717176" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.146]) by fmsmga005.fm.intel.com with ESMTP; 20 Jun 2019 17:55:22 -0700 From: Tianfei zhang To: dev@dpdk.org, ferruh.yigit@intel.com Cc: rosen.xu@intel.com, stable@dpdk.org, Tianfei zhang Date: Fri, 21 Jun 2019 16:40:14 +0800 Message-Id: <20190621084017.6763-2-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190621084017.6763-1-tianfei.zhang@intel.com> References: <20190621084017.6763-1-tianfei.zhang@intel.com> Subject: [dpdk-dev] [PATCH v4 2/5] raw/ifpga_rawdev: fix logically dead code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" add temporary variable in max10_reg_write(). Coverity issue: 337927 Fixes: 96ebfcf ("raw/ifpga/base: add SPI and MAX10 device driver") Cc: stable@dpdk.org Signed-off-by: Tianfei zhang Acked-by: Rosen Xu Acked-by: Rosen Xu --- drivers/raw/ifpga_rawdev/base/opae_intel_max10.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c index f354ee4b6..3ff6575d7 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c +++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c @@ -17,11 +17,13 @@ int max10_reg_read(unsigned int reg, unsigned int *val) int max10_reg_write(unsigned int reg, unsigned int val) { + unsigned int tmp = val; + if (!g_max10) return -ENODEV; return spi_transaction_write(g_max10->spi_tran_dev, - reg, 4, (unsigned char *)&val); + reg, 4, (unsigned char *)&tmp); } struct intel_max10_device * @@ -57,7 +59,7 @@ intel_max10_device_probe(struct altera_spi_device *spi, /* set PKVL Polling manually in BBS */ ret = max10_reg_write(PKVL_POLLING_CTRL, 0x3); - if (ret) { + if (ret != 0) { dev_err(dev, "%s set PKVL polling fail\n", __func__); goto spi_tran_fail; } From patchwork Fri Jun 21 08:40:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 55148 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B02D61D4E0; Fri, 21 Jun 2019 02:55:28 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 163CD1D4D7; Fri, 21 Jun 2019 02:55:25 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jun 2019 17:55:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,398,1557212400"; d="scan'208";a="358717179" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.146]) by fmsmga005.fm.intel.com with ESMTP; 20 Jun 2019 17:55:24 -0700 From: Tianfei zhang To: dev@dpdk.org, ferruh.yigit@intel.com Cc: rosen.xu@intel.com, stable@dpdk.org, Tianfei zhang Date: Fri, 21 Jun 2019 16:40:15 +0800 Message-Id: <20190621084017.6763-3-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190621084017.6763-1-tianfei.zhang@intel.com> References: <20190621084017.6763-1-tianfei.zhang@intel.com> Subject: [dpdk-dev] [PATCH v4 3/5] raw/ifpga_rawdev/base: fix bit fields definition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix CTRL_DEV_SELECT bit fields definition about eth_group devices. Fixes: 8a256bef32 ("raw/ifpga/base: add eth group driver") Cc: stable@dpdk.org Signed-off-by: Tianfei zhang Acked-by: Rosen Xu Acked-by: Rosen Xu --- drivers/raw/ifpga_rawdev/base/opae_eth_group.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h index 8d695cc8e..a66d77e27 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h +++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h @@ -31,7 +31,7 @@ #define CMD_NOP 0ULL #define CMD_RD 1ULL #define CMD_WR 2ULL -#define CTRL_DEV_SELECT GENMASK_ULL(52, 49) +#define CTRL_DEV_SELECT GENMASK_ULL(53, 49) #define CTRL_DS_SHIFT 49 #define CTRL_FEAT_SELECT BIT_ULL(48) #define SELECT_IP 0 From patchwork Fri Jun 21 08:40:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 55149 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3186B1D4E7; Fri, 21 Jun 2019 02:55:31 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 7EF4F1D4DD; Fri, 21 Jun 2019 02:55:28 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jun 2019 17:55:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,398,1557212400"; d="scan'208";a="358717186" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.146]) by fmsmga005.fm.intel.com with ESMTP; 20 Jun 2019 17:55:27 -0700 From: Tianfei zhang To: dev@dpdk.org, ferruh.yigit@intel.com Cc: rosen.xu@intel.com, stable@dpdk.org, Tianfei zhang Date: Fri, 21 Jun 2019 16:40:16 +0800 Message-Id: <20190621084017.6763-4-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190621084017.6763-1-tianfei.zhang@intel.com> References: <20190621084017.6763-1-tianfei.zhang@intel.com> Subject: [dpdk-dev] [PATCH v4 4/5] raw/ifpga_rawdev/base: fix miss physical address X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix miss phy_addr on ifpga_acc_get_region_info() function. Fixes: 56bb54ea1bd ("raw/ifpga/base: add Intel FPGA OPAE share code") Cc: stable@dpdk.org Signed-off-by: Tianfei zhang Acked-by: Rosen Xu Acked-by: Rosen Xu --- drivers/raw/ifpga_rawdev/base/ifpga_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.c b/drivers/raw/ifpga_rawdev/base/ifpga_api.c index 53d101daf..7ae626d64 100644 --- a/drivers/raw/ifpga_rawdev/base/ifpga_api.c +++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.c @@ -76,6 +76,7 @@ static int ifpga_acc_get_region_info(struct opae_accelerator *acc, info->flags = ACC_REGION_READ | ACC_REGION_WRITE | ACC_REGION_MMIO; info->len = afu_info->region[info->index].len; info->addr = afu_info->region[info->index].addr; + info->phys_addr = afu_info->region[info->index].phys_addr; return 0; } From patchwork Fri Jun 21 08:40:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 55150 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 92A4A1D4F9; Fri, 21 Jun 2019 02:55:34 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id D571B1D4D4; Fri, 21 Jun 2019 02:55:31 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Jun 2019 17:55:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,398,1557212400"; d="scan'208";a="358717195" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.146]) by fmsmga005.fm.intel.com with ESMTP; 20 Jun 2019 17:55:30 -0700 From: Tianfei zhang To: dev@dpdk.org, ferruh.yigit@intel.com Cc: rosen.xu@intel.com, stable@dpdk.org, Tianfei zhang Date: Fri, 21 Jun 2019 16:40:17 +0800 Message-Id: <20190621084017.6763-5-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190621084017.6763-1-tianfei.zhang@intel.com> References: <20190621084017.6763-1-tianfei.zhang@intel.com> Subject: [dpdk-dev] [PATCH v4 5/5] raw/ifpga_rawdev/base: fix retimer link status issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix the readout retimer link status incorrectly when we remove the linux intel-fpga-driver and run the DPDK application. The linux driver will stop the retimer when remove the kernel modules. Fixes: 8a256bef ("raw/ifpga/base: add eth group driver") Cc: stable@dpdk.org Reported-by: Sampath Amrutha Signed-off-by: Tianfei zhang Acked-by: Rosen Xu --- .../raw/ifpga_rawdev/base/opae_eth_group.c | 172 ++++++++++++++++++ .../raw/ifpga_rawdev/base/opae_eth_group.h | 6 + .../raw/ifpga_rawdev/base/opae_intel_max10.c | 7 - 3 files changed, 178 insertions(+), 7 deletions(-) diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.c b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c index 8db6693b1..d189dd578 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_eth_group.c +++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c @@ -113,6 +113,171 @@ int eth_group_read_reg(struct eth_group_device *dev, return 0; } +static int eth_group_reset_mac(struct eth_group_device *dev, u8 index, + bool enable) +{ + u32 val; + int ret; + + /* + * only support 25G & 40G mac reset for now. It uses internal reset. + * as PHY and MAC are integrated together, below action will trigger + * PHY reset too. + */ + if (dev->speed != 25 && dev->speed != 40) + return 0; + + ret = eth_group_read_reg(dev, ETH_GROUP_MAC, index, MAC_CONFIG, + &val); + if (ret) { + dev_err(dev, "fail to read PHY_CONFIG: %d\n", ret); + return ret; + } + + /* skip if mac is in expected state already */ + if ((((val & MAC_RESET_MASK) == MAC_RESET_MASK) && enable) || + (((val & MAC_RESET_MASK) == 0) && !enable)) + return 0; + + if (enable) + val |= MAC_RESET_MASK; + else + val &= ~MAC_RESET_MASK; + + ret = eth_group_write_reg(dev, ETH_GROUP_MAC, index, MAC_CONFIG, + val); + if (ret) + dev_err(dev, "fail to write PHY_CONFIG: %d\n", ret); + + return ret; +} + +static void eth_group_mac_uinit(struct eth_group_device *dev) +{ + u8 i; + + for (i = 0; i < dev->mac_num; i++) { + if (eth_group_reset_mac(dev, i, true)) + dev_err(dev, "fail to disable mac %d\n", i); + } +} + +static int eth_group_mac_init(struct eth_group_device *dev) +{ + int ret; + u8 i; + + for (i = 0; i < dev->mac_num; i++) { + ret = eth_group_reset_mac(dev, i, false); + if (ret) { + dev_err(dev, "fail to enable mac %d\n", i); + goto exit; + } + } + + return 0; + +exit: + while (i--) + eth_group_reset_mac(dev, i, true); + + return ret; +} + +static int eth_group_reset_phy(struct eth_group_device *dev, u8 index, + bool enable) +{ + u32 val; + int ret; + + /* only support 10G PHY reset for now. It uses external reset. */ + if (dev->speed != 10) + return 0; + + ret = eth_group_read_reg(dev, ETH_GROUP_PHY, index, + ADD_PHY_CTRL, &val); + if (ret) { + dev_err(dev, "fail to read ADD_PHY_CTRL reg: %d\n", ret); + return ret; + } + + /* return if PHY is already in expected state */ + if ((val & PHY_RESET && enable) || (!(val & PHY_RESET) && !enable)) + return 0; + + if (enable) + val |= PHY_RESET; + else + val &= ~PHY_RESET; + + ret = eth_group_write_reg(dev, ETH_GROUP_PHY, index, + ADD_PHY_CTRL, val); + if (ret) + dev_err(dev, "fail to write ADD_PHY_CTRL reg: %d\n", ret); + + return ret; +} + +static int eth_group_phy_init(struct eth_group_device *dev) +{ + int ret; + int i; + + for (i = 0; i < dev->phy_num; i++) { + ret = eth_group_reset_phy(dev, i, false); + if (ret) { + dev_err(dev, "fail to enable phy %d\n", i); + goto exit; + } + } + + return 0; +exit: + while (i--) + eth_group_reset_phy(dev, i, true); + + return ret; +} + +static void eth_group_phy_uinit(struct eth_group_device *dev) +{ + int i; + + for (i = 0; i < dev->phy_num; i++) { + if (eth_group_reset_phy(dev, i, true)) + dev_err(dev, "fail to disable phy %d\n", i); + } +} + +static int eth_group_hw_init(struct eth_group_device *dev) +{ + int ret; + + ret = eth_group_phy_init(dev); + if (ret) { + dev_err(dev, "fail to init eth group phys\n"); + return ret; + } + + ret = eth_group_mac_init(dev); + if (ret) { + dev_err(priv->dev, "fail to init eth group macs\n"); + goto phy_exit; + } + + return 0; + +phy_exit: + eth_group_phy_uinit(dev); + return ret; +} + +static void eth_group_hw_uinit(struct eth_group_device *dev) +{ + eth_group_mac_uinit(dev); + eth_group_phy_uinit(dev); +} + struct eth_group_device *eth_group_probe(void *base) { struct eth_group_device *dev; @@ -130,6 +295,11 @@ struct eth_group_device *eth_group_probe(void *base) dev->status = ETH_GROUP_DEV_ATTACHED; + if (eth_group_hw_init(dev)) { + dev_err(dev, "eth group hw init fail\n"); + return NULL; + } + dev_info(dev, "eth group device %d probe done: phy_num=mac_num:%d, speed=%d\n", dev->group_id, dev->phy_num, dev->speed); @@ -138,6 +308,8 @@ struct eth_group_device *eth_group_probe(void *base) void eth_group_release(struct eth_group_device *dev) { + eth_group_hw_uinit(dev); + if (dev) { dev->status = ETH_GROUP_DEV_NOUSED; opae_free(dev); diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h index a66d77e27..4868bd0e1 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h +++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h @@ -44,6 +44,12 @@ #define STAT_DATA_VAL BIT_ULL(32) #define STAT_RD_DATA GENMASK_ULL(31, 0) +/* Additional Feature Register */ +#define ADD_PHY_CTRL 0x0 +#define PHY_RESET BIT(0) +#define MAC_CONFIG 0x310 +#define MAC_RESET_MASK GENMASK(2, 0) + struct opae_eth_group_info { u8 group_id; u8 speed; diff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c index 3ff6575d7..9ed10e282 100644 --- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c +++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.c @@ -57,13 +57,6 @@ intel_max10_device_probe(struct altera_spi_device *spi, } dev_info(dev, "FPGA loaded from %s Image\n", val ? "User" : "Factory"); - /* set PKVL Polling manually in BBS */ - ret = max10_reg_write(PKVL_POLLING_CTRL, 0x3); - if (ret != 0) { - dev_err(dev, "%s set PKVL polling fail\n", __func__); - goto spi_tran_fail; - } - return dev; spi_tran_fail: