From patchwork Wed Aug 7 15:09:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57538 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D3F3E2BF1; Wed, 7 Aug 2019 17:09:44 +0200 (CEST) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by dpdk.org (Postfix) with ESMTP id 5D44F2BAC for ; Wed, 7 Aug 2019 17:09:39 +0200 (CEST) Received: by mail-wr1-f66.google.com with SMTP id t16so1629108wra.6 for ; Wed, 07 Aug 2019 08:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=8Zrz47bKGdm5AKYH7KFpcAgs3fa6BrxTmQEchj0jXOQ=; b=WmAm4dIjyCt8LdfYacerQVXEPZv3248VM5axiVIVWZzODPdHT9OfRibYuLA6njs8pA XlIq2LBWdLetNhtFlAwlzDGao5Q8gX6UNx48+TyFUXyAV8B2ErBAGNCwyWxCSSM+S7F7 a7bACVayL0+j4Y5VEd/PA+Q+QFl76+A3vjA0eEaPzv88msVnzauJmzTdHTd1YvHVtq0O aAK4H864z3jdjwvgna6gUvnvtImFkjaKklbRrHjQO7ZXbX1sJCDnjlSLsqbhMSZnEuuu XkWvp6XTlDoTaNC8l7k7vcSog+wsSRviABQ0tFwlvRGm3gE0aeXo+KE47c61P4mVLfMG qoXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=8Zrz47bKGdm5AKYH7KFpcAgs3fa6BrxTmQEchj0jXOQ=; b=abPn8zI4NB0a/BVB1JUcXoGY0aOz5OIhETanZrx0bg1yROTOGIj+O9JP0JemPLOxfw 5S5U6CRlV/uNrM/SRlCKN4syd0gN4w3Gf+NvUp8jNZ+DZZ/LK8YK4svzrwYvZRBYN/uW 7zIFtebdqOepfOCSFcHFKfu6Sq6rTEA1Wh+Ie/0YsVZlOfLEeNxn9++BO3X0Ip+DbTu5 VQ3XKGhzuA5tynWLIeMD7gm628dkP1WQ+Yu2fBqTDJpgwgZ/gQgy4ARQMuv9v++LwO25 2TFGoBrhOdJYxxGpMoSh4Fs+S/XssdcszgMItxo6JjCovABuiXgYa+Nw6k8nlSOM8kG9 P3bw== X-Gm-Message-State: APjAAAXSdSLroFxF+wN9p4kRPr/Kbe4iZcYVt0lDe7OEINhQ9QKN/4O/ nZ3/+vcP4IEuxEZ55CGuh9u86VQRug== X-Google-Smtp-Source: APXvYqwk/kJGwmlYEXd8Vbt38NXrEC7x2QRwbN9b4849aUryTD4hG/vUqVYzoAP2opCjYvY2cujHLQ== X-Received: by 2002:adf:b1d0:: with SMTP id r16mr11747930wra.332.1565190578739; Wed, 07 Aug 2019 08:09:38 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:37 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Guo Fengtian , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:10 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 01/12] net/ixgbevf: fix stats update after a PF reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Guo Fengtian When PF is set down, in VF, the value of stats register is zero. So only increase stats when it's non zero. Fixes: af75078fece3 ('first public release') Cc: stable@dpdk.org Signed-off-by: Guo Fengtian --- drivers/net/ixgbe/ixgbe_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 03fc1f71799c..57f5bfa219c1 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -385,7 +385,8 @@ static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); #define UPDATE_VF_STAT(reg, last, cur) \ { \ uint32_t latest = IXGBE_READ_REG(hw, reg); \ - cur += (latest - last) & UINT_MAX; \ + if (latest) \ + cur += (latest - last) & UINT_MAX; \ last = latest; \ } @@ -394,7 +395,8 @@ static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ u64 new_msb = IXGBE_READ_REG(hw, msb); \ u64 latest = ((new_msb << 32) | new_lsb); \ - cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ + if (latest) \ + cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL;\ last = latest; \ } From patchwork Wed Aug 7 15:09:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57539 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 032302C18; Wed, 7 Aug 2019 17:09:49 +0200 (CEST) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by dpdk.org (Postfix) with ESMTP id 3F4E72BD3 for ; Wed, 7 Aug 2019 17:09:40 +0200 (CEST) Received: by mail-wm1-f68.google.com with SMTP id l2so418821wmg.0 for ; Wed, 07 Aug 2019 08:09:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=1ap8Frg/Gf51xmOYNsf5m9BH5ZgczfUC5RTDt84nhnI=; b=i5OXx/pUkZhrD4NDNgAgmKIy2TF2IyXyDzpJQXsejzXIWsx4FJRrgSbJ3ivV+bQCfr CTlXXrgtQ9sVMNd+BhljbbGFd9vZbhj8lUAEf5pAK55QTD4Q56MwPvUd8ubYVHm4tFm7 y74/NRXZlzMsSu8cX6Q4HjD36Pn/59wQed2tzt9TDtT55OBFoFHFCYu7G45N1Obllq3C bEhG+qMXlIbva7K99YEepJWkl8V1xf0qyfn5uAhlc5PePovvlC/xAhXLB+43I2d73V2J idLuKpq0+W2eJKLGEflBF9hQ42Mi2bbxPmKuha6XGVwZbsbDgMEtqjlTCsIqfizCHQB5 Fmrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=1ap8Frg/Gf51xmOYNsf5m9BH5ZgczfUC5RTDt84nhnI=; b=G3Anxcse6Ps3+XEY7zo15U2VrHgW2e7nsi977l+n3AIbjeUvG+2T+A8zDBJPCWn5U6 84F4/j3pAKIB/Gi0x+0mdWY4gVMGZ2/5UJPuewjXaNqeG/M6ejRaNAkJ5RwAtmJ2Ljm2 n18z9atShp14jisUEWK+dJgD5UbxWO0zaTsgRKeEPGmJGtoKV4rwsSitwwtn4G0iH8FW bqEAo7Q2dAlUtz4m+RyPoXCMUCeIfx31KOtJpTYJ4dqaepec0bbO0bkfNNw50Kb+F3kU 5hWrMpzrmNeNt/T94aPw0T/qQfMCsY6JAD14qFS5dO3Afzhtni40fPjwf7fQ36xVTjZv GOIQ== X-Gm-Message-State: APjAAAUshrZbn4DyiU+fdkqVsAsy2L4gHXOBHAHvl3pfaT0HgHrUkePs DkFC22eCIu8N8DUxDi3199f18aUN/Q== X-Google-Smtp-Source: APXvYqxgtxB69wjL9mHofk2UHi4KItDvQCpjgWsmJ5RWMHTrbHx4CPcOkEyJ20Dr/q5TT09tIn2RFA== X-Received: by 2002:a1c:b146:: with SMTP id a67mr430452wmf.124.1565190579789; Wed, 07 Aug 2019 08:09:39 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:38 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:11 +0200 Message-Id: <57edb83bd966a82fa2a6b224ea4e5a8c544ec0fa.1565190405.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 02/12] ethdev: fix description of tx descriptor status X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The API comment of rte_eth_tx_descriptor_status() was incorrect. The reference descriptor (when offset = 0) is not where the next packet will be sent, but where the latest packet has been enqueued. Fixes: 52f5cdd2e897 ("ethdev: add descriptor status API") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- lib/librte_ethdev/rte_ethdev.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h index dc6596bc93b4..b423e71050e9 100644 --- a/lib/librte_ethdev/rte_ethdev.h +++ b/lib/librte_ethdev/rte_ethdev.h @@ -4245,8 +4245,8 @@ rte_eth_rx_descriptor_status(uint16_t port_id, uint16_t queue_id, * @param queue_id * A valid Tx queue identifier on this port. * @param offset - * The offset of the descriptor starting from tail (0 is the place where - * the next packet will be send). + * The offset of the descriptor starting from tail (0 is the last written + * descriptor). * * @return * - (RTE_ETH_TX_DESC_FULL) Descriptor is being processed by the hw, i.e. From patchwork Wed Aug 7 15:09:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57540 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A201C31FC; Wed, 7 Aug 2019 17:09:52 +0200 (CEST) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by dpdk.org (Postfix) with ESMTP id 113BB2BD3 for ; Wed, 7 Aug 2019 17:09:41 +0200 (CEST) Received: by mail-wm1-f65.google.com with SMTP id 10so406583wmp.3 for ; Wed, 07 Aug 2019 08:09:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=gTFJzslpHYR9f3LHN3S3BY6ntDu6T1luGQ2TnkCujSw=; b=gwekg01+K2ROk8rgN1MvmV23A7YN1+EmgHfiPl59XX7hcNbXvfGPMdDjNfv+eDue5h lhR0J79YQXRU+UAeOHyoD13KVXcBU3LGGzGJYMICCcBM8qXGIuSVJ22QyE3SEQ2lHUoT zjGm9YKOBvtjJyX/1q1B4THOeH7RdLDm24z/MTIajP3q4Izy3RQoe/+lV/0X6fDGbQQz 5rx9fe/T253O9WM/e8YTrGl2y/LRkOYQHtrYc3BPQjo2ZSAM272Z2SIjSk3IYM1CAa15 Pw2TbcpQRIImiorYPcZBVPRD9RssxVaG7AUky3f7jjOsBOTWcnGWCm2pX2GpvkYjIqjZ PQLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=gTFJzslpHYR9f3LHN3S3BY6ntDu6T1luGQ2TnkCujSw=; b=eyb7lcdLuWlMO6a4FNDa5cItrINiiYMLSC6yOzfy5LBuWG70x7kwyxlyS5rLSXcVtI iIWkLl6d8LHKwLnUD1/cSyOXPSqtW1RWLkQgJ7c7NS/ncm5P0oLa52BGNAqVYsOhyd78 thvRGdTszY8TCSwN8LP5AIxnUpifANvnG5YVZgZnQbsxZKq0wYF6vUU1wL/RImD1rFaB wuJOfP86f6oJZWZd7lSfEm89ULzZz7i1Y6pt6wbc+YzOBgjo+3PBON7MTxW373Rkv9W1 vo4LfSxC2km0GpROexV8ICd+++aiezWJO1HyQ6OCMvIj47sTifO7XVSfkjQfLnsBXHFE /GDA== X-Gm-Message-State: APjAAAXI7Co9z9oit+ZtTD4Bt2HpElFbI+EAbpqF2ME7lRMMxR36LeQ4 1nYmE4ej/v8lsWkAcQNUuJeYiqmREA== X-Google-Smtp-Source: APXvYqwEJrDsRtlXic/pihT1LvQOuNSvUBdwLAQ7eaEumpGjsT3NSnEtESpH6aP9lts7opaP0X02og== X-Received: by 2002:a1c:9889:: with SMTP id a131mr437926wme.22.1565190580625; Wed, 07 Aug 2019 08:09:40 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:40 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:12 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 03/12] net/e1000: fix Tx descriptor status api (igb) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. Fixes: 978f8eea1719 ("net/e1000: implement descriptor status API (igb)") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/e1000/igb_rxtx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index c5606de5d7a0..c22118e59a21 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -1835,14 +1835,15 @@ eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct igb_tx_queue *txq = tx_queue; volatile uint32_t *status; - uint32_t desc; + int32_t desc; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; - desc = txq->tx_tail + offset; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; + desc = txq->sw_ring[desc].last_id; status = &txq->tx_ring[desc].wb.status; if (*status & rte_cpu_to_le_32(E1000_TXD_STAT_DD)) From patchwork Wed Aug 7 15:09:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57541 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 639983423; Wed, 7 Aug 2019 17:09:54 +0200 (CEST) Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by dpdk.org (Postfix) with ESMTP id 05C5E2BD8 for ; Wed, 7 Aug 2019 17:09:42 +0200 (CEST) Received: by mail-wm1-f66.google.com with SMTP id 10so406637wmp.3 for ; Wed, 07 Aug 2019 08:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=kjmIHGsCfgqSzCSWzLj6cccbRySma6yWkdPueL4fIXk=; b=fnpkrq4qNcq6uZAmQ8wYQU4CMrm/JAgqRNUe0ikPWwO38TqBaB5drTvd+iacvEaGrz NyoaXL0bLK7HznsEIoubGTUjs3flsmh4gCg6sGIYUKhALYGZF/iZDSV8JJcqMD9o6/be lOLeeTU9QfDelPtDkMLOWf4fQn+6kU466i9Lb6ccIi2Dnu7bdjjuSIRbenMehTKp9wh5 fymafljA5uB584z+d8LGRnhy2faYNJF0wMzvrPr79v55BhUa+WrWrQ4zvJy4kkWZoBA0 cV0+/UMl/eEXIKFCHSm7IMT2sJFIRKebxovC1IEuYS5H52jn+h/dJykXK2CSbl8U4j6t 4t/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=kjmIHGsCfgqSzCSWzLj6cccbRySma6yWkdPueL4fIXk=; b=WzveOFRfSsGF7KcRJGcziOgQ6ERgMeD35EEWyIwBOk4Gh9o8HYZ42ZAzSp4p61PIaP wzqH2Ac5d+10uZJNQmgYNFLFqxV4tM79OEftgfaRcWVJOPnG8QMMFI8P6AgJ9a+rXuYX TYQ4XsuPkfIlCXCuy9RhefGAKDv5OdXt8g8/PahCMXgmf9XMSGKyjWByVlt4ac6B0rwM q49DZgz/9yrPfp0YPsVARWED+DwgJ3G4TvQJtiLKO6XA3g73jtwtNFg/XoX9SRujMkr7 KbRpYNOaVi1+9Nx+HFK0WK6eXzhp1+J0QR0IA2ruxNR4PQ91oBDkCJRABxe6NonRqOZD XAvg== X-Gm-Message-State: APjAAAXDRdDaEnTeMdWLnz5BqcryqB04wAoxorrDo1MxytE0e2BzfbPh zm01dL1CLaKn6YzVYaE4Rcmiwp/fOQ== X-Google-Smtp-Source: APXvYqw5chacDMDDtZMpKjV7ssMja9fUW4kkFxzGDG+YAoS3grNBjax3F8muBMmRoS820fPuzYNwNw== X-Received: by 2002:a1c:6555:: with SMTP id z82mr414257wmb.129.1565190581527; Wed, 07 Aug 2019 08:09:41 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:40 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:13 +0200 Message-Id: <792a739c6df952d3d132ec0b4ebc7a0e370d0277.1565190405.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 04/12] net/e1000: fix Tx descriptor status api (em) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: b9082317cab3 ("net/e1000: implement descriptor status API (em)") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/e1000/em_rxtx.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c index 5925e490641b..3061998c7768 100644 --- a/drivers/net/e1000/em_rxtx.c +++ b/drivers/net/e1000/em_rxtx.c @@ -152,6 +152,7 @@ struct em_tx_queue { uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */ struct em_tx_entry *sw_ring; /**< virtual address of SW ring. */ volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ + volatile uint32_t *tdh_reg_addr; /**< Address of TDH register. */ uint16_t nb_tx_desc; /**< number of TX descriptors. */ uint16_t tx_tail; /**< Current value of TDT register. */ /**< Start freeing TX buffers if there are less free descriptors than @@ -1304,6 +1305,7 @@ eth_em_tx_queue_setup(struct rte_eth_dev *dev, txq->port_id = dev->data->port_id; txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx)); + txq->tdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDH(queue_idx)); txq->tx_ring_phys_addr = tz->iova; txq->tx_ring = (struct e1000_data_desc *) tz->addr; @@ -1557,22 +1559,33 @@ eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct em_tx_queue *txq = tx_queue; volatile uint8_t *status; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; + + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = e1000_read_addr(txq->tdh_reg_addr); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].upper.fields.status; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].upper.fields.status; if (*status & E1000_TXD_STAT_DD) return RTE_ETH_TX_DESC_DONE; From patchwork Wed Aug 7 15:09:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57542 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 932D74C91; Wed, 7 Aug 2019 17:09:56 +0200 (CEST) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by dpdk.org (Postfix) with ESMTP id E62EB2BAF for ; Wed, 7 Aug 2019 17:09:42 +0200 (CEST) Received: by mail-wr1-f67.google.com with SMTP id p13so17167393wru.10 for ; Wed, 07 Aug 2019 08:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=8O5D8oaKajRKAycKCWBOPr1JPd+AjkcPPBYy+pLUd5Q=; b=J5argAjrsqxIF10vQ+trawcTTbSnBUkGJ2Ubz6jjrfR5kd9kjppkUkI5a8J+6V4Dbm 3ypvd7LGhbenHwPp1/vBk9hDPiXpC6uUrFsiAJFnZPPQ9fX0sKySE9753yiaj3JZELc8 tEWldKySL9uiESkdrv+tuk0NZU/OsTK93EW0ao7A5ictY4iE/In5hxCzJsFwxC2GgXxr nQg93VkTpTdQ7S0B5ArlUi4P8sNBK4IqFaqAWFJnQN3T7xN00+Jca/p9PH+MuSvGlH/d orjwsjlQYge8IYOf8Zvr33iEBDsRYQUVVVmNJ8QXy5WoALKwC+NKcVVg+6Nx2B+VR5Br Jm5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=8O5D8oaKajRKAycKCWBOPr1JPd+AjkcPPBYy+pLUd5Q=; b=YTTi9djvsHtEnVerwxbxSYKhb2HnbXlJ14MaYnqbYzoDiNfLh6HWtdLcjsMZ75Gpqv 1F4lIKdpzu9B1kqUCnTL0dcK18jUHKCc8N7u9lJc+DrJAY9tYUyeYJ+6U/MhwWkCPWkV rZxieuV9zLPR+gdKgVP2qTrRjpZ2ZBhoxqlyBhbqLmdaYNzn8SdjBHSTPea3/35EIk5g 9SC80/RWKnSPW7h6wimK21Bh5mgjXASOZf4V7Y9dXJ5zZTYarwVLZnYnYmdrQhWwW7no R2Zd9w0iq++uIym+Ys5pwyug7W6MqovVmhOHpHOhNptNZ1Bk+t4gTHwoH4jx577Xnvj6 jUrg== X-Gm-Message-State: APjAAAUOqb4RIzm8dDR+WJOY9LeJwpSYYJFLOew+YtrD26yh+ug34MTw b+lL9h/G4dGys7ZKGvSwjOzj7yJVkQ== X-Google-Smtp-Source: APXvYqwic2rt5JFw5Ykd0Hwc7PXK+NjT2JnicUPhi+BrLYuBg6np0fHA7GoxsmWLvm0Hkc1pXn8OIQ== X-Received: by 2002:a5d:50d1:: with SMTP id f17mr10744367wrt.124.1565190582406; Wed, 07 Aug 2019 08:09:42 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:41 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:14 +0200 Message-Id: <5411f97091b9d7806b88f847d138bd0ebb4024d3.1565190405.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 05/12] net/ixgbe: fix Tx descriptor status api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: 5da8b8814178 ("net/ixgbe: implement descriptor status API") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/ixgbe/ixgbe_rxtx.c | 45 +++++++++++++++++++++++++++++++----------- drivers/net/ixgbe/ixgbe_rxtx.h | 1 + 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index edcfa60cec98..4abc2fe37488 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -2627,10 +2627,15 @@ ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, hw->mac.type == ixgbe_mac_X540_vf || hw->mac.type == ixgbe_mac_X550_vf || hw->mac.type == ixgbe_mac_X550EM_x_vf || - hw->mac.type == ixgbe_mac_X550EM_a_vf) + hw->mac.type == ixgbe_mac_X550EM_a_vf) { txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx)); - else + txq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw, + IXGBE_VFTDH(queue_idx)); + } else { txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx)); + txq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw, + IXGBE_TDH(txq->reg_idx)); + } txq->tx_ring_phys_addr = tz->iova; txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr; @@ -3163,22 +3168,38 @@ ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) { struct ixgbe_tx_queue *txq = tx_queue; volatile uint32_t *status; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; + + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = ixgbe_read_addr(txq->tdh_reg_addr); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].wb.status; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + + /* In full featured mode, RS bit is only set in the last descriptor */ + /* of a multisegments packet */ + if (!(txq->offloads == 0 && + txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].wb.status; if (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)) return RTE_ETH_TX_DESC_DONE; diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h index 505d344b9cee..05fd4167576c 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.h +++ b/drivers/net/ixgbe/ixgbe_rxtx.h @@ -201,6 +201,7 @@ struct ixgbe_tx_queue { struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */ }; volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */ + volatile uint32_t *tdh_reg_addr; /**< Address of TDH register. */ uint16_t nb_tx_desc; /**< number of TX descriptors. */ uint16_t tx_tail; /**< current value of TDT reg. */ /**< Start freeing TX buffers if there are less free descriptors than From patchwork Wed Aug 7 15:09:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57543 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4B0424D27; Wed, 7 Aug 2019 17:09:58 +0200 (CEST) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by dpdk.org (Postfix) with ESMTP id 096172B9C for ; Wed, 7 Aug 2019 17:09:44 +0200 (CEST) Received: by mail-wr1-f65.google.com with SMTP id p17so91727762wrf.11 for ; Wed, 07 Aug 2019 08:09:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=0GlbaRdccY54BFN5ZohRBC0g+CI7Vg9FEOu0cE4CYKM=; b=hntc+Ac89OfdC90K51CMqtAtdeSvmEV4SVxwl+4QKttnpqlp86x241B9+zW8eOXw2v jH1ZcR+pzk7yBATnGSoUHZxJO5Ai0+lSv4H1aX6BrnBwErIm24gDz3GIBpxb6Y5ykm7t 66hjLnd7yDKRG9f9BLajbDs1XwhR1G/Rxk06x88AhQYyfUcWpAsdhtE7ssQs7qk5Ai0J b+l06rjYk9LegOHlZqrTH5crkYRdHE22Y9eRZEDPI/ba2NOPuV4WgnitXEjd2HtATXYi 4upiruWKWDPLIcAbdLSOg26Ycha4iCtY3aem/CQZxn/39dReR+5s4ZbRwYUnbX1Dv63b N8Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=0GlbaRdccY54BFN5ZohRBC0g+CI7Vg9FEOu0cE4CYKM=; b=QUigdlx+KruX80bpc1BgdrWh1Zs+1mSwRpSB0aFUXZ97MQhixGsNpF9Tu8LJWYazSO er0zVYKTNcGkVmH70raZMS6dcKHgKk12buo19lq4cElThJPomdqAPN4iQNskvpgaVPdN UKH8tVKcZyXm78FwGn1RTW5KwERE2IYs0rIc6OIAULELswI7hJ1orxHOY+6ABGbR+mnR wk9iimVDc1IORIxz9eXp8yO8y5CWjwnc17Q83QI3acdwjtz6H78vFZV+R2xAC2u0QwLn 39EEP+LYe21AfBFRULvJIYHCGt6q+FOuP4Bu1PJIfZQ6rPwMzmoKbiSTK6Bot8KU4ij0 bM/Q== X-Gm-Message-State: APjAAAV0+Y3139JtuOIqn2xerdcYoXVxav1EYXF884AxSYIzRUN0SMEc Kul+8bqjDWDga9KaJajk6Zxh0T4j5Q== X-Google-Smtp-Source: APXvYqxrLR3O3W2/YDo7kSIipKVZilUzEK81xy9ehmGD3um4jzYFFbog2zSAN7CMXQ83AN5qryPV6Q== X-Received: by 2002:adf:e691:: with SMTP id r17mr11687660wrm.67.1565190583362; Wed, 07 Aug 2019 08:09:43 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:42 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Olivier Matz , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:15 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 06/12] net/i40e: fix Tx descriptor status api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Olivier Matz The Tx descriptor status api was not behaving as expected. This API is used to inspect the content of the descriptors in the Tx ring to determine the length of the Tx queue. Since the software advances the tail pointer and the hardware advances the head pointer, the Tx queue is located before txq->tx_tail in the ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20) should inspect the 20th descriptor before the tail, not after. As before, we still need to take care about only checking descriptors that have the RS bit. Additionally, we can avoid an access to the ring if offset is greater or equal to nb_tx_desc - nb_tx_free. Fixes: a9dd9af6f38e ("net/i40e: implement descriptor status API") Cc: stable@dpdk.org Signed-off-by: Olivier Matz --- drivers/net/i40e/i40e_rxtx.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 692c3bab4b5f..d84a97732f1e 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -2031,22 +2031,39 @@ i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) struct i40e_tx_queue *txq = tx_queue; volatile uint64_t *status; uint64_t mask, expect; - uint32_t desc; + int32_t desc, dd; if (unlikely(offset >= txq->nb_tx_desc)) return -EINVAL; + if (offset >= txq->nb_tx_desc - txq->nb_tx_free) + return RTE_ETH_TX_DESC_DONE; + + desc = txq->tx_tail - offset - 1; + if (desc < 0) + desc += txq->nb_tx_desc; - desc = txq->tx_tail + offset; - /* go to next desc that has the RS bit */ - desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) * - txq->tx_rs_thresh; - if (desc >= txq->nb_tx_desc) { - desc -= txq->nb_tx_desc; - if (desc >= txq->nb_tx_desc) - desc -= txq->nb_tx_desc; + /* offset is too small, no other way than reading PCI reg */ + if (unlikely(offset < txq->tx_rs_thresh)) { + int16_t tx_head, queue_size; + tx_head = I40E_READ_REG(I40E_VSI_TO_HW(txq->vsi), + I40E_QTX_HEAD(txq->reg_idx)); + queue_size = txq->tx_tail - tx_head; + if (queue_size < 0) + queue_size += txq->nb_tx_desc; + return queue_size > offset ? RTE_ETH_TX_DESC_FULL : + RTE_ETH_TX_DESC_DONE; } - status = &txq->tx_ring[desc].cmd_type_offset_bsz; + /* index of the dd bit to look at */ + dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1; + + /* In full featured mode, RS bit is only set in the last descriptor */ + /* of a multisegments packet */ + if (!(txq->offloads == 0 && + txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) + dd = txq->sw_ring[dd].last_id; + + status = &txq->tx_ring[dd].cmd_type_offset_bsz; mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK); expect = rte_cpu_to_le_64( I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT); From patchwork Wed Aug 7 15:09:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57544 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4A4681B464; Wed, 7 Aug 2019 17:10:01 +0200 (CEST) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by dpdk.org (Postfix) with ESMTP id 64BBF2C16 for ; Wed, 7 Aug 2019 17:09:46 +0200 (CEST) Received: by mail-wm1-f68.google.com with SMTP id 10so406864wmp.3 for ; Wed, 07 Aug 2019 08:09:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=afZoqfzpWQuC9ViJWMOoQR0Yyw87jibufsab0QXr4mA=; b=ZXyRjiJ+pA41k6SbJRlip9Fymn/ToHqDsn9pGotD/z0mV1+Sm2vqMpaqpKlAI6GFa9 mMuLtSY2cEKWRuiPXRvt7eamHktK6Kiw/YoeEkmsPtMVoFJa8jCf77rU9ODHj1ErD7dk CPYrxGIxvTQMULNdQiLYKCat3g2a4Hjd38pwUQzqjkqw30JP/K1TXmOej+R+ZaklRszC Nz3zENRclCNjeK4R0HZ6aPYvwBldytpQcqy6xW8TGCFDr44xLJ2ubcAcz4FW8PL4+eRn rcOSwx/VkGvaFLBZvz73PIWQOy4ocx5d/Lm21KM7BMlnQTZ3/b7H/yP7vGab9fMLk4J7 gZVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=afZoqfzpWQuC9ViJWMOoQR0Yyw87jibufsab0QXr4mA=; b=Q/H4spA+3BWVwuQES5hG6ZRxehMo2CcJRT+PMJ/8NH1T0Goh/Pe7i14+US9IIjh2/J LaGI5Yh372r73WyVrYVr2K3hLCWF4bVlMnqKms1E7P+O4YFsZbuo6E7PRnr13idd5ODV ONTKxZCVjA0s+q60CHcxbHKhlToMWVVjghvNAZV5mE70v1OyKthg++odOYfHqkCf/rIT YoLZZ8VVDeE4g30J+fj+FUAGezAiXlmUeyxZxcHRF4NYVYNgCY6bhAoHv6jcFcDcaiGW Y624mUzj75zetWUy7I+kYEWKxISxEp3WlqZcgu8iF3lq1RHJOG1jmu4NcHOzuHj0Ysie Xj/A== X-Gm-Message-State: APjAAAVi3jzTSwyLjGokcnohO4PMmUAciHjg7GSVuiPvf1lHKVnGQjmi tMAsvREto5utZacGSb90UEIMFhgbQg== X-Google-Smtp-Source: APXvYqy28bJUk5U565z5V/UQMjP7yyJOS1zFA7VqWUYJ2KuBNFHJDVswLuThDBf/txXs6JvFfsP3oA== X-Received: by 2002:a1c:be19:: with SMTP id o25mr440486wmf.54.1565190584388; Wed, 07 Aug 2019 08:09:44 -0700 (PDT) Received: from ascain.dev.6wind.com. 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[62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:43 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Laurent Hardy , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:16 +0200 Message-Id: <22c111c3cd1eff557a5ea95997ba1033d9d31b5f.1565190405.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 07/12] net/i40e: set speed to undefined for default case in link update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Laurent Hardy During PF/VF link update, a default speed value of 100M will be set if get_link_info has failed or speed is unknown. Consequently if PF is put in no-carrier state, VFs will switch to "in carrier" state due to a link up + a link speed set to 100M (default value if no speed detected). To be consistent with linux drivers on which PF and VFs are in same carrier state, sets default speed to undefined (instead of 100M) and updates a link status of VF only if link is up and speed is different from undefined. Fixes: 4861cde46116 ('i40e: new poll mode driver') Cc: stable@dpdk.org Signed-off-by: Laurent Hardy --- drivers/net/i40e/i40e_ethdev.c | 4 ++-- drivers/net/i40e/i40e_ethdev_vf.c | 8 +++++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 4e40b7ab5250..76abe8209a10 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -2743,7 +2743,7 @@ update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, status = i40e_aq_get_link_info(hw, enable_lse, &link_status, NULL); if (unlikely(status != I40E_SUCCESS)) { - link->link_speed = ETH_SPEED_NUM_100M; + link->link_speed = ETH_SPEED_NUM_NONE; link->link_duplex = ETH_LINK_FULL_DUPLEX; PMD_DRV_LOG(ERR, "Failed to get link info"); return; @@ -2777,7 +2777,7 @@ update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link, link->link_speed = ETH_SPEED_NUM_40G; break; default: - link->link_speed = ETH_SPEED_NUM_100M; + link->link_speed = ETH_SPEED_NUM_NONE; break; } } diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 308fb9835ab1..bf707e57b29b 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -2143,13 +2143,15 @@ i40evf_dev_link_update(struct rte_eth_dev *dev, new_link.link_speed = ETH_SPEED_NUM_40G; break; default: - new_link.link_speed = ETH_SPEED_NUM_100M; + new_link.link_speed = ETH_SPEED_NUM_NONE; break; } /* full duplex only */ new_link.link_duplex = ETH_LINK_FULL_DUPLEX; - new_link.link_status = vf->link_up ? ETH_LINK_UP : - ETH_LINK_DOWN; + new_link.link_status = vf->link_up && + new_link.link_speed != ETH_SPEED_NUM_NONE + ? ETH_LINK_UP + : ETH_LINK_DOWN; new_link.link_autoneg = !(dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); From patchwork Wed Aug 7 15:09:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57545 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DC7371B954; Wed, 7 Aug 2019 17:10:04 +0200 (CEST) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by dpdk.org (Postfix) with ESMTP id 7C1B72C16 for ; Wed, 7 Aug 2019 17:09:47 +0200 (CEST) Received: by mail-wm1-f68.google.com with SMTP id v19so385062wmj.5 for ; Wed, 07 Aug 2019 08:09:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=jSQu2DFj7DD6iYsxknajP4MvciHyyDmKoyWDLHaf6hw=; b=j6aUIHFb7A3rSAW4Vc9MosY5dJI3nKzKbRZb1/qwKloEePti6u4BBLixf2qWBW7VDO 3BbQSPu/gG8NZA7XPhFOlC8n+BOD6dldEq84DyaI4cdAYBEwYhwmDDcWY534bTxIS63B rGW1sLtIJBnD+gmV4PJnKyUjjxvOArc7eTm4gbw2B42AIJHq2aIfSyjVHXP4+p5CuU4U 9VPimTWxCQzcxfnWeOeNSMLTZNqCh2Rj/MNH0lWSNhXB8RFU/aQU/MYzUY17/hv6YsLf YPEP8R7pgoDSRM3TA7A7dO5gPpcOrZjOVFF0t3ZIP0WNdzeDnEaXj4mi4LFCzN8/84yu nZ3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=jSQu2DFj7DD6iYsxknajP4MvciHyyDmKoyWDLHaf6hw=; b=F4XJxVS+VUzWK+lt6PCQQEauRGhZoRY2p+V2zMlDWHDtupJdpR2rY+2RAHMGsqGSzq 5W5m79zREhAv9kFGrW//yBkXx1mUNjVIM+q3cB6ozNAGvxFFbUSpo4J05YdzLia2Bvl+ kajrBhY7+6afu/EpD5CF/2Wb4HKBBri6yXNvY66/i6byxTE2LNWUB/baqxHVNyhWoAj7 hGtvlsM/3epcUKSLaVtk08kQZMaz1S5EzzdIsEKjlulhvVqASOv99VchDE+4JFHcdeIX 82cXiw89Fu2Mfs+5//a/1gI2/PGFttF7ZIlGcrTAV1gwnGfR4VDs1WTvBm0T7PXPZfde 9kCA== X-Gm-Message-State: APjAAAWO8n05Lwt6ougJZHX1+jQDZ4lQiWqzihzUOuRP0EHzpHHU5hkY MknQbmdHNGONCdQvq5qMrH1VIAqS+g== X-Google-Smtp-Source: APXvYqxwZ72xIVoRm8/w3WQWv7zDc/S/z/FkudMNeyt0avUm9Bc7hx34onXqJmV3se76hozHcAL17w== X-Received: by 2002:a1c:7a02:: with SMTP id v2mr390730wmc.159.1565190586979; Wed, 07 Aug 2019 08:09:46 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:46 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Thibaut Collet , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:17 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 08/12] virtio: fix rx stats with vectorized functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Thibaut Collet With vectorized functions, only the rx stats for number of packets is incremented. Update also the other statistics. Performance impact is about 2% Fixes: fc3d66212fed ("virtio: add vector Rx") Cc: stable@dpdk.org Signed-off-by: Thibaut Collet --- drivers/net/virtio/virtio_rxtx.c | 2 +- drivers/net/virtio/virtio_rxtx.h | 2 ++ drivers/net/virtio/virtio_rxtx_simple_neon.c | 6 ++++++ drivers/net/virtio/virtio_rxtx_simple_sse.c | 6 ++++++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/virtio/virtio_rxtx.c b/drivers/net/virtio/virtio_rxtx.c index 27ead19fbe81..6dd62bf51863 100644 --- a/drivers/net/virtio/virtio_rxtx.c +++ b/drivers/net/virtio/virtio_rxtx.c @@ -1083,7 +1083,7 @@ virtio_discard_rxbuf_inorder(struct virtqueue *vq, struct rte_mbuf *m) } } -static inline void +void virtio_update_packet_stats(struct virtnet_stats *stats, struct rte_mbuf *mbuf) { uint32_t s = mbuf->pkt_len; diff --git a/drivers/net/virtio/virtio_rxtx.h b/drivers/net/virtio/virtio_rxtx.h index 685cc4f8104c..1eb8dae227ee 100644 --- a/drivers/net/virtio/virtio_rxtx.h +++ b/drivers/net/virtio/virtio_rxtx.h @@ -59,5 +59,7 @@ struct virtnet_ctl { }; int virtio_rxq_vec_setup(struct virtnet_rx *rxvq); +void virtio_update_packet_stats(struct virtnet_stats *stats, + struct rte_mbuf *mbuf); #endif /* _VIRTIO_RXTX_H_ */ diff --git a/drivers/net/virtio/virtio_rxtx_simple_neon.c b/drivers/net/virtio/virtio_rxtx_simple_neon.c index cdc2a4d28ed5..e4b18cba0ce5 100644 --- a/drivers/net/virtio/virtio_rxtx_simple_neon.c +++ b/drivers/net/virtio/virtio_rxtx_simple_neon.c @@ -47,6 +47,7 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, struct vring_used_elem *rused; struct rte_mbuf **sw_ring; struct rte_mbuf **sw_ring_end; + struct rte_mbuf **ref_rx_pkts; uint16_t nb_pkts_received = 0; uint8x16_t shuf_msk1 = { @@ -105,6 +106,7 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, virtqueue_notify(vq); } + ref_rx_pkts = rx_pkts; for (nb_pkts_received = 0; nb_pkts_received < nb_used;) { uint64x2_t desc[RTE_VIRTIO_DESC_PER_LOOP / 2]; @@ -204,5 +206,9 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, vq->vq_used_cons_idx += nb_pkts_received; vq->vq_free_cnt += nb_pkts_received; rxvq->stats.packets += nb_pkts_received; + for (nb_used = 0; nb_used < nb_pkts_received; nb_used++) { + rxvq->stats.bytes += ref_rx_pkts[nb_used]->pkt_len; + virtio_update_packet_stats(&rxvq->stats, ref_rx_pkts[nb_used]); + } return nb_pkts_received; } diff --git a/drivers/net/virtio/virtio_rxtx_simple_sse.c b/drivers/net/virtio/virtio_rxtx_simple_sse.c index af76708d66ae..c757e8c9d601 100644 --- a/drivers/net/virtio/virtio_rxtx_simple_sse.c +++ b/drivers/net/virtio/virtio_rxtx_simple_sse.c @@ -48,6 +48,7 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, struct vring_used_elem *rused; struct rte_mbuf **sw_ring; struct rte_mbuf **sw_ring_end; + struct rte_mbuf **ref_rx_pkts; uint16_t nb_pkts_received = 0; __m128i shuf_msk1, shuf_msk2, len_adjust; @@ -107,6 +108,7 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, virtqueue_notify(vq); } + ref_rx_pkts = rx_pkts; for (nb_pkts_received = 0; nb_pkts_received < nb_used;) { __m128i desc[RTE_VIRTIO_DESC_PER_LOOP / 2]; @@ -190,5 +192,9 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, vq->vq_used_cons_idx += nb_pkts_received; vq->vq_free_cnt += nb_pkts_received; rxvq->stats.packets += nb_pkts_received; + for (nb_used = 0; nb_used < nb_pkts_received; nb_used++) { + rxvq->stats.bytes += ref_rx_pkts[nb_used]->pkt_len; + virtio_update_packet_stats(&rxvq->stats, ref_rx_pkts[nb_used]); + } return nb_pkts_received; } From patchwork Wed Aug 7 15:09:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57546 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8B99B1B956; Wed, 7 Aug 2019 17:10:09 +0200 (CEST) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by dpdk.org (Postfix) with ESMTP id 357962C58 for ; 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(host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:47 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: Thibaut Collet , stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:18 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 09/12] virtio: get all pending rx packets with vectorized functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Thibaut Collet The loop to read packets does not take all packets as the number of available packets (nb_used) is decremented in the loop. Take all available packets provides a performance improvement of 3%. Fixes: fc3d66212fed ("virtio: add vector Rx") Cc: stable@dpdk.org Signed-off-by: Thibaut Collet --- drivers/net/virtio/virtio_rxtx_simple_neon.c | 5 +++-- drivers/net/virtio/virtio_rxtx_simple_sse.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/virtio/virtio_rxtx_simple_neon.c b/drivers/net/virtio/virtio_rxtx_simple_neon.c index e4b18cba0ce5..66bdaa00e01f 100644 --- a/drivers/net/virtio/virtio_rxtx_simple_neon.c +++ b/drivers/net/virtio/virtio_rxtx_simple_neon.c @@ -42,7 +42,7 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, struct virtnet_rx *rxvq = rx_queue; struct virtqueue *vq = rxvq->vq; struct virtio_hw *hw = vq->hw; - uint16_t nb_used; + uint16_t nb_used, nb_total; uint16_t desc_idx; struct vring_used_elem *rused; struct rte_mbuf **sw_ring; @@ -106,9 +106,10 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, virtqueue_notify(vq); } + nb_total = nb_used; ref_rx_pkts = rx_pkts; for (nb_pkts_received = 0; - nb_pkts_received < nb_used;) { + nb_pkts_received < nb_total;) { uint64x2_t desc[RTE_VIRTIO_DESC_PER_LOOP / 2]; uint64x2_t mbp[RTE_VIRTIO_DESC_PER_LOOP / 2]; uint64x2_t pkt_mb[RTE_VIRTIO_DESC_PER_LOOP]; diff --git a/drivers/net/virtio/virtio_rxtx_simple_sse.c b/drivers/net/virtio/virtio_rxtx_simple_sse.c index c757e8c9d601..811b416755e7 100644 --- a/drivers/net/virtio/virtio_rxtx_simple_sse.c +++ b/drivers/net/virtio/virtio_rxtx_simple_sse.c @@ -43,7 +43,7 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, struct virtnet_rx *rxvq = rx_queue; struct virtqueue *vq = rxvq->vq; struct virtio_hw *hw = vq->hw; - uint16_t nb_used; + uint16_t nb_used, nb_total; uint16_t desc_idx; struct vring_used_elem *rused; struct rte_mbuf **sw_ring; @@ -108,9 +108,10 @@ virtio_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, virtqueue_notify(vq); } + nb_total = nb_used; ref_rx_pkts = rx_pkts; for (nb_pkts_received = 0; - nb_pkts_received < nb_used;) { + nb_pkts_received < nb_total;) { __m128i desc[RTE_VIRTIO_DESC_PER_LOOP / 2]; __m128i mbp[RTE_VIRTIO_DESC_PER_LOOP / 2]; __m128i pkt_mb[RTE_VIRTIO_DESC_PER_LOOP]; From patchwork Wed Aug 7 15:09:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57547 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 490121B95B; Wed, 7 Aug 2019 17:10:13 +0200 (CEST) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by dpdk.org (Postfix) with ESMTP id 176DA2C6A for ; Wed, 7 Aug 2019 17:09:50 +0200 (CEST) Received: by mail-wr1-f67.google.com with SMTP id q12so1478299wrj.12 for ; Wed, 07 Aug 2019 08:09:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=wgarJcXvidJ78ZEw1ta+Nge5CEfZ3EqDvpTZDWMalDE=; b=glJor6gGYIKWIANEj7n16ynXfqETsu+B67HgrTEp5BSOOPYKjmI6y2jBiSLw9O/bA/ bBU/KoJ2lp95bwlFhxNoOCQZhKKMwr9fRmq7TtqBm4RbhMCwYLPDeWzhzrZYU/uC8RdJ W52vPFLpDupyW9hoOzkGVrZuaVIskwqOmHRNOfV50xRN+Y4kNiPpEjtToBR7CjwW+wR3 105nPqoDstGMwo+ihhTvNDOlrwREDmoVly9lPJAnB9igK+iSDJ5+F4Ym9vxk0MJGe3pC PRnnMzbsfOyFGsNpiYvONlH6M14HNiMEaTtYQaoZJ4eQRALizdHfE7ZEpRXxCwQMkn+Q 8fYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=wgarJcXvidJ78ZEw1ta+Nge5CEfZ3EqDvpTZDWMalDE=; b=qfuYYdWa15nbDVAk3BsY/2NIQuxprx0Btwrmmgazye0n8xNrVdAObl5G4mP+q4bhr/ gkD4CRNtfb5BsphwCj68V2cY3izum9rOprn3H2Kx8Q6fkMhdl98PgLhrKRfNQqoVj1M9 bQcpBn9tD6LfxreFhEmFwcsrXdmRfY5sqNylCWH1cCnYVF29ON4PSb1la+U/T3Yu/ubU /LoE9zr0UkZp0iNZB0GZxpbWaYwV+Iyg3mkEfgj/uPwLc8VceJFJI45zjaohEX9V2HRk 6VDMzPZ+BzDJwmLPSDHVC5wnmo0ASB26HXLnOn2Ym61hDEGcF27Y0tGdoIdCWxmtZn7b uQQg== X-Gm-Message-State: APjAAAWrs4h1oGLJZvHJ67pMdzbVoF7hc1V0fsCFG9V8rhKxjnmtLxt/ zgBe16vf2cDkQXfJ5ML3f5jsfL772Q== X-Google-Smtp-Source: APXvYqyRock0pO8yAq0OG0zsG4jnmyZGWVb+fcD06REfh8JLEKyLCekV8Ct9a2HJUszgZ/hAi10qhg== X-Received: by 2002:a5d:6650:: with SMTP id f16mr11895234wrw.89.1565190589587; Wed, 07 Aug 2019 08:09:49 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:48 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:19 +0200 Message-Id: <8a592c1aaced192bae30aa2570b4853b1d33bbef.1565190405.git.thierry.herbelot@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 10/12] drivers/crypto/openssl: use a local copy for the session contexts X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Session contexts are used for temporary storage when processing a packet. If packets for the same session are to be processed simultaneously on multiple cores, separate contexts must be used. Note: with openssl 1.1.1 EVP_CIPHER_CTX can no longer be defined as a variable on the stack: it must be allocated. This in turn reduces the performance. Fixes: d61f70b4c918 ('crypto/libcrypto: add driver for OpenSSL library') Cc: stable@dpdk.org Signed-off-by: Thierry Herbelot --- drivers/crypto/openssl/rte_openssl_pmd.c | 34 +++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/openssl/rte_openssl_pmd.c b/drivers/crypto/openssl/rte_openssl_pmd.c index 2f5552840741..ce2d12347737 100644 --- a/drivers/crypto/openssl/rte_openssl_pmd.c +++ b/drivers/crypto/openssl/rte_openssl_pmd.c @@ -1290,6 +1290,7 @@ process_openssl_combined_op int srclen, aadlen, status = -1; uint32_t offset; uint8_t taglen; + EVP_CIPHER_CTX *ctx_copy; /* * Segmented destination buffer is not supported for @@ -1326,6 +1327,8 @@ process_openssl_combined_op } taglen = sess->auth.digest_length; + ctx_copy = EVP_CIPHER_CTX_new(); + EVP_CIPHER_CTX_copy(ctx_copy, sess->cipher.ctx); if (sess->cipher.direction == RTE_CRYPTO_CIPHER_OP_ENCRYPT) { if (sess->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC || @@ -1333,12 +1336,12 @@ process_openssl_combined_op status = process_openssl_auth_encryption_gcm( mbuf_src, offset, srclen, aad, aadlen, iv, - dst, tag, sess->cipher.ctx); + dst, tag, ctx_copy); else status = process_openssl_auth_encryption_ccm( mbuf_src, offset, srclen, aad, aadlen, iv, - dst, tag, taglen, sess->cipher.ctx); + dst, tag, taglen, ctx_copy); } else { if (sess->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC || @@ -1346,14 +1349,15 @@ process_openssl_combined_op status = process_openssl_auth_decryption_gcm( mbuf_src, offset, srclen, aad, aadlen, iv, - dst, tag, sess->cipher.ctx); + dst, tag, ctx_copy); else status = process_openssl_auth_decryption_ccm( mbuf_src, offset, srclen, aad, aadlen, iv, - dst, tag, taglen, sess->cipher.ctx); + dst, tag, taglen, ctx_copy); } + EVP_CIPHER_CTX_free(ctx_copy); if (status != 0) { if (status == (-EFAULT) && sess->auth.operation == @@ -1372,6 +1376,7 @@ process_openssl_cipher_op { uint8_t *dst, *iv; int srclen, status; + EVP_CIPHER_CTX *ctx_copy; /* * Segmented destination buffer is not supported for @@ -1388,22 +1393,25 @@ process_openssl_cipher_op iv = rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv.offset); + ctx_copy = EVP_CIPHER_CTX_new(); + EVP_CIPHER_CTX_copy(ctx_copy, sess->cipher.ctx); if (sess->cipher.mode == OPENSSL_CIPHER_LIB) if (sess->cipher.direction == RTE_CRYPTO_CIPHER_OP_ENCRYPT) status = process_openssl_cipher_encrypt(mbuf_src, dst, op->sym->cipher.data.offset, iv, - srclen, sess->cipher.ctx); + srclen, ctx_copy); else status = process_openssl_cipher_decrypt(mbuf_src, dst, op->sym->cipher.data.offset, iv, - srclen, sess->cipher.ctx); + srclen, ctx_copy); else status = process_openssl_cipher_des3ctr(mbuf_src, dst, op->sym->cipher.data.offset, iv, sess->cipher.key.data, srclen, - sess->cipher.ctx); + ctx_copy); + EVP_CIPHER_CTX_free(ctx_copy); if (status != 0) op->status = RTE_CRYPTO_OP_STATUS_ERROR; } @@ -1507,6 +1515,8 @@ process_openssl_auth_op(struct openssl_qp *qp, struct rte_crypto_op *op, { uint8_t *dst; int srclen, status; + EVP_MD_CTX *ctx_a; + HMAC_CTX *ctx_h; srclen = op->sym->auth.data.length; @@ -1514,14 +1524,20 @@ process_openssl_auth_op(struct openssl_qp *qp, struct rte_crypto_op *op, switch (sess->auth.mode) { case OPENSSL_AUTH_AS_AUTH: + ctx_a = EVP_MD_CTX_create(); + EVP_MD_CTX_copy_ex(ctx_a, sess->auth.auth.ctx); status = process_openssl_auth(mbuf_src, dst, op->sym->auth.data.offset, NULL, NULL, srclen, - sess->auth.auth.ctx, sess->auth.auth.evp_algo); + ctx_a, sess->auth.auth.evp_algo); + EVP_MD_CTX_destroy(ctx_a); break; case OPENSSL_AUTH_AS_HMAC: + ctx_h = HMAC_CTX_new(); + HMAC_CTX_copy(ctx_h, sess->auth.hmac.ctx); status = process_openssl_auth_hmac(mbuf_src, dst, op->sym->auth.data.offset, srclen, - sess->auth.hmac.ctx); + ctx_h); + HMAC_CTX_free(ctx_h); break; default: status = -1; From patchwork Wed Aug 7 15:09:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57548 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 03A171B997; Wed, 7 Aug 2019 17:10:16 +0200 (CEST) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by dpdk.org (Postfix) with ESMTP id E1A452BAE for ; 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(host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:49 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:20 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 11/12] drivers/crypto/dpaa_sec: update DPAA iova table in dpaa_mem_vtop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" dpaa_sec needs translations between physical and virtual addresses. V to P translation is relatively fast, as memory is managed in contiguous segments. The result of each V to P translation is used to update the DPAA iova table, which should be updated by a Mem event callback, but is not. Then the DPAA iova table has entries for all needed memory ranges. With this patch, dpaa_mem_ptov will always use dpaax_iova_table_get_va, which ensures optimal performance. Fixes: 5a7dbb934d75 ('dpaa: enable dpaax library') Cc: stable@dpdk.org Signed-off-by: Thierry Herbelot --- drivers/crypto/dpaa_sec/dpaa_sec.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/dpaa_sec/dpaa_sec.c b/drivers/crypto/dpaa_sec/dpaa_sec.c index 122c80a072ff..22b8b1d63ce0 100644 --- a/drivers/crypto/dpaa_sec/dpaa_sec.c +++ b/drivers/crypto/dpaa_sec/dpaa_sec.c @@ -38,6 +38,7 @@ #include #include #include +#include enum rta_sec_era rta_sec_era; @@ -100,8 +101,10 @@ dpaa_mem_vtop(void *vaddr) const struct rte_memseg *ms; ms = rte_mem_virt2memseg(vaddr, NULL); - if (ms) + if (ms) { + dpaax_iova_table_update(ms->iova, (void *)ms->addr_64, ms->len); return ms->iova + RTE_PTR_DIFF(vaddr, ms->addr); + } return (size_t)NULL; } From patchwork Wed Aug 7 15:09:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Herbelot X-Patchwork-Id: 57549 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7C9A31B9A6; Wed, 7 Aug 2019 17:10:18 +0200 (CEST) Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by dpdk.org (Postfix) with ESMTP id CB75C2C58 for ; Wed, 7 Aug 2019 17:09:51 +0200 (CEST) Received: by mail-wr1-f66.google.com with SMTP id p17so91728163wrf.11 for ; Wed, 07 Aug 2019 08:09:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=l/e2lobreFgY8/tp8VSoSDkLX5vQfNzhxpmxnCrZGkY=; b=Fau9ZSHZJuy5K+/gVkGUqIswh3qg1zROsmo1lK41D/thuDaWb0Kh+uCquTn0Uf/er7 aCH9Dm020iCRlGBPWyE8XLIsnrUwAzm/Wbilxo5josqV/6xJE+os1IFQ1xaA32YiLpvh V76ZcgYQVbSRhuM7HFkn6GuUdc9Snl0gaeai+duc6WgxNhslXbfV5+UMWc5H4C4iGKVw +2zYpg4VgT5jFsV3hpdu+W+sK6Y3iFRcCx5WNk7o9Kro66jixIutcMQ9YQz01D5Sl8sa dFFvIsCVvnInxY+7qm8MFMhGwUKvMRF0JVx7zwx5dqoniR7fqAJmTZYYKZQlTXfiiO0O FOUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=l/e2lobreFgY8/tp8VSoSDkLX5vQfNzhxpmxnCrZGkY=; b=t4qyJO+9Qz/LinF2HCi4+84f7EDUBWUszv+7lhQutNrI7EHbYGZMS8FQ4aR2efupSw MbieXb8JeVYYv5/jVOfrl13AHC1KfFO8bTaAJA8+SIqkkQAmHh+wFza7gL+IauDvWMW/ o4bZY51QegXkx+lvnkJB0EoZDtvEIfljiM+fRJG3qf9WC0CzJKffO1cYWESIzadxMSr9 zxlBRE6HWKKVwgvMuem9h4SMVd5MyF7MFxxpgj+3/mfDmlWmEX75bP+ae7PsKXqZiHJr O7NjRAb20x4k4EBL5YjmZMHyXams5NKVjtlkjCNTHyUh2CGT04NnJ0xerEUBsPtGDcsL o/Eg== X-Gm-Message-State: APjAAAWSpwzhDecDgSry8W57uNDXFwhxWwrWemt9h29PBpQ5G5ogex6O bZe7GN+d3h83CqZt5qS/ZcF/stL9rA== X-Google-Smtp-Source: APXvYqyDV/uVCJHiKz+79z9pcNwTtTD8E65OJd31k/l5NEV7GLZU8WmqWfZ6R/xiMKZHz9cBrEikqw== X-Received: by 2002:adf:b60c:: with SMTP id f12mr11774834wre.231.1565190591363; Wed, 07 Aug 2019 08:09:51 -0700 (PDT) Received: from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id r5sm382862wmh.35.2019.08.07.08.09.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Aug 2019 08:09:50 -0700 (PDT) From: Thierry Herbelot To: dev@dpdk.org Cc: stable@dpdk.org, Thomas Monjalon Date: Wed, 7 Aug 2019 17:09:21 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 19.11 V2 12/12] drivers/crypto/octeontx: enable unbinding for the OcteonTx crypto engines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Like for Ethernet ports, the OcteonTx crypto engines must first be unbound from their kernel module, then rebound to vfio-pci, before being usable in DPDK. As this capability is detected at runtime by dpdk-pmdinfo, add the info in the PMD registering directives. Then an external script can be used for bind and unbind. Fixes: bfe2ae495ee268 ('crypto/octeontx: add PMD skeleton') Cc: stable@dpdk.org Signed-off-by: Thierry Herbelot --- drivers/crypto/octeontx/otx_cryptodev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c index fc64a5f3041f..16f1909966d0 100644 --- a/drivers/crypto/octeontx/otx_cryptodev.c +++ b/drivers/crypto/octeontx/otx_cryptodev.c @@ -118,6 +118,7 @@ static struct cryptodev_driver otx_cryptodev_drv; RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd); RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table); +RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_OCTEONTX_PMD, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver, otx_cryptodev_driver_id);