From patchwork Thu Aug 8 16:01:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pei, Andy" X-Patchwork-Id: 57598 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CC73D1BE8A; Thu, 8 Aug 2019 18:10:46 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 413C41BE7D for ; Thu, 8 Aug 2019 18:10:44 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 09:10:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,362,1559545200"; d="scan'208";a="258757402" Received: from dpdk-dipei.sh.intel.com ([10.67.110.224]) by orsmga001.jf.intel.com with ESMTP; 08 Aug 2019 09:10:41 -0700 From: Andy Pei To: dev@dpdk.org Cc: rosen.xu@intel.com, tianfei.zhang@intel.com Date: Fri, 9 Aug 2019 00:01:30 +0800 Message-Id: <1565280090-344032-1-git-send-email-andy.pei@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1565255540-308917-1-git-send-email-andy.pei@intel.com> References: <1565255540-308917-1-git-send-email-andy.pei@intel.com> Subject: [dpdk-dev] [PATCH v2] net/ipn3ke: setup MTU when HW init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" set up mtu to the minimun in tx mtu, rx mtu and IPN3KE_MAC_FRAME_SIZE_MAX. Signed-off-by: Andy Pei --- v2: * modify low bound and upper bound. drivers/net/ipn3ke/ipn3ke_ethdev.c | 97 ++++++++++++++++++++++++++++++++++++++ drivers/net/ipn3ke/ipn3ke_ethdev.h | 19 ++++++++ 2 files changed, 116 insertions(+) diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c index c226d63..1a6c217 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c @@ -209,6 +209,100 @@ return 0; } +static void ipn3ke_10G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tx; + uint32_t rx; + uint32_t tmp; + + (*hw->f_mac_read)(hw, + &tx, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_read)(hw, + &rx, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + tmp = (tx > rx) ? rx : tx; + if (tmp < RTE_ETHER_MIN_MTU) + tmp = RTE_ETHER_MIN_MTU; + if (tmp > IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD) + tmp = IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_TX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_10G_RX_FRAME_MAXLENGTH, + mac_num, + eth_group_sel); +} + +static void ipn3ke_25G_mtu_setup +(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel) +{ + uint32_t tx; + uint32_t rx; + uint32_t tmp; + + (*hw->f_mac_read)(hw, + &tx, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_read)(hw, + &rx, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + tmp = (tx > rx) ? rx : tx; + if (tmp < RTE_ETHER_MIN_MTU) + tmp = RTE_ETHER_MIN_MTU; + if (tmp > IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD) + tmp = IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD; + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_TX_SIZE_CONFIG, + mac_num, + eth_group_sel); + + (*hw->f_mac_write)(hw, + tmp, + IPN3KE_25G_MAX_RX_SIZE_CONFIG, + mac_num, + eth_group_sel); +} + +static void +ipn3ke_mtu_setup(struct ipn3ke_hw *hw) +{ + int i; + if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { + for (i = 0; i < hw->port_num; i++) { + ipn3ke_10G_mtu_setup(hw, i, 0); + ipn3ke_10G_mtu_setup(hw, i, 1); + } + } else if (hw->retimer.mac_type == + IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) { + for (i = 0; i < hw->port_num; i++) { + ipn3ke_25G_mtu_setup(hw, i, 0); + ipn3ke_25G_mtu_setup(hw, i, 1); + } + } +} + static int ipn3ke_hw_init(struct rte_afu_device *afu_dev, struct ipn3ke_hw *hw) @@ -303,6 +397,9 @@ } } + /* init mtu */ + ipn3ke_mtu_setup(hw); + ret = rte_eth_switch_domain_alloc(&hw->switch_domain_id); if (ret) IPN3KE_AFU_PMD_WARN("failed to allocate switch domain for device %d", diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h index c7b336b..6419da3 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h @@ -654,6 +654,25 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \ IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT) +/* Additional Feature Register */ +#define ADD_PHY_CTRL 0x0 +#define PHY_RESET BIT(0) +/* registers for 25G/40G mac */ +#define MAC_CONFIG 0x310 +#define MAC_RESET_MASK GENMASK(2, 0) + +#define IPN3KE_MAX_MTU 0xffff + +#define IPN3KE_25G_PHY_PMA_SLOOP 0x313 +#define IPN3KE_25G_TX_FLOW_CTRL 0x640 +#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x407 +#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x506 + +#define IPN3KE_10G_TX_PAUSE_FRAME_QUANTA 0x0042 +#define IPN3KE_10G_TX_PAUSE_FRAME_HOLDOFF 0x0043 +#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x002C +#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0x00AE + #define IPN3KE_REGISTER_WIDTH 32 /*Bits[2:0]: Configuration of TX statistics counters: