From patchwork Tue Oct 8 01:50:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60657 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 088D01BFE1; Tue, 8 Oct 2019 03:47:31 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id C0DEA1BFCD for ; Tue, 8 Oct 2019 03:47:27 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556191" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:25 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Junfeng Guo , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:07 +0800 Message-Id: <20191008015018.17086-2-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 01/12] net/ice/base: fix for adding PPPoE switch rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update VLAN protocol ID to correct value for single VXLAN scenario. Fix the missing ethertype offset for PPPoE dummy packet offset to allow matching the corresponding field. Fixes: d341bdc30290 ("net/ice/base: add support for GTP and PPPoE protocols") Signed-off-by: Dan Nowlin Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_switch.c | 16 ++++++++++------ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h index f61345a7f..548c9730a 100644 --- a/drivers/net/ice/base/ice_protocol_type.h +++ b/drivers/net/ice/base/ice_protocol_type.h @@ -118,7 +118,7 @@ enum ice_prot_id { #define ICE_MAC_OFOS_HW 1 #define ICE_MAC_IL_HW 4 #define ICE_ETYPE_OL_HW 9 -#define ICE_VLAN_OL_HW 16 +#define ICE_VLAN_OL_HW 17 #define ICE_IPV4_OFOS_HW 32 #define ICE_IPV4_IL_HW 33 #define ICE_IPV6_OFOS_HW 40 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 80afa74cd..71d7f0737 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -419,6 +419,7 @@ dummy_udp_gtp_packet[] = { static const struct ice_dummy_pkt_offsets dummy_pppoe_packet_offsets[] = { { ICE_MAC_OFOS, 0 }, + { ICE_ETYPE_OL, 12 }, { ICE_VLAN_OFOS, 14}, { ICE_PPPOE, 18 }, { ICE_PROTOCOL_LAST, 0 }, @@ -429,20 +430,23 @@ dummy_pppoe_packet[] = { 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x81, 0x00, + + 0x81, 0x00, /* ICE_ETYPE_OL 12 */ 0x00, 0x00, 0x88, 0x64, /* ICE_VLAN_OFOS 14 */ - 0x11, 0x00, 0x00, 0x01, /* ICE_PPPOE 18 */ - 0x00, 0x4e, 0x00, 0x21, + 0x11, 0x00, 0x00, 0x00, /* ICE_PPPOE 18 */ + 0x00, 0x16, + + 0x00, 0x21, /* PPP Link Layer 24 */ - 0x45, 0x00, 0x00, 0x30, /* PDU */ + 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 26 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, /* 2 bytes for 4 byte alignment */ + 0x00, 0x00, /* 2 bytes for 4 bytes alignment */ }; /* this is a recipe to profile association bitmap */ From patchwork Tue Oct 8 01:50:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60658 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1E5271BFF3; Tue, 8 Oct 2019 03:47:34 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 2BF5E1BFDC for ; Tue, 8 Oct 2019 03:47:29 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556201" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:26 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:08 +0800 Message-Id: <20191008015018.17086-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 02/12] net/ice/base: fix for NVGRE switch rule programming X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Correct for GRE/NVGRE training packets to include the correct protocol IDs for TCP and UDP respectively. Fixes: b83a0c290322 ("net/ice/base: fix inner TCP and UDP support for GRE") Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 71d7f0737..334f1b5e0 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -93,7 +93,7 @@ u8 dummy_gre_tcp_packet[] = { 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -140,7 +140,7 @@ u8 dummy_gre_udp_packet[] = { 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_IL 56 */ 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, From patchwork Tue Oct 8 01:50:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60659 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 088091C00D; Tue, 8 Oct 2019 03:47:36 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 14C9C1BFE2 for ; Tue, 8 Oct 2019 03:47:30 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556207" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:28 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:09 +0800 Message-Id: <20191008015018.17086-4-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 03/12] net/ice/base: update flow ptype bitmaps X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In the flow api, the outer first ptype bitmaps contained many references to inner ptypes. Because of PTG assignments, these were causing issues when programming rules on the inner ptypes. For example, in RSS when programming the outer IPV6 hash fields, it also programmed several inner IPV4 PTGs with the same extraction. There were several ptypes that have been removed, thus this patch removes those bits from the type bitmaps. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flow.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index e03c5d0e7..8ed3f8eb7 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -141,9 +141,9 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { * Packet types for packets with an Outer/First/Single MAC header */ static const u32 ice_ptypes_mac_ofos[] = { - 0xFDC00CC6, 0xBFBF7F7E, 0xF7EFDFDF, 0xFEFDFDFB, - 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, - 0x000B0F0F, 0x00003000, 0x00000000, 0x00000000, + 0xFDC00846, 0xBFBF7F7E, 0xF70001DF, 0xFEFDFDFB, + 0x0000077E, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00003000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -165,9 +165,9 @@ static const u32 ice_ptypes_macvlan_il[] = { /* Packet types for packets with an Outer/First/Single IPv4 header */ static const u32 ice_ptypes_ipv4_ofos[] = { - 0xFDC00000, 0xBFBF7F7E, 0x00EFDFDF, 0x00000000, + 0x1DC00000, 0x04000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0003000F, 0x000FC000, 0x00000000, 0x00000000, + 0x00000000, 0x000FC000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -189,9 +189,9 @@ static const u32 ice_ptypes_ipv4_il[] = { /* Packet types for packets with an Outer/First/Single IPv6 header */ static const u32 ice_ptypes_ipv6_ofos[] = { - 0x00000000, 0x00000000, 0xF7000000, 0xFEFDFDFB, - 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, - 0x00080F00, 0x03F00000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x77000000, 0x10002000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x03F00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -201,8 +201,8 @@ static const u32 ice_ptypes_ipv6_ofos[] = { /* Packet types for packets with an Innermost/Last IPv6 header */ static const u32 ice_ptypes_ipv6_il[] = { - 0x00000000, 0x03B80770, 0x00EE01DC, 0x0EE00000, - 0x03B80770, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x03B80770, 0x000001DC, 0x0EE00000, + 0x00000770, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x7FE00000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -228,7 +228,7 @@ static const u32 ice_ptypes_arp_of[] = { */ static const u32 ice_ptypes_udp_il[] = { 0x81000000, 0x20204040, 0x04000010, 0x80810102, - 0x00200040, 0x00000000, 0x00000000, 0x00000000, + 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00410000, 0x10842000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -240,7 +240,7 @@ static const u32 ice_ptypes_udp_il[] = { /* Packet types for packets with an Innermost/Last TCP header */ static const u32 ice_ptypes_tcp_il[] = { 0x04000000, 0x80810102, 0x10000040, 0x02040408, - 0x00810102, 0x00000000, 0x00000000, 0x00000000, + 0x00000102, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00820000, 0x21084000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -252,7 +252,7 @@ static const u32 ice_ptypes_tcp_il[] = { /* Packet types for packets with an Innermost/Last SCTP header */ static const u32 ice_ptypes_sctp_il[] = { 0x08000000, 0x01020204, 0x20000081, 0x04080810, - 0x01020204, 0x00000000, 0x00000000, 0x00000000, + 0x00000204, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -275,8 +275,8 @@ static const u32 ice_ptypes_icmp_of[] = { /* Packet types for packets with an Innermost/Last ICMP header */ static const u32 ice_ptypes_icmp_il[] = { - 0x00000000, 0x02040408, 0x40810102, 0x08101020, - 0x02040408, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x02040408, 0x40000102, 0x08101020, + 0x00000408, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x42108000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -287,8 +287,8 @@ static const u32 ice_ptypes_icmp_il[] = { /* Packet types for packets with an Outermost/First GRE header */ static const u32 ice_ptypes_gre_of[] = { - 0x00000000, 0xBFBF7800, 0x00EFDFDF, 0xFEFDE000, - 0x03BF7F7E, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0xBFBF7800, 0x000001DF, 0xFEFDE000, + 0x0000017E, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -299,8 +299,8 @@ static const u32 ice_ptypes_gre_of[] = { /* Packet types for packets with an Innermost/Last MAC header */ static const u32 ice_ptypes_mac_il[] = { - 0x00000000, 0x00000000, 0x00EFDE00, 0x00000000, - 0x03BF7800, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, From patchwork Tue Oct 8 01:50:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60660 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E95961C012; Tue, 8 Oct 2019 03:47:37 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id B6DE81BFE2 for ; Tue, 8 Oct 2019 03:47:32 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556215" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:30 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Junfeng Guo , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:10 +0800 Message-Id: <20191008015018.17086-5-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 04/12] net/ice/base: add GTPU TEID support for FD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added the training packet for GTPU TEID field to the Flow director to allow matching against this field. Signed-off-by: Junfeng Guo Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_fdir.c | 2 ++ drivers/net/ice/base/ice_fdir.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c index 219588c46..37b388169 100644 --- a/drivers/net/ice/base/ice_fdir.c +++ b/drivers/net/ice/base/ice_fdir.c @@ -786,6 +786,8 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input, case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP: case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER: + ice_pkt_insert_u32(loc, ICE_IPV4_GTPU_TEID_OFFSET, + input->gtpu_data.teid); ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET, input->gtpu_data.qfi); break; diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 22e5bcf8c..db1f8351f 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -87,6 +87,7 @@ enum ice_status ice_clear_pf_fd_table(struct ice_hw *hw); #define ICE_IPV6_TC_OFFSET 14 #define ICE_IPV6_HLIM_OFFSET 21 #define ICE_IPV6_PROTO_OFFSET 20 +#define ICE_IPV4_GTPU_TEID_OFFSET 46 #define ICE_IPV4_GTPU_QFI_OFFSET 56 #define ICE_FDIR_MAX_FLTRS 16384 From patchwork Tue Oct 8 01:50:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60661 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B061F1C025; Tue, 8 Oct 2019 03:47:39 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id DDFDB1BFFB for ; Tue, 8 Oct 2019 03:47:34 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556228" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:32 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:11 +0800 Message-Id: <20191008015018.17086-6-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 05/12] net/ice/base: improvements to Flow Director masking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Currently, 3-tuple FD matching is implemented using masking. However, this is using up twenty-four of the thirty-two FD masks available. This patch uses the swap register more efficiently to implement the 3-tuple matches, which saves all FD masks for other uses. Added IPV6 versions of DSCP, TTL and Protocol fields for FD use. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flex_pipe.c | 71 +++++++++------------ drivers/net/ice/base/ice_flex_type.h | 4 +- drivers/net/ice/base/ice_flow.c | 118 ++++++++++++++++++++--------------- drivers/net/ice/base/ice_flow.h | 10 ++- 4 files changed, 108 insertions(+), 95 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 75bb87079..8f8cab86e 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1248,25 +1248,6 @@ void ice_free_seg(struct ice_hw *hw) } /** - * ice_init_fd_mask_regs - initialize Flow Director mask registers - * @hw: pointer to the HW struct - * - * This function sets up the Flow Director mask registers to allow for complete - * masking off of any of the 24 Field Vector words. After this call, mask 0 will - * mask off all of FV index 0, mask 1 will mask off all of FV index 1, etc. - */ -static void ice_init_fd_mask_regs(struct ice_hw *hw) -{ - u16 i; - - for (i = 0; i < hw->blk[ICE_BLK_FD].es.fvw; i++) { - wr32(hw, GLQF_FDMASK(i), i); - ice_debug(hw, ICE_DBG_INIT, "init fd mask(%d): %x = %x\n", i, - GLQF_FDMASK(i), i); - } -} - -/** * ice_init_pkg_regs - initialize additional package registers * @hw: pointer to the hardware structure */ @@ -1279,8 +1260,6 @@ static void ice_init_pkg_regs(struct ice_hw *hw) /* setup Switch block input mask, which is 48-bits in two parts */ wr32(hw, GL_PREEXT_L2_PMASK0(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_L); wr32(hw, GL_PREEXT_L2_PMASK1(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_H); - /* setup default flow director masks */ - ice_init_fd_mask_regs(hw); } /** @@ -2643,7 +2622,8 @@ ice_prof_has_mask_idx(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 idx, expect_no_mask = true; /* Scan the enabled masks on this profile, for the specified idx */ - for (i = 0; i < ICE_PROFILE_MASK_COUNT; i++) + for (i = hw->blk[blk].masks.first; i < hw->blk[blk].masks.first + + hw->blk[blk].masks.count; i++) if (hw->blk[blk].es.mask_ena[prof] & BIT(i)) if (hw->blk[blk].masks.masks[i].in_use && hw->blk[blk].masks.masks[i].idx == idx) { @@ -2981,14 +2961,15 @@ ice_write_prof_mask_enable_res(struct ice_hw *hw, enum ice_block blk, */ static void ice_init_prof_masks(struct ice_hw *hw, enum ice_block blk) { -#define MAX_NUM_PORTS 8 - u16 num_ports = MAX_NUM_PORTS; + u16 per_pf; u16 i; ice_init_lock(&hw->blk[blk].masks.lock); - hw->blk[blk].masks.count = ICE_PROFILE_MASK_COUNT / num_ports; - hw->blk[blk].masks.first = hw->pf_id * hw->blk[blk].masks.count; + per_pf = ICE_PROF_MASK_COUNT / hw->dev_caps.num_funcs; + + hw->blk[blk].masks.count = per_pf; + hw->blk[blk].masks.first = hw->pf_id * per_pf; ice_memset(hw->blk[blk].masks.masks, 0, sizeof(hw->blk[blk].masks.masks), ICE_NONDMA_MEM); @@ -4241,8 +4222,6 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) ice_zero_bitmap(pair_list, ICE_FD_SRC_DST_PAIR_COUNT); - ice_init_fd_mask_regs(hw); - /* This code assumes that the Flow Director field vectors are assigned * from the end of the FV indexes working towards the zero index, that * only complete fields will be included and will be consecutive, and @@ -4298,7 +4277,7 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) return ICE_ERR_OUT_OF_RANGE; /* keep track of non-relevant fields */ - mask_sel |= 1 << (first_free - k); + mask_sel |= BIT(first_free - k); } pair_start[index] = first_free; @@ -4342,29 +4321,39 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) si -= indexes_used; } - /* for each set of 4 swap indexes, write the appropriate register */ + /* for each set of 4 swap and 4 inset indexes, write the appropriate + * register + */ for (j = 0; j < hw->blk[ICE_BLK_FD].es.fvw / 4; j++) { - u32 raw_entry = 0; + u32 raw_swap = 0; + u32 raw_in = 0; for (k = 0; k < 4; k++) { u8 idx; idx = (j * 4) + k; - if (used[idx]) - raw_entry |= used[idx] << (k * BITS_PER_BYTE); + if (used[idx] && !(mask_sel & BIT(idx))) { + raw_swap |= used[idx] << (k * BITS_PER_BYTE); +#define ICE_INSET_DFLT 0x9f + raw_in |= ICE_INSET_DFLT << (k * BITS_PER_BYTE); + } } - /* write the appropriate register set, based on HW block */ - wr32(hw, GLQF_FDSWAP(prof_id, j), raw_entry); + /* write the appropriate swap register set */ + wr32(hw, GLQF_FDSWAP(prof_id, j), raw_swap); + + ice_debug(hw, ICE_DBG_INIT, "swap wr(%d, %d): %x = %08x\n", + prof_id, j, GLQF_FDSWAP(prof_id, j), raw_swap); - ice_debug(hw, ICE_DBG_INIT, "swap wr(%d, %d): %x = %x\n", - prof_id, j, GLQF_FDSWAP(prof_id, j), raw_entry); + /* write the appropriate inset register set */ + wr32(hw, GLQF_FDINSET(prof_id, j), raw_in); + + ice_debug(hw, ICE_DBG_INIT, "inset wr(%d, %d): %x = %08x\n", + prof_id, j, GLQF_FDINSET(prof_id, j), raw_in); } - /* update the masks for this profile to be sure we ignore fields that - * are not relevant to our match criteria - */ - ice_update_fd_mask(hw, prof_id, mask_sel); + /* initially clear the mask select for this profile */ + ice_update_fd_mask(hw, prof_id, 0); return ICE_SUCCESS; } diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 48c1e5184..92d205ac7 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -668,8 +668,8 @@ struct ice_masks { struct ice_lock lock; /* lock to protect this structure */ u16 first; /* first mask owned by the PF */ u16 count; /* number of masks owned by the PF */ -#define ICE_PROFILE_MASK_COUNT 32 - struct ice_mask masks[ICE_PROFILE_MASK_COUNT]; +#define ICE_PROF_MASK_COUNT 32 + struct ice_mask masks[ICE_PROF_MASK_COUNT]; }; /* Tables per block */ diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 8ed3f8eb7..370ad9ba3 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -22,15 +22,6 @@ #define ICE_FLOW_FLD_SZ_GTP_TEID 4 #define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2 -/* Protocol header fields are extracted at the word boundaries as word-sized - * values. Specify the displacement value of some non-word-aligned fields needed - * to compute the offset of words containing the fields in the corresponding - * protocol headers. Displacement values are expressed in number of bits. - */ -#define ICE_FLOW_FLD_IPV6_TTL_DSCP_DISP (-4) -#define ICE_FLOW_FLD_IPV6_TTL_PROT_DISP ((-2) * BITS_PER_BYTE) -#define ICE_FLOW_FLD_IPV6_TTL_TTL_DISP ((-1) * BITS_PER_BYTE) - /* Describe properties of a protocol header field */ struct ice_flow_field_info { enum ice_flow_seg_hdr hdr; @@ -67,18 +58,29 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_VLAN, 14, ICE_FLOW_FLD_SZ_VLAN), /* ICE_FLOW_FIELD_IDX_ETH_TYPE */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_ETH, 12, ICE_FLOW_FLD_SZ_ETH_TYPE), - /* IPv4 */ - /* ICE_FLOW_FIELD_IDX_IP_DSCP */ - ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 1, 1), - /* ICE_FLOW_FIELD_IDX_IP_TTL */ - ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NONE, 8, 1), - /* ICE_FLOW_FIELD_IDX_IP_PROT */ - ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_NONE, 9, ICE_FLOW_FLD_SZ_IP_PROT), + /* IPv4 / IPv6 */ + /* ICE_FLOW_FIELD_IDX_IPV4_DSCP */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_IPV4, 0, ICE_FLOW_FLD_SZ_IP_DSCP, + 0x00fc), + /* ICE_FLOW_FIELD_IDX_IPV6_DSCP */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_IPV6, 0, ICE_FLOW_FLD_SZ_IP_DSCP, + 0x0ff0), + /* ICE_FLOW_FIELD_IDX_IPV4_TTL */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 8, + ICE_FLOW_FLD_SZ_IP_TTL, 0xff00), + /* ICE_FLOW_FIELD_IDX_IPV4_PROT */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 8, + ICE_FLOW_FLD_SZ_IP_PROT, 0x00ff), + /* ICE_FLOW_FIELD_IDX_IPV6_TTL */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 6, + ICE_FLOW_FLD_SZ_IP_TTL, 0x00ff), + /* ICE_FLOW_FIELD_IDX_IPV6_PROT */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_NONE, 6, + ICE_FLOW_FLD_SZ_IP_PROT, 0xff00), /* ICE_FLOW_FIELD_IDX_IPV4_SA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 12, ICE_FLOW_FLD_SZ_IPV4_ADDR), /* ICE_FLOW_FIELD_IDX_IPV4_DA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV4, 16, ICE_FLOW_FLD_SZ_IPV4_ADDR), - /* IPv6 */ /* ICE_FLOW_FIELD_IDX_IPV6_SA */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_IPV6, 8, ICE_FLOW_FLD_SZ_IPV6_ADDR), /* ICE_FLOW_FIELD_IDX_IPV6_DA */ @@ -608,6 +610,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw, * @params: information about the flow to be processed * @seg: packet segment index of the field to be extracted * @fld: ID of field to be extracted + * @match: bitfield of all fields * * This function determines the protocol ID, offset, and size of the given * field. It then allocates one or more extraction sequence entries for the @@ -615,13 +618,14 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw, */ static enum ice_status ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, - u8 seg, enum ice_flow_field fld) + u8 seg, enum ice_flow_field fld, u64 match) { enum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX; enum ice_prot_id prot_id = ICE_PROT_ID_INVAL; u8 fv_words = hw->blk[params->blk].es.fvw; struct ice_flow_fld_info *flds; u16 cnt, ese_bits, i; + u16 sib_mask = 0; s16 adj = 0; u16 mask; u16 off; @@ -638,35 +642,49 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_ETH_TYPE: prot_id = seg == 0 ? ICE_PROT_ETYPE_OL : ICE_PROT_ETYPE_IL; break; - case ICE_FLOW_FIELD_IDX_IP_DSCP: - if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV6) - adj = ICE_FLOW_FLD_IPV6_TTL_DSCP_DISP; - /* Fall through */ - case ICE_FLOW_FIELD_IDX_IP_TTL: - case ICE_FLOW_FIELD_IDX_IP_PROT: - /* Some fields are located at different offsets in IPv4 and - * IPv6 + case ICE_FLOW_FIELD_IDX_IPV4_DSCP: + prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL; + break; + case ICE_FLOW_FIELD_IDX_IPV6_DSCP: + prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL; + break; + case ICE_FLOW_FIELD_IDX_IPV4_TTL: + case ICE_FLOW_FIELD_IDX_IPV4_PROT: + prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL; + + /* TTL and PROT share the same extraction seq. entry. + * Each is considered a sibling to the other in terms of sharing + * the same extraction sequence entry. */ - if (params->prof->segs[seg].hdrs & ICE_FLOW_SEG_HDR_IPV4) { - prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : - ICE_PROT_IPV4_IL; - /* TTL and PROT share the same extraction seq. entry. - * Each is considered a sibling to the other in term - * sharing the same extraction sequence entry. - */ - if (fld == ICE_FLOW_FIELD_IDX_IP_TTL) - sib = ICE_FLOW_FIELD_IDX_IP_PROT; - else if (fld == ICE_FLOW_FIELD_IDX_IP_PROT) - sib = ICE_FLOW_FIELD_IDX_IP_TTL; - } else if (params->prof->segs[seg].hdrs & - ICE_FLOW_SEG_HDR_IPV6) { - prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : - ICE_PROT_IPV6_IL; - if (fld == ICE_FLOW_FIELD_IDX_IP_TTL) - adj = ICE_FLOW_FLD_IPV6_TTL_TTL_DISP; - else if (fld == ICE_FLOW_FIELD_IDX_IP_PROT) - adj = ICE_FLOW_FLD_IPV6_TTL_PROT_DISP; - } + if (fld == ICE_FLOW_FIELD_IDX_IPV4_TTL) + sib = ICE_FLOW_FIELD_IDX_IPV4_PROT; + else if (fld == ICE_FLOW_FIELD_IDX_IPV4_PROT) + sib = ICE_FLOW_FIELD_IDX_IPV4_TTL; + + /* If the sibling field is also included, that field's + * mask needs to be included. + */ + if (match & BIT(sib)) + sib_mask = ice_flds_info[sib].mask; + break; + case ICE_FLOW_FIELD_IDX_IPV6_TTL: + case ICE_FLOW_FIELD_IDX_IPV6_PROT: + prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL; + + /* TTL and PROT share the same extraction seq. entry. + * Each is considered a sibling to the other in terms of sharing + * the same extraction sequence entry. + */ + if (fld == ICE_FLOW_FIELD_IDX_IPV6_TTL) + sib = ICE_FLOW_FIELD_IDX_IPV6_PROT; + else if (fld == ICE_FLOW_FIELD_IDX_IPV6_PROT) + sib = ICE_FLOW_FIELD_IDX_IPV6_TTL; + + /* If the sibling field is also included, that field's + * mask needs to be included. + */ + if (match & BIT(sib)) + sib_mask = ice_flds_info[sib].mask; break; case ICE_FLOW_FIELD_IDX_IPV4_SA: case ICE_FLOW_FIELD_IDX_IPV4_DA: @@ -733,6 +751,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, ICE_FLOW_FV_EXTRACT_SZ; flds[fld].xtrct.disp = (u8)((ice_flds_info[fld].off + adj) % ese_bits); flds[fld].xtrct.idx = params->es_cnt; + flds[fld].xtrct.mask = ice_flds_info[fld].mask; /* Adjust the next field-entry index after accommodating the number of * entries this field consumes @@ -742,7 +761,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, /* Fill in the extraction sequence entries needed for this field */ off = flds[fld].xtrct.off; - mask = ice_flds_info[fld].mask; + mask = flds[fld].xtrct.mask; for (i = 0; i < cnt; i++) { /* Only consume an extraction sequence entry if there is no * sibling field associated with this field or the sibling entry @@ -767,7 +786,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, params->es[idx].prot_id = prot_id; params->es[idx].off = off; - params->mask[idx] = mask; + params->mask[idx] = mask | sib_mask; params->es_cnt++; } @@ -885,7 +904,8 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw, if (match & bit) { status = ice_flow_xtract_fld - (hw, params, i, (enum ice_flow_field)j); + (hw, params, i, (enum ice_flow_field)j, + match); if (status) return status; match &= ~bit; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index 326ff6f81..c224e6ebf 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -114,9 +114,12 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_C_VLAN, ICE_FLOW_FIELD_IDX_ETH_TYPE, /* L3 */ - ICE_FLOW_FIELD_IDX_IP_DSCP, - ICE_FLOW_FIELD_IDX_IP_TTL, - ICE_FLOW_FIELD_IDX_IP_PROT, + ICE_FLOW_FIELD_IDX_IPV4_DSCP, + ICE_FLOW_FIELD_IDX_IPV6_DSCP, + ICE_FLOW_FIELD_IDX_IPV4_TTL, + ICE_FLOW_FIELD_IDX_IPV4_PROT, + ICE_FLOW_FIELD_IDX_IPV6_TTL, + ICE_FLOW_FIELD_IDX_IPV6_PROT, ICE_FLOW_FIELD_IDX_IPV4_SA, ICE_FLOW_FIELD_IDX_IPV4_DA, ICE_FLOW_FIELD_IDX_IPV6_SA, @@ -232,6 +235,7 @@ struct ice_flow_seg_xtrct { u16 off; /* Starting offset of the field in header in bytes */ u8 idx; /* Index of FV entry used */ u8 disp; /* Displacement of field in bits fr. FV entry's start */ + u16 mask; /* Mask for field */ }; enum ice_flow_fld_match_type { From patchwork Tue Oct 8 01:50:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60662 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2455B1C06A; Tue, 8 Oct 2019 03:47:42 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id A65751C00F for ; Tue, 8 Oct 2019 03:47:36 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556231" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:34 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jeb Cramer , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:12 +0800 Message-Id: <20191008015018.17086-7-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 06/12] net/ice/base: remove dead error condition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The pointer cmd is set to an address of a structure, which can never be NULL. Remove the check-for-NULL lines since it's dead code anyway. Signed-off-by: Jeb Cramer Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 48ba160f7..4ba3ab202 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -176,9 +176,6 @@ ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, cmd = &desc.params.get_link_topo; - if (!cmd) - return ICE_ERR_PARAM; - ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << From patchwork Tue Oct 8 01:50:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60663 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0230E1C0AF; Tue, 8 Oct 2019 03:47:44 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 8597B1C01F for ; Tue, 8 Oct 2019 03:47:38 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556236" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:36 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Jeb Cramer , Jesse Brandeburg , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:13 +0800 Message-Id: <20191008015018.17086-8-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 07/12] net/ice/base: zero initialize structures X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some functions create ice_pkg_enum structure, but it seems it's possible some of the members are used un-initialized. So we'll initialize all instantiations of this structure within ice_flex_pipe.c The patch also fix header comment mismatch issue for ice_init_prof_result_bm Signed-off-by: Jeb Cramer Signed-off-by: Jesse Brandeburg Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flex_pipe.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index 8f8cab86e..bf14149b8 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -470,6 +470,7 @@ static void ice_init_pkg_hints(struct ice_hw *hw, struct ice_seg *ice_seg) int i; ice_memset(&hw->tnl, 0, sizeof(hw->tnl), ICE_NONDMA_MEM); + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); if (!ice_seg) return; @@ -1517,6 +1518,8 @@ ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type, struct ice_seg *ice_seg; struct ice_fv *fv; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + if (type == ICE_PROF_ALL) { u16 i; @@ -1573,6 +1576,8 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt, struct ice_fv *fv; u32 offset; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + if (!ids_cnt || !hw->seg) return ICE_ERR_PARAM; @@ -1633,16 +1638,17 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt, } /** - * ice_init_profile_to_result_bm - Initialize the profile result index bitmap + * ice_init_prof_result_bm - Initialize the profile result index bitmap * @hw: pointer to hardware structure */ -void -ice_init_prof_result_bm(struct ice_hw *hw) +void ice_init_prof_result_bm(struct ice_hw *hw) { struct ice_pkg_enum state; struct ice_seg *ice_seg; struct ice_fv *fv; + ice_memset(&state, 0, sizeof(state), ICE_NONDMA_MEM); + if (!hw->seg) return; From patchwork Tue Oct 8 01:50:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60664 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E96FA1C0BC; Tue, 8 Oct 2019 03:47:45 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 124971C02D for ; Tue, 8 Oct 2019 03:47:39 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556241" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:38 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:14 +0800 Message-Id: <20191008015018.17086-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 08/12] net/ice/base: fix unexpected switch rule overwrite X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A switch rule with "drop" action will be overwritten by a rule with same pattern match but with a "to queue" action. While in an inversed flow creation sequence, the "to queue" can't be overwritten by the "drop" rule. The inconsistent behavior is not expected, the patch fix the issue by preventing rule overwrite in both cases. Fixes: fed0c5ca5f19 ("net/ice/base: support programming a new switch recipe") Signed-off-by: Qi Zhang Signed-off-by: Paul M Stillwell Jr Acked-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 334f1b5e0..2c02021b1 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -5977,13 +5977,10 @@ ice_adv_add_update_vsi_list(struct ice_hw *hw, u16 vsi_list_id = 0; if (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_Q || - cur_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP) + cur_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP || + cur_fltr->sw_act.fltr_act == ICE_DROP_PACKET) return ICE_ERR_NOT_IMPL; - if (cur_fltr->sw_act.fltr_act == ICE_DROP_PACKET && - new_fltr->sw_act.fltr_act == ICE_DROP_PACKET) - return ICE_ERR_ALREADY_EXISTS; - if ((new_fltr->sw_act.fltr_act == ICE_FWD_TO_Q || new_fltr->sw_act.fltr_act == ICE_FWD_TO_QGRP) && (cur_fltr->sw_act.fltr_act == ICE_FWD_TO_VSI || From patchwork Tue Oct 8 01:50:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60665 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6310E1C0CB; Tue, 8 Oct 2019 03:47:47 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id C1F721C038 for ; Tue, 8 Oct 2019 03:47:41 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556249" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:39 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:15 +0800 Message-Id: <20191008015018.17086-10-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 09/12] net/ice/base: fix flow raw field vector extraction X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Correct the ordering of raw field extraction in the field vector by taking into account the ordering setting for requesting block. Fixes: aa1cd410fa64 ("net/ice/base: add flow module") Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flow.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 370ad9ba3..38c7c42f7 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -806,6 +806,7 @@ static enum ice_status ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params, u8 seg) { + u16 fv_words; u16 hdrs_sz; u8 i; @@ -821,6 +822,8 @@ ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params, if (!hdrs_sz) return ICE_ERR_PARAM; + fv_words = hw->blk[params->blk].es.fvw; + for (i = 0; i < params->prof->segs[seg].raws_cnt; i++) { struct ice_flow_seg_fld_raw *raw; u16 off, cnt, j; @@ -853,6 +856,8 @@ ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params, BITS_PER_BYTE)); off = raw->info.xtrct.off; for (j = 0; j < cnt; j++) { + u16 idx; + /* Make sure the number of extraction sequence required * does not exceed the block's capability */ @@ -860,8 +865,14 @@ ice_flow_xtract_raws(struct ice_hw *hw, struct ice_flow_prof_params *params, params->es_cnt >= ICE_MAX_FV_WORDS) return ICE_ERR_MAX_LIMIT; - params->es[params->es_cnt].prot_id = ICE_PROT_PAY; - params->es[params->es_cnt].off = off; + /* some blocks require a reversed field vector layout */ + if (hw->blk[params->blk].es.reverse) + idx = fv_words - params->es_cnt - 1; + else + idx = params->es_cnt; + + params->es[idx].prot_id = ICE_PROT_PAY; + params->es[idx].off = off; params->es_cnt++; off += ICE_FLOW_FV_EXTRACT_SZ; } From patchwork Tue Oct 8 01:50:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60666 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A93591C0D3; Tue, 8 Oct 2019 03:47:49 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 9C50B1C00F for ; Tue, 8 Oct 2019 03:47:43 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556257" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:41 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:16 +0800 Message-Id: <20191008015018.17086-11-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 10/12] net/ice/base: fix switch rule programming for all profiles X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In switch rule programming, if the caller requested tunnel type of ICE_SW_TUN_AND_NON_TUN, then the code would incorrectly attempt to add a tunneled UDP port in the training packet, this would cause the rule addition to fail. This patch does not attempt to add the UDP port so that the rule programming will succeed. Fixes: 75c06a770e25 ("net/ice/base: update switch training packets with open ports") Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_switch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 2c02021b1..36da27f78 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -6214,7 +6214,8 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups, if (status) goto err_ice_add_adv_rule; - if (rinfo->tun_type != ICE_NON_TUN) { + if (rinfo->tun_type != ICE_NON_TUN && + rinfo->tun_type != ICE_SW_TUN_AND_NON_TUN) { status = ice_fill_adv_packet_tun(hw, rinfo->tun_type, s_rule->pdata.lkup_tx_rx.hdr, pkt_offsets); From patchwork Tue Oct 8 01:50:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60667 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7BC251C113; Tue, 8 Oct 2019 03:47:51 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id F3ABE1C0BD for ; Tue, 8 Oct 2019 03:47:45 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556262" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:43 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Dan Nowlin , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:17 +0800 Message-Id: <20191008015018.17086-12-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 11/12] net/ice/base: add QFI for Flow Director X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added the GTP QFI field to the Flow director interface to allow matching against this field. Since this field only appears in GTP packets with extension headers, this also requires adding profile TCAM mask matching capability. This allows comprehending different PTYPE attributes by examining flags from the parser. Using this method, different profiles can be used by examining flag values from the parser. Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Signed-off-by: Dan Nowlin Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flex_pipe.c | 245 ++++++++++++++--------------------- drivers/net/ice/base/ice_flex_pipe.h | 6 +- drivers/net/ice/base/ice_flex_type.h | 66 ++++++++++ drivers/net/ice/base/ice_flow.c | 57 +++++++- drivers/net/ice/base/ice_flow.h | 24 +++- 5 files changed, 238 insertions(+), 160 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index bf14149b8..c2af1dfe8 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -2692,34 +2692,7 @@ ice_find_prof_id_with_mask(struct ice_hw *hw, enum ice_block blk, continue; /* check if masks settings are the same for this profile */ - if (!ice_prof_has_mask(hw, blk, i, masks)) - continue; - - *prof_id = i; - return ICE_SUCCESS; - } - - return ICE_ERR_DOES_NOT_EXIST; -} - -/** - * ice_find_prof_id - find profile ID for a given field vector - * @hw: pointer to the hardware structure - * @blk: HW block - * @fv: field vector to search for - * @prof_id: receives the profile ID - */ -static enum ice_status -ice_find_prof_id(struct ice_hw *hw, enum ice_block blk, - struct ice_fv_word *fv, u8 *prof_id) -{ - struct ice_es *es = &hw->blk[blk].es; - u16 off, i; - - for (i = 0; i < es->count; i++) { - off = i * es->fvw; - - if (memcmp(&es->t[off], fv, es->fvw * sizeof(*fv))) + if (masks && !ice_prof_has_mask(hw, blk, i, masks)) continue; *prof_id = i; @@ -4364,127 +4337,58 @@ ice_update_fd_swap(struct ice_hw *hw, u16 prof_id, struct ice_fv_word *es) return ICE_SUCCESS; } +/* The entries here needs to match the order of enum ice_ptype_attrib */ +static const struct ice_ptype_attrib_info ice_ptype_attributes[] = { + { ICE_GTP_PDU_EH, ICE_GTP_PDU_FLAG_MASK }, + { ICE_GTP_SESSION, ICE_GTP_FLAGS_MASK }, + { ICE_GTP_DOWNLINK, ICE_GTP_FLAGS_MASK }, + { ICE_GTP_UPLINK, ICE_GTP_FLAGS_MASK }, +}; + /** - * ice_add_prof_with_mask - add profile - * @hw: pointer to the HW struct - * @blk: hardware block - * @id: profile tracking ID - * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits) - * @es: extraction sequence (length of array is determined by the block) - * @masks: extraction sequence (length of array is determined by the block) - * - * This function registers a profile, which matches a set of PTYPES with a - * particular extraction sequence. While the hardware profile is allocated - * it will not be written until the first call to ice_add_flow that specifies - * the ID value used here. + * ice_get_ptype_attrib_info - get ptype attribute information + * @type: attribute type + * @info: pointer to variable to the attribute information */ -enum ice_status -ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id, - u8 ptypes[], struct ice_fv_word *es, u16 *masks) +static void +ice_get_ptype_attrib_info(enum ice_ptype_attrib_type type, + struct ice_ptype_attrib_info *info) { - u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE); - ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT); - struct ice_prof_map *prof; - enum ice_status status; - u32 byte = 0; - u8 prof_id; - - ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT); - - ice_acquire_lock(&hw->blk[blk].es.prof_map_lock); - - /* search for existing profile */ - status = ice_find_prof_id_with_mask(hw, blk, es, masks, &prof_id); - if (status) { - /* allocate profile ID */ - status = ice_alloc_prof_id(hw, blk, &prof_id); - if (status) - goto err_ice_add_prof; - if (blk == ICE_BLK_FD) { - /* For Flow Director block, the extraction sequence may - * need to be altered in the case where there are paired - * fields that have no match. This is necessary because - * for Flow Director, src and dest fields need to paired - * for filter programming and these values are swapped - * during Tx. - */ - status = ice_update_fd_swap(hw, prof_id, es); - if (status) - goto err_ice_add_prof; - } - status = ice_update_prof_masking(hw, blk, prof_id, es, masks); - if (status) - goto err_ice_add_prof; - - /* and write new es */ - ice_write_es(hw, blk, prof_id, es); - } - - ice_prof_inc_ref(hw, blk, prof_id); - - /* add profile info */ - - prof = (struct ice_prof_map *)ice_malloc(hw, sizeof(*prof)); - if (!prof) - goto err_ice_add_prof; - - prof->profile_cookie = id; - prof->prof_id = prof_id; - prof->ptg_cnt = 0; - prof->context = 0; - - /* build list of ptgs */ - while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) { - u32 bit; - - if (!ptypes[byte]) { - bytes--; - byte++; - continue; - } - /* Examine 8 bits per byte */ - for (bit = 0; bit < 8; bit++) { - if (ptypes[byte] & BIT(bit)) { - u16 ptype; - u8 ptg; - u8 m; - - ptype = byte * BITS_PER_BYTE + bit; - - /* The package should place all ptypes in a - * non-zero PTG, so the following call should - * never fail. - */ - if (ice_ptg_find_ptype(hw, blk, ptype, &ptg)) - continue; + *info = ice_ptype_attributes[type]; +} - /* If PTG is already added, skip and continue */ - if (ice_is_bit_set(ptgs_used, ptg)) - continue; +/** + * ice_add_prof_attrib - add any ptg with attributes to profile + * @prof: pointer to the profile to which ptg entries will be added + * @ptg: PTG to be added + * @ptype: PTYPE that needs to be looked up + * @attr: array of attributes that will be considered + * @attr_cnt: number of elements in the attribute array + */ +static enum ice_status +ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg, u16 ptype, + const struct ice_ptype_attributes *attr, u16 attr_cnt) +{ + bool found = false; + u16 i; - ice_set_bit(ptg, ptgs_used); - prof->ptg[prof->ptg_cnt] = ptg; + for (i = 0; i < attr_cnt; i++) { + if (attr[i].ptype == ptype) { + found = true; - if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE) - break; + prof->ptg[prof->ptg_cnt] = ptg; + ice_get_ptype_attrib_info(attr[i].attrib, + &prof->attr[prof->ptg_cnt]); - /* nothing left in byte, then exit */ - m = ~((1 << (bit + 1)) - 1); - if (!(ptypes[byte] & m)) - break; - } + if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE) + return ICE_ERR_MAX_LIMIT; } - - bytes--; - byte++; } - LIST_ADD(&prof->list, &hw->blk[blk].es.prof_map); - status = ICE_SUCCESS; + if (!found) + return ICE_ERR_DOES_NOT_EXIST; -err_ice_add_prof: - ice_release_lock(&hw->blk[blk].es.prof_map_lock); - return status; + return ICE_SUCCESS; } /** @@ -4493,16 +4397,20 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id, * @blk: hardware block * @id: profile tracking ID * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits) + * @attr: array of attributes + * @attr_cnt: number of elements in attrib array * @es: extraction sequence (length of array is determined by the block) + * @masks: mask for extraction sequence * - * This function registers a profile, which matches a set of PTGs with a + * This function registers a profile, which matches a set of PTYPES with a * particular extraction sequence. While the hardware profile is allocated * it will not be written until the first call to ice_add_flow that specifies * the ID value used here. */ enum ice_status ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], - struct ice_fv_word *es) + const struct ice_ptype_attributes *attr, u16 attr_cnt, + struct ice_fv_word *es, u16 *masks) { u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE); ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT); @@ -4516,7 +4424,7 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], ice_acquire_lock(&hw->blk[blk].es.prof_map_lock); /* search for existing profile */ - status = ice_find_prof_id(hw, blk, es, &prof_id); + status = ice_find_prof_id_with_mask(hw, blk, es, masks, &prof_id); if (status) { /* allocate profile ID */ status = ice_alloc_prof_id(hw, blk, &prof_id); @@ -4534,6 +4442,9 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], if (status) goto err_ice_add_prof; } + status = ice_update_prof_masking(hw, blk, prof_id, es, masks); + if (status) + goto err_ice_add_prof; /* and write new es */ ice_write_es(hw, blk, prof_id, es); @@ -4582,10 +4493,25 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], continue; ice_set_bit(ptg, ptgs_used); - prof->ptg[prof->ptg_cnt] = ptg; - - if (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE) + /* Check to see there are any attributes for + * this ptype, and add them if found. + */ + status = ice_add_prof_attrib(prof, ptg, ptype, + attr, attr_cnt); + if (status == ICE_ERR_MAX_LIMIT) break; + if (status) { + /* This is simple a ptype/ptg with no + * attribute + */ + prof->ptg[prof->ptg_cnt] = ptg; + prof->attr[prof->ptg_cnt].flags = 0; + prof->attr[prof->ptg_cnt].mask = 0; + + if (++prof->ptg_cnt >= + ICE_MAX_PTG_PER_PROFILE) + break; + } /* nothing left in byte, then exit */ m = ~((1 << (bit + 1)) - 1); @@ -4928,6 +4854,7 @@ ice_get_prof(struct ice_hw *hw, enum ice_block blk, u64 hdl, p->type = ICE_PTG_ES_ADD; p->ptype = 0; p->ptg = map->ptg[i]; + p->attr = map->attr[i]; p->add_ptg = 0; p->add_prof = 1; @@ -5017,6 +4944,7 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk, p->tcam[i].prof_id = map->prof_id; p->tcam[i].tcam_idx = ICE_INVALID_TCAM; p->tcam[i].ptg = map->ptg[i]; + p->tcam[i].attr = map->attr[i]; } LIST_ADD(&p->list, lst); @@ -5064,6 +4992,19 @@ ice_move_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig, } /** + * ice_set_tcam_flags - set tcam flag don't care mask + * @mask: mask for flags + * @dc_mask: pointer to the don't care mask + */ +static void ice_set_tcam_flags(u16 mask, u8 dc_mask[ICE_TCAM_KEY_VAL_SZ]) +{ + u16 *flag_word; + + /* flags are lowest u16 */ + flag_word = (u16 *)dc_mask; + *flag_word = ~mask; +} +/** * ice_prof_tcam_ena_dis - add enable or disable TCAM change * @hw: pointer to the HW struct * @blk: hardware block @@ -5105,9 +5046,12 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable, if (!p) return ICE_ERR_NO_MEMORY; + /* set don't care masks for tcam flags */ + ice_set_tcam_flags(tcam->attr.mask, dc_msk); + status = ice_tcam_write_entry(hw, blk, tcam->tcam_idx, tcam->prof_id, - tcam->ptg, vsig, 0, 0, vl_msk, dc_msk, - nm_msk); + tcam->ptg, vsig, 0, tcam->attr.flags, + vl_msk, dc_msk, nm_msk); if (status) goto err_ice_prof_tcam_ena_dis; @@ -5258,6 +5202,7 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl, t->tcam[i].ptg = map->ptg[i]; t->tcam[i].prof_id = map->prof_id; t->tcam[i].tcam_idx = tcam_idx; + t->tcam[i].attr = map->attr[i]; t->tcam[i].in_use = true; p->type = ICE_TCAM_ADD; @@ -5267,11 +5212,15 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl, p->vsig = vsig; p->tcam_idx = t->tcam[i].tcam_idx; + /* set don't care masks for tcam flags */ + ice_set_tcam_flags(t->tcam[i].attr.mask, dc_msk); + /* write the TCAM entry */ status = ice_tcam_write_entry(hw, blk, t->tcam[i].tcam_idx, t->tcam[i].prof_id, - t->tcam[i].ptg, vsig, 0, 0, - vl_msk, dc_msk, nm_msk); + t->tcam[i].ptg, vsig, 0, + t->tcam[i].attr.flags, vl_msk, + dc_msk, nm_msk); if (status) goto err_ice_add_prof_id_vsig; diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index e7d42e3de..b24a09b4d 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -52,11 +52,9 @@ ice_tunnel_get_type(struct ice_hw *hw, u16 port, enum ice_tunnel_type *type); enum ice_status ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig); enum ice_status -ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id, - u8 ptypes[], struct ice_fv_word *es, u16 *masks); -enum ice_status ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[], - struct ice_fv_word *es); + const struct ice_ptype_attributes *attr, u16 attr_cnt, + struct ice_fv_word *es, u16 *masks); void ice_init_all_prof_masks(struct ice_hw *hw); void ice_shutdown_all_prof_masks(struct ice_hw *hw); struct ice_prof_map * diff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h index 92d205ac7..1be98ea52 100644 --- a/drivers/net/ice/base/ice_flex_type.h +++ b/drivers/net/ice/base/ice_flex_type.h @@ -278,6 +278,69 @@ enum ice_sect { #define ICE_PTYPE_IPV6_TCP_PAY 92 #define ICE_PTYPE_IPV6_SCTP_PAY 93 #define ICE_PTYPE_IPV6_ICMP_PAY 94 +#define ICE_MAC_IPV4_GTPC_TEID 325 +#define ICE_MAC_IPV6_GTPC_TEID 326 +#define ICE_MAC_IPV4_GTPC 327 +#define ICE_MAC_IPV6_GTPC 328 +#define ICE_MAC_IPV4_GTPU 329 +#define ICE_MAC_IPV6_GTPU 330 +#define ICE_MAC_IPV4_GTPU_IPV4_FRAG 331 +#define ICE_MAC_IPV4_GTPU_IPV4_PAY 332 +#define ICE_MAC_IPV4_GTPU_IPV4_UDP_PAY 333 +#define ICE_MAC_IPV4_GTPU_IPV4_TCP 334 +#define ICE_MAC_IPV4_GTPU_IPV4_ICMP 335 +#define ICE_MAC_IPV6_GTPU_IPV4_FRAG 336 +#define ICE_MAC_IPV6_GTPU_IPV4_PAY 337 +#define ICE_MAC_IPV6_GTPU_IPV4_UDP_PAY 338 +#define ICE_MAC_IPV6_GTPU_IPV4_TCP 339 +#define ICE_MAC_IPV6_GTPU_IPV4_ICMP 340 +#define ICE_MAC_IPV4_GTPU_IPV6_FRAG 341 +#define ICE_MAC_IPV4_GTPU_IPV6_PAY 342 +#define ICE_MAC_IPV4_GTPU_IPV6_UDP_PAY 343 +#define ICE_MAC_IPV4_GTPU_IPV6_TCP 344 +#define ICE_MAC_IPV4_GTPU_IPV6_ICMPV6 345 +#define ICE_MAC_IPV6_GTPU_IPV6_FRAG 346 +#define ICE_MAC_IPV6_GTPU_IPV6_PAY 347 +#define ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY 348 +#define ICE_MAC_IPV6_GTPU_IPV6_TCP 349 +#define ICE_MAC_IPV6_GTPU_IPV6_ICMPV6 350 + +/* Attributes that can modify PTYPE definitions. + * + * These values will represent special attributes for PTYPES, which will + * resolve into metadata packet flags definitions that can be used in the TCAM + * for identifying a PTYPE with specific characteristics. + */ +enum ice_ptype_attrib_type { + /* GTP PTYPES */ + ICE_PTYPE_ATTR_GTP_PDU_EH, + ICE_PTYPE_ATTR_GTP_SESSION, + ICE_PTYPE_ATTR_GTP_DOWNLINK, + ICE_PTYPE_ATTR_GTP_UPLINK, +}; + +struct ice_ptype_attrib_info { + u16 flags; + u16 mask; +}; + +/* TCAM flag definitions */ +#define ICE_GTP_PDU BIT(14) +#define ICE_GTP_PDU_LINK BIT(13) + +/* GTP attributes */ +#define ICE_GTP_PDU_FLAG_MASK (ICE_GTP_PDU) +#define ICE_GTP_PDU_EH ICE_GTP_PDU + +#define ICE_GTP_FLAGS_MASK (ICE_GTP_PDU | ICE_GTP_PDU_LINK) +#define ICE_GTP_SESSION 0 +#define ICE_GTP_DOWNLINK ICE_GTP_PDU +#define ICE_GTP_UPLINK (ICE_GTP_PDU | ICE_GTP_PDU_LINK) + +struct ice_ptype_attributes { + u16 ptype; + enum ice_ptype_attrib_type attrib; +}; /* Packet Type Groups (PTG) - Inner Most fields (IM) */ #define ICE_PTG_IM_IPV4_TCP 16 @@ -530,12 +593,14 @@ struct ice_prof_map { u8 prof_id; u8 ptg_cnt; u8 ptg[ICE_MAX_PTG_PER_PROFILE]; + struct ice_ptype_attrib_info attr[ICE_MAX_PTG_PER_PROFILE]; }; #define ICE_INVALID_TCAM 0xFFFF struct ice_tcam_inf { u16 tcam_idx; + struct ice_ptype_attrib_info attr; u8 ptg; u8 prof_id; u8 in_use; @@ -708,6 +773,7 @@ struct ice_chs_chg { u16 vsig; u16 orig_vsig; u16 tcam_idx; + struct ice_ptype_attrib_info attr; }; #define ICE_FLOW_PTYPE_MAX ICE_XLT1_CNT diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index 38c7c42f7..f4f961167 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -20,6 +20,7 @@ #define ICE_FLOW_FLD_SZ_ARP_OPER 2 #define ICE_FLOW_FLD_SZ_GRE_KEYID 4 #define ICE_FLOW_FLD_SZ_GTP_TEID 4 +#define ICE_FLOW_FLD_SZ_GTP_QFI 2 #define ICE_FLOW_FLD_SZ_PPPOE_SESS_ID 2 /* Describe properties of a protocol header field */ @@ -126,6 +127,12 @@ struct ice_flow_field_info ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = { /* ICE_FLOW_FIELD_IDX_GTPU_IP_TEID */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_IP, 12, ICE_FLOW_FLD_SZ_GTP_TEID), + /* ICE_FLOW_FIELD_IDX_GTPU_EH_TEID */ + ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_EH, 12, + ICE_FLOW_FLD_SZ_GTP_TEID), + /* ICE_FLOW_FIELD_IDX_GTPU_EH_QFI */ + ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_GTPU_EH, 20, + ICE_FLOW_FLD_SZ_GTP_QFI, 0x003f), /* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12, ICE_FLOW_FLD_SZ_GTP_TEID), @@ -169,7 +176,7 @@ static const u32 ice_ptypes_macvlan_il[] = { static const u32 ice_ptypes_ipv4_ofos[] = { 0x1DC00000, 0x04000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x000FC000, 0x00000000, 0x00000000, + 0x0003000F, 0x000FC000, 0x03E0F800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -193,7 +200,7 @@ static const u32 ice_ptypes_ipv4_il[] = { static const u32 ice_ptypes_ipv6_ofos[] = { 0x00000000, 0x00000000, 0x77000000, 0x10002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x03F00000, 0x00000000, 0x00000000, + 0x00080F00, 0x03F00000, 0x7C1F0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -336,10 +343,33 @@ static const u32 ice_ptypes_gtpc_tid[] = { }; /* Packet types for GTPU */ +static const struct ice_ptype_attributes ice_attr_gtpu_eh[] = { + { ICE_MAC_IPV4_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV4_ICMP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV4_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_FRAG, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_UDP_PAY, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_TCP, ICE_PTYPE_ATTR_GTP_PDU_EH }, + { ICE_MAC_IPV6_GTPU_IPV6_ICMPV6, ICE_PTYPE_ATTR_GTP_PDU_EH }, +}; + static const u32 ice_ptypes_gtpu[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x7FFFF800, 0x00000000, + 0x00000000, 0x00000000, 0x7FFFFE00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -370,6 +400,10 @@ struct ice_flow_prof_params { * This will give us the direction flags. */ struct ice_fv_word es[ICE_MAX_FV_WORDS]; + /* attributes can be used to add attributes to a particular PTYPE */ + const struct ice_ptype_attributes *attr; + u16 attr_cnt; + u16 mask[ICE_MAX_FV_WORDS]; ice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX); }; @@ -562,6 +596,16 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); } + } else if (hdrs & ICE_FLOW_SEG_HDR_GTPU_EH) { + if (!i) { + src = (const ice_bitmap_t *)ice_ptypes_gtpu; + ice_and_bitmap(params->ptypes, params->ptypes, + src, ICE_FLOW_PTYPE_MAX); + } + + /* Attributes for GTP packet with Extension Header */ + params->attr = ice_attr_gtpu_eh; + params->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_eh); } } @@ -711,6 +755,8 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params, case ICE_FLOW_FIELD_IDX_GTPU_IP_TEID: case ICE_FLOW_FIELD_IDX_GTPU_UP_TEID: case ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID: + case ICE_FLOW_FIELD_IDX_GTPU_EH_TEID: + case ICE_FLOW_FIELD_IDX_GTPU_EH_QFI: /* GTP is accessed through UDP OF protocol */ prot_id = ICE_PROT_UDP_OF; break; @@ -1176,8 +1222,9 @@ ice_flow_add_prof_sync(struct ice_hw *hw, enum ice_block blk, } /* Add a HW profile for this flow profile */ - status = ice_add_prof_with_mask(hw, blk, prof_id, (u8 *)params.ptypes, - params.es, params.mask); + status = ice_add_prof(hw, blk, prof_id, (u8 *)params.ptypes, + params.attr, params.attr_cnt, params.es, + params.mask); if (status) { ice_debug(hw, ICE_DBG_FLOW, "Error adding a HW flow profile\n"); goto out; diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h index c224e6ebf..4686274af 100644 --- a/drivers/net/ice/base/ice_flow.h +++ b/drivers/net/ice/base/ice_flow.h @@ -58,6 +58,19 @@ #define ICE_FLOW_HASH_GTP_U_IPV6_TEID \ (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_TEID) +#define ICE_FLOW_HASH_GTP_U_EH_TEID \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_TEID)) + +#define ICE_FLOW_HASH_GTP_U_EH_QFI \ + (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_QFI)) + +#define ICE_FLOW_HASH_GTP_U_IPV4_EH \ + (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_U_EH_TEID | \ + ICE_FLOW_HASH_GTP_U_EH_QFI) +#define ICE_FLOW_HASH_GTP_U_IPV6_EH \ + (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_EH_TEID | \ + ICE_FLOW_HASH_GTP_U_EH_QFI) + #define ICE_FLOW_HASH_PPPOE_SESS_ID \ (BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID)) @@ -89,9 +102,10 @@ enum ice_flow_seg_hdr { ICE_FLOW_SEG_HDR_GTPC = 0x00000400, ICE_FLOW_SEG_HDR_GTPC_TEID = 0x00000800, ICE_FLOW_SEG_HDR_GTPU_IP = 0x00001000, - ICE_FLOW_SEG_HDR_GTPU_DWN = 0x00002000, - ICE_FLOW_SEG_HDR_GTPU_UP = 0x00004000, - ICE_FLOW_SEG_HDR_PPPOE = 0x00008000, + ICE_FLOW_SEG_HDR_GTPU_EH = 0x00002000, + ICE_FLOW_SEG_HDR_GTPU_DWN = 0x00004000, + ICE_FLOW_SEG_HDR_GTPU_UP = 0x00008000, + ICE_FLOW_SEG_HDR_PPPOE = 0x00010000, }; /* These segements all have the same PTYPES, but are otherwise distinguished by @@ -99,6 +113,7 @@ enum ice_flow_seg_hdr { * * gtp_eh_pdu gtp_eh_pdu_link * ICE_FLOW_SEG_HDR_GTPU_IP 0 0 + * ICE_FLOW_SEG_HDR_GTPU_EH 1 don't care * ICE_FLOW_SEG_HDR_GTPU_DWN 1 0 * ICE_FLOW_SEG_HDR_GTPU_UP 1 1 */ @@ -147,6 +162,9 @@ enum ice_flow_field { ICE_FLOW_FIELD_IDX_GTPC_TEID, /* GTPU_IP */ ICE_FLOW_FIELD_IDX_GTPU_IP_TEID, + /* GTPU_EH */ + ICE_FLOW_FIELD_IDX_GTPU_EH_TEID, + ICE_FLOW_FIELD_IDX_GTPU_EH_QFI, /* GTPU_UP */ ICE_FLOW_FIELD_IDX_GTPU_UP_TEID, /* GTPU_DWN */ From patchwork Tue Oct 8 01:50:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 60668 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9A4AD1C19F; Tue, 8 Oct 2019 03:47:53 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id B00761C0CE for ; Tue, 8 Oct 2019 03:47:47 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 18:47:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="197556271" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga006.jf.intel.com with ESMTP; 07 Oct 2019 18:47:45 -0700 From: Qi Zhang To: wenzhuo.lu@intel.com, qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Tony Nguyen , Paul M Stillwell Jr Date: Tue, 8 Oct 2019 09:50:18 +0800 Message-Id: <20191008015018.17086-13-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20191008015018.17086-1-qi.z.zhang@intel.com> References: <20190902035551.16852-1-qi.z.zhang@intel.com> <20191008015018.17086-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 12/12] net/ice/base: improve misc code style X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Combine a couple of function definitions that can fit on one line. RCT a variable declaration. Signed-off-by: Tony Nguyen Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Signed-off-by: Tony Nguyen Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_flex_pipe.c | 6 ++---- drivers/net/ice/base/ice_flex_pipe.h | 3 +-- drivers/net/ice/base/ice_nvm.c | 2 +- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index c2af1dfe8..dd098f529 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -2131,8 +2131,7 @@ ice_ptg_find_ptype(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 *ptg) * This function allocates a given packet type group ID specified by the ptg * parameter. */ -static -void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg) +static void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg) { hw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true; } @@ -3286,8 +3285,7 @@ static const u32 ice_blk_sids[ICE_BLK_COUNT][ICE_SID_OFF_COUNT] = { * @hw: pointer to the hardware structure * @blk: the HW block to initialize */ -static -void ice_init_sw_xlt1_db(struct ice_hw *hw, enum ice_block blk) +static void ice_init_sw_xlt1_db(struct ice_hw *hw, enum ice_block blk) { u16 pt; diff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h index b24a09b4d..ee606af15 100644 --- a/drivers/net/ice/base/ice_flex_pipe.h +++ b/drivers/net/ice/base/ice_flex_pipe.h @@ -65,8 +65,7 @@ enum ice_status ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl); enum ice_status ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl); -enum ice_status -ice_init_pkg(struct ice_hw *hw, u8 *buff, u32 len); +enum ice_status ice_init_pkg(struct ice_hw *hw, u8 *buff, u32 len); enum ice_status ice_copy_and_init_pkg(struct ice_hw *hw, const u8 *buf, u32 len); enum ice_status ice_init_hw_tbls(struct ice_hw *hw); diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c index e00942528..1dbfc2dcc 100644 --- a/drivers/net/ice/base/ice_nvm.c +++ b/drivers/net/ice/base/ice_nvm.c @@ -260,8 +260,8 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data) */ enum ice_status ice_init_nvm(struct ice_hw *hw) { - struct ice_nvm_info *nvm = &hw->nvm; u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len; + struct ice_nvm_info *nvm = &hw->nvm; u16 eetrack_lo, eetrack_hi; enum ice_status status; u32 fla, gens_stat;