From patchwork Wed Oct 9 14:16:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 60803 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0DD5D1E8AB; Wed, 9 Oct 2019 16:17:17 +0200 (CEST) Received: from smtp.tom.com (smtprz15.163.net [106.3.154.248]) by dpdk.org (Postfix) with ESMTP id A41E61E53A for ; Wed, 9 Oct 2019 16:17:10 +0200 (CEST) Received: from my-app01.tom.com (my-app01.tom.com [127.0.0.1]) by freemail01.tom.com (Postfix) with ESMTP id EEE7C1C82C24 for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) Received: from my-app01.tom.com (HELO smtp.tom.com) ([127.0.0.1]) by my-app01 (TOM SMTP Server) with SMTP ID 812506802 for ; Wed, 09 Oct 2019 22:17:27 +0800 (CST) Received: from antispam1.tom.com (unknown [172.25.16.55]) by freemail01.tom.com (Postfix) with ESMTP id E4CCC1C8276B for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tom.com; s=201807; t=1570630647; bh=tfi0p//QISJyFjZZ9/Ue5wV7rq/k7IDdOAezfSE2jR0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I0VWUyELUnRXxp0tO3uKE73BkHEEgo42eL1UKNvNofiFK9H4iM9Y1DvftaoA3x8Ra LTXJQADrB3KwghOX5TBB3y2NfT8R9anaBWf5N2Osq7iW3KQMgZsYVceKGZbYX8YAnB m25AfAUtv07tkBwBIYzXpbwIICXNOPiwIP/uZOs0= Received: from antispam1.tom.com (antispam1.tom.com [127.0.0.1]) by antispam1.tom.com (Postfix) with ESMTP id 7AF1F10016AE for ; Wed, 9 Oct 2019 22:16:01 +0800 (CST) X-Virus-Scanned: Debian amavisd-new at antispam1.tom.com Received: from antispam1.tom.com ([127.0.0.1]) by antispam1.tom.com (antispam1.tom.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 56FvOJN6rvj9 for ; Wed, 9 Oct 2019 22:15:59 +0800 (CST) Received: from localhost.localdomain (unknown [114.119.4.74]) by antispam1.tom.com (Postfix) with ESMTPA id 9B1CF1001471; Wed, 9 Oct 2019 22:15:59 +0800 (CST) From: "Wei Hu (Xavier)" To: dev@dpdk.org Cc: xavier.huwei@huawei.com Date: Wed, 9 Oct 2019 22:16:50 +0800 Message-Id: <20191009141653.39364-2-xavier.huwei@tom.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009141653.39364-1-xavier.huwei@tom.com> References: <20191009141653.39364-1-xavier.huwei@tom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 1/4] net/hns3: modify the statistics for sending and receiving messages X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hao Chen In receiving direction, for FCS error messages, drivers no longer record them in rte_eth_stats.ipackets statistics. In sending direction, for messages of illegal length, too long or equals 0, drivers will not notify the network card hardware to send them, will not continue to send the remaining message in burst, and will not record them in rte_eth_stats.opackets statistics. Signed-off-by: Hao Chen Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_rxtx.c | 11 ++--- drivers/net/hns3/hns3_rxtx.h | 3 -- drivers/net/hns3/hns3_stats.c | 84 ++++++++--------------------------- 3 files changed, 22 insertions(+), 76 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 184b8e4b6..709e07c80 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -660,7 +660,6 @@ hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, rxq->l4_csum_erros = 0; rxq->ol3_csum_erros = 0; rxq->ol4_csum_erros = 0; - rxq->errors = 0; rte_spinlock_lock(&hw->lock); dev->data->rx_queues[idx] = rxq; @@ -816,14 +815,12 @@ hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm, if (unlikely(l234_info & BIT(HNS3_RXD_L2E_B))) { rxq->l2_errors++; - rxq->errors++; return -EINVAL; } if (unlikely(rxm->pkt_len == 0 || (l234_info & BIT(HNS3_RXD_TRUNCAT_B)))) { rxq->pkt_len_errors++; - rxq->errors++; return -EINVAL; } @@ -979,6 +976,7 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) first_seg->pkt_len = pkt_len; first_seg->port = rxq->port_id; first_seg->hash.rss = rte_le_to_cpu_32(rxdp->rx.rss_hash); + first_seg->ol_flags |= PKT_RX_RSS_HASH; if (unlikely(hns3_get_bit(bd_base_info, HNS3_RXD_LUM_B))) { first_seg->hash.fdir.hi = rte_le_to_cpu_32(rxdp->rx.fd_id); @@ -1097,7 +1095,6 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc, txq->next_to_clean = 0; txq->tx_bd_ready = txq->nb_tx_desc; txq->port_id = dev->data->port_id; - txq->pkt_len_errors = 0; txq->configured = true; txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET + idx * HNS3_TQP_REG_SIZE); @@ -1604,10 +1601,8 @@ hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) * will be ignored. */ if (unlikely(tx_pkt->pkt_len > HNS3_MAX_FRAME_LEN || - tx_pkt->pkt_len == 0)) { - txq->pkt_len_errors++; - continue; - } + tx_pkt->pkt_len == 0)) + break; m_seg = tx_pkt; if (unlikely(nb_buf > HNS3_MAX_TX_BD_PER_PKT)) { diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h index 358f12984..daf51f409 100644 --- a/drivers/net/hns3/hns3_rxtx.h +++ b/drivers/net/hns3/hns3_rxtx.h @@ -252,7 +252,6 @@ struct hns3_rx_queue { uint64_t l4_csum_erros; uint64_t ol3_csum_erros; uint64_t ol4_csum_erros; - uint64_t errors; /* num of error rx packets recorded by driver */ }; struct hns3_tx_queue { @@ -272,8 +271,6 @@ struct hns3_tx_queue { bool tx_deferred_start; /* don't start this queue in dev start */ bool configured; /* indicate if tx queue has been configured */ - - uint64_t pkt_len_errors; }; #define HNS3_TX_CKSUM_OFFLOAD_MASK ( \ diff --git a/drivers/net/hns3/hns3_stats.c b/drivers/net/hns3/hns3_stats.c index a0252eacc..9948beb17 100644 --- a/drivers/net/hns3/hns3_stats.c +++ b/drivers/net/hns3/hns3_stats.c @@ -235,12 +235,6 @@ static const struct hns3_xstats_name_offset hns3_rx_bd_error_strings[] = { HNS3_RX_BD_ERROR_STATS_FIELD_OFFSET(ol4_csum_erros)} }; -/* The statistic of errors in Tx */ -static const struct hns3_xstats_name_offset hns3_tx_error_strings[] = { - {"TX_PKT_LEN_ERRORS", - HNS3_TX_ERROR_STATS_FIELD_OFFSET(pkt_len_errors)} -}; - #define HNS3_NUM_MAC_STATS (sizeof(hns3_mac_strings) / \ sizeof(hns3_mac_strings[0])) @@ -253,9 +247,6 @@ static const struct hns3_xstats_name_offset hns3_tx_error_strings[] = { #define HNS3_NUM_RX_BD_ERROR_XSTATS (sizeof(hns3_rx_bd_error_strings) / \ sizeof(hns3_rx_bd_error_strings[0])) -#define HNS3_NUM_TX_ERROR_XSTATS (sizeof(hns3_tx_error_strings) / \ - sizeof(hns3_tx_error_strings[0])) - #define HNS3_FIX_NUM_STATS (HNS3_NUM_MAC_STATS + HNS3_NUM_ERROR_INT_XSTATS + \ HNS3_NUM_RESET_XSTATS) @@ -434,6 +425,7 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) struct hns3_hw *hw = &hns->hw; struct hns3_tqp_stats *stats = &hw->tqp_stats; struct hns3_rx_queue *rxq; + struct hns3_tx_queue *txq; uint64_t cnt; uint64_t num; uint16_t i; @@ -446,25 +438,32 @@ hns3_stats_get(struct rte_eth_dev *eth_dev, struct rte_eth_stats *rte_stats) return ret; } - rte_stats->ipackets = stats->rcb_rx_ring_pktnum_rcd; - rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd; - rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed; - - num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, hw->tqps_num); - for (i = 0; i < num; i++) { - rte_stats->q_ipackets[i] = stats->rcb_rx_ring_pktnum[i]; - rte_stats->q_opackets[i] = stats->rcb_tx_ring_pktnum[i]; - } - + /* Get the error stats of received packets */ num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, eth_dev->data->nb_rx_queues); for (i = 0; i != num; ++i) { rxq = eth_dev->data->rx_queues[i]; if (rxq) { - cnt = rxq->errors; + cnt = rxq->l2_errors + rxq->pkt_len_errors; rte_stats->q_errors[i] = cnt; + rte_stats->q_ipackets[i] = + stats->rcb_rx_ring_pktnum[i] - cnt; rte_stats->ierrors += cnt; } } + /* Get the error stats of transmitted packets */ + num = RTE_MIN(RTE_ETHDEV_QUEUE_STAT_CNTRS, eth_dev->data->nb_tx_queues); + for (i = 0; i < num; i++) { + txq = eth_dev->data->tx_queues[i]; + if (txq) + rte_stats->q_opackets[i] = stats->rcb_tx_ring_pktnum[i]; + } + + rte_stats->oerrors = 0; + rte_stats->ipackets = stats->rcb_rx_ring_pktnum_rcd - + rte_stats->ierrors; + rte_stats->opackets = stats->rcb_tx_ring_pktnum_rcd - + rte_stats->oerrors; + rte_stats->rx_nombuf = eth_dev->data->rx_mbuf_alloc_failed; return 0; } @@ -477,7 +476,6 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) struct hns3_tqp_stats *stats = &hw->tqp_stats; struct hns3_cmd_desc desc_reset; struct hns3_rx_queue *rxq; - struct hns3_tx_queue *txq; uint16_t i; int ret; @@ -518,12 +516,7 @@ hns3_stats_reset(struct rte_eth_dev *eth_dev) rxq->l4_csum_erros = 0; rxq->ol3_csum_erros = 0; rxq->ol4_csum_erros = 0; - rxq->errors = 0; } - - txq = eth_dev->data->tx_queues[i]; - if (txq) - txq->pkt_len_errors = 0; } memset(stats, 0, sizeof(struct hns3_tqp_stats)); @@ -554,11 +547,9 @@ hns3_xstats_calc_num(struct rte_eth_dev *dev) if (hns->is_vf) return dev->data->nb_rx_queues * HNS3_NUM_RX_BD_ERROR_XSTATS + - dev->data->nb_tx_queues * HNS3_NUM_TX_ERROR_XSTATS + HNS3_NUM_RESET_XSTATS; else return dev->data->nb_rx_queues * HNS3_NUM_RX_BD_ERROR_XSTATS + - dev->data->nb_tx_queues * HNS3_NUM_TX_ERROR_XSTATS + HNS3_FIX_NUM_STATS; } @@ -585,7 +576,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_queue *rxq; - struct hns3_tx_queue *txq; uint16_t i, j; char *addr; int count; @@ -644,16 +634,6 @@ hns3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, } } - /* Get the Tx errors stats */ - for (j = 0; j != dev->data->nb_tx_queues; ++j) { - for (i = 0; i < HNS3_NUM_TX_ERROR_XSTATS; i++) { - txq = dev->data->tx_queues[j]; - addr = (char *)txq + hns3_tx_error_strings[i].offset; - xstats[count].value = *(uint64_t *)addr; - xstats[count].id = count; - count++; - } - } return count; } @@ -727,14 +707,6 @@ hns3_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, count++; } } - for (j = 0; j < dev->data->nb_tx_queues; j++) { - for (i = 0; i < HNS3_NUM_TX_ERROR_XSTATS; i++) { - snprintf(xstats_names[count].name, - sizeof(xstats_names[count].name), - "tx_q%u%s", j, hns3_tx_error_strings[i].name); - count++; - } - } return count; } @@ -772,7 +744,6 @@ hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, struct hns3_mac_stats *mac_stats = &hw->mac_stats; struct hns3_reset_stats *reset_stats = &hw->reset.stats; struct hns3_rx_queue *rxq; - struct hns3_tx_queue *txq; const uint32_t cnt_stats = hns3_xstats_calc_num(dev); uint64_t *values_copy; uint64_t len; @@ -831,15 +802,6 @@ hns3_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, } } - for (j = 0; j != dev->data->nb_tx_queues; ++j) { - for (i = 0; i < HNS3_NUM_TX_ERROR_XSTATS; i++) { - txq = dev->data->tx_queues[j]; - addr = (char *)txq + hns3_tx_error_strings[i].offset; - values_copy[count] = *(uint64_t *)addr; - count++; - } - } - for (i = 0; i < size; i++) { if (ids[i] >= cnt_stats) { hns3_err(hw, "ids[%d] (%" PRIx64 ") is invalid, " @@ -928,14 +890,6 @@ hns3_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, count_name++; } } - for (j = 0; j != dev->data->nb_rx_queues; ++j) { - for (i = 0; i < HNS3_NUM_TX_ERROR_XSTATS; i++) { - snprintf(xstats_names_copy[count_name].name, - sizeof(xstats_names_copy[count_name].name), - "tx_q%u%s", j, hns3_tx_error_strings[i].name); - count_name++; - } - } for (i = 0; i < size; i++) { if (ids[i] >= cnt_stats) { From patchwork Wed Oct 9 14:16:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 60804 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 906981E8C9; Wed, 9 Oct 2019 16:17:19 +0200 (CEST) Received: from smtp.tom.com (smtprz14.163.net [106.3.154.247]) by dpdk.org (Postfix) with ESMTP id BF81F1E8A0 for ; Wed, 9 Oct 2019 16:17:15 +0200 (CEST) Received: from my-app01.tom.com (my-app01.tom.com [127.0.0.1]) by freemail01.tom.com (Postfix) with ESMTP id D6D1E1C8291B for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) Received: from my-app01.tom.com (HELO smtp.tom.com) ([127.0.0.1]) by my-app01 (TOM SMTP Server) with SMTP ID 2049061700 for ; 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Wed, 9 Oct 2019 22:15:59 +0800 (CST) From: "Wei Hu (Xavier)" To: dev@dpdk.org Cc: xavier.huwei@huawei.com Date: Wed, 9 Oct 2019 22:16:51 +0800 Message-Id: <20191009141653.39364-3-xavier.huwei@tom.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009141653.39364-1-xavier.huwei@tom.com> References: <20191009141653.39364-1-xavier.huwei@tom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 2/4] net/hns3: change the return value of firmware processing timeout from -EBADE to -ETIME X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hongbo Zheng Configuration commands are sent to firmware for processing. When firmware processing timeout, the corresponding error code is returned. Considering that it is more reasonable to use error code -ETIME for timeout error, the error code for processing timeout is changed from -EBADE to -ETIME. Signed-off-by: Hongbo Zheng Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_cmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 3eebfdd42..58776c2ec 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -359,7 +359,7 @@ static int hns3_cmd_poll_reply(struct hns3_hw *hw) timeout++; } while (timeout < hw->cmq.tx_timeout); hns3_err(hw, "Wait for reply timeout"); - return -EBADE; + return -ETIME; } /* From patchwork Wed Oct 9 14:16:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 60802 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AC5621E87D; Wed, 9 Oct 2019 16:17:14 +0200 (CEST) Received: from smtp.tom.com (smtprz14.163.net [106.3.154.247]) by dpdk.org (Postfix) with ESMTP id 69C231E537 for ; Wed, 9 Oct 2019 16:17:11 +0200 (CEST) Received: from my-app01.tom.com (my-app01.tom.com [127.0.0.1]) by freemail01.tom.com (Postfix) with ESMTP id EECF51C82C06 for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) Received: from my-app01.tom.com (HELO smtp.tom.com) ([127.0.0.1]) by my-app01 (TOM SMTP Server) with SMTP ID 1012280281 for ; Wed, 09 Oct 2019 22:17:27 +0800 (CST) Received: from antispam1.tom.com (unknown [172.25.16.55]) by freemail01.tom.com (Postfix) with ESMTP id EC61B1C82A58 for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tom.com; s=201807; t=1570630647; bh=j+HivmFoIK3h6YCQLOn6aoGYCGv8mdtnKf2ecaaddNk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=xdrmafA2WVxRAHkZehmfkiqAXP4NsLgSpLZnE1IA+SOzpv/IOy45+ksgk4uGr1mim fw4LDYWGhvm26BwsZEULHKfo1dClRKgd4bt3kq7GpvNnAFUAplJUHaYrHYa2zcbQ95 UouwE0MAm8H5hLL8xltuajWFhE8cpOLvDu+4lDbw= Received: from antispam1.tom.com (antispam1.tom.com [127.0.0.1]) by antispam1.tom.com (Postfix) with ESMTP id 829C710011A1 for ; Wed, 9 Oct 2019 22:16:01 +0800 (CST) X-Virus-Scanned: Debian amavisd-new at antispam1.tom.com Received: from antispam1.tom.com ([127.0.0.1]) by antispam1.tom.com (antispam1.tom.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xTHPFrS0l-kW for ; Wed, 9 Oct 2019 22:16:00 +0800 (CST) Received: from localhost.localdomain (unknown [114.119.4.74]) by antispam1.tom.com (Postfix) with ESMTPA id 38C2A10011AD; Wed, 9 Oct 2019 22:16:00 +0800 (CST) From: "Wei Hu (Xavier)" To: dev@dpdk.org Cc: xavier.huwei@huawei.com Date: Wed, 9 Oct 2019 22:16:52 +0800 Message-Id: <20191009141653.39364-4-xavier.huwei@tom.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009141653.39364-1-xavier.huwei@tom.com> References: <20191009141653.39364-1-xavier.huwei@tom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 3/4] net/hns3: Renew command and desc structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: humin This patch adds commands and modifies descriptor structures for accessing manage table and mac table. Signed-off-by: humin Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_cmd.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index be0ecbe86..13a3b87d5 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -217,6 +217,8 @@ enum hns3_opcode_type { /* PPP module intr commands */ HNS3_PPP_CMD0_INT_CMD = 0x2100, HNS3_PPP_CMD1_INT_CMD = 0x2101, + HNS3_PPP_MAC_VLAN_IDX_RD = 0x2104, + HNS3_MAC_ETHERTYPE_IDX_RD = 0x2105, }; #define HNS3_CMD_FLAG_IN BIT(0) @@ -642,7 +644,7 @@ struct hns3_mac_mgr_tbl_entry_cmd { uint16_t vlan_tag; uint32_t mac_addr_hi32; uint16_t mac_addr_lo16; - uint16_t rsv1; + uint16_t index; uint16_t ethter_type; uint16_t egress_port; uint16_t egress_queue; @@ -707,12 +709,13 @@ struct hns3_mac_vlan_tbl_entry_cmd { uint16_t vlan_tag; uint32_t mac_addr_hi32; uint16_t mac_addr_lo16; - uint16_t rsv1; + uint16_t port; uint8_t entry_type; uint8_t mc_mac_en; uint16_t egress_port; uint16_t egress_queue; - uint8_t rsv2[6]; + uint8_t rsv2[2]; + uint32_t index; }; #define HNS3_TQP_RESET_B 0 From patchwork Wed Oct 9 14:16:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 60805 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 80FAF1E8D7; Wed, 9 Oct 2019 16:17:21 +0200 (CEST) Received: from smtp.tom.com (smtprz14.163.net [106.3.154.247]) by dpdk.org (Postfix) with ESMTP id EA9101E545 for ; Wed, 9 Oct 2019 16:17:11 +0200 (CEST) Received: from my-app01.tom.com (my-app01.tom.com [127.0.0.1]) by freemail01.tom.com (Postfix) with ESMTP id EE9261C82ADF for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) Received: from my-app01.tom.com (HELO smtp.tom.com) ([127.0.0.1]) by my-app01 (TOM SMTP Server) with SMTP ID 608605570 for ; Wed, 09 Oct 2019 22:17:27 +0800 (CST) Received: from antispam1.tom.com (unknown [172.25.16.55]) by freemail01.tom.com (Postfix) with ESMTP id E4D161C82956 for ; Wed, 9 Oct 2019 22:17:27 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tom.com; s=201807; t=1570630647; bh=aJUSDkdq0EnHqibkV2LcMmB1C5h+K0+dXVi6lDMHG2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Swi+iJHjltA1T69+1s2WrvGMXm6PFfOfSN8xm/qO3Cnys1a3s73LyiTkSryrDlOPQ ZuSIwUWkMkQYGgWTqzQmoUHSP+YFiPA+1DZaQM9jSQzRjzZuqzAtAYJ/686fXCFdVT 9Yq5JlZoFz0OnkTdx6s/k9NWzRz6xldEIvKY+62k= Received: from antispam1.tom.com (antispam1.tom.com [127.0.0.1]) by antispam1.tom.com (Postfix) with ESMTP id 7B32710016C0 for ; Wed, 9 Oct 2019 22:16:01 +0800 (CST) X-Virus-Scanned: Debian amavisd-new at antispam1.tom.com Received: from antispam1.tom.com ([127.0.0.1]) by antispam1.tom.com (antispam1.tom.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id If4dyj4FnOYC for ; Wed, 9 Oct 2019 22:16:00 +0800 (CST) Received: from localhost.localdomain (unknown [114.119.4.74]) by antispam1.tom.com (Postfix) with ESMTPA id 7C2151001667; Wed, 9 Oct 2019 22:16:00 +0800 (CST) From: "Wei Hu (Xavier)" To: dev@dpdk.org Cc: xavier.huwei@huawei.com Date: Wed, 9 Oct 2019 22:16:53 +0800 Message-Id: <20191009141653.39364-5-xavier.huwei@tom.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191009141653.39364-1-xavier.huwei@tom.com> References: <20191009141653.39364-1-xavier.huwei@tom.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 4/4] net/hns3: restores bus_master_en and msix_enable during PF FLR reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chunsong Feng PF FLR resets the PCIe ECAM space of all VFs under the PF and does not automatically recover. Therefore, the VF driver needs to restore the ECAM configuration, including bus_master_en, msix_enable. Signed-off-by: Chunsong Feng Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_cmd.c | 15 ---- drivers/net/hns3/hns3_ethdev.c | 5 ++ drivers/net/hns3/hns3_ethdev_vf.c | 135 +++++++++++++++++++++++++++++- drivers/net/hns3/hns3_intr.c | 5 +- 4 files changed, 139 insertions(+), 21 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 58776c2ec..65a5af8e4 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -216,24 +216,9 @@ hns3_cmd_csq_clean(struct hns3_hw *hw) if (!is_valid_csq_clean_head(csq, head)) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - uint32_t global; - uint32_t fun_rst; hns3_err(hw, "wrong cmd head (%u, %u-%u)", head, csq->next_to_use, csq->next_to_clean); rte_atomic16_set(&hw->reset.disable_cmd, 1); - if (hns->is_vf) { - global = hns3_read_dev(hw, HNS3_VF_RST_ING); - fun_rst = hns3_read_dev(hw, HNS3_FUN_RST_ING); - hns3_err(hw, "Delayed VF reset global: %x fun_rst: %x", - global, fun_rst); - hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); - } else { - global = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); - fun_rst = hns3_read_dev(hw, HNS3_FUN_RST_ING); - hns3_err(hw, "Delayed IMP reset global: %x fun_rst: %x", - global, fun_rst); - hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); - } hns3_schedule_delayed_reset(hns); diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 862a717fd..3435bce26 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -4680,6 +4680,11 @@ hns3_reset_service(void *param) rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); hns3_err(hw, "Handling interrupts in delayed tasks"); hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); + reset_level = hns3_get_reset_level(hns, &hw->reset.pending); + if (reset_level == HNS3_NONE_RESET) { + hns3_err(hw, "No reset level is set, try IMP reset"); + hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); + } } rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 121beb58d..1e9acd4f9 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -9,6 +9,8 @@ #include #include #include +#include + #include #include #include @@ -24,6 +26,7 @@ #include #include #include +#include #include "hns3_ethdev.h" #include "hns3_logs.h" @@ -56,6 +59,81 @@ static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw, static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev); +/* set PCI bus mastering */ +static void +hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) +{ + uint16_t reg; + + rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); + + if (op) + /* set the master bit */ + reg |= PCI_COMMAND_MASTER; + else + reg &= ~(PCI_COMMAND_MASTER); + + rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); +} + +/** + * hns3vf_find_pci_capability - lookup a capability in the PCI capability list + * @cap: the capability + * + * Return the address of the given capability within the PCI capability list. + */ +static inline int +hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) +{ +#define MAX_PCIE_CAPABILITY 48 + uint16_t status; + uint8_t pos; + uint8_t id; + int ttl; + + rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + ttl = MAX_PCIE_CAPABILITY; + rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST); + while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { + rte_pci_read_config(device, &id, sizeof(id), + (pos + PCI_CAP_LIST_ID)); + + if (id == 0xFF) + break; + + if (id == cap) + return (int)pos; + + rte_pci_read_config(device, &pos, sizeof(pos), + (pos + PCI_CAP_LIST_NEXT)); + } + return 0; +} + +static int +hns3vf_enable_msix(const struct rte_pci_device *device, bool op) +{ + uint16_t control; + int pos; + + pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); + if (pos) { + rte_pci_read_config(device, &control, sizeof(control), + (pos + PCI_MSIX_FLAGS)); + if (op) + control |= PCI_MSIX_FLAGS_ENABLE; + else + control &= ~PCI_MSIX_FLAGS_ENABLE; + rte_pci_write_config(device, &control, sizeof(control), + (pos + PCI_MSIX_FLAGS)); + return 0; + } + return -1; +} + static int hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, __attribute__ ((unused)) uint32_t idx, @@ -1308,9 +1386,30 @@ hns3vf_wait_hardware_ready(struct hns3_adapter *hns) struct hns3_wait_data *wait_data = hw->reset.wait_data; struct timeval tv; - if (wait_data->result == HNS3_WAIT_SUCCESS) - return 0; - else if (wait_data->result == HNS3_WAIT_TIMEOUT) { + if (wait_data->result == HNS3_WAIT_SUCCESS) { + /* + * After vf reset is ready, the PF may not have completed + * the reset processing. The vf sending mbox to PF may fail + * during the pf reset, so it is better to add extra delay. + */ + if (hw->reset.level == HNS3_VF_FUNC_RESET || + hw->reset.level == HNS3_FLR_RESET) + return 0; + /* Reset retry process, no need to add extra delay. */ + if (hw->reset.attempts) + return 0; + if (wait_data->check_completion == NULL) + return 0; + + wait_data->check_completion = NULL; + wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC; + wait_data->count = 1; + wait_data->result = HNS3_WAIT_REQUEST; + rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, + wait_data); + hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete"); + return -EAGAIN; + } else if (wait_data->result == HNS3_WAIT_TIMEOUT) { gettimeofday(&tv, NULL); hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); @@ -1473,6 +1572,11 @@ hns3vf_reset_service(void *param) rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); hns3_err(hw, "Handling interrupts in delayed tasks"); hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]); + reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending); + if (reset_level == HNS3_NONE_RESET) { + hns3_err(hw, "No reset level is set, try global reset"); + hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending); + } } rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); @@ -1498,14 +1602,35 @@ hns3vf_reset_service(void *param) static int hns3vf_reinit_dev(struct hns3_adapter *hns) { + struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id]; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); struct hns3_hw *hw = &hns->hw; int ret; + if (hw->reset.level == HNS3_VF_FULL_RESET) { + rte_intr_disable(&pci_dev->intr_handle); + hns3vf_set_bus_master(pci_dev, true); + } + /* Firmware command initialize */ ret = hns3_cmd_init(hw); if (ret) { hns3_err(hw, "Failed to init cmd: %d", ret); - return ret; + goto err_cmd_init; + } + + if (hw->reset.level == HNS3_VF_FULL_RESET) { + /* + * UIO enables msix by writing the pcie configuration space + * vfio_pci enables msix in rte_intr_enable. + */ + if (pci_dev->kdrv == RTE_KDRV_IGB_UIO || + pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) { + if (hns3vf_enable_msix(pci_dev, true)) + hns3_err(hw, "Failed to enable msix"); + } + + rte_intr_enable(&pci_dev->intr_handle); } ret = hns3_reset_all_queues(hns); @@ -1522,6 +1647,8 @@ hns3vf_reinit_dev(struct hns3_adapter *hns) return 0; +err_cmd_init: + hns3vf_set_bus_master(pci_dev, false); err_init: hns3_cmd_uninit(hw); return ret; diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c index 9e2d81156..6c3ebd3ee 100644 --- a/drivers/net/hns3/hns3_intr.c +++ b/drivers/net/hns3/hns3_intr.c @@ -890,11 +890,12 @@ hns3_reset_err_handle(struct hns3_adapter *hns) hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64 - " merge_cnt:%" PRIx64, + " merge_cnt:%" PRIx64 "adapter_state:%d", reset_string[hw->reset.level], hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt, hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt, - hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt); + hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt, + hw->adapter_state); /* IMP no longer waiting the ready flag */ hns3_notify_reset_ready(hw, true);