[dpdk-dev,05/12] net/i40e/base: enable 25G get PHY abilities
Commit Message
Add extended PHY types to get PHY abilities command response struct
for 25G, then put PHY types for 25g into the proper PHY_Type_Ext field.
Signed-off-by: Zhang Qi <qi.z.zhang@intel.com>
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 15 +++++++++++++--
drivers/net/i40e/base/i40e_common.c | 4 +++-
2 files changed, 16 insertions(+), 3 deletions(-)
Comments
On 8/25/2016 9:05 PM, Zhang Qi wrote:
> Add extended PHY types to get PHY abilities command response struct
> for 25G, then put PHY types for 25g into the proper PHY_Type_Ext field.
>
> Signed-off-by: Zhang Qi <qi.z.zhang@intel.com>
> ---
> drivers/net/i40e/base/i40e_adminq_cmd.h | 15 +++++++++++++--
> drivers/net/i40e/base/i40e_common.c | 4 +++-
> 2 files changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
> index 2831593..4ae4315 100644
> --- a/drivers/net/i40e/base/i40e_adminq_cmd.h
> +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
> @@ -1733,7 +1733,13 @@ struct i40e_aq_get_phy_abilities_resp {
> __le32 eeer_val;
> u8 d3_lpan;
> #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
> - u8 reserved[3];
> + u8 phy_type_ext;
> +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
> +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
> +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
> +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
> + u8 mod_type_ext;
> + u8 ext_comp_code;
> u8 phy_id[4];
> u8 module_type[3];
> u8 qualified_module_count;
> @@ -1755,7 +1761,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */
> __le16 eee_capability;
> __le32 eeer;
> u8 low_power_ctrl;
> - u8 reserved[3];
> + u8 phy_type_ext;
> +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
> +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
> +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
> +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
These defines looks like duplicate.
Hi:
> -----Original Message-----
> From: Yigit, Ferruh
> Sent: Friday, September 23, 2016 12:54 AM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>;
> Zhang, Helin <helin.zhang@intel.com>
> Cc: dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 05/12] net/i40e/base: enable 25G get PHY
> abilities
>
> On 8/25/2016 9:05 PM, Zhang Qi wrote:
> > Add extended PHY types to get PHY abilities command response struct
> > for 25G, then put PHY types for 25g into the proper PHY_Type_Ext field.
> >
> > Signed-off-by: Zhang Qi <qi.z.zhang@intel.com>
> > ---
> > drivers/net/i40e/base/i40e_adminq_cmd.h | 15 +++++++++++++--
> > drivers/net/i40e/base/i40e_common.c | 4 +++-
> > 2 files changed, 16 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h
> > b/drivers/net/i40e/base/i40e_adminq_cmd.h
> > index 2831593..4ae4315 100644
> > --- a/drivers/net/i40e/base/i40e_adminq_cmd.h
> > +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
> > @@ -1733,7 +1733,13 @@ struct i40e_aq_get_phy_abilities_resp {
> > __le32 eeer_val;
> > u8 d3_lpan;
> > #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
> > - u8 reserved[3];
> > + u8 phy_type_ext;
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
> > + u8 mod_type_ext;
> > + u8 ext_comp_code;
> > u8 phy_id[4];
> > u8 module_type[3];
> > u8 qualified_module_count;
> > @@ -1755,7 +1761,12 @@ struct i40e_aq_set_phy_config { /* same bits as
> above in all */
> > __le16 eee_capability;
> > __le32 eeer;
> > u8 low_power_ctrl;
> > - u8 reserved[3];
> > + u8 phy_type_ext;
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
> > +#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
>
> These defines looks like duplicate.
>
>
This is copied from base driver, usually we will not modify the code if there is no critical issue.
I will feedback this issue to base driver maintainer. Thanks for capture!
Regards
Qi
@@ -1733,7 +1733,13 @@ struct i40e_aq_get_phy_abilities_resp {
__le32 eeer_val;
u8 d3_lpan;
#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
- u8 reserved[3];
+ u8 phy_type_ext;
+#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
+#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
+#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
+#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
+ u8 mod_type_ext;
+ u8 ext_comp_code;
u8 phy_id[4];
u8 module_type[3];
u8 qualified_module_count;
@@ -1755,7 +1761,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */
__le16 eee_capability;
__le32 eeer;
u8 low_power_ctrl;
- u8 reserved[3];
+ u8 phy_type_ext;
+#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
+#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
+#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
+#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
+ u8 reserved[2];
};
I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
@@ -1670,8 +1670,10 @@ enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
status = I40E_ERR_UNKNOWN_PHY;
- if (report_init)
+ if (report_init) {
hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
+ hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
+ }
return status;
}