From patchwork Thu Nov 1 09:53:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 47654 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DB18A4F91; Thu, 1 Nov 2018 10:54:11 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by dpdk.org (Postfix) with ESMTP id 0A04D91 for ; Thu, 1 Nov 2018 10:54:09 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39E37A78; Thu, 1 Nov 2018 02:54:09 -0700 (PDT) Received: from net-arm-c2400.shanghai.arm.com (net-arm-c2400.shanghai.arm.com [10.169.42.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 76D2A3F71D; Thu, 1 Nov 2018 02:54:07 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: thomas@monjalon.net, stephen@networkplumber.org, olivier.matz@6wind.com, chaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, jerin.jacob@caviumnetworks.com, Honnappa.Nagarahalli@arm.com, gavin.hu@arm.com Date: Thu, 1 Nov 2018 17:53:49 +0800 Message-Id: <1541066031-29125-1-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1539757786-226178-1-git-send-email-gavin.hu@arm.com> References: <1539757786-226178-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v4 0/2] ring library with c11 memory model bug fix and optimization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" v3->v4 1) Move the variable declarations to the beginning of the block. v2->v3 1) reword the change and relocate it in the release note. v1->v2 1) Add the changes to the 18.11 release note. V1: Updated the ring library with C11 memory model including the following changes 1) Synchronize the load and store of the tail to ensure the enqueue/dequeue operations are really completed before seen by the observers on the other sides. 2) Move the atomic load of head above the loop for the first iteration,it is not unnecessary and degrade performance for the other iteration as the head was loaded in the failure case of CAS. Gavin Hu (2): ring: synchronize the load and store of the tail ring: move the atomic load of head above the loop doc/guides/rel_notes/release_18_11.rst | 7 +++++++ lib/librte_ring/rte_ring_c11_mem.h | 24 ++++++++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-)