[v2,036/148] net/ice/base: refactor control queue send delay

Message ID 0a78b17d7e8f10b331069686d330563db2fed2f0.1718204528.git.anatoly.burakov@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Bruce Richardson
Headers
Series Update net/ice base driver to latest upstream snapshot |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Burakov, Anatoly June 12, 2024, 3 p.m. UTC
From: Ian Stokes <ian.stokes@intel.com>

Since we know that most side band queue messages complete within 2-3
microseconds, introduce an initial 5 microsecond delay before we enter the main
timeout loop. Use ice_flush(hw) first to ensure that we immediately flush the
tail bump before delaying. This should mean that in practice almost all side
band messages will be completed at the first ice_sq_done() check.

Because the driver already uses non-sleeping delays, it should not affect the
CPU usage in a negative way to check more frequently.

Currently, the delay is specified using a macro which makes reading the code
difficult as you must look up the macro to figure out the delay value. In
general we try to avoid such "magic" numbers. However, delay values aren't
really magic they're a number. Using a macro obscures the intent here, plus the
macro names are rather long. I double checked the Linux kernel and nearly all
invocations of udelay, usleep_range, and msleep today use raw values or some
multiple of HZ in the case of msleep.

These changes should reduce the amount of time that the driver spins a CPU,
minimizing CPU waste, and reducing the time required to process most control
queue messages.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Ian Stokes <ian.stokes@intel.com>
---
 drivers/net/ice/base/ice_controlq.c | 8 +++++++-
 drivers/net/ice/base/ice_controlq.h | 3 +--
 2 files changed, 8 insertions(+), 3 deletions(-)
  

Patch

diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index cac04c6a98..c2cf747b65 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -1048,12 +1048,18 @@  ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,
 	if (cq->sq.next_to_use == cq->sq.count)
 		cq->sq.next_to_use = 0;
 	wr32(hw, cq->sq.tail, cq->sq.next_to_use);
+	ice_flush(hw);
+
+	/* Wait a short time before initial ice_sq_done() check, to allow
+	 * hardware time for completion.
+	 */
+	ice_usec_delay(5, false);
 
 	do {
 		if (ice_sq_done(hw, cq))
 			break;
 
-		ice_usec_delay(ICE_CTL_Q_SQ_CMD_USEC, false);
+		ice_usec_delay(10, false);
 		total_delay++;
 	} while (total_delay < cq->sq_cmd_timeout);
 
diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index 5c5bb069d8..45394ee695 100644
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -35,8 +35,7 @@  enum ice_ctl_q {
 };
 
 /* Control Queue timeout settings - max delay 1s */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT	10000 /* Count 10000 times */
-#define ICE_CTL_Q_SQ_CMD_USEC		100   /* Check every 100usec */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT	100000	/* Count 100000 times */
 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT	10    /* Count 10 times */
 #define ICE_CTL_Q_ADMIN_INIT_MSEC	100   /* Check every 100msec */