From patchwork Sat Jul 8 19:54:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 26681 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 6661F2C54; Sun, 9 Jul 2017 05:01:40 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id A26D323D; Sun, 9 Jul 2017 05:01:38 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jul 2017 20:01:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.40,332,1496127600"; d="scan'208"; a="1170314520" Received: from dpdk777.sh.intel.com ([10.67.111.90]) by fmsmga001.fm.intel.com with ESMTP; 08 Jul 2017 20:01:34 -0700 From: Qi Zhang To: jingjing.wu@intel.com, beilei.xing@intel.com, ferruh.yigit@intel.com Cc: dev@dpdk.org, helin.zhang@intel.com, Qi Zhang , stable@dpdk.org Date: Sat, 8 Jul 2017 15:54:25 -0400 Message-Id: <1499543665-16166-1-git-send-email-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [dpdk-dev] [PATCH] net/i40e: fix VF Tx bytes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" CRC size on Tx path is not necessary to be excluded. Fixes: 98abce237ba7 ("net/i40e: fix VF statistics") Cc: stable@dpdk.org Signed-off-by: Qi Zhang Acked-by: Beilei Xing --- drivers/net/i40e/i40e_ethdev.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 71cb7d3..0585869 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -2353,9 +2353,6 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx), vsi->offset_loaded, &oes->tx_broadcast, &nes->tx_broadcast); - /* exclude CRC bytes */ - nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast + - nes->tx_broadcast) * ETHER_CRC_LEN; /* GLV_TDPC not supported */ i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, &oes->tx_errors, &nes->tx_errors);