From patchwork Fri Aug 25 07:50:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xing, Beilei" X-Patchwork-Id: 27915 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 628227D53; Fri, 25 Aug 2017 09:51:20 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 051F07D05 for ; Fri, 25 Aug 2017 09:51:16 +0200 (CEST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Aug 2017 00:51:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,424,1498546800"; d="scan'208";a="144422383" Received: from unknown (HELO dpdk9.sh.intel.com) ([10.67.119.137]) by fmsmga006.fm.intel.com with ESMTP; 25 Aug 2017 00:51:15 -0700 From: Beilei Xing To: jingjing.wu@intel.com Cc: dev@dpdk.org Date: Fri, 25 Aug 2017 15:50:24 +0800 Message-Id: <1503647430-93905-2-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1503647430-93905-1-git-send-email-beilei.xing@intel.com> References: <1503647430-93905-1-git-send-email-beilei.xing@intel.com> Subject: [dpdk-dev] [PATCH 1/7] net/i40e: support RSS for GTP-C and GTP-U X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" GTP-C and GTP-U are supported by new profile. Add new PCTYPE and enable RSS for GTP-C and GTP-U. Signed-off-by: Beilei Xing --- drivers/net/i40e/i40e_ethdev.c | 14 ++++++++++++++ drivers/net/i40e/i40e_ethdev.h | 10 +++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 4a2e3f2..7c9e5af 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -197,6 +197,8 @@ #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL /* UDP Tunneling ID, NVGRE/GRE key */ #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL +/* GTP TEID */ +#define I40E_REG_INSET_GTP_TEID 0x0000000000020000ULL /* Last ether type */ #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL /* Tunneling outer destination IPv4 address */ @@ -6760,6 +6762,11 @@ i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf) else hena &= ~I40E_RSS_HENA_ALL; hena |= i40e_config_hena(rss_hf, hw->mac.type); + + /* Enable GTP-C/U by default */ + hena |= 1ULL << I40E_FILTER_PCTYPE_GTPC; + hena |= 1ULL << I40E_FILTER_PCTYPE_GTPU; + i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena); i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32)); I40E_WRITE_FLUSH(hw); @@ -8123,6 +8130,12 @@ i40e_get_valid_input_set(enum i40e_filter_pctype pctype, I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER | I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD, + [I40E_FILTER_PCTYPE_GTPC] = + I40E_INSET_GTP_TEID | I40E_INSET_IPV4_SRC | + I40E_INSET_IPV4_DST, + [I40E_FILTER_PCTYPE_GTPU] = + I40E_INSET_GTP_TEID | I40E_INSET_IPV4_SRC | + I40E_INSET_IPV4_DST, }; /** @@ -8449,6 +8462,7 @@ i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input) {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6}, {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7}, {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8}, + {I40E_INSET_GTP_TEID, I40E_REG_INSET_GTP_TEID}, }; /* some different registers map in x722*/ diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index 48abc05..ab2a5cd 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -119,6 +119,10 @@ enum i40e_flxpld_layer_idx { #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ +/* New PCTYE for GTP-C and GTP-U */ +#define I40E_FILTER_PCTYPE_GTPC 23 +#define I40E_FILTER_PCTYPE_GTPU 24 + /* i40e flags */ #define I40E_FLAG_RSS (1ULL << 0) #define I40E_FLAG_DCB (1ULL << 1) @@ -234,6 +238,8 @@ enum i40e_flxpld_layer_idx { #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL +#define I40E_INSET_GTP_TEID 0x0000004000000000ULL + /* bit 48 ~ bit 55 */ #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL @@ -1131,7 +1137,9 @@ i40e_calc_itr_interval(int16_t interval) (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \ (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \ - (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD) + (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD || \ + (pctype) == I40E_FILTER_PCTYPE_GTPC || \ + (pctype) == I40E_FILTER_PCTYPE_GTPU) #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \ (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \