From patchwork Mon Nov 27 12:29:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rybalchenko, Kirill" X-Patchwork-Id: 31684 X-Patchwork-Delegate: helin.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C3B681B1A1; Mon, 27 Nov 2017 13:30:05 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 38914199B4 for ; Mon, 27 Nov 2017 13:30:02 +0100 (CET) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Nov 2017 04:30:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,465,1505804400"; d="scan'208";a="180644837" Received: from silpixa00389036.ir.intel.com (HELO silpixa00389036.ger.corp.intel.com) ([10.237.223.231]) by fmsmga005.fm.intel.com with ESMTP; 27 Nov 2017 04:29:59 -0800 From: Kirill Rybalchenko To: dev@dpdk.org Cc: jingjing.wu@intel.com, beilei.xing@intel.com, johndale@cisco.com, neescoba@cisco.com, adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com, yskoh@mellanox.com, wenzhuo.lu@intel.com, konstantin.ananyev@intel.com, kirill.rybalchenko@intel.com, andrey.chilikin@intel.com Date: Mon, 27 Nov 2017 12:29:47 +0000 Message-Id: <1511785787-127452-1-git-send-email-kirill.rybalchenko@intel.com> X-Mailer: git-send-email 2.5.5 Subject: [dpdk-dev] [PATCH] ethdev: increase flow type limit from 32 to 64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Increase the internal limit for flow types from 32 to 64 to support future flow type extensions. Change type of variables from uint32_t[] to uint64_t[]: rte_eth_fdir_info.flow_types_mask rte_eth_hash_global_conf.sym_hash_enable_mask rte_eth_hash_global_conf.valid_bit_mask This modification affects the following components: net/i40e net/enic net/mlx5 net/ixgbe app/testpmd Signed-off-by: Kirill Rybalchenko Reviewed-by: Beilei Xing --- app/test-pmd/cmdline.c | 22 +++++++++++----------- drivers/net/enic/enic_clsf.c | 6 +++++- drivers/net/i40e/i40e_ethdev.c | 38 +++++++++++++++++++------------------- drivers/net/i40e/i40e_fdir.c | 25 ++++++++++++++----------- drivers/net/ixgbe/ixgbe_fdir.c | 22 ++++++++++++---------- drivers/net/mlx5/mlx5_flow.c | 4 +++- lib/librte_ether/rte_eth_ctrl.h | 12 ++++++------ 7 files changed, 70 insertions(+), 59 deletions(-) diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c index f71d963..3e57715 100644 --- a/app/test-pmd/cmdline.c +++ b/app/test-pmd/cmdline.c @@ -10681,7 +10681,7 @@ cmd_flow_director_flex_mask_parsed(void *parsed_result, struct rte_eth_fdir_info fdir_info; struct rte_eth_fdir_flex_mask flex_mask; struct rte_port *port; - uint32_t flow_type_mask; + uint64_t flow_type_mask; uint16_t i; int ret; @@ -10734,7 +10734,7 @@ cmd_flow_director_flex_mask_parsed(void *parsed_result, return; } for (i = RTE_ETH_FLOW_UNKNOWN; i < RTE_ETH_FLOW_MAX; i++) { - if (flow_type_mask & (1 << i)) { + if (flow_type_mask & (1ULL << i)) { flex_mask.flow_type = i; fdir_set_flex_mask(res->port_id, &flex_mask); } @@ -10743,7 +10743,7 @@ cmd_flow_director_flex_mask_parsed(void *parsed_result, return; } flex_mask.flow_type = str2flowtype(res->flow_type); - if (!(flow_type_mask & (1 << flex_mask.flow_type))) { + if (!(flow_type_mask & (1ULL << flex_mask.flow_type))) { printf("Flow type %s not supported on port %d\n", res->flow_type, res->port_id); return; @@ -11105,10 +11105,10 @@ cmd_get_hash_global_config_parsed(void *parsed_result, } for (i = 0; i < RTE_ETH_FLOW_MAX; i++) { - idx = i / UINT32_BIT; - offset = i % UINT32_BIT; + idx = i / UINT64_BIT; + offset = i % UINT64_BIT; if (!(info.info.global_conf.valid_bit_mask[idx] & - (1UL << offset))) + (1ULL << offset))) continue; str = flowtype_to_str(i); if (!str) @@ -11116,7 +11116,7 @@ cmd_get_hash_global_config_parsed(void *parsed_result, printf("Symmetric hash is %s globally for flow type %s " "by port %d\n", ((info.info.global_conf.sym_hash_enable_mask[idx] & - (1UL << offset)) ? "enabled" : "disabled"), str, + (1ULL << offset)) ? "enabled" : "disabled"), str, res->port_id); } } @@ -11177,12 +11177,12 @@ cmd_set_hash_global_config_parsed(void *parsed_result, RTE_ETH_HASH_FUNCTION_DEFAULT; ftype = str2flowtype(res->flow_type); - idx = ftype / (CHAR_BIT * sizeof(uint32_t)); - offset = ftype % (CHAR_BIT * sizeof(uint32_t)); - info.info.global_conf.valid_bit_mask[idx] |= (1UL << offset); + idx = ftype / UINT64_BIT; + offset = ftype % UINT64_BIT; + info.info.global_conf.valid_bit_mask[idx] |= (1ULL << offset); if (!strcmp(res->enable, "enable")) info.info.global_conf.sym_hash_enable_mask[idx] |= - (1UL << offset); + (1ULL << offset); ret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_HASH, RTE_ETH_FILTER_SET, &info); if (ret < 0) diff --git a/drivers/net/enic/enic_clsf.c b/drivers/net/enic/enic_clsf.c index 9b46142..c5644cb 100644 --- a/drivers/net/enic/enic_clsf.c +++ b/drivers/net/enic/enic_clsf.c @@ -74,8 +74,12 @@ void enic_fdir_stats_get(struct enic *enic, struct rte_eth_fdir_stats *stats) void enic_fdir_info_get(struct enic *enic, struct rte_eth_fdir_info *info) { + uint32_t i; + info->mode = (enum rte_fdir_mode)enic->fdir.modes; - info->flow_types_mask[0] = enic->fdir.types_mask; + info->flow_types_mask[0] = (uint64_t)enic->fdir.types_mask; + for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++) + info->flow_types_mask[i] = 0ULL; } void enic_fdir_info(struct enic *enic) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 811cc9f..78744c2 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -7984,14 +7984,17 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw, (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR"); /* - * We work only with lowest 32 bits which is not correct, but to work - * properly the valid_bit_mask size should be increased up to 64 bits - * and this will brake ABI. This modification will be done in next - * release + * As i40e supports less than 64 flow types, only first 64 bits need to + * be checked. */ - g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask; + for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) { + g_cfg->valid_bit_mask[i] = 0ULL; + g_cfg->sym_hash_enable_mask[i] = 0ULL; + } - for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) { + g_cfg->valid_bit_mask[0] = adapter->flow_types_mask; + + for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) { if (!adapter->pctypes_tbl[i]) continue; for (j = I40E_FILTER_PCTYPE_INVALID + 1; @@ -8000,7 +8003,7 @@ i40e_get_hash_filter_global_config(struct i40e_hw *hw, reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j)); if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) { g_cfg->sym_hash_enable_mask[0] |= - (1UL << i); + (1ULL << i); } } } @@ -8014,7 +8017,7 @@ i40e_hash_global_config_check(const struct i40e_adapter *adapter, const struct rte_eth_hash_global_conf *g_cfg) { uint32_t i; - uint32_t mask0, i40e_mask = adapter->flow_types_mask; + uint64_t mask0, i40e_mask = adapter->flow_types_mask; if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ && g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && @@ -8025,7 +8028,7 @@ i40e_hash_global_config_check(const struct i40e_adapter *adapter, } /* - * As i40e supports less than 32 flow types, only first 32 bits need to + * As i40e supports less than 64 flow types, only first 64 bits need to * be checked. */ mask0 = g_cfg->valid_bit_mask[0]; @@ -8061,23 +8064,20 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, int ret; uint16_t i, j; uint32_t reg; - /* - * We work only with lowest 32 bits which is not correct, but to work - * properly the valid_bit_mask size should be increased up to 64 bits - * and this will brake ABI. This modification will be done in next - * release - */ - uint32_t mask0 = g_cfg->valid_bit_mask[0] & - (uint32_t)adapter->flow_types_mask; + uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask; /* Check the input parameters */ ret = i40e_hash_global_config_check(adapter, g_cfg); if (ret < 0) return ret; - for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) { + /* + * As i40e supports less than 64 flow types, only first 64 bits need to + * be configured. + */ + for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) { if (mask0 & (1UL << i)) { - reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ? + reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ? I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; for (j = I40E_FILTER_PCTYPE_INVALID + 1; diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index 3d7170d..fbc46ee 100644 --- a/drivers/net/i40e/i40e_fdir.c +++ b/drivers/net/i40e/i40e_fdir.c @@ -95,17 +95,17 @@ #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF) #define I40E_FDIR_FLOWS ( \ - (1 << RTE_ETH_FLOW_FRAG_IPV4) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ - (1 << RTE_ETH_FLOW_FRAG_IPV6) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ - (1 << RTE_ETH_FLOW_L2_PAYLOAD)) + (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ + (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \ + (1ULL << RTE_ETH_FLOW_L2_PAYLOAD)) static int i40e_fdir_filter_programming(struct i40e_pf *pf, enum i40e_filter_pctype pctype, @@ -2020,6 +2020,7 @@ i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir) struct i40e_hw *hw = I40E_PF_TO_HW(pf); uint16_t num_flex_set = 0; uint16_t num_flex_mask = 0; + uint16_t i; if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) fdir->mode = RTE_FDIR_MODE_PERFECT; @@ -2032,6 +2033,8 @@ i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir) (uint32_t)hw->func_caps.fd_filters_best_effort; fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN; fdir->flow_types_mask[0] = I40E_FDIR_FLOWS; + for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++) + fdir->flow_types_mask[i] = 0ULL; fdir->flex_payload_unit = sizeof(uint16_t); fdir->flex_bitmask_unit = sizeof(uint16_t); fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED; diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.c index 9281dc1..6870a57 100644 --- a/drivers/net/ixgbe/ixgbe_fdir.c +++ b/drivers/net/ixgbe/ixgbe_fdir.c @@ -70,14 +70,14 @@ #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10 #define IXGBE_FDIR_FLOW_TYPES ( \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ - (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)) + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \ + (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)) #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \ uint8_t ipv6_addr[16]; \ @@ -1435,7 +1435,7 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ixgbe_hw_fdir_info *info = IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); - uint32_t fdirctrl, max_num; + uint32_t fdirctrl, max_num, i; uint8_t offset; fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); @@ -1467,9 +1467,11 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN || fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL) - fdir_info->flow_types_mask[0] = 0; + fdir_info->flow_types_mask[0] = 0ULL; else fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES; + for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++) + fdir_info->flow_types_mask[i] = 0ULL; fdir_info->flex_payload_unit = sizeof(uint16_t); fdir_info->max_flex_payload_segment_num = 1; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index f32dfdd..84927ff 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -2987,6 +2987,7 @@ priv_fdir_filter_flush(struct priv *priv) static void priv_fdir_info_get(struct priv *priv, struct rte_eth_fdir_info *fdir_info) { + uint32_t i; struct rte_eth_fdir_masks *mask = &priv->dev->data->dev_conf.fdir_conf.mask; @@ -2994,7 +2995,8 @@ priv_fdir_info_get(struct priv *priv, struct rte_eth_fdir_info *fdir_info) fdir_info->guarant_spc = 0; rte_memcpy(&fdir_info->mask, mask, sizeof(fdir_info->mask)); fdir_info->max_flexpayload = 0; - fdir_info->flow_types_mask[0] = 0; + for (i = 0; i < RTE_FLOW_MASK_ARRAY_SIZE; i++) + info->flow_types_mask[i] = 0ULL; fdir_info->flex_payload_unit = 0; fdir_info->max_flex_payload_segment_num = 0; fdir_info->flex_payload_limit = 0; diff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h index 8386904..4f24a93 100644 --- a/lib/librte_ether/rte_eth_ctrl.h +++ b/lib/librte_ether/rte_eth_ctrl.h @@ -691,9 +691,9 @@ enum rte_fdir_mode { RTE_FDIR_MODE_PERFECT_TUNNEL, /**< Enable FDIR filter mode - tunnel. */ }; -#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) +#define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) #define RTE_FLOW_MASK_ARRAY_SIZE \ - (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) + (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) /** * A structure used to get the information of flow director filter. @@ -710,7 +710,7 @@ struct rte_eth_fdir_info { uint32_t guarant_spc; /**< Guaranteed spaces.*/ uint32_t best_spc; /**< Best effort spaces.*/ /** Bit mask for every supported flow type. */ - uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]; + uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]; uint32_t max_flexpayload; /**< Total flex payload in bytes. */ /** Flexible payload unit in bytes. Size and alignments of all flex payload segments should be multiplies of this value. */ @@ -803,7 +803,7 @@ enum rte_eth_hash_function { }; #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ - (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT) + (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) /** * A structure used to set or get global hash function configurations which * include symmetric hash enable per flow type and hash function type. @@ -816,9 +816,9 @@ enum rte_eth_hash_function { struct rte_eth_hash_global_conf { enum rte_eth_hash_function hash_func; /**< Hash function type */ /** Bit mask for symmetric hash enable per flow type */ - uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE]; + uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE]; /** Bit mask indicates if the corresponding bit is valid */ - uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE]; + uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE]; }; /**