@@ -12,6 +12,63 @@
/**
+ * Perform access to the registers. Reads data from and writes data to
+ * the specified register.
+ *
+ * @param[in] ctx
+ * Context returned from mlx5 open_device() glue function.
+ * @param[in] reg_id
+ * Register identifier according to the PRM.
+ * @param[in] arg
+ * Register access auxiliary parameter according to the PRM.
+ * @param[inout] value
+ * Pointer to the value to be wriiten to the register or
+ * to the buffer where the read data to be stored.
+ * @param[in] write
+ * Non-zero value means write to the register should be performed,
+ * otherwise read access will be performed.
+ *
+ * @return
+ * 0 on success, a negative value otherwise.
+ */
+int
+mlx5_devx_cmd_register_access(void *ctx, uint16_t reg_id,
+ uint32_t arg, uint32_t *value,
+ uint32_t write)
+{
+ uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
+ uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
+ int status, rc;
+
+ MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REGISTER);
+ MLX5_SET(access_register_in, in, op_mod, write ?
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE :
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
+ MLX5_SET(access_register_in, in, register_id, reg_id);
+ MLX5_SET(access_register_in, in, argument, arg);
+ if (write && value)
+ MLX5_SET(access_register_in, in, register_data, *value);
+ rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
+ if (rc)
+ goto error;
+ status = MLX5_GET(access_register_out, out, status);
+ if (status) {
+ int syndrome = MLX5_GET(access_register_out, out, syndrome);
+
+ DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
+ "status %x, syndrome = %x",
+ reg_id, status, syndrome);
+ return -1;
+ }
+ if (value && !write)
+ *value = MLX5_GET(access_register_out, out, register_data);
+ return 0;
+error:
+ rc = (rc > 0) ? -rc : rc;
+ return rc;
+};
+
+/**
* Allocate flow counters via devx interface.
*
* @param[in] ctx
@@ -383,6 +383,10 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
+__rte_internal
+int mlx5_devx_cmd_register_access(void *ctx, uint16_t reg_id,
+ uint32_t arg, uint32_t *value,
+ uint32_t write);
/**
* Create virtio queue counters object DevX API.
*
@@ -776,6 +776,7 @@ enum {
MLX5_CMD_OP_SUSPEND_QP = 0x50F,
MLX5_CMD_OP_RESUME_QP = 0x510,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+ MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
MLX5_CMD_OP_CREATE_TIR = 0x900,
MLX5_CMD_OP_CREATE_SQ = 0X904,
@@ -2545,6 +2546,30 @@ struct mlx5_ifc_set_pp_rate_limit_context_bits {
u8 reserved_at_60[0x120];
};
+struct mlx5_ifc_access_register_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+ u8 register_data[0][0x20];
+};
+
+enum {
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
+ MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
+};
+
+struct mlx5_ifc_access_register_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x10];
+ u8 register_id[0x10];
+ u8 argument[0x20];
+ u8 register_data[0][0x20];
+};
+
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc
@@ -34,6 +34,7 @@ INTERNAL {
mlx5_devx_cmd_query_hca_attr;
mlx5_devx_cmd_query_virtio_q_counters;
mlx5_devx_cmd_query_virtq;
+ mlx5_devx_cmd_register_access;
mlx5_devx_get_out_command_status;
mlx5_get_ifname_sysfs;