diff mbox series

net/hns3: fix TM QCN error event report by MSIX

Message ID 1620459657-38326-1-git-send-email-humin29@huawei.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers show
Series net/hns3: fix TM QCN error event report by MSIX | expand

Checks

Context Check Description
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/github-robot success github build: passed
ci/iol-abi-testing success Testing PASS
ci/iol-testing success Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/checkpatch success coding style OK

Commit Message

Min Hu (Connor) May 8, 2021, 7:40 a.m. UTC
From: Chengwen Feng <fengchengwen@huawei.com>

The TM QCN error event should report by RAS other than MSIX.

Also this patch adds fifo int enable configuration before the TM QCN
error event is enabled.

Fixes: f53a793bb7c2 ("net/hns3: add more hardware error types")
Fixes: 3903c05382c5 ("net/hns3: remove read when enabling TM QCN error event")
Cc: stable@dpdk.org

Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
---
 drivers/net/hns3/hns3_intr.c | 5 ++++-
 drivers/net/hns3/hns3_intr.h | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

Ferruh Yigit May 11, 2021, 5:35 p.m. UTC | #1
On 5/8/2021 8:40 AM, Min Hu (Connor) wrote:
> From: Chengwen Feng <fengchengwen@huawei.com>
> 
> The TM QCN error event should report by RAS other than MSIX.
> 
> Also this patch adds fifo int enable configuration before the TM QCN
> error event is enabled.
> 
> Fixes: f53a793bb7c2 ("net/hns3: add more hardware error types")
> Fixes: 3903c05382c5 ("net/hns3: remove read when enabling TM QCN error event")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>

Applied to dpdk-next-net/main, thanks.
diff mbox series

Patch

diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c
index 905c6d9..6bdb17f 100644
--- a/drivers/net/hns3/hns3_intr.c
+++ b/drivers/net/hns3/hns3_intr.c
@@ -1783,8 +1783,11 @@  enable_tm_err_intr(struct hns3_adapter *hns, bool en)
 
 	/* configure TM QCN hw errors */
 	hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, false);
-	if (en)
+	desc.data[0] = rte_cpu_to_le_32(HNS3_TM_QCN_ERR_INT_TYPE);
+	if (en) {
+		desc.data[0] |= rte_cpu_to_le_32(HNS3_TM_QCN_FIFO_INT_EN);
 		desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN);
+	}
 
 	ret = hns3_cmd_send(hw, &desc, 1);
 	if (ret)
diff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h
index 8bee8d7..1a0f196 100644
--- a/drivers/net/hns3/hns3_intr.h
+++ b/drivers/net/hns3/hns3_intr.h
@@ -77,6 +77,8 @@ 
 #define HNS3_NCSI_ERR_INT_EN			0x3
 
 #define HNS3_TM_SCH_ECC_ERR_INT_EN		0x3
+#define HNS3_TM_QCN_ERR_INT_TYPE		0x29
+#define HNS3_TM_QCN_FIFO_INT_EN			0xFFFF00
 #define HNS3_TM_QCN_MEM_ERR_INT_EN		0xFFFFFF
 
 #define HNS3_RESET_PROCESS_MS			200